1
S
R
R1
TRIG
THRES
VCC
CONT
RESET
OUT
DISCH
GND
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
4
8
5
6
2
1
7
3
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
xx555 Precision Timers
1 Features 3 Description
These devices are precision timing circuits capable of
1• Timing From Microseconds to Hours producing accurate time delays or oscillation. In the
• Astable or Monostable Operation time-delay or mono-stable mode of operation, the
• Adjustable Duty Cycle timed interval is controlled by a single external
resistor and capacitor network. In the a-stable mode
• TTL-Compatible Output Can Sink or Source of operation, the frequency and duty cycle can be
Up to 200 mA controlled independently with two external resistors
• On Products Compliant to MIL-PRF-38535, and a single external capacitor.
All Parameters Are Tested Unless Otherwise The threshold and trigger levels normally are two-
Noted. On All Other Products, Production thirds and one-third, respectively, of VCC. These
Processing Does Not Necessarily Include levels can be altered by use of the control-voltage
Testing of All Parameters. terminal. When the trigger input falls below the trigger
level, the flip-flop is set, and the output goes high. If
2 Applications the trigger input is above the trigger level and the
• Fingerprint Biometrics threshold input is above the threshold level, the flip-
flop is reset and the output is low. The reset (RESET)
• Iris Biometrics input can override all other inputs and can be used to
• RFID Reader initiate a new timing cycle. When RESET goes low,
the flip-flop is reset, and the output goes low. When
the output is low, a low-impedance path is provided
between discharge (DISCH) and ground.
The output circuit is capable of sinking or sourcing
current up to 200 mA. Operation is specified for
supplies of 5 V to 15 V. With a 5-V supply, output
levels are compatible with TTL inputs.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
PDIP (8) 9.81 mm × 6.35 mm
SOP (8) 6.20 mm × 5.30 mm
xx555 TSSOP (8) 3.00 mm × 4.40 mm
SOIC (8) 4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
8.1 Overview................................................................... 9
1 Features.................................................................. 18.2 Functional Block Diagram......................................... 9
2 Applications ........................................................... 18.3 Feature Description................................................... 9
3 Description............................................................. 18.4 Device Functional Modes........................................ 12
4 Simplified Schematic............................................. 19 Applications and Implementation ...................... 13
5 Revision History..................................................... 29.1 Application Information............................................ 13
6 Pin Configuration and Functions......................... 39.2 Typical Applications ................................................ 13
7 Specifications......................................................... 410 Power Supply Recommendations ..................... 18
7.1 Absolute Maximum Ratings ..................................... 411 Device and Documentation Support................. 19
7.2 Handling Ratings....................................................... 411.1 Related Links ........................................................ 19
7.3 Recommended Operating Conditions....................... 411.2 Trademarks........................................................... 19
7.4 Electrical Characteristics........................................... 511.3 Electrostatic Discharge Caution............................ 19
7.5 Operating Characteristics.......................................... 611.4 Glossary................................................................ 19
7.6 Typical Characteristics.............................................. 712 Mechanical, Packaging, and Orderable
8 Detailed Description.............................................. 9Information........................................................... 19
5 Revision History
Changes from Revision H (June 2010) to Revision I Page
• Updated document to new TI enhanced data sheet format................................................................................................... 1
• Deleted Ordering Information table. ...................................................................................................................................... 1
• Added Military Disclaimer to Features list.............................................................................................................................. 1
• Added Applications................................................................................................................................................................. 1
• Added Device Information table. ............................................................................................................................................ 1
• Moved Tstg to Handling Ratings table..................................................................................................................................... 4
• Added DISCH switch on-state voltage parameter.................................................................................................................. 5
• Added Device and Documentation Support section............................................................................................................. 19
• Added ESD warning............................................................................................................................................................. 19
• Added Mechanical, Packaging, and Orderable Information section..................................................................................... 19
2Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
6 Pin Configuration and Functions
Pin Functions
PIN
D, P, PS, FK I/O DESCRIPTION
PW, JG
NAME NO.
Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitor
CONT 5 12 I/O connection
DISCH 7 17 O Open collector output to discharge timing capacitor
GND 1 2 – Ground
1, 3, 4, 6, 8,
9, 11, 13,
NC – No internal connection
14, 16, 18,
19
OUT 3 7 O High current timer output signal
RESET 4 10 I Active low reset input forces output and discharge low.
THRES 6 15 I End of timing input. THRES > CONT sets output low and discharge low
TRIG 2 5 I Start of timing input. TRIG < ½ CONT sets output high and discharge open
VCC 8 20 – Input supply voltage, 4.5 V to 16 V. (SE555 maximum is 18 V)
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: NA555 NE555 SA555 SE555
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage(2) 18 V
VIInput voltage CONT, RESET, THRES, TRIG VCC V
IOOutput current ±225 mA
D package 97
P package 85
θJA Package thermal impedance(3)(4) °C/W
PS package 95
PW package 149
FK package 5.61
θJC Package thermal impedance(5)(6) °C/W
JG package 14.5
TJOperating virtual junction temperature 150 °C
Case temperature for 60 s FK package 260 °C
Lead temperature 1,6 mm (1/16 in) from case for 60 s JG package 300 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD= (TJ(max) - TA) / θJA. Operating at the absolute maximum TJof 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD= (TJ(max) - TC) / θJC. Operating at the absolute maximum TJof 150°C can affect reliability.
(6) The package thermal impedance is calculated in accordance with MIL-STD-883.
7.2 Handling Ratings
PARAMETER DEFINITION MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
NA555, NE555, SA555 4.5 16
VCC Supply voltage V
SE555 4.5 18
VIInput voltage CONT, RESET, THRES, and TRIG VCC V
IOOutput current ±200 mA
NA555 –40 105
NE555 0 70
TAOperating free-air temperature °C
SA555 –40 85
SE555 –55 125
4Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
7.4 Electrical Characteristics
VCC = 5 V to 15 V, TA= 25°C (unless otherwise noted) NA555
SE555 NE555
PARAMETER TEST CONDITIONS UNIT
SA555
MIN TYP MAX MIN TYP MAX
VCC = 15 V 9.4 10 10.6 8.8 10 11.2
THRES voltage level V
VCC = 5 V 2.7 3.3 4 2.4 3.3 4.2
THRES current(1) 30 250 30 250 nA
4.8 5 5.2 4.5 5 5.6
VCC = 15 V TA= –55°C to 125°C 3 6
TRIG voltage level V
1.45 1.67 1.9 1.1 1.67 2.2
VCC = 5 V TA= –55°C to 125°C 1.9
TRIG current TRIG at 0 V 0.5 0.9 0.5 2 μA
0.3 0.7 1 0.3 0.7 1
RESET voltage level V
TA= –55°C to 125°C 1.1
RESET at VCC 0.1 0.4 0.1 0.4
RESET current mA
RESET at 0 V –0.4 –1 –0.4 –1.5
DISCH switch off-state 20 100 20 100 nA
current
DISCH switch on-state VCC = 5 V, IO= 8 mA 0.15 0.4 V
voltage 9.6 10 10.4 9 10 11
VCC = 15 V TA= –55°C to 125°C 9.6 10.4
CONT voltage V
(open circuit) 2.9 3.3 3.8 2.6 3.3 4
VCC = 5 V TA= –55°C to 125°C 2.9 3.8
0.1 0.15 0.1 0.25
VCC = 15 V, IOL = 10 mA TA= –55°C to 125°C 0.2
0.4 0.5 0.4 0.75
VCC = 15 V, IOL = 50 mA TA= –55°C to 125°C 1
2 2.2 2 2.5
VCC = 15 V, IOL = 100 mA
Low-level output voltage TA= –55°C to 125°C 2.7 V
VCC = 15 V, IOL = 200 mA 2.5 2.5
VCC = 5 V, IOL = 3.5 mA TA= –55°C to 125°C 0.35
0.1 0.2 0.1 0.35
VCC = 5 V, IOL = 5 mA TA= –55°C to 125°C 0.8
VCC = 5 V, IOL = 8 mA 0.15 0.25 0.15 0.4
13 13.3 12.75 13.3
VCC = 15 V, IOH = –100 mA TA= –55°C to 125°C 12
High-level output voltage VCC = 15 V, IOH = –200 mA 12.5 12.5 V
3 3.3 2.75 3.3
VCC = 5 V, IOH = –100 mA TA= –55°C to 125°C 2
VCC = 15 V 10 12 10 15
Output low, No load VCC = 5 V 3 5 3 6
Supply current mA
VCC = 15 V 9 10 9 13
Output high, No load VCC = 5 V 2 4 2 5
(1) This parameter influences the maximum value of the timing resistors RAand RBin the circuit of Figure 12. For example,
when VCC = 5 V, the maximum value is R = RA+ RB≉3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ.
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: NA555 NE555 SA555 SE555
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
7.5 Operating Characteristics
VCC = 5 V to 15 V, TA= 25°C (unless otherwise noted) NA555
SE555 NE555
TEST
PARAMETER UNIT
SA555
CONDITIONS(1)
MIN TYP MAX MIN TYP MAX
Each timer, monostable(3) TA= 25°C 0.5 1.5(4) 1 3
Initial error of timing %
interval(2) Each timer, astable(5) 1.5 2.25
Each timer, monostable(3) TA= MIN to MAX 30 100(4) 50
Temperature coefficient of ppm/
timing interval °C
Each timer, astable(5) 90 150
Each timer, monostable(3) TA= 25°C 0.05 0.2(4) 0.1 0.5
Supply-voltage sensitivity of %/V
timing interval Each timer, astable(5) 0.15 0.3
CL= 15 pF,
Output-pulse rise time 100 200(4) 100 300 ns
TA= 25°C
CL= 15 pF,
Output-pulse fall time 100 200(4) 100 300 ns
TA= 25°C
(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
(2) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each
process run.
(3) Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA= 2 kΩto 100 kΩ,
C = 0.1 μF.
(4) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(5) Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA= 1 kΩto 100 kΩ,
C = 0.1 μF.
6Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
5
4
2
1
0
9
3
5 6 7 8 9 10 11
− Supply Current − mA
7
6
8
10
12 13 14 15
TA= 25°C
TA= 125°C
TA= −55°C
Output Low,
No Load
CC
I
VCC − Supply Voltage − V
1
0.995
0.990
0.985
0 5 10
1.005
1.010
1.015
15 20
CC
V
Pulse Duration Relative to V
alue at = 10 V
VCC − Supply Voltage − V
8
TA= 125°C
TA= 25°C
TA= −55°C
VCC = 15 V
− Low-Level Output V
oltage − V
VOL
IOL − Low-Level Output Current − mA
0.1
0.04
0.01
1 2 4 7 10 20 40 70 100
0.07
1
0.4
0.7
10
4
7
0.02
0.2
2
1
0.6
0.2
0
1.4
1.8
2.0
0.4
1.6
0.8
1.2
−
IOH − High-Level Output Current − mA
TA= 125°C
TA= 25°C
100704020107421
VCC = 5 V to 15 V
TA= −55°C
VCC VOH − Voltage Drop − V
)
(
TA= 125°C
TA= 25°C
IOL − Low-Level Output Current − mA
VCC = 5 V
TA= −55°C
0.1
0.04
0.01
1 2 4 7 10 20 40 70 100
0.07
1
0.4
0.7
10
4
7
0.02
0.2
2
− Low-Level Output V
oltage − V
VOL
VCC = 10 V
− Low-Level Output V
oltage − V
VOL
IOL − Low-Level Output Current − mA
0.1
0.04
0.01
1 2 4 7 10 20 40 70 100
0.07
1
0.4
0.7
10
4
7
0.02
0.2
2
TA= 125°C
TA= 25°C
TA= −55°C
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
7.6 Typical Characteristics
Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only.
Figure 1. Low-Level Output Voltage Figure 2. Low-Level Output Voltage
vs Low-Level Output Current vs Low-Level Output Current
Figure 3. Low-Level Output Voltage Figure 4. Drop Between Supply Voltage and Output
vs Low-Level Output Current vs High-Level Output Current
Figure 5. Supply Current Figure 6. Normalized Output Pulse Duration
vs Supply Voltage (Monostable Operation)
vs Supply Voltage
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: NA555 NE555 SA555 SE555
0
100
200
300
400
500
600
700
800
900
1000
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Lowest Level of Trigger Pulse – ×VCC
tPD – Propagation Delay Time – ns
TA= 125 C°
TA= 70 C°
TA= 25 C°
TA= 0 C°
TA= –55 C°
8
1
0.995
0.990
0.985
−75 −25 25
1.005
1.010
1.015
75 125
TA− Free-Air Temperature − °C
−50 0 50 100
VCC = 10 V
Pulse Duration Relative to V
alue at TA= 25 C
8
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
Typical Characteristics (continued)
Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only.
Figure 7. Normalized Output Pulse Duration Figure 8. Propagation Delay Time
(Monostable Operation) vs
vs Lowest Voltage Level of Trigger Pulse
Free-Air Temperature
8Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
1
S
R
R1
TRIG
THRES
VCC
CONT
RESET
OUT
DISCH
GND
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
4
8
5
6
2
1
7
3
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
8 Detailed Description
8.1 Overview
The xx555 timer is a popular and easy to use for general purpose timing applications from 10 µs to hours or from
< 1mHz to 100 kHz. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a
single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle
can be controlled independently with two external resistors and a single external capacitor. Maximum output sink
and discharge sink current is greater for higher VCC and less for lower VCC.
8.2 Functional Block Diagram
A. Pin numbers shown are for the D, JG, P, PS, and PW packages.
B. RESET can override TRIG, which can override THRES.
8.3 Feature Description
8.3.1 Mono-stable Operation
For mono-stable operation, any of these timers can be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high,
and turns off Q1. Capacitor C then is charged through RAuntil the voltage across the capacitor reaches the
threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold
comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: NA555 NE555 SA555 SE555
Voltage − 2 V/div
Time − 0.1 ms/div
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
Capacitor Voltage
Output Voltage
Input Voltage
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
RA = 9.1 kΩ
CL = 0.01 µF
RL = 1 kΩ
See Figure 9
− Output Pulse Duration − s
C − Capacitance − µF
10
1
10−1
10−2
10−3
10−4
1001010.10.01
10−5
0.001
tw
RA = 10 MΩ
RA = 10 kΩ
RA = 1 kΩ
RA = 100 kΩ
RA = 1 MΩ
VCC
(5 V to 15 V)
RARL
Output
GND
OUT
VCC
CONT
RESET
DISCH
THRES
TRIGInput
Î
Î
Î
58
4
7
6
2
3
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
Feature Description (continued)
Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger is
grounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse
width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is
approximately tw= 1.1RAC. Figure 11 is a plot of the time constant for various values of RAand C. The threshold
levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore,
independent of the supply voltage, so long as the supply voltage is constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long
as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.
Figure 10. Typical Monostable Waveforms Figure 11. Output Pulse Duration vs Capacitance
10 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
L B
H A B
t R
Low-to-high ratio t R R
= =
+
H B
H L A B
t R
Output waveform duty cycle 1
t t R 2R
= = -
+ +
L B
H L A B
t R
Output driver duty cycle t t R 2R
= =
+ +
( )
A B
1.44
frequency R 2R C
»+
( )
H L A B
period t t 0.693 R 2R C= + = +
( )
L B
t 0.693 R C=
( )
H A B
t 0.693 R R C= +
GND
OUT
VCC
CONT
RESET
DISCH
THRES
TRIG
C
RB
RA
Output
RL
0.01 µF
VCC
(5 V to 15 V)
(see Note A)
Î
Î
Î
NOTE A: Decoupling CONT voltage to ground with a capacitor can
improve operation. This should be evaluated for individual
applications.
Open
5 8
4
7
6
2
3
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
Voltage − 1 V/div
Time − 0.5 ms/div
tH
Capacitor Voltage
Output Voltage
tL
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
RA = 5 kW RL = 1 kW
RB = 3 kW See Figure 12
C = 0.15 µF
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
Feature Description (continued)
8.3.2 A-stable Operation
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to
the threshold input causes the timer to self-trigger and run as a multi-vibrator. The capacitor C charges through
RAand RBand then discharges through RBonly. Therefore, the duty cycle is controlled by the values of RAand
RB.
This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≈
0.67 × VCC) and the trigger-voltage level (≈0.33 × VCC). As in the mono-stable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
Figure 12. Circuit for Astable Operation Figure 13. Typical Astable Waveforms
Figure 12 shows typical waveforms generated during astable operation. The output high-level duration tHand
low-level duration tLcan be calculated as follows:
(1)
(2)
Other useful relationships are shown below:
(3)
(4)
(5)
(6)
(7)
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: NA555 NE555 SA555 SE555
Voltage − 2 V/div
Time − 0.1 ms/div
Capacitor Voltage
Output Voltage
Input Voltage
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
VCC = 5 V
RA = 1250 Ω
C = 0.02 µF
See Figure 9
f − Free-Running Frequency − Hz
C − Capacitance − µF
100 k
10 k
1 k
100
10
1
1001010.10.01
0.1
0.001
RA + 2 RB = 10 MΩ
RA + 2 RB = 1 MΩ
RA + 2 RB = 100 kΩ
RA + 2 RB = 10 kΩ
RA + 2 RB = 1 kΩ
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
Feature Description (continued)
Figure 14. Free-Running Frequency
8.3.3 Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 15 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during
the timing cycle.
Figure 15. Divide-by-Three Circuit Waveforms
8.4 Device Functional Modes
Table 1. Function Table
RESET TRIGGER VOLTAGE(1) THRESHOLD VOLTAGE(1) OUTPUT DISCHARGE SWITCH
Low Irrelevant Irrelevant Low On
High <1/3 VCC Irrelevant High Off
High >1/3 VCC >2/3 VCC Low On
High >1/3 VCC <2/3 VCC As previously established
(1) Voltage levels shown are nominal.
12 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
VCC (5 V to 15 V)
DISCH
OUT
VCC
RESET
RLRA
A5T3644
C
THRES
GND
CONT
TRIG
Input
0.01 µF
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output
4 8
3
7
6
2
5
1
Pin numbers shown are shown for the D, JG, P, PS, and PW packages.
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The xx555 timer devices use resistor and capacitor charging delay to provide a programmable time delay or
operating frequency. This section presents a simplified discussion of the design process.
9.2 Typical Applications
9.2.1 Missing-Pulse Detector
The circuit shown in Figure 16 can be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is re-triggered continuously
by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing,
missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output
pulse as shown in Figure 17.
Figure 16. Circuit for Missing-Pulse Detector
9.2.1.1 Design Requirements
Input fault (missing pulses) must be input high. Input stuck low will not be detected because timing capacitor "C"
will remain discharged.
9.2.1.2 Detailed Design Procedure
Choose RAand C so that RA× C > [maximum normal input high time]. RLimproves VOH, but it is not required for
TTL compatibility.
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: NA555 NE555 SA555 SE555
THRES
GND C
RA
RL
VCC (5 V to 15 V)
Output
DISCH
OUT
VCC
RESET
TRIG
CONT
Modulation
Input
(see Note A)
Clock
Input
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation source
voltage and impedance on the bias of the timer should be
considered.
4 8
3
7
6
2
5
Pin numbers shown are for the D, JG, P, PS, and PW packages.
1
Time − 0.1 ms/div
Voltage − 2 V/div
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC = 5 V
RA = 1 kΩ
C = 0.1 µF
See Figure 15
Capacitor Voltage
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Output Voltage
Input Voltage
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
Typical Applications (continued)
9.2.1.3 Application Curves
Figure 17. Completed Timing Waveforms for Missing-Pulse Detector
9.2.2 Pulse-Width Modulation
The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation
signal is shown, any wave shape could be used.
Figure 18. Circuit for Pulse-Width Modulation
14 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
Voltage − 2 V/div
Time − 0.5 ms/div
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
Capacitor Voltage
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
Output Voltage
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
Clock Input Voltage
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
RA = 3 kΩ
C = 0.02 µF
RL = 1 kΩ
See Figure 18
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
Modulation Input Voltage
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
Typical Applications (continued)
9.2.2.1 Design Requirements
Clock input must have VOL and VOH levels that are less than and greater than 1/3 VCC. Modulation input can
vary from ground to VCC. The application must be tolerant of a nonlinear transfer function; the relationship
between modulation input and pulse width is not linear because the capacitor charge is based RC on an negative
exponential curve.
9.2.2.2 Detailed Design Procedure
Choose RAand C so that RA× C = 1/4 [clock input period]. RLimproves VOH, but it is not required for TTL
compatibility.
9.2.2.3 Application Curves
Figure 19. Pulse-Width-Modulation Waveforms
9.2.3 Pulse-Position Modulation
As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a
triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: NA555 NE555 SA555 SE555
RB
Modulation
Input
(see Note A) CONT
TRIG
RESET VCC
OUT
DISCH
VCC (5 V to 15 V)
RLRA
C
GND
THRES
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation
source voltage and impedance on the bias of the timer
should be considered.
Pin numbers shown are for the D, JG, P, PS, and PW packages.
4 8
3
7
6
2
5
Output
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
Typical Applications (continued)
Figure 20. Circuit for Pulse-Position Modulation
9.2.3.1 Design Requirements
Both DC and AC coupled modulation input will change the upper and lower voltage thresholds for the timing
capacitor. Both frequency and duty cycle will vary with the modulation voltage.
9.2.3.2 Detailed Design Procedure
The nominal output frequency and duty cycle can be determined using formulas in A-stable Operation section. RL
improves VOH, but it is not required for TTL compatibility.
16 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
S
VCC
RESET VCC
OUT
DISCH
GND
CONT
TRIG
4 8
3
7
6
1
5
2
THRES
RC
CC
0.01
CC = 14.7 µF
RC = 100 kΩOutput C
RESET VCC
OUT
DISCH
GND
CONT
TRIG
4 8
3
7
6
1
5
2
THRES
RB33 kΩ
0.001
0.01
µF
CB = 4.7 µF
RB = 100 kΩ
Output BOutput A
RA = 100 kΩ
CA = 10 µF
µF
0.01
µF
0.001
33 kΩ
RA
THRES
2
5
1
6
7
3
84
TRIG
CONT
GND
DISCH
OUT
VCC
RESET
µF
µF
CB
CA
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: S closes momentarily at t = 0.
Voltage − 2 V/div
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
RA = 3 kΩ
RB = 500 Ω
RL = 1 kΩ
See Figure 20
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Capacitor Voltage
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Output Voltage
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Modulation Input Voltage
Time − 0.1 ms/div
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
Typical Applications (continued)
9.2.3.3 Application Curves
Figure 21. Pulse-Position-Modulation Waveforms
9.2.4 Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be
connected to provide such sequential control. The timers can be used in various combinations of astable or
monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22
shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output
waveforms.
Figure 22. Sequential Timer Circuit
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: NA555 NE555 SA555 SE555
Voltage − 5 V/div
t − Time − 1 s/div
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
See Figure 22
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
Output A
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
Output B
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
Output C
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
t = 0
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
twC = 1.1 RCCC
ÏÏ
ÏÏ
ÏÏ
twC
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
twB = 1.1 RBCB
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
twA = 1.1 RACA
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
twA
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
twB
NA555
,
NE555
,
SA555
,
SE555
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
www.ti.com
Typical Applications (continued)
9.2.4.1 Design Requirements
The sequential timer application chains together multiple mono-stable timers. The joining components are the 33-
kΩresistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next
monostable.
9.2.4.2 Detailed Design Procedure
The timing resistors and capacitors can be chosen using this formula. tw= 1.1 × R × C.
9.2.4.3 Application Curves
Figure 23. Sequential Timer Waveforms
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 16 V. (18 V for
SE555). A bypass capacitor is highly recommended from VCC to ground pin; ceramic 0.1 µF capacitor is
sufficient.
18 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated
Product Folder Links: NA555 NE555 SA555 SE555
NA555
,
NE555
,
SA555
,
SE555
www.ti.com
SLFS022I –SEPTEMBER 1973–REVISED SEPTEMBER 2014
11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
NA555 Click here Click here Click here Click here Click here
NE555 Click here Click here Click here Click here Click here
SA555 Click here Click here Click here Click here Click here
SE555 Click here Click here Click here Click here Click here
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 1973–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: NA555 NE555 SA555 SE555
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
JM38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/10901BPA
M38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/10901BPA
NA555D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555
NA555DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555
NA555DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555
NA555P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN N / A for Pkg Type -40 to 105 NA555P
NA555PE4 ACTIVE PDIP P 8 50 TBD Call TI Call TI -40 to 105 NA555P
NE555D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 NE555
NE555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 NE555P
NE555PE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 NE555P
NE555PSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PSRE4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
NE555PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
SA555D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555DE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 SA555
SA555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P
SA555PE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P
SE555D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555
SE555DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555
SE555DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555
SE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555
SE555FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SE555FKB
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SE555JG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JG
SE555JGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JGB
SE555P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 SE555P
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 4
OTHER QUALIFIED VERSIONS OF SE555, SE555M :
•Catalog: SE555
•Military: SE555M
•Space: SE555-SP, SE555-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
NA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
NE555DR SOIC D 8 2500 330.0 15.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
NE555PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
SA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SA555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
NA555DR SOIC D 8 2500 340.5 338.1 20.6
NA555DR SOIC D 8 2500 367.0 367.0 35.0
NE555DR SOIC D 8 2500 340.5 338.1 20.6
NE555DR SOIC D 8 2500 367.0 367.0 35.0
NE555DR SOIC D 8 2500 364.0 364.0 27.0
NE555DR SOIC D 8 2500 333.2 345.9 28.6
NE555DRG4 SOIC D 8 2500 340.5 338.1 20.6
NE555DRG4 SOIC D 8 2500 367.0 367.0 35.0
NE555PSR SO PS 8 2000 367.0 367.0 38.0
NE555PWR TSSOP PW 8 2000 367.0 367.0 35.0
SA555DR SOIC D 8 2500 340.5 338.1 20.6
SA555DRG4 SOIC D 8 2500 340.5 338.1 20.6
SE555DR SOIC D 8 2500 367.0 367.0 38.0
SE555DRG4 SOIC D 8 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Sep-2016
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
NE555P NE555PSRG4 NE555PSR NE555DR NE555D NE555DE4 NE555DG4 NE555DRE4 NE555DRG4
NE555PE4 NE555PSRE4 NE555PW NE555PWE4 NE555PWR NE555PWRE4 NE555PWG4 NE555PWRG4