TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 D High-Performance Operation: D D D TIBPAL16L8' J OR W PACKAGE Propagation Delay . . . 15 ns Max Power-Up Clear on Registered Devices (All Register Outputs are Set High, but Voltage Levels at the Output Pins Go Low) Package Options Include Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Ceramic (J) 300-mil DIPs Dependable Texas Instruments Quality and Reliability DEVICE I INPUTS 3-STATE O OUTPUTS REGISTERED Q OUTPUTS I/O PORTS PAL16L8 10 2 0 6 PAL16R4 8 0 4 (3-state buffers) 4 PAL16R6 8 0 6 (3-state buffers) 2 PAL16R8 8 0 8 (3-state buffers) 0 (TOP VIEW) I I I I I I I I I GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC O I/O I/O I/O I/O I/O I/O O I TIBPAL16L8' FK PACKAGE (TOP VIEW) I I I VCC O description These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT-XTM circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board space. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I/O I/O I/O I/O I/O I GND I O I/O I I I I I Pin assignments in operating mode The TIBPAL16' M series is characterized for operation over the full military temperature range of -55C to 125C. IMPORTANT PROGAMMING NOTE: For TIBPAL16L8-15M devices in J, W, or FK packages - For date code 9903A or later device programming, select from either TI Military/16L8-12 or TI commercial TI/16L8-10 on the Manufacturer/Device menu listing in your programming system. IMPORTANT PROGAMMING NOTE: For TIBPAL16R4-15M devices in J, W, or FK packages - For date code 9616A or later device programming, select from either TI Military/16R4-12 or TI commercial TI /16R4-10 on the Manufacturer/Device menu listing in your programming system. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IMPACT is a trademark of Texas Instruments Incorporated. PAL is a registered trademark of Advanced Micro Devices Inc. Copyright (c) 1996 - 2011, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 TIBPAL16R4' J OR W PACKAGE TIBPAL16R4' FK PACKAGE 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC I/O I/O Q Q Q Q I/O I/O OE I I I I I 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 TIBPAL16R6' J OR W PACKAGE TIBPAL16R6' FK PACKAGE 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC I/O Q Q Q Q Q Q I/O OE I I I I I 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I GND 1 (TOP VIEW) I I CLK VCC I/O (TOP VIEW) CLK I I I I I I I I GND TIBPAL16R8' J OR W PACKAGE 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 I I CLK VCC Q 20 2 (TOP VIEW) VCC Q Q Q Q Q Q Q Q OE I I I I I Pin assignments in operating mode 2 POST OFFICE BOX 655303 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I GND 1 Q Q Q Q Q TIBPAL16R8' FK PACKAGE (TOP VIEW) CLK I I I I I I I I GND I/O Q Q Q Q OE I/O I/O 19 OE I/O Q 20 2 * DALLAS, TEXAS 75265 OE Q Q 1 I GND CLK I I I I I I I I GND (TOP VIEW) I I CLK VCC I/O (TOP VIEW) Q Q Q Q Q TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 functional block diagrams (positive logic) TIBPAL16L8' & 32 X 64 I 16 x 10 6 16 16 EN 1 7 O 7 O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 6 TIBPAL16R4' OE CLK EN 2 C1 & 32 X 64 I 16 x 8 I=1 2 1 8 Q 1D 8 Q 8 Q 8 Q 16 4 4 16 EN 1 7 I/O 7 I/O 7 I/O 7 I/O 4 4 denotes fused inputs POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 functional block diagrams (positive logic) TIBPAL16R6' OE CLK EN 2 C1 & 32 X 64 I 16 x 8 1 8 I=1 2 Q 1D 8 Q 8 Q 8 Q 8 Q 8 Q 16 6 2 16 EN 1 7 I/O I/O 7 2 6 TIBPAL16R8' OE CLK EN 2 C1 & 32 X 64 I 16 x 8 8 8 I=1 2 1 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 16 16 8 denotes fused inputs 4 Q 1D POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 TIBPAL16L8-15M logic diagram (positive logic) I 1 First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 Increment 0 4 8 12 16 20 24 28 0 32 64 96 128 160 192 224 31 19 256 288 320 352 384 416 448 480 18 512 544 576 608 640 672 704 736 17 768 800 832 864 896 928 960 992 16 1024 1056 1088 1120 1152 1184 1216 1248 15 1280 1312 1344 1376 1408 1440 1472 1504 14 1536 1568 1600 1632 1664 1696 1728 1760 13 1792 1824 1856 1888 1920 1952 1984 2016 12 11 O I/O I/O I/O I/O I/O I/O O I Fuse number = First fuse number + Increment POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 TIBPAL16R4-15M logic diagram (positive logic) CLK 1 First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 Increment 0 4 8 12 16 20 24 28 19 256 288 320 352 384 416 448 480 18 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 17 I/O I/O Q C1 16 Q C1 15 Q C1 14 Q C1 1536 1568 1600 1632 1664 1696 1728 1760 13 1792 1824 1856 1888 1920 1952 1984 2016 12 11 Fuse number = First fuse number + Increment 6 31 0 32 64 96 128 160 192 224 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 I/O I/O OE TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 TIBPAL16R6-15M logic diagram (positive logic) CLK 1 First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 Increment 0 4 8 12 16 20 24 28 31 0 32 64 96 128 160 192 224 19 256 288 320 352 384 416 448 480 I=1 1D 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 1536 1568 1600 1632 1664 1696 1728 1760 I=1 1D 18 I/O Q C1 17 Q C1 16 Q C1 15 Q C1 14 Q C1 13 Q C1 1792 1824 1856 1888 1920 1952 1984 2016 12 11 Fuse number = First fuse number + Increment POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 I/O OE 7 TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 TIBPAL16R8-15M logic diagram (positive logic) CLK 1 First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 Increment 0 4 8 12 16 20 24 31 I=1 1D 256 288 320 352 384 416 448 480 I=1 1D 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 1536 1568 1600 1632 1664 1696 1728 1760 I=1 1D 1792 1824 1856 1888 1920 1952 1984 2016 I=1 1D 19 Q C1 18 Q C1 17 Q C1 16 Q C1 15 Q C1 14 Q C1 13 Q C1 12 Q C1 11 Fuse number = First fuse number + Increment 8 28 0 32 64 96 128 160 192 224 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OE TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: These ratings apply except for programming pins during a programming cycle. recommended operating conditions MIN NOM MAX UNIT 4.5 5 5.5 V 5.5 V VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current -2 mA IOL Low-level output current 12 mA fclock Clock frequency 50 MHz 2 0 tw duration clock (see Note 2) Pulse duration, tsu Setup time, input or feedback before clock th Hold time, input or feedback after clock TA Operating free-air temperature High 9 Low 10 ns 15 ns 0 ns -55 25 125 C NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are only for clock high or low, but not for both simultaneously. electrical characteristics over recommended operating free-air temperature range PARAMETER TIBPAL16R4-15M TEST CONDITIONS MIN TYP 2.4 3.3 MAX VIK VCC = 4.5 V, II = - 18 mA VOH VCC = 4.5 V, IOH = - 2 mA VOL VCC = 4.5 V, IOL = 12 mA VCC = 5 5.5 5V V, VO = 2.7 27V 5V VCC = 5 5.5 V, 04V VO = 0.4 VCC = 5 5.5 5V V, VI = 5.5 55V VCC = 5.5 V, VI = 2.7 V 100 IIL VCC = 5.5 V, VI = 0.4 V -0.25 mA IOS VCC = 5.5 V, VO = 0.5 V -250 mA ICC VCC = 5.5 V, VI = 0, 220 mA IOZH IOZL II Outputs I/O ports Outputs I/O ports Pin 1, 11 All others -1.5 UNIT 0.35 I/O ports V 0.5 20 100 -20 -250 0.2 0.1 Pin 1, 11 IIH V V A A A A mA 50 All others A 25 -30 Outputs open 170 All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set V at 0.5 V to avoid O test equipment degradation. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 electrical characteristics over recommended operating free-air temperature range TIBPAL16L8-15M PARAMETER VIK VCC = 4.5 V, II = - 18 mA VOH VCC = 4.5 V, IOH = - 2 mA VOL VCC = 4.5 V, IOL = 12 mA 5V VCC = 5 5.5 V, 27V VO = 2.7 VCC = 5 5.5 5V V, VO = 0.4 04V VCC = 5 5.5 5V V, VI = 5.5 55V IOZH IOZL II IIH Outputs I/O ports Outputs I/O ports Pin 1, 11 All others TIBPAL16R6-15M TEST CONDITIONS TIBPAL16R8-15M MIN TYP 2.4 3.3 20 -20 -250 0.2 0.1 Pin 1, 11 50 I/O ports 100 VCC = 5.5 V, VI = 2.7 V I/O ports V A A A A mA A 20 VCC = 5 5.5 5V V, VI = 0.4 04V IOS VCC = 5.5 V, VO = 0.5 V ICC VCC = 5.5 V, VI = 0, All others V V 0.5 100 All others IIL MAX -1.5 0.35 UNIT -0.25 -0.2 -30 Outputs open 170 mA -250 mA 220 mA All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set V at 0.5 V to avoid O test equipment degradation. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) FROM (INPUT) TO (OUTPUT) tpd I, I/O O, I/O tpd CLK Q ten OE Q PARAMETER TYP MAX 8 15 ns R1 = 390 , 7 12 ns R2 = 750 , 8 12 ns See Figure 1 TEST CONDITIONS fmax MIN 50 UNIT MHz tdis OE Q 7 12 ns ten I, I/O O, I/O 8 15 ns tdis I, I/O O, I/O 8 15 ns All typical values are at VCC = 5 V, TA = 25C. Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be calculated accordingly. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. The TIBPAL16R4-15M with date codes prior to 9616A must be programmed according to programming algorithms/specifications corresponding to the TIBPAL16R4-12C. The TIBPAL16R4-15M with date code 9616A or newer must be programmed according to programming algorithms/specifications corresponding to the TIBPAL16R4-10C. Regardless of date code, the TIBPAL16L8-15M, TIBPAL16R6-15M, and TIBPAL16R8-15M must be programmed according to programming algorithms/specifications corresponding to the TIBPAL16L8-12C, TIBPAL16R6-12C, and TIBPAL16R8-12C, respectively. Failure to do so may damage the devices. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. Table 1. Programming Reference Table (see Note 3) DESC SMD NUMBER DEVICE FAMILY/PINOUT CODE TIBPAL16L8-15MJB 5962-8515509RA 9A/17 TIBPAL16L8-15MFKB 5962-85155092A 9A/717 TIBPAL16L8-15MWB 5962-8515509SA 9A/17 TIBPAL16R4-15MJB 5962-8515512RA A1/24 TIBPAL16R4-15MFKB 5962-85155122A 0A1/724 TIBPAL16R4-15MWB 5962-8515512SA A1/24 TIBPAL16R6-15MJB 5962-8515511RA 9A/24 TIBPAL16R6-15MFKB 5962-85155112A 9A/724 TIBPAL16R6-15MWB 5962-8515511SA 9A/24 TIBPAL16R8-15MJB 5962-8515510RA 9A/24 TIBPAL16R8-15MFKB 5962-85155102A 9A/724 TIBPAL16R8-15MWB 5962-8515510SA 9A/24 NOTE 3: Programming information for TIBPAL16R4-15M with date codes 9616A or newer. Programming information for TIBPAL16L8-15M, TIBPAL16R6-15M, and TIBPAL16R8-15M regardless of date code. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TIBPAL16L8-15M is Not Recommended for New Designs TIBPAL16L8-15M, TIBPAL16R4-15M HIGH-PERFORMANCE IMPACTTM PAL(R) CIRCUITS SRPS018B - D3338, JANUARY 1986 - REVISED NOVEMBER 2011 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 0 0 1.5 V 3V 1.5 V tpd tpd 1.5 V VOH 1.5 V VOL tpd tpd 1.5 V 3V Low-Level Pulse 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS 0 Out-of-Phase Output (see Note D) 0 tw VOLTAGE WAVEFORMS SETUP AND HOLD TIMES In-Phase Output 1.5 V 3V 1.5 V 1.5 V Input 1.5 V th tsu Data Input 3V High-Level Pulse VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Control (low-level enabling) 3V 1.5 V 0 ten Waveform 1 S1 Closed (see Note B) 1.5 V tdis 1.5 V tdis ten Waveform 2 S1 Open (see Note B) 3.3 V VOL + 0.5 V VOL VOH 1.5 V VOH - 0.5 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR 10 MHz, tr and tf 2 ns, duty cycle = 50%. D. When measuring propagation delay times of 3- state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 1. Load Circuit and Voltage Waveforms 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) 5962-85155092A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596285155092A TIBPAL16 L8-15MFKB 5962-8515509RA NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515509RA TIBPAL16L8-15M JB 5962-8515509SA NRND CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515509SA TIBPAL16L8-15M WB 5962-85155102A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 596285155102A TIBPAL16 R8-15MFKB 5962-8515510RA OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 5962-8515510SA OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 5962-85155112A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 5962-8515511RA OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 5962-8515511SA OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 5962-85155122A ACTIVE LCCC FK 20 1 TBD Call TI Call TI -55 to 125 596285155122A TIBPAL16 R4-15MFKB 5962-8515512RA ACTIVE CDIP J 20 1 TBD Call TI Call TI -55 to 125 5962-8515512RA TIBPAL16R4-15M JB 5962-8515512SA ACTIVE CFP W 20 1 TBD Call TI Call TI -55 to 125 5962-8515512SA TIBPAL16R4-15M WB TIBPAL16L8-15MFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596285155092A TIBPAL16 L8-15MFKB TIBPAL16L8-15MJ NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 TIBPAL16L8-15M J Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Sep-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) TIBPAL16L8-15MJB NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515509RA TIBPAL16L8-15M JB TIBPAL16L8-15MWB NRND CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515509SA TIBPAL16L8-15M WB TIBPAL16R4-15MFKB NRND LCCC FK 20 1 TBD Call TI Call TI -55 to 125 596285155122A TIBPAL16 R4-15MFKB TIBPAL16R4-15MJB NRND CDIP J 20 1 TBD Call TI Call TI -55 to 125 5962-8515512RA TIBPAL16R4-15M JB TIBPAL16R4-15MWB NRND CFP W 20 1 TBD Call TI Call TI -55 to 125 5962-8515512SA TIBPAL16R4-15M WB TIBPAL16R6-15MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 596285155112A TIBPAL16 R6-15MFKB TIBPAL16R6-15MJ OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 TIBPAL16R6-15M J TIBPAL16R6-15MJB OBSOLETE CDIP J 20 TBD A42 N / A for Pkg Type -55 to 125 5962-8515511RA TIBPAL16R6-15M JB TIBPAL16R6-15MWB OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 5962-8515511SA TIBPAL16R6-15M WB TIBPAL16R8-15MFKB OBSOLETE LCCC FK 20 TBD POST-PLATE N / A for Pkg Type -55 to 125 596285155102A TIBPAL16 R8-15MFKB TIBPAL16R8-15MJB OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 5962-8515510RA TIBPAL16R8-15M JB TIBPAL16R8-15MWB OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 5962-8515510SA TIBPAL16R8-15M WB Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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