TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DHigh-Performance Operation:
Propagation Delay . . . 15 ns Max
DPower-Up Clear on Registered Devices (All
Register Outputs are Set High, but Voltage
Levels at the Output Pins Go Low)
DPackage Options Include Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) 300-mil DIPs
DDependable Texas Instruments Quality and
Reliability
DEVICE I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORTS
PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT-X™ circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
The TIBPAL16’ M series is characterized for
operation over the full military temperature range
of −55°C to 125°C.
IMPORTANT PROGAMMING NOTE: For TIBPAL16L8−15M devices in J, W, or FK packages − For date code
9903A or later device programming, select from either TI Military/16L8−12 or TI commercial TI/16L8−10 on
the Manufacturer/Device menu listing in your programming system.
IMPORTANT PROGAMMING NOTE: For TIBPAL16R4−15M devices in J, W, or FK packages − For date code
9616A or later device programming, select from either TI Military/16R4−12 or TI commercial TI /16R4−10 on
the Manufacturer/Device menu listing in your programming system.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1996 − 2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
I
I
I
I
I
I
I
I
GND
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8’
J OR W PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
TIBPAL16L8’
FK PACKAGE
(TOP VIEW)
I
I
I
O
I/O O
I
GND
I
VCC
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
(TOP VIEW)
TIBPAL16R4’
J OR W PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
(TOP VIEW)
TIBPAL16R6’
J OR W PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
(TOP VIEW)
TIBPAL16R8’
J OR W PACKAGE
I
I
CLK
I/O
I/O I/O
I
GND
VCC
OE
3212019
910111213
4
5
6
7
8
18
17
16
15
14
I/O
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R4’
FK PACKAGE
I
I
CLK
I/O
QI/O
I
GND
VCC
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
OE
TIBPAL16R6’
FK PACKAGE
I
I
CLK
Q
QQ
I
GND
VCC
OE
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R8’
FK PACKAGE
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams (positive logic)
TIBPAL16L8’
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN ≥1
&
32 X 64
10 16
166
7
7
7
7
7
7
7
7
6
16 x
denotes fused inputs
TIBPAL16R4’
Q
I/O
I/O
I/O
I/O
I
EN
816
164
7
7
7
8
8
8
7
4
16 x
≥1
&
32 X 64
≥1
8
Q
Q
Q
4
1D
I = 1 2
CLK C1
EN 2
OE
4
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams (positive logic)
TIBPAL16R6’
Q
I/O
I/O
I
EN
816
162
7
8
8
8
7
2
16 x
≥1
&
32 X 64
≥1
8
Q
Q
Q
6
1D
I = 1 2
CLK C1
EN 2
OE
6
8Q
8Q
denotes fused inputs
TIBPAL16R8’
Q
I816
168
8
8
8
8
16 x
8
Q
Q
Q
1D
I = 1 2
CLK C1
EN 2
8Q
8Q
&
32 X 64
≥1
OE
8Q
8Q
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
O
12
I
11
Increment
I1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16R4-15M logic diagram (positive logic)
04812 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
I/O
18
Q
17
Q
16
Q
15
Q
14
I/O
13
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
OE
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16R6-15M logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
Q
17
Q
16
Q
15
Q
14
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
OE
Q
18
C1
1D
I = 1
Q
13
C1
1D
I = 1
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16R8-15M logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
Q
17
Q
16
Q
15
Q
14
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
OE
Q
18
C1
1D
I = 1
Q
13
C1
1D
I = 1
Q
19
C1
1D
I = 1
Q
12
C1
1D
I = 1
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −2 mA
IOL Low-level output current 12 mA
fclock Clock frequency 0 50 MHz
t
Pulse duration clock (see Note 2)
High 9
ns
twPulse duration, clock (see Note 2) Low 10 ns
tsu Setup time, input or feedback before clock↑15 ns
thHold time, input or feedback after clock↑0 ns
TAOperating free-air temperature −55 25 125 °C
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are
only for clock high or low, but not for both simultaneously.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
TIBPAL16R4-15M
UNIT
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −1.5 V
VOH VCC = 4.5 V, IOH = −2 mA 2.4 3.3 V
VOL VCC = 4.5 V, IOL = 12 mA 0.35 0.5 V
I
Outputs
V 55 V
V 27 V
20
A
IOZH I/O ports VCC = 5.5 V, VO = 2.7 V 100 μA
I
Outputs
V 55 V
V 04 V
−20
A
IOZL I/O ports VCC = 5.5 V, VO = 0.4 V −250 μA
I
Pin 1, 11
V 55 V
V 55 V
0.2
mA
IIAll others VCC = 5.5 V, VI = 5.5 V 0.1 mA
Pin 1, 11 50
IIH I/O ports VCC = 5.5 V, VI = 2.7 V 100 μA
IIH
All others
VCC 5.5 V,
VI 2.7 V
25
μA
IIL VCC = 5.5 V, VI = 0.4 V −0.25 mA
IOS§VCC = 5.5 V, VO = 0.5 V −30 −250 mA
ICC VCC = 5.5 V, VI = 0, Outputs open 170 220 mA
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
TIBPAL16L8-15M
PARAMETER
TEST CONDITIONS
TIBPAL16R6-15M
UNIT
PARAMETER TEST CONDITIONS TIBPAL16R8-15M UNIT
MIN TYP†MAX
VIK VCC = 4.5 V, II = −18 mA −1.5 V
VOH VCC = 4.5 V, IOH = −2 mA 2.4 3.3 V
VOL VCC = 4.5 V, IOL = 12 mA 0.35 0.5 V
I
Outputs
V 55 V
V 27 V
20
A
IOZH I/O ports VCC = 5.5 V, VO = 2.7 V 100 μA
I
Outputs
V 55 V
V 04 V
−20
A
IOZL I/O ports VCC = 5.5 V, VO = 0.4 V −250 μA
I
Pin 1, 11
V 55 V
V 55 V
0.2
mA
IIAll others VCC = 5.5 V, VI = 5.5 V 0.1 mA
Pin 1, 11 50
IIH I/O ports VCC = 5.5 V, VI = 2.7 V 100 μA
IIH
All others
VCC 5.5 V,
VI 2.7 V
20
μA
I
I/O ports
V 55 V
V 04 V
−0.25
mA
IIL All others VCC = 5.5 V, VI = 0.4 V −0.2 mA
IOS‡VCC = 5.5 V, VO = 0.5 V −30 −250 mA
ICC VCC = 5.5 V, VI = 0, Outputs open 170 220 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITIONS MIN TYP†MAX UNIT
fmax§50 MHz
tpd I, I/O O, I/O 8 15 ns
tpd CLK↑QR1 = 390 Ω, 7 12 ns
ten OE↓QR2 = 750 Ω, 8 12 ns
tdis OE↑QSee Figure 1 7 12 ns
ten I, I/O O, I/O 8 15 ns
tdis I, I/O O, I/O 8 15 ns
†All typical values are at VCC = 5 V, TA = 25°C.
§Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be calculated
accordingly.
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
The TIBPAL16R4-15M with date codes prior to 9616A must be programmed according to programming
algorithms/specifications corresponding to the TIBPAL16R4-12C. The TIBPAL16R4-15M with date code 9616A
or newer must be programmed according to programming algorithms/specifications corresponding to the
TIBPAL16R4-10C.
Regardless of date code, the TIBPAL16L8-15M, TIBPAL16R6-15M, and TIBPAL16R8-15M must be
programmed according to programming algorithms/specifications corresponding to the TIBPAL16L8-12C,
TIBPAL16R6-12C, and TIBPAL16R8-12C, respectively. Failure to do so may damage the devices.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
Table 1. Programming Reference Table
(see Note 3)
DEVICE DESC SMD
NUMBER
FAMILY/PINOUT
CODE
TIBPAL16L8-15MJB 5962-8515509RA 9A/17
TIBPAL16L8-15MFKB 5962-85155092A 9A/717
TIBPAL16L8-15MWB 5962-8515509SA 9A/17
TIBPAL16R4-15MJB 5962-8515512RA A1/24
TIBPAL16R4-15MFKB 5962-85155122A 0A1/724
TIBPAL16R4-15MWB 5962-8515512SA A1/24
TIBPAL16R6-15MJB 5962-8515511RA 9A/24
TIBPAL16R6-15MFKB 5962-85155112A 9A/724
TIBPAL16R6-15MWB 5962-8515511SA 9A/24
TIBPAL16R8-15MJB 5962-8515510RA 9A/24
TIBPAL16R8-15MFKB 5962-85155102A 9A/724
TIBPAL16R8-15MWB 5962-8515510SA 9A/24
NOTE 3: Programming information for TIBPAL16R4-15M with date codes
9616A or newer. Programming information for TIBPAL16L8-15M,
TIBPAL16R6-15M, and TIBPAL16R8-15M regardless of date code.
TIBPAL16L8-15M is Not Recommended for New Designs
TIBPAL16L8-15M, TIBPAL16R4-15M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS018B − D3338, JANUARY 1986 − REVISED NOVEMBER 2011
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tsu
S1
From Output
Under Test
Test
Point
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
1.5 V
1.5 V
th
1.5 V
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note D)
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
3 V
0
3 V
0
1.5 V 1.5 V
1.5 V 1.5 V
tw
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
1.5 V 1.5 V
3 V
0
≈ 3.3 V
VOL
VOH
VOH − 0.5 V
≈ 0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
R1
3 V
3 V
0
0
VOL + 0.5 V
5 V
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3- state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 1. Load Circuit and Voltage Waveforms
TIBPAL16L8-15M is Not Recommended for New Designs
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-85155092A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155092A
TIBPAL16
L8-15MFKB
5962-8515509RA NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515509RA
TIBPAL16L8-15M
JB
5962-8515509SA NRND CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515509SA
TIBPAL16L8-15M
WB
5962-85155102A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 5962-
85155102A
TIBPAL16
R8-15MFKB
5962-8515510RA OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125
5962-8515510SA OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125
5962-85155112A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
5962-8515511RA OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125
5962-8515511SA OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125
5962-85155122A ACTIVE LCCC FK 20 1 TBD Call TI Call TI -55 to 125 5962-
85155122A
TIBPAL16
R4-15MFKB
5962-8515512RA ACTIVE CDIP J 20 1 TBD Call TI Call TI -55 to 125 5962-8515512RA
TIBPAL16R4-15M
JB
5962-8515512SA ACTIVE CFP W 20 1 TBD Call TI Call TI -55 to 125 5962-8515512SA
TIBPAL16R4-15M
WB
TIBPAL16L8-15MFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155092A
TIBPAL16
L8-15MFKB
TIBPAL16L8-15MJ NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 TIBPAL16L8-15M
J
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TIBPAL16L8-15MJB NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515509RA
TIBPAL16L8-15M
JB
TIBPAL16L8-15MWB NRND CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515509SA
TIBPAL16L8-15M
WB
TIBPAL16R4-15MFKB NRND LCCC FK 20 1 TBD Call TI Call TI -55 to 125 5962-
85155122A
TIBPAL16
R4-15MFKB
TIBPAL16R4-15MJB NRND CDIP J 20 1 TBD Call TI Call TI -55 to 125 5962-8515512RA
TIBPAL16R4-15M
JB
TIBPAL16R4-15MWB NRND CFP W 20 1 TBD Call TI Call TI -55 to 125 5962-8515512SA
TIBPAL16R4-15M
WB
TIBPAL16R6-15MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 5962-
85155112A
TIBPAL16
R6-15MFKB
TIBPAL16R6-15MJ OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 TIBPAL16R6-15M
J
TIBPAL16R6-15MJB OBSOLETE CDIP J 20 TBD A42 N / A for Pkg Type -55 to 125 5962-8515511RA
TIBPAL16R6-15M
JB
TIBPAL16R6-15MWB OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 5962-8515511SA
TIBPAL16R6-15M
WB
TIBPAL16R8-15MFKB OBSOLETE LCCC FK 20 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155102A
TIBPAL16
R8-15MFKB
TIBPAL16R8-15MJB OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 5962-8515510RA
TIBPAL16R8-15M
JB
TIBPAL16R8-15MWB OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 5962-8515510SA
TIBPAL16R8-15M
WB
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.