WKSG) MME 790 DOIiSGITAL MULTIMETER LOGIC GENERAL DESCAIPTION MMP 136 is a digital multimeter logic integrated cir- cuit fabricated in PMOS enhancement-depletion aluminium gate technology. The circuit consists of 2 internal oscilators (one for multiplexing, one for counting], a 4 decades BCD counter, an output mul- tiplexer which cen drive a LED or LCD 3 3/4 digit dis- play and an autoranging and dual-slope A/D conver- sion controi logic. MMP 1380 is supplied in 28-lead dual-in-line plastic packages. FEATURES @ 3 9/4 digit digital multimeter logic (max. 599.3) autoranging @ multiplexed BCD output @ dual-slope integration @ overrange indicated (blinking) @ low-power dissipation @ CMOS compatibility APPLICATIONS @ digital multimeter @ decade counter ABSOLUTE MAXIMUM RATINGS Voo Supply voltage -20 to +03 V Vv; Voltage between any pin and ground -20 to "ae : 2 W=O35V: = cs ieheeit aribidne ternperative > Otc +70 *C Tstg Storage temperature -55 to +125 C PIN CONNECTIONS ss O at ogg 27,901 a %[) 02 cr 2S} 03 F258, % LJ D4 BI ZBL] GA B3 A] OB 62 TLIC Al 0] QD BO pop & Oo BLIK F3 Ue Yeo si Gp 6L) 4 SU ISL} S2 PIN |SYMBOL PIN FUNCTION PIN |SYMBOL PIN FUNCTION d Ves Supply voltage 15 Se Dual-slope contrul output 2 DF LCD frequency output 16 S, i 3 CL External clock input 1a Vpo Supply voltage 4 CR Counting clock input 18 K Analog input 5 Fos Range select input 19 P Polarity output 6 B, Measuring range output 20 Qp 8CD output 7 B a 21 Ge is 8 B. "i 22 Os = 9 F, Range select input 23 Qa * 10 Bo Measuring range output 24 D, Digit selection output 11 Ba . 25 Bs . 12 Fa Range select input 26 Ds 13 S, Dual-slope contro! output 27 D, 14 S3 e 28 M Scan oscilator input ee MMP 1950 STATIC ELECTRICAL CHARACTERISTICS T,= 25C; unless otherwise specified) VALUES , PARAMETER TEST CONDITIONS UNIT \ MIN. MAX. Vopo Supply voltage reference Oo oO V Vss Supply voltage Voo =OV 8 14 Vv Vit K input low voltage Von=OV 0 Vss7 Vv fy = 30 kHz Vin K input high voltage Von = OV Vgs-e@ Ves Vv fy = 3O kHz Vic Input low voltage Vop=OV 0 Vss-7 Vv {except K input) fy = 3O kHz Vin Input high valtage Vop= OV Ve5-O.5 Vss Vv fexcept K input) fy = GO kHz Vor Output low voltage lp = 25 pA 0 4 Vv (Gy, Gg. Ge, Gp, D,, Ds, D3, Dz, P outputs) Vou Output high voltage lo = 200 pA Vg571 Ves Vv (Q,, Gg, Ge, Gp, D;, Dz, D3, D,, P outputs) Vat Output low voltage Ip = AOA 0 4 Vv (By, By, Ba B3.B4 $1, S2, S3, S, outputs) Vou Output high voltage ip = 200 pA Ves5-1 Vss Vv (By B;, Ba, Bs, Bg, Si, Ss, S3, Sz outputs) Va DF output low voltage lp = 50 pA 0 1 Voy OF output high voltage Ip = 50 pA Vss-1 Vss Py Power dissipation Vpp-Vss = 12 V 70 mw open outputs DYNAMIC ELECTRICAL CHARACTERISTICS (Ta = 25C, unless otherwise specified) VALUES PARAMETER TEST CONDITIONS UNIT MIN. MAX. ty Defay time between C, = 200 pF BS K input and S outputs R_ = 10 Mohm fry Counter oscilator frequency Voo-Vss= -12 V 0 100 KHz Fr Counting frequency stability Vsg = 1241 V #3 %o/V Fa Counting frequency stability Ves = 12V +0.8 %o/C To = Oto 70C fra Multiplexing frequency Vss=12V oO 800 HzMMP 490 src mie Mat too MODES OF OPERATION FUNCTIONAL DESCRIPTION GENERAL \og =0(-12v) Yog=0V1-i2V) The circet comorises the logic functions for a digital multimeter, on the basis of dual-slope method, with ; EXTERNAL aucomatic range switching. By means of four measuring-range\ Outputs, small units with 3 3/4 digits and cl CLOCK ct four et ranges can be ot see additional exterval Components for the range selection. By _p~__ switching the logic range, up to eight different measuring ranges can be switched automatically: however, GENERATOR LO decoding of these ranges must be done externally. The maximum display is 6000. 6000 steps mean a relatively smal! analog circuit requirement, however, CR COUNTER that permit the measuring of voltages between 100 yA and GOO V in four measuring ranges. When the ciLatee Tins highest Measuring range is exceeded, the value 6000 is displayed. Through an additional blinking circuit, [G-anF ee which does not require an additional connection pin, the user is made aware of the measuring range being ; COUNTER rr exceeded OSCILLATOR R,~500.0. FUNCTION o I The block diagram shows a simple unit with four automatically selected measuring ranges. The external Veg =12V(0V) = Meg 2121 0V) wialog partion consists of only the analog amplifiers, reterence voltage source, and the analog switches for the measunng phase and range switching * Input Cl oper "leaped FR permeen re bay Vopr OVI-12 if MULTIPLEX BLOCK DIAGRAM NT GSURLATOR fe: EE -400Hz To C2-0,pF Ta fing counter [ . . L. Ls Lai : =12V(0V fh Pf | es=12V(0V) +f Se ee [ DISPLAY INTERFACE DFS Or p Ore D3,D, Oa? py Oc} Op MOS-LSI A ' Vo = 0V (42) Yoo* | tii ry" MULTIPLEXER pal r{4x4BIT MEMORY ; EXTERNAL - MULTIPLEX ur i PTT TH CLOCK GENERATOR OSCILLATOR [-> _M | _[OsciLLaTor || 109 101 102 103 ae TT") Bcd COUNTER 7 CR OSCILLATOR Vsg =12Vi0V) i 1OHz - i00KHz [500 5000 & : i * Only for testing purposes andR, O K ANALOG CONTROL LOGIC AUTORANGING Fas 3 , i B Sap Sag 9534 P O fiztate ro 1 |Por UREF MEASURING RANGE | ___ 71! So00y 000 Kn 7000 1000/0 xX 7000 5.000V 5000 Ka DUAL SLOPE 5000 S000 Ka A/D CONVERTER 5000V 5000Ka.ae Reeeo iviivir= Ph ] wine Contre! aed generation of tle value measured is done by the MMP 190. The main portion of the circuit 15 made up of a four decade BCO counter which is driven by a counting oscillator contained on the ciip, together with an externally connected RC-circuit. The counting oscillator may be replaced by con- ing a clock generator. At particular periods of timing, the cantents of the counter is transferred into the 4 x 4-bit memory by means of @ st se derived from the K-input. The information contained in the memory is transfered by means of a multiplexer in a bit-paralle! mody to outputs Q, through Gp. whereby outputs 0, through O, indicate the just transferred decimal pl.jce (Q, = LSB, Gp = MSS: D, = units digit, 0, = thousands digit, active condition = high level). To ensure rehable driving of the memories in the display interface, e.g. liquid crystal display, the correct BCD-infor- mation is maintained at the G outputs until after the end of the active condition of the D-outputs. The indi- cation of the decimal position occcurs in the sequence 1-3-2-4, to avoid flickering when the display units are driven directly. For the generation of scan-frequency for the multiplexer a second oscillator has been provided on the MMP 180. Replacement by an external clock generator is possible but should be used only for testing pur- poses The display frequency OF of about 50 Hz required by liquid crystal displays is also derived from the multiplex oscillator. & Sequelit ote oi MEASURING SEQUENCE The measuring sequence is also controlled by the BCD-counter, via measuring-phase outputs S, through S, (compare timing diagram and principle circuit diagram). EXTERNAL ANALOG crreculitT TIMING DIAGRAM PHASE I, INTEGRATION OF TRE MEASURING VOLTAGE The measuring cycle starts at counter position 7000; at this point output S, becomes high, whereby the input voltage is switched to the integrator until counter position OOOO has been reached. At the moment when the counter jumps from 9999 to OOOO, the signal level of the comparator (input k) is stored. At this moment phase Il is started. PHASE i, INTEGRATION OF REFERENCE VOLTAGE Depending on the condition of the comparator, only S2 or S, is activated whereby the reference voltage is switched to the integrator with a polarity opposite to the previously applied input voltage. With this refe- rence voltage the integrator is reduced until the sensitivity thresnold of the Comparator has been rea- ched and the signal condition at the input K changes. This change of signal activates S3. The number of counting pulses between counter position OOOO and X is praportional to the measuring voltage. Through the low-high transition of S; the counter contents is loaded into the display memory; at this point of time phase Ill is started. PHASE Ill, ZERO REGULATION In this process the input of the AD-converter is set to zero and the resulting error voltage is stored in ca- pacitor Cr. An error voltage is compensated hy a feedback loop. The duration of phase | is determined by the counter frequency and the fixed number of 3O00 counting steps. For a SO KHz counting frequency, phase | lasts exactly 100 ms. The longer the integration time, the better the suppression of noise voltages superimposed on the measuring signal. If the duration of the noise voltage period iS contained in the integration time @s an even number, this noise is suppressed completely. As noise voltages can be ex- pected to occur especially at line frequency, 100 ms integration time constitute a favourable compromise between integration time and noise voltage suppression. The duration of phase Il is determined by the level of the measuring voltage. If the measuring voltage is too large, the integrator cannot be discharged during the 6000 counting steps available as a maximum: consequently, at sten GOOO phase Ill is initiated Hence the integrator will have assumed the correct starting position at the begining of phase which follows for excessive measuring voltages the disolay is therefore 6000. In order to bring the incorrectness of this display to the user's attention, the pseudo-decade HHHH is made active at the outputs, synchro- nously to signal S,; thereby a blinking effect of approx. 3 Hz is obtained. AUTOMATIC RANGE SWITCHING The measuring range is changed whenever the measuring result has been > 5500 or < 500. -ar n > 5500 the range counter (3 bit up/down counter) is stepped by une count, jor n < 500 stepped down by,One, whe- reby the counter its blocked on the lowest or highest digit position, respectively. The range se'ection can be controlled through control inputs F,, Fog and Fs. : TRUTH TABLE Nr x= Fa ae Laer eee xryx elcecile cir leicieris = a ZL er LL cl CLL oye cl circ ie XLprjpL lol Lye] Llc jeer [Lleol cc ycycis jcc yz =x = ese |2e Ea Oe Se ie eee eile i ele erie ie lees 1 L L L L L L L L H H H H H H H H x L H xXMMP 190 When the control inputs F,, Fos and fF, are in a jow condition, the Counter can move within the lower 5 positions up or down. Should it be in a higher position, it can step only downward until the free zone has been reached; the decoder produces correct values also for counter positions outsside the free zone so that the system adjusts itself. By an H-signal at input F, the correlation between the counter position and decoder output can be chan- ged. Thereby it is made possible to perform range setting for the voltage and resistance ranges and the control of the decimal point in a simple unit with four measuring ranges without external decoding. Input F3 is used to set the counter to the highest level. The highest measuring range is activated and maintained as long as Fz is kept at a high level. For example, thereby the range 500.QV is activated, which is an advan- tage for quick overview-measurements. A high level at input Fag has the effect that the outputs of the ranae counter are directly transferred ta the outputs 8 different ranges are then available which must be decoded by external means. In the case of Fag = H, the frea zone of the counter is expanded to the full counting range; the prevention of running wild is maintained. THE TRUTH TABLE FOR SETTING THE MEASURING RANGES SHOULD BE UNDERSTOOD AS FOLLOWS: The range outputs Bp...B, are intended to directly drive the five possible decimal places of a 4 decade dis- play. Simple units with 4 measuring ranges have been taken into consideration. For example, in the case of voltages the measuring ranges with F, = low are: Bo 5000 Vv B; 5.000 V Bs 50.00 Vv Bs 500.0 v The total measuring range therefore comprises 0.1 mV through 599.9 V. For resistance measuring, ho- wever, F, must be high: B, 5.000 kohm Bs 50.00 kohm Bs 500.0 kohm Ba 5000. kohm The total measuring therefore comprises 1 ohm through 5.999 Mohm. Hence, using control input F,, a choice of one of the two groups Is basically possible. / The range outputs are also intended to directly drive the appropriate four selection relays without additio- nal logic gating. When the automatic range selection (e.g. after turn-on) has not yet found the correct range, some measuring range expected to be shown anyway. This side-condition is considered in the truth table of vectors 0...17. os It should be noted, however, that G,, Gz, and GQ, in the truth table are internal outputs of the built-in up- down counter. It is also possible to select one of 5 measuring ranges automatically. To do this, the 4th and the Sth measuring ranges are separated by external gating at F, = low (whereby MB, = 83: Ba and MB; = B,). MB, is measuring range 4, MBs; is measuring range 5. Fos = high causes an extension of all eight possible measuring ranges. The range selected appears at out- puts B, (=Q,), B, (=Q.), and B, GQ.) dual-coded, Hence, vectors 20.27 of the truth table are fixed.