\\\ SPICE Device Model Si4804BDY Vishay Siliconix Dual N-Channel 30-V (D-S) MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70323 08-Dec-02 www.vishay.com 1 SPICE Device Model Si4804BDY Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data VGS(th) VDS = VGS, ID = 250A 1.8 Measured Data Unit Static Gate Threshold Voltage a On-State Drain Current ID(on) a Drain-Source On-State Resistance a Forward Transconductance a Schottky Diode Forward Voltage Dynamic rDS(on) V VDS = 5V, VGS = 10V 261 VGS = 10V, ID = 7.5A 0.018 0.017 A VGS = 4.5V, ID = 6.5A 0.025 0.024 gfs VDS = 15V, ID = 7.5A 19 19 S VSD IS = 1A, VGS = 0V 0.73 0.75 V b Total Gate Charge Qg Gate-Source Charge Qgs VDS = 15V, VGS = 4.5V, ID = 7.5A 7.2 7 2.9 2.9 2.5 Gate-Drain Charge Qgd 2.5 Turn-On Delay Time td(on) 13 9 tr 8 10 11 19 10 9 34 35 Rise Time Turn-Off Delay Time td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDD = 15V, RL = 15 ID 1A, VGEN = 10V, RG = 6 IF = 1.7A, di/dt = 100A/s nC Ns Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70323 08-Dec-02 \\\ SPICE Device Model Si4804BDY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70323 08-Dec-02 www.vishay.com 3