DATA SH EET
Product specification
Supersedes data of November 1994
File under Discrete Semiconductors, SC13b
1997 Jun 20
DISCRETE SEMICONDUCTORS
PHC21025
Complementary enhancement
mode MOS transistors
1997 Jun 20 2
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
FEATURES
High-speed switching
No secondary breakdown
Very low on-resistance.
APPLICATIONS
Motor and actuator driver
Power management
Synchronized rectification.
DESCRIPTION
One N-channel and one P-channel enhancement mode
MOS transistor in an 8-pin plastic SOT96-1 (SO8)
package.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
PINNING - SOT96-1 (SO8)
PIN SYMBOL DESCRIPTION
1s
1
source 1
2g
1
gate 1
3s
2
source 2
4g
2
gate 2
5d
2
drain 2
6d
2
drain 2
7d
1
drain 1
8d
1
drain 1
Fig.1 Simplified outline and symbol.
handbook, halfpage
1
MAM118
14
58
d1
d2
d2
d
2
g
2
s
1
g
1
s
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Per channel
VDS drain-source voltage (DC)
N-channel 30 V
P-channel −−30 V
VSD source-drain diode forward voltage
N-channel IS= 1.25 A 1.2 V
P-channel IS=1.25 A −−1.6 V
VGSO gate-source voltage (DC) open drain −±20 V
VGSth gate-source threshold voltage V
N-channel VDS =V
GS; ID= 1 mA 1 2.8 V
P-channel VDS =V
GS; ID=1mA 12.8 V
IDdrain current (DC)
N-channel 3.5 A
P-channel −−2.3 A
RDSon drain-source on-state resistance
N-channel VGS =10V; I
D= 2.2 A 0.1
P-channel VGS =10 V; ID=1A 0.25
Ptot total power dissipation Ts=80°C2W
1997 Jun 20 3
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. Pulse width and duty cycle limited by maximum junction temperature.
2. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same time.
3. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp
(ambient to tie-point) of 27.5 K/W.
4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp
(ambient to tie-point) of 90 K/W.
5. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with
an Rth a-tp (ambient to tie-point) of 90 K/W.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Per channel
VDS drain-source voltage (DC)
N-channel 30 V
P-channel −−30 V
VGSO gate-source voltage (DC) open drain −±20 V
IDdrain current (DC) Ts80 °C
N-channel 3.5 A
P-channel −−2.3 A
IDM peak drain current note 1
N-channel 14 A
P-channel −−10 A
Ptot total power dissipation Ts=80°C; note 2 2W
T
amb =25°C; note 3 2W
T
amb =25°C; note 4 1W
T
amb =25°C; note 5 1.3 W
Tstg storage temperature 65 +150 °C
Tjoperating junction temperature 150 °C
Source-drain diode
ISsource current (DC) Ts80 °C
N-channel 1.5 A
P-channel −−1.25 A
ISM peak pulsed source current note 1
N-channel 6A
P-channel −−5A
1997 Jun 20 4
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
Fig.2 Power derating curve.
handbook, halfpage
0 200
2.5
0
0.5
1.0
1.5
2.0
MLB836
T ( C)
so
50 100 150
Ptot
(W)
δ= 0.01.
Ts=80°C.
(1) RDSon limitation.
Fig.3 SOAR; N-channel.
handbook, halfpage
MLB833 - 1
10
2
10
11010
V
DS (V)
ID
(A)
1
2
1
10
1
10
2
10
tpT
P
t
tp
T
δ
=
0.1 s
1 ms
DC
(1) tp =
10 µs
δ= 0.01.
Ts=80°C.
(1) RDSon limitation.
Fig.4 SOAR; P-channel.
handbook, halfpage
MBE155
102
10
11010
V
DS (V)
ID
(A)
1
2
1
10
1
10
2
10
tpT
P
t
tp
T
δ=
0.1 s
1 ms
DC
(1) tp =
10 µs
1997 Jun 20 5
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
THERMAL CHARACTERISTICS
CHARACTERISTICS
Tj=25°C unless otherwise specified.
SYMBOL PARAMETER VALUE UNIT
Rth j-s thermal resistance from junction to soldering point 35 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Per channel
V(BR)DSS drain-source breakdown voltage
N-channel VGS = 0; ID=10µA30−−V
P-channel VGS = 0; ID=10 µA30 −−V
V
GSth gate-source threshold voltage
N-channel VGS =V
DS; ID= 1 mA 1 2.8 V
P-channel VGS =V
DS; ID=1mA 1−−2.8 V
IDSS drain-source leakage current
N-channel VGS = 0; VDS =24V −−100 nA
P-channel VGS = 0; VDS =24 V −−−100 nA
IGSS gate leakage current VGS =±20 V; VDS =0
N-channel −−±100 nA
P-channel −−±100 nA
IDon on-state drain current
N-channel VGS =10V; V
DS = 1 V 3.5 −−A
V
GS = 4.5 V; VDS =5V 2 −−A
P-channel VGS =10 V; VDS =1V 2.3 −−A
V
GS =4.5 V; VDS =5V 1−−A
R
DSon drain-source on-state resistance
N-channel VGS = 4.5 V; ID=1A 0.11 0.2
VGS =10V; I
D= 2.2 A 0.08 0.1
P-channel VGS =4.5 V; ID= 0.5 A 0.33 0.4
VGS =10 V; ID=1A 0.22 0.25
yfsforward transfer admittance
N-channel VDS =20V; I
D= 2.2 A 2 4.5 S
P-channel VDS =20 V; ID=1A 1 2 S
C
iss input capacitance
N-channel VGS = 0; VDS = 20 V; f = 1 MHz 250 pF
P-channel VGS = 0; VDS =20 V; f = 1 MHz 250 pF
Coss output capacitance
N-channel VGS = 0; VDS = 20 V; f = 1 MHz 140 pF
P-channel VGS = 0; VDS =20 V; f = 1 MHz 140 pF
1997 Jun 20 6
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
Crss reverse transfer capacitance
N-channel VGS = 0; VDS = 20 V; f = 1 MHz 50 pF
P-channel VGS = 0; VDS =20 V; f = 1 MHz 50 pF
QGtotal gate charge
N-channel VGS =10V; V
DS = 15 V; ID= 2.3 A 10 30 nC
P-channel VGS =10 V; VDS =15 V; ID=2.3 A 10 25 nC
QGS gate-source charge
N-channel VGS =10V; V
DS = 15 V; ID= 2.3 A 1nC
P-channel VGS =10 V; VDS =15 V; ID=2.3 A 1nC
QGD gate-drain charge
N-channel VGS =10V; V
DS = 15 V; ID= 2.3 A 2.5 nC
P-channel VGS =10 V; VDS =15 V; ID=2.3 A 3nC
Switching times
ton turn-on time
N-channel VGS = 0to10V; V
DD =20V;
I
D= 1 A; RL=2015 40 ns
P-channel VGS =0to10 V; VDD =20 V;
ID=1 A; RL=2020 80 ns
toff turn-off time
N-channel VGS =10to0V; V
DD =20V;
I
D= 1 A; RL=2025 140 ns
P-channel VGS =10 to 0 V; VDD =20 V;
ID=1 A; RL=2050 140 ns
Source-drain diode
VSD source-drain diode forward
voltage
N-channel VGD = 0; IS= 1.25 A −−1.2 V
P-channel VGD = 0; IS=1.25 A −−−1.6 V
trr reverse recovery time
N-channel IS= 1.25 A; di/dt = 100 A/µs35 100 ns
P-channel IS=1.25 A; di/dt = 100 A/µs150 200 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1997 Jun 20 7
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
Fig.5 Capacitance as a function of drain-source
voltage; N-channel; typical values.
handbook, halfpage
0
600
400
200
010 20 30
MBE137
C
(pF)
V (V)
DS
Ciss
Coss
Crss
VGS =0.
T
j=25°C.
Fig.6 Capacitance as a function of drain source
voltage; P-channel; typical values.
VGS =0.
T
j=25°C.
handbook, halfpage
0
600
400
200
010 20 30
MBE144
C
(pF)
V (V)
DS
Ciss
Coss
Crss
Fig.7 Output characteristics; typical values;
N-channel.
handbook, halfpage
0 2 10 12
16
12
4
0
8
MBE142
468
V (V)
DS
ID
(A)
V =
GS
10 V 6 V
5 V
4.5 V
4 V
3.5 V
3 V
Tj=25°C.
Fig.8 Output characteristics; typical values;
P-channel.
Tj=25°C.
h
an
db
oo
k
,
h
a
lf
page
0 2 10 12
10
8
6
2
0
4
MBE154
468
V (V)
DS
V =
GS
10 V 7.5 V 6 V
5 V
4.5 V
4 V
3.5 V
3 V
2.5 V
ID
(A)
1997 Jun 20 8
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
Fig.9 Transfer characteristic; typical values;
N-channel.
handbook, halfpage
024 8
16
12
4
0
8
MBE141
6
ID
(A)
V (V)
GS
VDS =10V.
T
j=25°C.
Fig.10 Transfer characteristic; typical values;
P-channel.
VDS =10 V.
Tj=25°C.
handbook, halfpage
024 8
10
8
6
2
0
4
MBE157
6
ID
(A)
V (V)
GS
Fig.11 Gate-source voltage as a function of total
gate charge; N-channel.
handbook, halfpage
024 8
10
0
8
MBE136
6
6
4
2
Q (nC)
g
VGS
(V)
VDD =15V.
I
D= 3.5 A.
Fig.12 Gate-source voltage as a function of total
gate charge; P-channel.
VDD =15 V.
ID=2.3 A.
handbook, halfpage
024 108
10
0
8
MBE145
6
6
4
2
Q (nC)
g
VGS
(V)
1997 Jun 20 9
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
Fig.13 Source current as a function of source-drain
diode forward voltage; N-channel.
VGD =0.
(1) Tj= 150 °C.
(2) Tj=25°C.
(3) Tj=55 °C.
handbook, halfpage
0 0.5 1 1.5
6
2
0
4
MBE159
IS
(A)
SD
V (V)
(1) (2) (3)
Fig.14 Source current as a function of source-drain
diode forward voltage; P-channel.
VGD =0.
(1) Tj= 150 °C.
(2) Tj=25°C.
(3) Tj=55 °C.
handbook, halfpage
0 0.5 1 21.5
6
2
0
4
MBE158
IS
(A)
SD
V (V)
(1) (2) (3)
Fig.15 Drain-source on-state resistance as a
function of gate-source voltage; typical
values; N-channel.
VDS ID×RDSon; Tj=25°C.
(1) ID= 0.1 A.
(2) ID= 0.5 A.
(3) ID=1A.
(4) ID= 2.2 A.
(5) ID= 3.5 A.
(6) ID=7A.
handbook, halfpage
100
(1)(2) (6)
VGS (V)
RDSon
(m)
2468
104
103
102
10
MDA217
(3)(4)(5)
Fig.16 Drain-source on-state resistance as a
function of gate-source voltage; typical
values; P-channel.
VDS ≥−I
D×R
DSon; Tj=25°C.
(1) ID=0.1 A.
(2) ID=0.5 A.
(3) ID=1A. (4) ID=2.3 A.
(5) ID=4.5 A.
handbook, halfpage
100 VGS (V)
RDSon
(m)
2468
104
103
102
MDA165
(1) (4) (5)(2)(3)
1997 Jun 20 10
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
Fig.17 Temperature coefficient of gate-source
threshold voltage; N and P-channels.
handbook, halfpage
0.6
0.7
0.8
0.9
1.0
1.2
1.1
0 50 100 15050
k
T ( C)
jo
MBE138
Typical VGSth at ID= 1 mA; VDS =VGS =V
GSth.
kVGSth at Tj
VGSth at 25°C
--------------------------------------
=
Fig.18 Temperature coefficient of drain-source
on-resistance; N-channel.
handbook, halfpage
0.6
0.8
1.0
1.2
1.4
1.8
1.6
0 50 100 15050
k
T ( C)
jo
MBE139
(1)
(2)
Typical RDSon at:
(1) ID= 2.2 A; VGS =10V.
(2) ID= 1 A; VGS = 4.5 V.
kRDSon at Tj
RDSon at 25 °C
-----------------------------------------
=
Fig.19 Temperature coefficient of drain-source
on-resistance; P-channel.
Typical RDSon at:
(1) ID=1 A; VGS =10 V.
(2) ID=0.5 A; VGS =4.5 V.
kRDSon at Tj
RDSon at 25 °C
-----------------------------------------
=
handbook, halfpage
0.6
0.8
1.0
1.2
1.4
1.8
1.6
0 50 100 15050
k
T ( C)
jo
MBE146
(1)
(2)
1997 Jun 20 11
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
Fig.20 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.
1
10
10
tp(s) 1
MBE152
(K/W)
Rth j-s
1
10 5
10
6
10 3
10
4
10 2
10 1
10
tpT
P
t
tp
T
δ=
δ =
0.75
0.5
0.1
0
0.05
0.33
0.01
0.02
0.2
2
1997 Jun 20 12
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
PACKAGE OUTLINE
UNIT A
max. A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 5.0
4.8 4.0
3.8 1.27 6.2
5.8 1.05 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
4
5
pin 1 index
1
8
y
076E03S MS-012AA
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.20
0.19 0.16
0.15 0.050 0.244
0.228 0.028
0.024 0.028
0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
95-02-04
97-05-22
1997 Jun 20 13
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data Sheet Status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1997 Jun 20 14
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
NOTES
1997 Jun 20 15
Philips Semiconductors Product specification
Complementary enhancement
mode MOS transistors PHC21025
NOTES
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Printed in The Netherlands 137107/00/02/pp16 Date of release: 1997 Jun 20 Document order number: 9397 750 02509