ACPL-K34T Automotive 2.5 A Peak High Output Current MOSFET Gate Drive Optocoupler with Rail-to-Rail Output Voltage in Stretched SO8 Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features Avago's 2.5 Amp Automotive R2Coupler Gate Drive Optocoupler contains an AlGaAs LED, which is optically coupled to an integrated circuit with a power output stage. The ACPL-K34T features fast propagation delay and tight timing skew, is ideally designed for driving power MOSFETs used in AC-DC and DC-DC converters. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving power MOSFETs at high frequency for high efficiency conversion. * Qualified to AEC-Q100 Grade 1 Test Guidelines Avago R2Coupler isolation products provide reinforced insulation and reliability that delivers safe signal isolation critical in automotive and high temperature industrial applications. * Low supply current allow bootstrap half-bridge topology: ICC = 3.9 mA max. Functional Diagram * Wide operating VCC range: 10 V to 20 V * Automotive temperature range: -40 C to 125 C * Peak output current: 2.0 A min. * Rail-to-rail output voltage * Propagation delay: 110 ns max. * Dead time distortion: +50 ns/-40 ns * LED current input drive with hysteresis * Common Mode Rejection (CMR): 35 kV/s min. at VCM = 1500 V * Under Voltage Lock-Out (UVLO) protection with hysteresis for power MOSFET * Safety Approvals: ANODE 1 8 VCC NC 2 7 VOUT 6 NC CATHODE 3 NC 4 5 VEE SHIELD - UL Recognized 5000 VRMS for 1 min - CSA - IEC/EN/DIN EN 60747-5-5 VIORM = 1140 Vpeak Applications * Hybrid Power Train DC/DC Converter * EV/PHEV Charger Figure 1. ACPL-K34T Functional Diagram * Automotive Isolated MOSFET Gate Drive Note: Minimum 1 F bypass capacitor must be connected between pins VCC and VEE. * AC and Brushless DC motor drives Truth Table LED VCC - VEE VOUT OFF 0 - 20V LOW ON <VUVLO- LOW ON >VUVLO+ HIGH CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information Part number Option (RoHS Compliant) ACPL-K34T -000E Surface Mount Package Stretched SO-8 -060E Tape & Reel UL 5000 Vrms / 1 Minute rating X X X X -500E X X X -560E X X X IEC/EN/DIN EN 60747-5-5 Quantity 80 per tube X 80 per tube 1000 per reel X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-K34T-560E to order product of SSO-8 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawings (Stretched SO8) RECOMMENDED LAND PATTERN 5.850 0.254 (0.230 0.010) PART NUMBER 8 7 6 KXXT YWW EE RoHS-COMPLIANCE INDICATOR 1 2 3 DATE CODE 5 12.650 (0.498) 6.807 0.127 (0.268 0.005) 1.905 (0.075) 4 EXTENDED DATECODE FOR LOT TRACKING 0.64 (0.025) 7 3.180 0.127 (0.125 0.005) 0.381 0.127 (0.015 0.005) 0.200 0.100 (0.008 0.004) 1.270 (0.050) BSG 0.450 (0.018) 1.590 0.127 (0.063 0.005) 45 0.750 0.250 (0.0295 0.010) 11.50 0.250 (0.453 0.010) 0.254 0.100 (0.010 0.004) Dimensions in millimeters and (inches). Note: Lead coplanarity = 0.1 mm (0.004 inches). Floating lead protrusion = 0.25mm (10mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Note: Non-halide flux should be used 2 Regulatory Information The ACPL-K34T is approved by the following organizations: UL UL 1577, component recognition program up to VISO = 5 kVRMS CSA CSA Component Acceptance Notice #5. IEC/EN/DIN EN 60747-5-5 IEC 60747-5-5 EN 60747-5-5 DIN EN 60747-5-5 IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristic (Option 060 and 560 only) Description Symbol Option 060 and 560 Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage < 600 Vrms for rated mains voltage < 1000 Vrms I - IV I - III Climatic Classification 40/125/21 Pollution Degree (DIN VDE 0110/1.89) 2 Units Maximum Working Insulation Voltage VIORM 1140 Vpeak Input to Output Test Voltage, Method b VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 2137 Vpeak Input to Output Test Voltage, Method a VIORM x 1.6=VPR, Type and Sample Test with tm=10 sec, Partial discharge < 5 pC VPR 1824 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak Safety-limiting values - maximum values allowed in the event of a failure, also see Figure 5. Case Temperature Input Current Output Power Ts IS, INPUT PS,OUTPUT 175 230 600 C mA mW Insulation Resistance at Ts, VIO=500 V Rs >109 Insulation and Safety Related Specifications Parameter Symbol ACPL-K34T Units Conditions Minimum External Air Gap (Clearance) L(101) 8 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 V Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group (DIN VDE0109) 3 CTI IIIa DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0109) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature TS -55 150 C Operating Temperature TA -40 125 C IC Junction Temperature TJ 150 C Average Input Current IF(AVG) 20 mA Peak Input Current (50% duty cycle, < 1 ms pulse width) IF(PEAK) 40 mA Peak Transient Input Current (<1 s pulse width, 300 pps) IF(TRAN) 1 A Reverse Input Voltage VR 6 V "High" Peak Output Current IOH(PEAK) 2.5 A 1 "Low" Peak Output Current IOL(PEAK) 2.5 A 1 Total Output Supply Voltage (VCC - VEE) 0 25 V Output Voltage VO(PEAK) -0.5 VCC V Output IC Power Dissipation PO 500 mW 2 Total Power Dissipation PT 550 mW 3 Note 3 Recommended Operating Conditions Parameter Symbol Min Max. Units Operating Temperature TA - 40 125 C Output Supply Voltage (VCC - VEE) 10 20 V Input Current (ON) IF(ON) 7 13 mA Input Voltage (OFF) VF(OFF) -5.5 0.8 V Electrical Specifications (DC) Unless otherwise noted, all Minimum/Maximum specifications are at Recommended Operating Conditions. All typical values are at TA = 25 C, VCC - VEE = 10 V, VEE = Ground . Parameter Symbol High Level Peak Output Current IOH Min. Low Level Peak Output Current IOL High Output Transistor RDS(ON) RDS,OH 2.2 Low Output Transistor RDS(ON) RDS,OL 1.0 High Level Output Voltage VOH Low Level Output Voltage VOL 0.1 High Level Supply Current ICCH 2.5 Low Level Supply Current ICCL Threshold Input Current Low to High IFLH Threshold Input Voltage High to Low VFHL 0.8 Input Forward Voltage VF 1.25 2.0 Vcc-0.4 Temperature Coefficient of Input Forward Voltage DVF/DTA Typ. Max. Units Test Conditions Fig. -3.5 -2.0 A VCC - VO = 10 V 3 A VO - VEE = 10 V 4 4.0 IOH = -2.0 A 4 2.0 IOL = 2.0 A 4 V IF = 10 mA, IO = -100 mA 5, 6 0.25 V IO = 100 mA 3.9 mA IF = 10 mA 5 2.5 3.9 mA VF = 0 V 6 1.5 4.9 mA VO > 5 V 7 IF = 10 mA 7 4.4 Vcc-0.2 V 1.5 1.85 -1.5 mV/ C Input Reverse Breakdown Voltage BVR Input Capacitance CIN UVLO Threshold VUVLO+ 8.1 8.6 9.1 VUVLO- 7.1 7.6 8.1 UVLOHYS 0.5 1.0 UVLO Hysteresis 4 V 6 90 V IR = 100 A pF f = 1 MHz, VF = 0 V V VO > 5 V, IF = 10 mA V 8 8 Note Switching Specifications (AC) Unless otherwise noted, all Minimum/Maximum specifications are at Recommended Operating Conditions. All typical values are at TA = 25 C, VCC - VEE = 10 V, VEE = Ground. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level tPLH 30 60 110 ns 9,12,14 7 Propagation Delay Time to Low Output Level tPHL 30 60 110 ns Pulse Width Distortion (tPHL-tPLH) PWD -40 0 40 ns VCC = 10 V RG = 4.7, CL = 10 nF, f = 200 kHz , Duty Cycle = 50% Vin = 4.5 V - 5.5 V, Rin = 350 Dead Time Distortion Caused by Any Two Parts (tPLH-tPHL) DTD -40 50 ns Rise Time tR 10 30 ns Fall Time tF 10 30 ns Output High Level Common Mode Transient Immunity |CMH| 35 >50 kV/s Output Low Level Common Mode Transient Immunity |CML| 35 >50 kV/s 10,12,14 11 8 9 VCC = 10 V, CL = 1 nF, f = 200 kHz , Duty Cycle = 50% Vin = 4.5 V- 5.5 V, Rin = 350 13, 14 TA = 25 C, VCC = 20 V, VCM=1500 V, with split resistors 15 10, 11 10, 12 Package Characteristics Unless otherwise noted, all Minimum/Maximum specifications are at Recommended Operating Conditions. All typical values are at TA = 25C. Parameter Symbol Min. Input-Output Momentary Withstand Voltage* VISO 5000 Input-Output Resistance RI-O Input-Output Capacitance CI-O * 5 Typ. Max. Units Test Conditions Fig. Note VRMS RH < 50%, t = 1 min, TA = 25 C 13, 14 1014 VI-O = 500 VDC 14 0.6 pF f =1 MHz The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." PO - OUTPUT IC POWER DISSIPATION - mW Notes: 1. Maximum pulse width = 100 ns, Duty cycle = 2%. 2. Derate linearly above 110 C free-air temperature at a rate of 13 mW/C. Refer to Figure 2 from Output IC Power Dissipation Derating Chart. 3. Total power dissipation is derated linearly above 110 C free-air temperature at a rate of 13 mW/C. The maximum LED and IC junction temperature should not exceed 150 C. 4. Output is source at -2.0 A or 2.0 A with a maximum pulse width of 10 s. 5. In this test VOH is measured with a DC load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. 6. Maximum pulse width = 1 ms. 7. This load condition approximates the gate load of a 600 V/50 A power MOSFET. 8. Pulse Width Distortion (PWD) is defined as tPHL-tPLH for any given device. 9. Dead Time Distortion (DTD) is defined as tPLH - tPHLbetween any two parts under the same test condition. A negative DTD reduces original system dead time; while a positive DTD increases original system dead time. 10. Pin 2 and Pin 4 must be connected to LED common. 11. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state, (i.e., VO > 10 V). 12. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). 13. In accordance with UL1577, each optocoupler is proof-tested by applying an insulation test voltage 6000 VRMS for 1 second. 14. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together. 600 Po 500 400 300 200 100 0 0 25 50 75 100 125 Ta - AMBIENT TEMPERATURE - C Figure 2. Output IC Power Dissipation Derating Chart 6 150 175 Typical Performance Plots 125C 25C -40C 0 1 2 3 4 5 6 7 8 9 (VCC -VOH) - HIGH OUTPUT VOLTAGE DROP - V IOL - OUTPUT LOW CURRENT - A IOH - OUTPUT HIGH CURRENT - A 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 10 3 2.8 2.6 2.4 VCC=10V VCC=15V VCC=20V 2.2 -20 0 20 40 60 80 TA - TEMPERATURE - C 100 120 1 2 3 4 5 6 7 VOL - OUTPUT LOW VOLTAGE - V 8 9 10 3 2.8 2.6 2.4 -20 14 1.7 12 1.6 IF - INPUT CURRENT - mA 1.4 1.3 IFLH =10mA 1.1 -20 0 Figure 7. VF vs. Temperature 20 40 60 80 TA - TEMPERATURE - C 20 40 60 80 TA - TEMPERATURE - C 100 120 140 1.7 1.8 -40 C 25 C 125 C 10 1.5 1.2 0 Figure 6. ICCL vs. Temperature 1.8 VF - INPUT FORWARD VOLTAGE - F VCC=10V VCC=15V VCC=20V 2.2 2 -40 140 Figure 5. ICCH vs. Temperature 7 0 3.2 ICCL - LOW LEVEL SUPPLY CURRENT - mA ICCH - HIGH LEVEL SUPPLY CURRENT - mA 3.2 1 -40 125 C 25 C -40 C Figure 4. IOL vs. VOL Figure 3. IOH vs. (VCC - VOH) 2 -40 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 100 120 8 6 4 2 140 0 1 1.1 Figure 8. IF vs. VF 1.2 1.3 1.4 1.5 1.6 VF - INPUT FORWARD VOLTAGE - V 80 80 75 TPHL - PROPAGATION DELAY - ns TPLH - PROPAGATION DELAY - ns 85 75 70 65 60 Vin=4.5V 55 Vin=5V 50 -40 Vin=5.5V -20 0 20 40 60 80 TA - TEMPERATURE - C 100 120 140 PWD - PULSE WIDTH DISTORTION - ns Figure 9. tPLH vs. Temperature 10 8 6 4 2 0 -2 -4 -6 -8 -10 -40 0 20 8 40 60 TA - TEMPERATURE - C Figure 11. PWD vs. Temperature 65 60 Vin=4.5V Vin=5V Vin=5.5V 55 50 -40 -20 0 20 40 60 80 TA - TEMPERATURE - C Figure 10. tPHL vs. Temperature Vin=4.5V Vin=5V Vin=5.5V -20 70 80 100 120 140 100 120 140 1 8 1uF _+ Vin =4.5 to 5.5V 50% Duty Cycle 200kHz 2 7 3 6 _+ VCC=10V Rg=4.7 CL=10nF Rin=350 4 5 SHIELD Figure 12. tPLH and tPHL test circuit 1 8 1uF _+ Vin =4.5 to 5.5V 50% Duty Cycle 200kHz 2 7 3 6 Vin _+ 0.1 + uF A 1 8 1uF 2 7 3 6 4 SHIELD + _ Rin2 175 Switch at A: CMH test Switch at B: CML test Figure 15. CMR test circuit 9 tPLH tPHL Figure 14. tPLH, tPHL, tr and tf reference waveforms B _ 10% V OUT 5 SHIELD Figure 13. tr and tf test circuit 5V 90% CL=1nF 4 tf 50% Rin=350 Rin1 175 tr VCC=10V VCM=1500V 5 VO + _ VCC=20V Application Information Typical High Speed MOSFET Gate Drive Circuit +5V VDD 0.1uF +HVDC U5 uP PHA Rin1 Rin2 PHA U6 U1 AN U3 VCC V OUT NC CA NC AN 10u 4.7 NC VEE Q1 ACPL-K34T 10uF PHA LED(U1) Rin4 LED(U2) NC CA NC Q3 D2 D1 U4 U2 AN 4.7 10V Anti-cross conduction drive logic Rin3 NC VEE 10u ACPL-K34T +12V PHA VCC V OUT NC CA NC VCC V OUT NC VEE ACPL-K34T 10u 4.7 AN Q2 VCC V OUT NC NC CA VEE NC ACPL-K34T 10u 4.7 Q4 - HVDC Figure 16. Typical high-speed MOSFET gate drive circuit Anti-Cross Conduction Drive One of the many benefits of using ACPL-K34T is the ease to implement anti-cross conduction drive between the high side and low side gate drivers to prevent shoot through event. This safety interlock drive can be realized by interlocking the output of buffer U5 and U6 to both high and low side gate drivers, as shown in Figure 16. However, due to the propagation delay difference between optocouplers, certain amount of dead time has to be added to ensure sufficient dead time at MOSFET gate. Refer to Dead Time and Propagation Delay section for more details. Recommended LED Drive Circuits Common mode noise exists whenever there is a difference in the ground level of the optocoupler's input control circuitry and output control circuitry. Figure 17 and 18 show recommended LED drive circuits for high common mode rejection (CMR) performance of the optocoupler gate driver. Split limiting resistors are used to balance the impedance at both anode and cathode of the input LED for high common mode noise rejection. Open drain and open collector drive circuits showed in Figure 19 are not recommended. During the off state of the MOSFET/transistor, cathode of the input LED sees high impedance and becomes sensitive to noise. In any cases, if designer still prefers to use single MOSFET/transistor drive over the recommended CMOS buffer drive showed in Figure 17 and 18, designer can choose alternative circuits showed in Figure 20; however M1/Q1 in Figure 20 drive circuits will shunt current during LED off state, which result in more power consumption. Drive Power If CMOS buffer is used to drive LED, it is recommended to connect the CMOS buffer at the LED cathode. This is because the sinking capability of the NMOS is usually more than the driving capability of the PMOS in a CMOS buffer. Drive Logic Designer can configure LED drive circuits for non-inverting and inverting logic as recommended in Figure 17 and 18. External power supply, VDD1 has to be connected to the CMOS buffer for the inverting and non-inverting logic to work. If VDD1 supply is lost, LED will be permanently off and output will be at low. 10 Bypass and Reservoir Capacitors Supply bypass capacitors are necessary at the input buffer and ACPL-K34T output supply pin. A ceramic capacitor with the value of 0.1 F is recommended at the input buffer to provide high frequency bypass, which also helps to improve CMR performance. At the output supply pin (VCC - VEE), it is recommended to use a 10 F, low ESR and low ESL capacitor as a charge reservoir to supply instant driving current to MOSFET at VOUT during switching. ISOLATION VDD1 0.1uF VCC 0.1uF Rin1 AN VDD1 ISOLATION VDD1 VCC Rin1 AN VDD1 V OUT Rin2 CA V OUT Rin2 10uF Ro V EE ACPL-K34T VDD1= 5V +/-10% Rin1 = Rin2 +Ro Recommended Ro+Rin1+Rin2 = 350 Figure 18. Recommended inverting drive circuit ISOLATION ISOLATION VDD1 VCC 0.1uF 10uF V EE ACPL-K34T VDD1= 5V +/ - 10% Rin 1= Rin2 +Ro Recommended Ro+Rin1+Rin2 = 350 Figure 17. Recommended non-inverting drive circuit VDD1 CA Ro VCC 0.1uF AN AN V OUT V OUT Rin CA Rin CA 10uF 10uF V EE V EE ACPL-K34T ACPL-K34T Figure 19(b) Figure 19(a) Figure 19(a) and Figure 19(b). Not recommended - Open drain/open collector drive circuit ISOLATION VDD1 VCC 0.1uF Rin/2 Rin/2 V OUT V EE CA Figure 20(a) V OUT 10uF Rin/2 V EE CA ACPL-K34T VDD1= 5V +/-10% Recommended Rin = 350 Figure 20(b) Figure 20(a) and Figure 20(b). Alternative LED drive circuits to replace Figure 19(a) and 19(b) 11 AN Q1 ACPL-K34T VDD1= 5V +/ -10% Recommended Rin = 350 VCC 0.1uF AN M1 Rin/2 ISOLATION VDD1 10uF Initial Power Up and UVLO Operation Insufficient gate voltage to MOSFET can increase turn on resistance of MOSFET, resulting in large power loss and MOSFET damage due to high heat dissipation. ACPL-K34T monitors the output power supply constantly. During initial power up, the ACPL-K34T requires maximum 50 s of initial startup time for the internal bias and circuitry to get ready. The gate driver output (VOUT ) is hold at off state during initial startup time. Thereafter, when the output power supply is lower than under voltage lockout (VUVLO-) threshold, gate driver output will shut off to protect MOSFET from low voltage bias. When the output power supply is more than the VUVLO+ threshold, VOUT is released from low state and it follows the input LED drive signal, as shown in Figure 21. VCC V UVLO + V UVLO - V UVLO+ Vin(LED) V OUT Initial startup time Figure 21. ACPL-K34T initial power-up and UVLO operation Dead Time Distortion and Propagation Delay Dead time is the period of time during which both high side and low side power transistors (shown as Q1 and Q2 in Figure 16) are off. Any overlap in Q1 and Q2 conduction will result in a shoot-through event and large short circuit current will flow through the power devices between the high side and low side power rail. ACPL-K34T includes a Dead Time Distortion (DTD) specification intended to help designers optimize dead time in a power inverter design. A negative DTD value will decrease the system dead time, and so a negative DTD must be compensated by adding extra dead time to the design. Figure 22a shows that dead time after optocoupler is reduced by negative DTD. On the other hand, a positive DTD will add to the system original dead time, and so a positive DTD will cause dead time redundancy to the system. Figure 22b shows that dead time after optocoupler is increased by positive DTD. Figure 22a. Negative DTD reduces original DT Figure 22. Dead Time and Propagation Delay Waveforms 12 Figure 22b. Positive DTD increased original DT To prevent cross-conduction between high side and low side power transistors, minimum dead time (DT MIN) must be introduced to the system. For example, given DTD MIN = -40 ns and DTD MAX = 50 ns, if designers target to have minimum dead time (DT MIN) of 20 ns after the optocoupler, then initial dead time (DT) needed for the system can be calculated as: DT = DT MIN - DTD MIN = 20ns - (-40ns) = 60ns Maximum dead time (DT MAX) after the optocoupler can be calculated as: DT MAX = DT + DTD MAX = 60 ns + 50 ns = 110 ns By introducing DT = 60 ns, the overall system dead time can vary from 20 ns to 110 ns due to the optocoupler's DTD. Note: The propagation delays used to calculate dead time distortion (DTD) are taken at equal temperatures and test conditions since the optocouplers used are typically mounted close to each other and are switching the same type of MOSFETs. 13 Thermal Resistance Model for ACPL-K34T The diagram for measurement is shown in Figure 23. Here, one die is heated first and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the second die is heated and all the dice temperatures are recorded. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 2 by 2 matrix for our case of two heat sources. 1 8 2 Die1: LED 3 Die 2: Detector 7 6 4 5 Figure 23. Diagram of ACPL-K34T for measurement R11 R12 R21 R22 * P1 P2 = T1 T2 R11: Thermal Resistance of Die1 due to heating of Die1 (C/W) R12: Thermal Resistance of Die1 due to heating of Die2 (C/W) R21: Thermal Resistance of Die2 due to heating of Die1 (C/W) R22: Thermal Resistance of Die2 due to heating of Die2 (C/W) P1: Power dissipation of Die1 (W) P2: Power dissipation of Die2 (W) T1: Junction temperature of Die1 due to heat from all dice (C) T2: Junction temperature of Die2 due to heat from all dice (C) TA: Ambient temperature (C) T1: Temperature difference between Die1 junction and ambient (C) T2: Temperature deference between Die2 junction and ambient (C) T1 = (R11 x P1 + R12 x P2) + TA ------------------(1) T2 = (R21 x P1 + R22 x P2) + TA ------------------(2) Measurement is done on both low and high conductivity boards as shown below: Layout Measurement data Low conductivity board: R11=191 C/W R12=R21= 68.5C/W R22=77C/W High conductivity board: R11=155 C/W R12=R21= 64C/W R22=41C/W 79mm 76mm Note that the above thermal resistance R11, R12, R21 and R22 can be improved by increasing the ground plane/copper area. 14 Application and environment design for ACPL-K34T needs to ensure that the junction temperature of the internal IC and LED within the gate drive optocoupler do not exceed 150 C. The equation (1) and (2) provided above are for the purposes of estimating the junction temperatures. For example: Calculation of LED and output IC power dissipation LED power dissipation, PE = IF(LED) (Recommended Max) * VF(LED) (at 125 C) * Duty Cycle = 13 mA * 1.25 V * 50% = 8.125 mW Output IC power dissipation, PO = VCC (Recommended Max) * ICC(Max) + PHS + PLS = 20 V * 4 mA + 53.3 mW + 32 mW = 165.3 mW where PHS = High side switching power dissipation = (VCC * QG * fPWM)* RDS,OH(MAX) / (RDS,OH(MAX) + RGH) /2 = (20 V * 80nC * 200 kHz) * 4/(4+8)/2 = 53.3mW PLS = Low side switching power dissipation = (VCC * QG * fPWM)* RDS,OL(MAX) / (RDS,OL(MAX) + RGL) /2 = (20 V * 80 nC * 200 kHz) * 2/(2+8)/2 = 32 mW QG = Gate charge at supply voltage fPWM = LED switching frequency RGH = Gate charging resistance RGL = Gate discharging resistance Calculation of LED junction temperature and output IC junction temperature at Ta=125 C: LED junction temperature, T1 = (R11 x PE + R12 x PO) + TA = (191C/W * 8.125 mW + 68.5 C/W * 165.3 mW) + 125 C = 138 C < TJ(absolute max) of 150 C Output IC junction temperature, T2 = (R21 x PE + R22 x PO) + TA = (68.5 C/W * 8.125 mW + 77 C/W * 165.3 mW) + 125 C = 138 C < TJ(absolute max) of 150 C For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, the A logo, and R2Coupler are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2013 Avago Technologies. All rights reserved. AV02-4229EN - August 30, 2013 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Avago Technologies: ACPL-K34T-560E ACPL-K34T-500E