ue aan MICRO NETWORKS MN3040 10-Bit DIA CONVERTER with INPUT REGISTER FEATURES Complete With Internal: Input Register Output Op Amp Reference +1/2LSB Linearity and Monotonicity Guaranteed Over Temperature Small 18-Pin DIP e 40nsec Setup Time e Adjustment-Free e +0.1% FSR Unadjusted Absolute Accuracy Over Temperature 10sec Max Settling Time (20V step to +1/2LSB) e Full Mil Operation -55C to +125C MIL-H-38534 Screening Optional. MIL-STD-1772 Qualified Facility 18 PIN DIP PIN1 0.035 (0.89) 0.105 26} iv 0.015 (0.38) + a 0,075 (1.91) 1/ = Pes 0.100 (2 54) 0.977 24.821 1.027 (26.09) 0.016 (0.41) 0.020 (0.51) } : 0.480 (12.19) esses ae 0.120 (3.05) 0 170 (4.32) 0.200 (5.08) - 0 230 (5.84) 0.009 (0 23) 0.012 (0.30) | 0 30 (7 62) Dimensions in Inches (millimeters) DESCRIPTION The MN3040 is a fast, 10-bit digital-to-analog converter with a fast TTL input register for easy interfacing and rapid throughputs in microprocessor-based systems. 't is packaged ina hermetically sealed, ceramic, 18-pin dual-in-line and is complete with internal reference and output amplifier. Two output ranges are available (0 to 10V and +10V), and performance features include the following: fast output settling (typically 5usec for a 20V change), +0.1%FSR overall accuracy, and + /2LSB lineari- ty and monotonicity guaranteed over the entire operating temperature range. Maximum power consumption is 715 mW. The MN3040 is actively laser trimmed as a complete device for linearity, gain and offset, eliminating the need for externa! ad- justing potentiometers. Units are available for either OC to +70C or ~55C to +125C (H models) operation, and Micro Networks 100% tests and guarantees both linearity and ac- curacy at room temperature and at both operating temperature extremes. For military/aerospace or harsh-environment com- mercial/industrial applications, H/B CH models are fully screened to MIL-H-38534 in Micro Networks MIL-STD-1772 qualified facility. The MN3040s digital inputs are TTL compatible, and its inter- nal input register facilitates interfacing to microprocessor and minicomputer data buses. Applications include microprocessor- based data distribution systems, programmable power supplies, low-resolution displays and servo drivers. Optional MIL-H-38534 processing and linearity and accuracy specs guaranteed over the -55C to +125C temperature range make MN3040 and excellent choice for military avionics and fire control systems. May 1988 aa MICRO NETWORKS 324 Clark St., Worcester, MA 01606 (508) 852-5400 7-47MN3040 10-Bit D/A CONVERTER with INPUT REGISTER ABSOLUTE MAXIMUM RATINGS Operating Temperature Specified Temperature MN3040H/B CH rening. ir 100% screening DIGITAL INPUTS MIN. TYP. | MAX. UNITS Logic Coding: Unipolar (0 to -10V) Range Complementary Binary Bipolar (-10 to +10V) Range Complementary Offset Binary Logic Levels: Logic1" 2.0 Volts + Logic O 0.7 Volts Input Currents Data Inputs: Logic 1 (Vin = 2.4 Volts) 30 vA Logic O" (Vin = 0.3 Volts) - 06 mA Register Enabie: Logic 1" (Vin = 2.4 Volts) 60 vA Logic 0 (Vin = 0.3 Volts) - 12 mA Register Enable (Note 2): Pulse Width . 60 nSec Setup Time Digital Data to Enable 40 nSec ANALOG OUTPUTS _ Output Impedance 0.5 0} Output Load Current +4 mA TRANSFER CHARACTERISTICS inearity Error (Notes 3,5): 0C to +70C +% +% LSB -5C to +125C ("H" Models) +% LSB Monotonicity Guaranteed Over Temperature Absolute Accuracy Error (Notes 4, 5): +25C + 0.05 +0.1 %FSR 0C to +70C +01 +0.4 %FSR ~55C to +125C ("H Models) + 0.2 +0.4 %FSR Gain Error + 0.1 % Gain Drift +15 ppm/C DYNAMIC CHARACTERISTICS Settling Time (20V Change to +1/2 LSB) 5 10 uSec Output Slew Rate 15 V/pSec POWER SUPPLY REQUIREMENTS Power Supply Range: +15V Supply +14.00 +15.00 +17.00 Volts -15V Supply -14.00 15.00 -17.00 Volts +5V Supply + 4.75 + 5.00 + 5.25 Volts Power Supply Rejection: +15V Supply + 0.005 %FSR/%Vs 15V Supply + 0.005 %FSR/%Vs Curre t Drain, Output Unioaded: +15V Supply 13 20 mA ~15V Supply -7 -11 mA +5V Supply 30 50 mA Power Consumption 450 715 mw SPECIFICATIONS NOTES 1. 2. 7-48 The output is short circuit protected to ground or either supply. Converter analog output will follow digital input when Register Enable is a logic 0. Digital input data will be latched and analog output voltage constant when Register Er.able is a logic 1. The minimum Register Enable pulse width to latch new digital input data is 60 nSec. See Timing Diagram. . Micro Networks tests ano guarantees maximum Linearity Error at room temperature and at both extremes of the specified operating temperature range. 4. The Absolute Accuracy Error specification applies over the converter's entire output range. See Absolute Accuracy Error section below for an explanation of how Micro Networks Corporation tests and specifies Absolute Accuracy Error and Gain Error. . 1 LSB for a 10 bit converter corresponds to 0.098% FSA. See Note 6. 6. FSR stands for Full Scale Range and is equal to the peak to peak voltage of the selected output range. For the +10V output range, FSR is 20 volts, and 1 LSB is equal to 19.5 mV. For the 0 to 10V range, FSR is 10 volts,and1LSB is equal to9 8mvV.BLOCK DIAGRAM Register Enable eT tW La] C0 (12) Summing PIN DESIGNATIONS Junction e 18 PIN 1 MSB (14)0_ + lp ~ Bit 2 (15)o1 } -0(13) Analog Bit 3 (16)02_} + Output Bit 4 (17)o +} nae pt: Bit (180 4 555 - asx = 9 10 Bit6 (1lo 435 +4 od Bit? (2)o_+ ie pereend T Bit8 (3)o Lean Bit9 (4)o_ ei LSB (5) io mm 0011) Bipolar 1 Bit 18 Bit 5 94 Say Go L 287 vor -15V Supply (9)o_-> 1 ' +5V Supply (7)o$__> 7 4 Bitg 15 Bit 2 Ground (10)o__> 5 Bit 10 (LSB) 14 Bit 1 (MSB) 6 Register Enable 13 Analog Output 7 +5V Supply 12 Summing Junction 8 +15V Supply 11 Bipolar Offset 9 -15V Supply 10 Ground ABSOLUTE ACCURACY ERROR The Absolute Accuracy Error of a voltage output D/A converter is the difference between the actual, unadjusted output voltage that appears following the application of a given digital input code and the ideal or expected output voltage for that code. This difference is usually expressed in LSBs or %FSR (see Note 6 in the Specification Notes). Absolute Accuracy Error includes gain, offset, linearity, and noise errors and encompasses the drifts of these errors when specified over temperature. For the MN3040, Micro Networks tests Absolute Accuracy Error at both endpoints of the unipolar output range (0 to -10V) and at both endpoints and the midpoint of the bipotar output range +10V). These tests are performed at room temperature and at the high and tow extremes of the specified operating temperature range. Example: For the MN3040H (55C to +125C temperature range) operating on its +10V output range, the expected analog output fora 11 1111 1111 digital input is 9.9805V (see Input Coding and Range Selection). The expected output for a 10 0000 0000 digital input is 0 volts, and the expected output for a 00 0000 0000 digital input is +10.0000V. Micro Networks measures all three actual, unadjusted output voltages at ~55C, +25C, and +125C. We guarantee that at +25C, all three will be within +0.1%FSR (20mV) of their ideal values and that over the entire -55C to +125C operating temperature range, all three wil! be within +0.4%FSR (+80 mV) of their ideal values. By also testing and guaranteeing +% LSB Linearity over temperature, we guarantee the transfer function wiil be monotonic and that every output level will be within our Absolute Accuracy specification of where it is ideally supposed to be. Please see the Input Coding Table. OFFSET ERROR Bipolar and Unipolar Offset Error are Absolute Accuracy Errors. It would be redundant to specify them after giving an Absolute Accuracy Error that applies over the converters entire output range. GAIN ERROR Gain Error is the difference between the ideal and the measured values of a converters full scale range (minus 1 LSB). It is a measure of the slope of the converters transfer function. Gain Error is not a type of Absolute Accuracy Error, but it can be calculated using two Absolute Accuracy Error measurements. It is equivalent to the Absolute Accuracy Error measured for the 00 0000 0000 digital input minus that measured for the 11 1111 1111 digital input, and it is usually expressed as a percentage. See the Converter Tutorial Section of the Micro Networks Product Guide and Applications Manual for a complete discussion of converter specifications, and be sure you clearly understand each manufacturer's specification definition before you compare converters solely on a data sheet basis. INPUT CODING AND OUTPUT RANGE SELECTION DIGITAL INPUT ANALOG OUTPUT (DC VOLTS) MSB LsB 0 to -10V - 10 to ~-10V 00 0000 0000 0.0000 *10.0000 00 0000 0001 0.0098 + 9.9805 0111111111 - 49902 + 0.0195 10 0000 0000 5.0000 0.0000 10 0000 0001 - 5.0098 - 0.0195 1111111110 9.9805 ~ 9.9609 11:1111:11171 9.9902 - 9.9805 Pin Connections Pin 11 Open Pin 11 to Pin 12 Pin 12 Open 49APPLICATIONS INFORMATION LAYOUT CONSIDERATIONS Proper attention to layout and decoupling is necessary to obtain specified accuracy from the MN3040. The units Ground pin (pin 10) should be tied to system analog ground as close to the package as possible, preferably through a large ground plane underneath the package. POWER SUPPLY DECOUPLING Tabl Lene: | cel. | Lane 0.01 pF 0.01 pF Pin 10 Ground Pin ete Ground 0.01 uF Ping -15V Power supplies should be decoupled with tantalum or electrolytic capacitors located close to the MN3040. For optimum performance, 1uF capacitors paralleled with 0.01 uF ceramic capacitors should be used as shown in the diagrams below. REGISTER ENABLE When the Register Enable (Pin 6) is high (hold mode) the digital data in the input register will be latched, and when the Register Enable is low (track mode), the converters output will follow its input. In order to latch new digital data into the register, the Register Enable must go low for a minimum of 60 nSec and digital input data must be valid for a minimum of 40 nSec prior to Register Enable going high again. INPUT REGISTER TIMING DIAGRAM kK Twerw Jegister Enable TH Cigital Input Data Output / Voitage TIMING NOTES: Tmepw Minimum enable pulse width is 60 nSec. TSDE Minimum setup time digital input data to enable is 40 nSec. TH Hold time is defined as the required delay between the leading edge of register enable and the end of valid input data. For the MN3040 the hold time is zero. Tos Output settling time for a 20 voit change to +%LSB is 10uSec max. \ MiCROPROCESSOR INTERFACING Interfacing the MN3040 to 8, 12, and 16 bit microprocessors is simplified by the MN3040s internal 10 bit register. External address and control decoding will be required, however. Interfacing to 12 and 16 bit processors is fairly direct and can usually be accomplished by NANDing the desired address lines with processor's MEMORY WRITE or I/O WRITE line and using the output to drive the MN3040's Register Enable input. For most processors, valid data remains on the data bus for a period of time after the removal of either valid address or control signals. This results in data being latched into the MN3040 immediately after one of the address or control signals changes but before valid data goes away. Interfacing to 8 bit processors is slightly more complicated and an 8 bit external register is needed as shown in the sketch below. Address decoding must be organized such that the 8 bit intermediate register and the MN3040s internal 10 bit regis- ter appear at two different addresses. The 10 bits of digital data are sent to the MN3040 via two data transfers. First, the8 least significant bits of digital data are written to the intermediate latch. Then the 2 most significant bits of digital data are written to the MN3040s 10 bit latch. The result is that the 2 MSBs on the data bus and the 8 LSB's held in the intermediate latch are all latched into the MN3040's latch simultaneously. If one wants to change only the MSB and/or bit 2, only a single write operation is necessary. If the intermediate latch is tied to the MN3040s 8 most significant bits, it would take only a single write operation to change only the LSB and/or bit 9. To change any of the other bits would involve two write operations. This latter configuration would reduce software if one were using the MN3040 to generate smooth waveforms. ADDRESS AND CONTROL DECODING MN3040 tANALOG OUTPUT I DATA BUS 9 x 10 BIT REGISTER HTT LTT 8 BIT INTERMEDIATE REGISTER Do ean MICRO NETWORKS 324 Clark St., Worcester, MA 01606 (508) 852-5400 7-50