Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999
Features
• High-speed, low-power, first-in fir st- out (FIFO)
memories
• 8K x 9 FIFO (CY7C460A)
• 16K x 9 FIFO (CY7C462A)
• 32K x 9 FIFO (CY7C464A)
• 64K x 9 FIFO (CY7C466A)
• 10 -ns access time s, 20-ns rea d/write cycle times
• High-speed 50-MHz read/write independent of
depth/width
• Low op er ati n g pow e r
—ICC= 60 mA
—ISB =8 mA
• Asy nchronous read/write
• Empty and Full flags
• Half Full flag (in standalone mode)
• Retransmit (in standalone m ode)
• TTL-compatible
• Width and Depth Expansion Capability
•5V ± 10% supply
• PLCC, LCC, 300-mil and 600-mil DIP packag ing
• Three-state outputs
• Pin compatible density upgrade to CY7C42X/46X famil y
• Pin compatible and functionall y equival ent to IDT7205,
IDT7206, IDT7 207, IDT7208
Functional Descri pti on
The CY7C460A, CY7 C462A, CY7C4 64A, and CY7C46 6A ar e
respect ively, 8K, 16K , 32K, and 64K wo rds by 9- bit wide fir st-in
first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it
was written . Full and Empty fl ags are provided to prev ent ov er-
run and underrun. Three additi onal pins are also provided to
facilitate unlimited expansion in width, depth, or both. The
depth e xpansion technique steer s the control si gnals from one
device to another by passing tokens.
The read and write operations may be asynchronous; each
can occur at a rate of up to 50 MHz. The writ e operati on occurs
when the Write (W) signal is LOW. Read occurs when Read
(R) goes LOW. The nine data outputs go to the high-imped-
ance state when R is HI G H .
A Half Full (HF) out put fla g is pro vided th at is v alid in the stan-
dalone (single devi ce) and width expansion configurations. In
the depth expansion configuration, this pin provides the expan-
sion out (XO) in f ormatio n that is us ed t o tell th e ne xt FI FO tha t
it will be activated.
In the standalone and width expansion configurations , a LOW
on the Retransmit (RT) input causes the FIFOs to retransmit
the dat a. Read Enab l e (R) a nd Write Ena b le (W) mu st bot h be
HIGH during a retransmit cycle, and then R is used to access
the data.
The CY7C460A, CY7 C462A, CY7C4 64A, and CY7C46 6A ar e
fa bricate d using Cy pre ss’s adv anced 0.5µ RAM3 CMOS tech -
nology. Input ESD protection is greater than 2000V and
latch-up is prevented by careful layout and the use of guard
rings.
32K x
LogicBlockDiagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
Top View
DIP
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
GND
VCC
D4
FL/RT
MR
EF
XO/HF
Q7
R
PLCC/LCC
Top View
Q3
Q8
D5
D6
D7
Q6
Q5
Q4
4 3 2 1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
FL/RT
MR
EF
XO/HF
Q7
D6
Q6
D7
NC
READ
CONTROL
WRITE
CONTROL
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
RAM ARRAY
8K x 9
16K x 9
9
DATAINPUTS
(D0−D8)
THREE–
STATE
BUFFERS
DATAOUTPUTS
(Q0-Q 8)
W
READ
POINTER
FLAG
LOGIC
R
XI
EF
FF
XO/HF
MR
FL/RT
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
D
D
W
NC
V
D
D
3
8
cc
4
5
Q
Q
GND
NC
R
Q
Q
3
8
4
5
C46XA–1
C46XA–2
C46XA–3
7C460A
7C462A
7C464A
7C460A
7C462A
7C464A
64K x 9
7C466A 7C466A
DUAL PORT
CY7C460A/CY7C462A
CY7C464A/CY7C466A
2
Maximum Ratings
(Above which the usefu l l ife may be impair ed. For user gui de-
li nes, not tested .)
Storage Temperature.... .. ..... .. ..... .. ........ .. ....–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +1 2 5 °C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Power Dissipation ..........................................................1.0W
Output Current, into Outputs (LOW)............................ 20 mA
Static Discharge Voltage..... ..... ........ .. .. ..... ..... ..... .. ....>2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current....... ....... .......... ....... .......... ....... .....>200 mA
Selec tion Guid e
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25
Frequency (MHz ) 50 40 28.5
Maximum Access Time (ns) 10 15 25
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to + 70°C 5V ± 10%
Industrial –40°C to +85 °C5V ± 10%
Military[1] –55°C to +1 2 5 °C 5V ± 10%
Electrical Characteristics O ver the Ope rating Range[2]
Parameter Description Test Condi ti ons
7C460A/462A/464A/466A
(-10,-15,-25) UnitMin. Max.
VOH Output HIGH Voltage VCC = Min., IOH = −2.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 m A 0.4 V
VIH Input HIGH Volt age 2.2 VCC V
VIL Input LO W Volta ge −0.5 0.8 V
IIX Input Leakage Current GND < VI < VCC –10 +10 µA
IOZ Output Leakage Current R > VIH, GND < VO < VCC –10 +10 µA
ICC Oper ating Current VCC = Max.,
IOUT = 0 mA, Freq. = 20 MHz 60 mA
ISB Standby Current All In puts = VIH mi n. 8mA
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capac it ance TA = 25°C , f = 1 MHz,
VCC = 4.5V 10 pF
COUT Output Capaci tance 12 pF
Notes:
1. TA is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second.
4. Tested initially and after any design or process changes that may affect these parameters.
CY7C460A/CY7C462A
CY7C464A/CY7C466A
3
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 500Ω
R2
333Ω
30pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤5ns ≤5ns
5V
OUTPUT
R1 500Ω
R2
333Ω
5pF
INCLUDING
JIG AND
SCOPE
OUTPUT 2V
Equivalent to: THÉ VENIN EQUIVALENT
(b)
C460A–4C460A–5C460A–6
(a)
ALL INPUT PULSES
200Ω
Switching Characteristics Over the Operati ng Range[2, 5 ]
Parameter Description
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25 UnitMin. Max. Min. Max. Min. Max.
tRC Read Cycle Time 20 25 35 ns
tAAcc ess Time 10 15 25 ns
tRR Read Recover y Time 10 10 10 ns
tPR Read Pulse Width 10 15 25 ns
tLZR Read LOW to Low Z 3 3 3 ns
tDVR[6] Data V alid After Read HIGH 3 3 3 ns
tHZR[6] Read HIGH to High Z 15 15 18 ns
tWC Write Cycle Time 20 25 35 ns
tPW Write Pul se Width 10 15 25 ns
tHWZ Write HIGH to Low Z 5 5 5 ns
tWR Write Recovery Time 10 10 10 ns
tSD Data Set- Up Time 9 9 9 ns
tHD Data Hold Time 0 0 0 ns
tMRSC MR Cycle Time 20 25 35 ns
tPMR MR Pulse Width 10 15 25 ns
tRMR MR Recovery Time 10 10 10 ns
tRPW Read HIGH to MR HIGH 10 15 25 ns
tWPW Write HIGH to M R HIGH 10 15 25 ns
tRTC Retransmit Cycle Time 20 25 35 ns
tPRT Retransm it Pulse Width 10 15 25 ns
tRTR Retransmit Recovery Time 10 10 10 ns
tEFL MR to EF LOW 20 25 35 ns
tHFH MR to HF HIGH 20 25 35 ns
tFFH MR to FF HIGH 20 25 35 ns
tREF Read LOW to EF LO W 10 15 25 ns
tRFF Read HIGH to FF HIGH 10 15 25 ns
Notes:
5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load
capacitance, as in part (a) of AC Test Loads, unless otherwise specified.
6. tHZR and tDVR use capacitance loading as in part (b) of AC Test Loads.
CY7C460A/CY7C462A
CY7C464A/CY7C466A
4
tWEF Write HIGH to EF HIGH 10 15 25 ns
tWFF Write LOW to FF LOW 10 15 25 ns
tWHF Write LOW to HF LOW 10 15 35 ns
tRHF Read HIGH to HF HI GH 10 15 35 ns
tRAE Effective Read from Write
HIGH 10 15 25 ns
tRPE E ff ec tiv e R e ad P u l s e W idth
After EF HIG H 10 15 25 ns
tWAF Effective Write from Read
HIGH 10 15 25 ns
tWPF Effective Wr i te Puls e
Width After FF HIG H 10 15 25 ns
tXOL Expansion Out LOW
Delay from Clock 10 15 25 ns
tXOH Expansion Out HIGH
Delay from Clock 10 15 25 ns
Switching Characteristics Over the Operati ng Range[2, 5 ] (co ntinued)
Parameter Description
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25 UnitMin. Max. Min. Max. Min. Max.
CY7C460A/CY7C462A
CY7C464A/CY7C466A
5
Switching Wavef orms[7]
Notes:
7. A HIGH-to-LO W transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW- to-HIGH strobe
transition causes a LOW-to-HIGH flag transition.
8. W and R = VIH around the rising edge of MR.
9. tMSRC = t PMR + t RMR
Asynchronous Read and Write
C460A–7
DATA VALIDDATA VALID
DATA VALID DATA VALID
tSD tHD
tRC tPR
tAtRR tA
tLZR tDVR tHZR
tWC
tPW tWR
R
Q0−Q8
W
D0−D8
tSD tHD
tPW
Master Reset
MR
R,W
HF
FF
EF
tMRSC
tPMR
tEFL
tHFH
tFFH
tRPW
tWPW tRMR
C460A–8
[9]
[8]
HA LF FULL+1HALF FULL HA LF FULL
W
R
HF tWHF
tRHF
Half FullFlag
C460A–9
CY7C460A/CY7C462A
CY7C464A/CY7C466A
6
Notes:
10. tRTC = tPRT + tRTR.
11. EF, HF , and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC, except for the CY7C46x-20
(Military), whose flags will be valid after tRTC + 10 ns.
Switching Wavef orms[7] (continued)
Last Write toFirst ReadFullFlag
C460A–10
LAST WRITE FIRST READ ADDITIONAL
READS FIR ST WRITE
tWFF tRFF
R
W
FF
Last READ to First WRITE Empty Flag
C460A–11
VALID
LAST READ FIRST WRITE ADDITIONAL
WRITES FI RST READ
VALID
tREF tWEF
tA
W
R
EF
DATA OUT
Retransmit
C460A–12
tRTC
tPRT
tRTR
FL/RT
R,W
tRTC
tRTR
[10,11]
CY7C460A/CY7C462A
CY7C464A/CY7C466A
7
Switching Wavef orms[7] (continued)
Full Flag and WriteData Flow-Through Mode
C460A–13
R
W
FF
DATA IN
DATA OUT
DATA VALID
DATA VALID
tWAF tWPF
tWFF
tRFF
tSD
tHD
tA
EmptyFlag and Read Data Flow-Through Mode
C460A–14
W
R
EF
DATA IN
DATA OUT DATA VALID
tRAE
tREF
tWEF tHWZ tA
tRPE
CY7C460A/CY7C462A
CY7C464A/CY7C466A
8
Architecture
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset
(MR) cycle . This ca uses the FI FO t o enter the empt y condit ion
sign ifi ed by t he Empty flag (EF) being LOW, and both the Half
Full (HF), and Full f lags (FF) being HIGH. Read (R) and Write
(W) must be HIGH tRPW/tWPW before and tRMR after the risin g
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Writi ng Data to the FIFO
The av ai labi lit y of at least one empty loc ation is indi cated b y a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0−D8) tSD before and tHD after the
rising edge of W will be stor ed sequentially in t he FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LO W tWHF after the falling edge of W following the FIFO actu-
ally being half full. Therefore, the HF is active once the FIFO
is f illed to ha lf its c apacity plus one word. HF will remain LOW
while less than one half of total memory is available f or writing.
The LO W -t o-HIGH tr ansit ion of HF oc curs tRHF after the rising
edge of R when the FIFO goes from half full +1 to half full. HF
is available in standalone and width expansion modes. FF
goes LOW t WFF afte r the falling e dge of W, during the cycle in
which th e last av ailab le location is fi lled. Internal logi c prevent s
overr unning a full FIFO. Writes to a full FIFO are ignored and
the write pointe r is not incr em ented. FF goes HIGH tRFF after
a read from a full FIFO.
Reading Data from the FIFO
The f alling e dge of R initi ates a read cy cle if th e EF is not LO W .
Data outputs (Q0−Q8) ar e in a hi gh-impedance condition be-
tween read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the activ e de vice in th e depth expa nsi on
mode.
When one word is i n the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. When the FIFO is empty, the
outputs are in a high-impedance state. Reads to an empty
FIFO are i gnored and do no t incr ement the read poi nter. From
the empty condition, the FIFO can be read tWEF after a valid
write.
Retransmit
The retransmit feature is benefi cial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
(RT) input is active in the standalone and width expansion
modes. The re trans mit f eature i s intend ed for u se when a n um-
Note:
12. Expansion out of device 1 (XO1) is connected to expansion in of device 2 (XI2).
Switching Wavef orms[7] (continued)
Expansion TimingDiagrams
C460A–15
R
W
XO1(XI2)
D0−D8DATA VALID
DATA DATA
VALID VALID
tXOL
tHD
tSD tSD tHD
tXOL
tLZR
tA
tDVR
tA
tDVR
tHZR
XO1(XI2)
Q0−Q8
C460A–16
tWR
tRR
D ATA VAL ID
tXOH
tXOH
[12]
[12]
CY7C460A/CY7C462A
CY7C464A/CY7C466A
9
ber of writes equal-to- or-less-than the depth of t he FIFO have
occurr ed since the last MR cycle. A LOW pulse on RT resets
the internal read pointer to the first physical location of the
FIFO. R and W must both be HIGH while and tRTR after re-
transmi t i s LOW. With every read cycl e after retransmit , previ-
ousl y acce ssed d ata is r ead an d the read p ointer incre mente d
unti l equal to the write pointer. Ful l, Half Fu ll , and Empty flags
are governed by the relative locations of the read and write
pointers and are u pdated during a retransmit cycle. Data writ-
ten to the FIFO after activation of RT are transmitted also.
The full depth of the FI FO can be repeatedly retr ansmitted.
Standalone/W idt h Expansion Modes
Standalon e and width e xpansion mode s are set b y grounding
expansion in (XI) and tying fir st lo ad (FL) to VCC prior to a MR
cycl e. FI FOs can b e e xpanded i n width to pro vide wor d widths
greater than nine in increments of nine. During width expan-
sion m ode, all control line inputs are common to all devices,
and flag outputs from any device can be monit ored.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, during a MR cycle,
expansion out (XO) of one device is connected to expansion
in ( X I ) of the ne x t de vice, with XO of t he last device con nected
to XI of the first device. In the depth expansion mode, the first
load (FL) input, when grounded, indicates t hat this is the first
par t to be loaded. All other devices must have this pi n HIGH.
To enable the correct FIFO, XO is pulsed LOW when the last
physical location of the previous FIFO is written to and is
pulsed LOW a gain wh en the l ast ph ysica l location is re ad. Only
one FIFO is enabled for Read and one is enab led f or Writ e at
any given time. All other devices are in st andby.
FIFOs can also be expanded simultaneously in depth and
width. Consequently, any depth or width FIFO can be created
with word widths in increments of nine. When expanding in
depth, a composite FF is created by ORing the FFs together.
Likewise, a composite EF is created by ORing EFs together.
HF and RT functions are not available in depth expansion
mode.
Figure 1. Depth Expansion
CY7C460A
CY7C462A
CY7C464A
W
RS
XI
FL
EF
XO
FF
XI
FL
EF
XO
XI
FL
EF
XO
FF
R
EMPTY
FULL
D0-8 Q0-8
9
9
9
9
9
FF
VCC
* FIRSTDEVICE
*
C460A–17
CY7C460A
CY7C462A
CY7C464A
CY7C460A
CY7C462A
CY7C464A
CY7C466A
CY7C466A
CY7C466A
CY7C460A/CY7C462A
CY7C464A/CY7C466A
10
Ordering Information
8K x 9 Asynchronous FIFO
Speed
(ns) Ordering Code Package
Name P ackage Type Operating
Range
10 CY7C460A-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C460A-10PC P15 28-Lead (600- M il ) Molded DIP
CY7C460A-10PTC P21 28-Lead (300- M il ) Molded DIP
CY7C460A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
15 CY7C460A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C460A-15PC P15 28-Lead (600- M il ) Molded DIP
CY7C460A-15PTC P21 28-Lead (300- M il ) Molded DIP
25 CY7C460A-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C460A-25PC P15 28-Lead (600- M il ) Molded DIP
CY7C460A-25PTC P21 28-Lead (300- M il ) Molded DIP
16K x 9 Asynchronous FIFO
Speed
(ns) Ordering Code Package
Name Package T ype Operating
Range
10 CY7C462A-10JC J65 32-Lead Plast ic Leaded Chip Carrier Commercial
CY7C462A-10PC P15 28-Lead (600- Mil) Molded DIP
CY7C462A-10PTC P21 28-Lead (300- Mil) Molded DIP
CY7C462A-10JI J65 32-Lead Plast ic Leaded Chip Carrier Industrial
15 CY7C462A-15JC J65 32-Lead Plast ic Leaded Chip Carrier Commercial
CY7C462A-15PC P15 28-Lead (600- Mil) Molded DIP
CY7C462A-15PTC P21 28-Lead (300- Mil) Molded DIP
25 CY7C462A-25JC J65 32-Lead Plast ic Leaded Chip Carrier Commercial
CY7C462A-25PC P15 28-Lead (600- Mil) Molded DIP
CY7C462A-25PTC P21 28-Lead (300- Mil) Molded DIP
32K x 9 Asynchronous FIFO
Speed
(ns) Ordering Code Package
Name Pack age Type Operating
Range
10 CY7C464A-10JC J65 32-Lead Plastic Leaded Chip Carr ier Commercial
CY7C464A-10PC P15 28- Lead (600-Mil) Molded DIP
CY7C464A-10PTC P21 28-Lead (300-Mil) Molded DIP
CY7C464A-10JI J65 32-Lead Plastic Leaded Chip Carr ier Industrial
15 CY7C464A-15JC J65 32-Lead Plastic Leaded Chip Carr ier Commercial
CY7C464A-15PC P15 28- Lead (600-Mil) Molded DIP
CY7C464A-15PTC P21 28-Lead (300-Mil) Molded DIP
CY7C464A-15LMB L55 32-Pi n Rectangular Leadl ess Chip Carrier Military
25 CY7C464A-25JC J65 32-Lead Plastic Leaded Chip Carr ier Commercial
CY7C464A-25PC P15 28- Lead (600-Mil) Molded DIP
CY7C464A-25PTC P21 28-Lead (300-Mil) Molded DIP
CY7C460A/CY7C462A
CY7C464A/CY7C466A
11
Orde ring Information (continued)
64K x 9 Asynchronous FIFO
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
10 CY7C466A-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C466A-10PC P15 28-Lead (600-Mil) Molded DIP
CY7C466A-10PTC P21 28-Lead (300-Mil) Molded DIP
CY7C466A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industr ial
15 CY7C466A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C466A-15PC P15 28-Lead (600-Mil) Molded DIP
CY7C466A-15PTC P21 28-Lead (300-Mil) Molded DIP
CY7C4 66A-15LMB L55 32- Pin Rectangular Leadle ss Chip Carrier Mili tary
25 CY7C466A-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C466A-25PC P15 28-Lead (600-Mil) Molded DIP
CY7C466A-25PTC P21 28-Lead (300-Mil) Molded DIP
CY7C460A/CY7C462A
CY7C464A/CY7C466A
12
MIL ITARY SPEC I F ICATIONS
Group A Subgroup Testing
Document #: 38-0062 7-A
DC C h ar acteri stics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL Max. 1, 2, 3
IIX 1, 2, 3
ICC 1, 2, 3
ISB1 1, 2, 3
ISB2 1, 2, 3
IOS 1, 2, 3
IOZ 1, 2, 3
Switching Chara cteristics
Parameter Subgroups
tRC 9, 10, 11
tA9, 10, 11
tRR 9, 10, 11
tPR 9, 10, 11
tLZR 9, 10, 11
tDVR 9, 10, 11
tHZR 9, 10, 11
tWC 9, 10, 11
tPW 9, 10, 11
tHWZ 9, 10, 11
tWR 9, 10, 11
tSD 9, 10, 11
tHD 9, 10, 11
tMRSC 9, 10, 11
tPMR 9, 10, 11
tRMR 9, 10, 11
tRPW 9, 10, 11
tWPW 9, 10, 11
tRTC 9, 10, 11
tPRT 9, 10, 11
tRTR 9, 10, 11
tEFL 9, 10, 11
tHFH 9, 10, 11
tFFH 9, 10, 11
tREF 9, 10, 11
tRFF 9, 10, 11
tWEF 9, 10, 11
tWFF 9, 10, 11
tWHF 9, 10, 11
tRHF 9, 10, 11
tRAE 9, 10, 11
tRPE 9, 10, 11
tWAF 9, 10, 11
tWPF 9, 10, 11
tXOL 9, 10, 11
tXOH 9, 10, 11
CY7C460A/CY7C462A
CY7C464A/CY7C466A
13
Package Diagrams
32-Lead Plastic Leaded Chip Carrier J65
51-85002-B
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068
CY7C460A/CY7C462A
CY7C464A/CY7C466A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (cont inued)
51-85017-A
28-Lead (600-Mil) Molded DIP P15
51-85014-B
28-Lead (300-Mil) Molded DIP P21
