Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 ISO5500 2.5-A Isolated IGBT, MOSFET Gate Driver 1 Features 3 Description * * * * * * * The ISO5500 is an isolated gate driver for IGBTs and MOSFETs with power ratings of up to IC = 150 A and VCE = 600 V. Input TTL logic and output power stage are separated by a capacitive, silicon dioxide (SiO2), isolation barrier. When used in conjunction with isolated power supplies, the device blocks high voltage, isolates ground, and prevents noise currents from entering the local ground and interfering with or damaging sensitive circuitry. 1 * * * * * * * 2.5-A Maximum Peak Output Current Drives IGBTs up to IC = 150 A, VCE = 600 V Capacitive Isolated Fault Feedback CMOS/TTL Compatible Inputs 300-ns Maximum Propagation Delay Soft IGBT Turnoff Integrated Fail-Safe IGBT Protection - High VCE (DESAT) Detection - Undervoltage Lockout (UVLO) Protection With Hysteresis User Configurable Functions - Inverting, Noninverting Inputs - Auto-Reset - Auto-Shutdown Wide VCC1 Range: 3 V to 5.5 V Wide VCC2 Range: 15 V to 30 V Operating Temperature: -40C to 125C Wide-Body SO-16 Package 50-kV/us Transient Immunity Typical Safety and Regulatory Approvals: - VDE 6000 VPK Basic Isolation per DIN V VDE V 0884-10 (VDE V 0884-10) and DIN EN 61010-1 - 4243 VRMS Isolation for One Minute per UL 1577 - CSA Component Acceptance Notice #5A, IEC 61010-1, and IEC 60950-1 End Equipment Standards 2 Applications * Isolated IGBT and MOSFET Drives in - Motor Control - Motion Control - Industrial Inverters - Switched-Mode Power Supplies The device provides over-current protection (DESAT) to an IGBT or MOSFET while an Undervoltage Lockout circuit (UVLO) monitors the output power supply to ensure sufficient gate drive voltage. If the output supply drops below 12 V, the UVLO turns the power transistor off by driving the gate drive output to a logic low state. For a DESAT fault, the ISO5500 initiates a soft shutdown procedure that slowly reduces the IGBT/MOSFET current to zero while preventing large di/dt induced voltage spikes. A fault signal is then transmitted across the isolation barrier, actively driving the open-drain FAULT output low and disabling the device inputs. The inputs are blocked as long as the FAULT-pin is low. FAULT remains low until the inputs are configured for an output low state, followed by a logic low input on the RESET pin. The ISO5500 is available in a 16-pin SOIC package and is specified for operating temperatures from -40C to 125C. Device Information(1) PART NUMBER ISO5500 PACKAGE BODY SIZE (NOM) SOIC (16) 10.30 mm x 7.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Functional Block Diagram ISO5500 VREG VCC1 VCC2 - VIN+ UVLO + ISO - Barri er V INDELAY FAULT Gate Drive VC DESAT + DESAT - 12 .3V and 7.2 V Fault Logic Q1b Q1a Q4 VOUT Q S VE R RESET GND1 Q3 Q2b Q2a VEE-P VEE-L 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 12 Detailed Description ............................................ 16 8.1 Overview ................................................................. 16 8.2 Functional Block Diagram ....................................... 16 8.3 Feature Description................................................. 17 8.4 Device Functional Modes........................................ 25 9 Application and Implementation ........................ 26 9.1 Application Information............................................ 26 9.2 Typical Application ................................................. 26 10 Power Supply Recommendations ..................... 35 11 Layout................................................................... 35 11.1 Layout Guidelines ................................................. 35 11.2 PCB Material ......................................................... 35 11.3 Layout Example .................................................... 35 12 Device and Documentation Support ................. 36 12.1 12.2 12.3 12.4 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ 36 36 36 36 13 Mechanical, Packaging, and Orderable Information ........................................................... 36 4 Revision History Changes from Revision C (June 2013) to Revision D Page * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 * VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1 * Added FAULT limits to Absolute Maximum Ratings .............................................................................................................. 4 Changes from Revision B (May 2013) to Revision C Page * Changed VCE from1200 V to 600 V ........................................................................................................................................ 1 * Added the Thermal Information table inside the data sheet below the Absolute Maximum Ratings table ............................ 5 * Changed row VIORM and VPR specification from VIORM of 1200Vpk to 680 Vpk....................................................................... 17 * Changed 1200 VPK in the Regulatory Information table from 1200 VPK to 680 VPK ............................................................. 17 * Deleted last row of the IEC 60664-1 Rating Table............................................................................................................... 18 * Added Isolation Lifetime at a Maximum Continuous Working Voltage table........................................................................ 18 * Added Function Table under the Functional Block Diagram ................................................................................................ 25 Changes from Revision A (July 2012) to Revision B Page * Changed the Regulatory Approvals List ................................................................................................................................. 1 * Changed the REGULATORY INFORMATION table, VDE Column From: File Number: pending To: File Number: 40016131.............................................................................................................................................................................. 17 * Changed the REGULATORY INFORMATION table, CSA Column From: File Number: pending To: File Number: 220991.................................................................................................................................................................................. 17 Changes from Original (September 2011) to Revision A * 2 Page Changed the device From: Product Preview To: Production ................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 5 Pin Configuration and Functions DW Package 16-Pin SOIC Top View VIN+ 1 16 VE VIN- 2 15 VEE-L 14 DESAT 13 VCC2 12 VC 11 VOUT 3 4 RESET 5 FAULT 6 NC 7 10 VEE-L GND1 8 9 VEE-P ISOLATION VCC1 GND1 Pin Functions PIN NO. 1 NAME VIN+ I/O DESCRIPTION I Noninverting gate drive voltage control input Inverting gate drive voltage control input 2 VIN- I 3 VCC1 Supply Positive input supply (3 V to 5.5 V) 4,8 GND1 Ground Input ground 5 RESET I FAULT reset input 6 FAULT O Open-drain output. Connect to 3.3k pullup resistor 7 NC NC 9 VEE-P Supply Most negative output-supply potential of the power output. Connect externally to pin 10. 10, 15 VEE-L Supply Most negative output-supply potential of the logic circuitry. Pin 10 and 15 are internally connected. Connect at least pin 10 externally to pin 9. Pin 15 can be floating. 11 VOUT O 12 VC Supply Gate driver supply. Connect to VCC2. 13 VCC2 Supply Most positive output supply potential 14 DESAT I 16 VE Ground Not connected Gate drive output voltage Desaturation voltage input Gate drive common. Connect to IGBT Emitter. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 3 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC1 Total output supply voltage, VOUT(total) (VCC2 - VEE-P) Positive output supply voltage, VOUT+ (VCC2 - VE) Negative output supply voltage, VOUT- (VE - VEE-P) MIN MAX UNIT -0.5 6 V -0.5 35 V -0.5 35 - (VE - VEE-P) V V -0.5 VCC2 VE - 0.5 VCC2 VIN+, VIN-, RESET, FAULT -0.5 6 Vo(peak) -0.5 VCC2 V -0.5 VCC2 V 2.8 A FAULT output current, IFL 20 mA Maximum junction temperature, TJ 170 C 150 C DESAT Voltage at Peak gate drive output voltage Collector voltage, VC Output current , IO (1) Storage temperature, Tstg (1) -65 V Maximum pulse width = 10 s, maximum duty cycle = 0.2%. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT 4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1500 Machine model JEDEC JESD22-A115-A 200 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC1 Supply voltage VOUT(total) NOM MAX UNIT 3 5.5 V Total output supply voltage (VCC2 - VEE-P) 15 30 V VOUT+ Positive output supply voltage (VCC2 - VE) 15 30 - (VE - VEE-P) V VOUT- Negative output supply voltage (VE - VEE-P) 0 15 V VC Collector voltage VEE-P + 8 VCC2 V tui Input pulse width 0.1 tuiR RESET Input pulse width 0.1 VIH High-level input voltage (VIN+, VIN-, RESET) 2 VIL Low-level input voltage (VIN+, VIN-, RESET) 0 fINP Input frequency VSUP_SR Supply Slew Rate (VCC1 or VCC2 - VEE-P) TJ Junction temperature -40 TA Ambient temperature -40 (1) (2) 4 s s VCC 0.8 (2) 25 V V 520 (1) kHz 75 V/ms 150 C 125 C If TA = 125C, VCC1= 5.5 V, VCC2 = 30 V, RG = 10 , CL = 1 nF If VCC1 skew is faster than 75 V/ms (especially for the falling edge) then VCC2 must be powered up after VCC1 and powered down before VCC1 to avoid output glitches. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 6.4 Thermal Information ISO5500 THERMAL METRIC (1) JA Junction-to-ambient thermal resistance 76 JCtop Junction-to-case (top) thermal resistance 34 JB Junction-to-board thermal resistance 36 JT Junction-to-top characterization parameter 8 JB Junction-to-board characterization parameter TSHDN+ TSHDN- UNIT DW (SOIC) 16 PINS C/W 35 Thermal Shutdown 185 C 173 C TSHDN-HYS Thermal Shutdown Hysteresis 12 C PD Power Dissipation See Equation 2 through Equation 6 592 mW (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics All typical values are at TA = 25C, VCC1 = 5 V, VCC2 - VE = 30 V, VE - VEE-P = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent MIN TYP MAX VI = VCC1 or 0 V, No load, See Figure 1, Figure 2, Figure 28, and Figure 29 5.5 8.5 5.7 8.7 VI = VCC1 or 0 V, No load, See Figure 3 through Figure 5, Figure 30, and Figure 31 8.4 12 9 14 ICC1 Supply current ICC2 Supply current ICH High-level collector current ICL Low-level collector current See Figure 27 and Figure 31 IEH VE High-level supply current See Figure 6 and Figure 40 -0.5 -0.3 IEL VE Low-level supply current See Figure 6 and Figure 41 -0.8 -0.53 IIH High-level input leakage IIL Low-level input leakage IFH High-level FAULT pin output current VFAULT = VCC1, no pull-up, See Figure 33 IFL Low-level FAULT pin output current VFAULT = 0.4 V, no pull-up, See Figure 34 VIT+(UVLO) Positive-going UVLO threshold voltage VIT-(UVLO) Negative-going UVLO threshold voltage VHYS UVLO Hysteresis voltage (VIT+ - VIT-) (UVLO) IOH 300 kHz Quiescent 300 kHz High-level output current IOL Low-level output current IOF Output-low fault current VOH High-level output voltage IOUT = 0, See Figure 27 and Figure 30 1.3 IOUT = -650 A, See Figure 27 and Figure 30 1.9 IN from 0 to VCC VOUT = VCC2 - 4 V (1), See Figure 7 and Figure 35 VOUT = VCC2 - 15 V (2), See Figure 7 and Figure 35 10 5 12 11.6 12.3 13.5 11.1 12.4 0.7 1.2 -1 -1.6 VOUT = VEE-P + 15 V (2), See Figure 8 and Figure 36 2.5 VOUT - VEE-P = 14 V, See Figure 9 and Figure 37 90 140 VC-1.5 VC-0.8 VC-0.15 VC-0.05 Low-level output voltage IOUT = 100 mA, See Figure 12, Figure 13 and Figure 39 ICHG Blanking capacitor charging current VDESAT = 0 V to 6 V, See Figure 14 and Figure 42 IDSCHG Blanking capacitor discharge current VDESAT = 8 V, See Figure 42 mA A A mA V A 1 IOUT = -650 A, See Figure 10, Figure 11 and Figure 38 mA -2.5 VOUT = VEE-P + 2.5 V (1), See Figure 8 and Figure 36 IOUT = -100 mA, See Figure 10, Figure 11 and Figure 38 mA mA -10 -10 mA mA 10 See Figure 32 VOL (1) (2) 0.4 UNIT 1.8 A 230 mA V 0.2 0.5 V -180 -270 -380 A 20 45 mA Maximum pulse width is 50 s, maximum duty cycle is 0.5% Maximum pulse width is 10 s, maximum duty cycle is 0.2% Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 5 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com Electrical Characteristics (continued) All typical values are at TA = 25C, VCC1 = 5 V, VCC2 - VE = 30 V, VE - VEE-P = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS VDSTH DESAT threshold voltage (VCC2 - VE) > VTH-(UVLO), See Figure 15 and Figure 42 CMTI Common mode transient immunity VI = VCC1 or 0 V, VCM at 1500 V, See Figure 43 though Figure 46 MIN TYP MAX 6.7 7.2 7.7 25 50 UNIT V kV/S 6.6 Switching Characteristics All typical values are at TA = 25C, VCC1 = 5 V, VCC2 - VE = 30 V, VE - VEE-P = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation Delay tsk-p Pulse Skew |tPHL - tPLH| tsk-pp Part-to-part skew (1) tsk2-pp Part-to-part skew (2) tr Output signal rise time tf Output signal fall time tDESAT RG = 10 , CG = 10 nF, 50 % duty cycle, 10 kHz input, VCC2 - VEE = 30 V, VE - VEE = 0 V, See Figure 16 through Figure 19, Figure 26, Figure 47, Figure 49, and Figure 50 (90%) DESAT sense to 90% VOUT delay tDESAT (10%) DESAT sense to 10% VOUT delay tDESAT (FAULT) DESAT sense to FAULT low output delay tDESAT (LOW) DESAT sense to DESAT low propagation delay tRESET (FAULT) RESET to high-level FAULT signal delay tUVLO tUVLO MAX UNIT 200 300 ns 1.7 10 ns 45 ns 50 ns -50 55 ns 10 RG = 10 , CG = 10 nF, VCC2 - VEE-P = 30 V, VE - VEE-P = 0 V, See Figure 20 through Figure 25, Figure 48 and Figure 51 ns 300 550 ns 1.8 2.3 s 290 550 ns 180 3 8.2 ns 13 s UVLO to VOUT high delay 1ms ramp from 0 V to 30 V 4 s (OFF) UVLO to VOUT low delay 1ms ramp from 30 V to 0 V 6 s 2.8 s Failsafe output delay time from input power loss tsk-pp is the maximum difference in same edge propagation delay times (either VIN+ to VOUT or VIN- to VOUT) between two devices operating at the same supply voltage, same temperature, and having identical packages and test circuits. i.e. max (2) TYP 150 (ON) tFS (1) MIN ( ( ie i etP HL-ma x VCC1, VCC2, TA i i eetP LH-ma x VCC1, VCC2, TA i ))- ( ( ) ) tPHL -m in VCC1, VCC2,TA uu,iu y tPL H-m in VCC1, VCC2,TA uu i tsk2-pp is the propagation delay difference in high-to-low to low-to-high transition ( any of the combinations VIN+ to VOUT or VIN- to VOUT) between two devices operating at the same supply voltage, same temperature, and having identical packages and test circuits. i.e. min = tPHL-min (VCC1, VCC2,TA ) - tPLH-max (VCC1 ,VCC2 ,TA ) max = tP HL -ma x (VCC1, VCC2,TA ) - tPL H-min (VCC1, VCC2,TA ) 6 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 6.7 Typical Characteristics 8 7 ICC1 - Supply Current (mA) ICC1 - Supply Current (mA) 7 6 5 4 3 2 VCC1 = 4.5 V VCC1 = 5 V VCC1 = 5.5 V VCC1 = 3 V VCC1 = 3.3 V VCC1 = 3.6 V 1 0 -40 -20 0 40 20 60 80 100 120 6 5 4 3 2 VCC1 = 3.3 V VCC1 = 5 V 1 0 140 100 50 o Ambient Temperature ( C) Figure 1. VCC1 Supply Current vs. Temperature 250 300 12 No Load ICC2 - Supply Current (mA) 11 ICC2 - Supply Current (mA) 200 Figure 2. VCC1 Supply Current vs. Frequency 12 10 9 8 7 6 VCC2 = 15 V VCC2 = 20 V VCC2 = 30 V 5 4 -40 -20 0 40 20 60 80 100 120 11 10 9 8 VCC2 = 15 V VCC2 = 20 V VCC2 = 30 V 7 6 0 140 100 50 o Ambient Temperature ( C) Figure 3. VCC2 Supply Current vs. Temperature 250 300 Figure 4. VCC2 Supply Current vs. Frequency IEH, IEL - Supply Current (mA) fINP = 20 kHz 50 40 30 20 10 VCC2 = 15 V VCC2 = 30 V 0 -0.1 -0.2 -0.3 -0.4 -0.5 IEH, VE - VEE = 0 V IEH, VE - VEE = 15 V IEL, VE - VEE = 0 V IEL, VE - VEE = 15 V -0.6 -0.7 -0.8 0 200 0 RG = 10 W 60 150 Input Frequency (KHz) 70 ICC2 - Supply Current (mA) 150 Input Frequency (KHz) 20 40 60 80 100 -20 -40 0 20 40 60 80 100 120 140 o Load Capacitance (nF) Ambient Temperature ( C) Figure 5. VCC2 Supply Current vs. Load Capacitance Figure 6. VE Supply Current vs. Temperature Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 7 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) 8 IOL - Output Sink Current (A) IOH - Output Drive Current (A) 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 VOUT = VC - 4 V VOUT = VC - 15 V -4.5 -5 -40 -20 0 40 20 60 80 100 120 VOUT = 2.5 V VOUT = 15 V 7 6 5 4 3 2 1 0 -40 140 -20 0 Figure 7. Output Drive Current vs. Temperature VOH - VC - High Output Voltage Drop (V) IOF - Output Sink Current During a Fault Condition (mA) 140 130 120 110 100 TA = -40oC TA = 25oC TA = 125oC 0 10 5 15 20 25 30 28 27.5 27 26.5 26 25.5 25 8 0.2 0.4 0.6 0.8 1 140 -0.1 -0.3 -0.5 -0.7 -0.9 -1.1 IOUT = -650 mA IOUT = -100 mA -1.3 -1.5 -40 -20 0 20 40 60 80 100 120 140 1.2 1.4 1.5 Figure 10. High Output Voltage Drop vs. Temperature 0.35 IOUT = 100 mA VOL - Low Output Voltage (V) VOH - High Output Voltage (V) 28.5 0 120 o TA = -40oC TA = 25oC TA = 125oC 29 100 Ambient Temperature ( C) Figure 9. Output Sink Current During a Fault Condition vs. Output Voltage 30 80 0.1 Output Voltage (V) 29.5 60 Figure 8. Output Sink Current vs. Temperature 150 80 40 Ambient Temperature ( C) 160 90 20 o o Ambient Temperature ( C) 0.3 0.25 0.2 0.15 0.1 -40 -20 0 20 40 60 80 100 120 140 o Output Drive Current (A) Ambient Temperature ( C) Figure 11. High Output Voltage vs. Output Drive Current Figure 12. Low Output Voltage vs. Temperature Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 Typical Characteristics (continued) -0.15 ICHG - Blanking Capacitor Charging Current (mA) VOL - Low Output Voltage (V) 6 5 4 3 2 TA = -40oC TA = 25oC TA = 125oC 1 0 0 1 0.5 1.5 -0.21 -0.23 -0.25 -0.27 -0.29 -0.31 -0.33 -0.35 -40 2.5 2 -0.17 -0.19 -20 0 60 240 7.7 Propagation Delay (ns) 7.5 7.3 7.1 6.9 0 40 20 60 140 CL = 10 nF 220 210 200 tPLH at VCC1 = 3.3 V tPHL at VCC1 = 3.3 V tPLH at VCC1 = 5 V tPHL at VCC1 = 5 V 190 6.7 -20 120 RG = 10 W, 230 6.5 -40 100 80 Figure 14. Blanking Capacitance Charging Current vs. Temperature 7.9 VDSTH - Desat Threshold (V) 40 o Figure 13. Low Output Voltage vs. Output Sink Current 80 100 120 180 -40 140 -20 0 o 40 20 60 100 80 120 140 o Ambient Temperature ( C) Ambient Temperature ( C) Figure 15. DESAT Threshold vs. Temperature Figure 16. Propagation Delay vs. Temperature 225 230 RG = 10 W, 225 CL = 10 nF Propagation Delay (ns) 220 Propagation Delay (ns) 20 Ambient Temperature ( C) Output Sink Current (A) 215 210 205 tPLH tPHL CL = 10 nF 220 215 210 205 tPLH at VCC1 = 3.3 V tPHL at VCC1 = 3.3 V tPLH at VCC1 = 5 V tPHL at VCC1 = 5 V 200 195 200 3 RG = 10 W, 3.5 4 4.5 5 5.5 190 14 VCC1 Supply Voltage (V) 16 18 20 22 24 26 28 30 VCC2 Supply Voltage (V) Figure 17. Propagation Delay vs. VCC1 Supply Voltage Figure 18. Propagation Delay vs. VCC2 Supply Voltage Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 9 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) 450 RG = 10 W Propagation Delay (ns) 1200 1000 800 600 400 tPLH at VCC1 = 3.3 V tPHL at VCC1 = 3.3 V tPLH at VCC1 = 5 V tPHL at VCC1 = 5 V 200 0 0 10 20 30 40 50 60 70 80 90 Desat Sense to 90% VOUT Delay (ns) 1400 100 CL = 10 nF 350 300 250 200 VCC2 = 15 V VCC2 = 30 V 150 -40 -20 0 60 80 100 120 140 o Figure 19. Propagation Delay vs. Load Capacitance Figure 20. DESAT Sense to 90% VOUT Delay vs Temperature 2.5 Desat Sense to 10% VOUT Delay (ms) RG = 10 W 1400 1200 1000 800 600 400 VCC2 = 15 V VCC2 = 30 V 200 0 10 20 30 40 50 70 60 80 90 100 RG = 10 W, 2 CL = 10 nF 1.5 1 0.5 VCC2 = 15 V VCC2 = 30 V 0 -40 -20 0 20 40 60 80 100 120 140 o Ambient Temperature ( C) Load Capacitance (nF) Figure 21. DESAT Sense to 90% VOUT Delay vs Load Capacitance Figure 22. DESAT Sense to 10% VOUT Delay vs Temperature 450 18 RG = 10 W 15 Desat Sense to Fault Low Delay (ns) Desat Sense to 10% VOUT Delay (ms) 40 Ambient Temperature ( C) 0 14 12 10 8 6 4 VCC2 = 15 V VCC2 = 30 V 2 0 0 10 20 30 40 50 60 70 80 90 100 400 350 300 250 200 150 -40 VCC2 = 15 V VCC2 = 30 V -20 0 20 40 60 80 100 120 140 o Ambient Temperature ( C) Load Capacitance (nF) Figure 23. DESAT Sense to 10% VOUT Delay vs Load Capacitance 10 20 Load Capacitance (nF) 1600 Desat Sense to 90% VOUT Delay (ns) RG = 10 W, 400 Figure 24. DESAT Sense to Fault Low Delay vs Temperature Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 Typical Characteristics (continued) 10 VCC2 - VEE = 30 V R G = 0 W, 9 CL = 10 nF 8.5 8 7.5 7 VCC1 = 3 V VCC1 = 3.3 V VCC1 = 3.6 V VCC1 = 4.5 V VCC1 = 5 V VCC1 = 5.5 V 6.5 6 5.5 5 -40 -20 0 20 40 60 100 80 120 5 V / div Reset to Fault Delay (ms) 9.5 140 o Ambient Temperature ( C) Time 125 ns / div Figure 26. Output Waveform Figure 25. Reset to Fault Delay vs Temperature ICH, ICL - Supply Current (mA) 3 2.5 2 1.5 ICH, IOUT = -500 mA ICH, IOUT = -1 mA ICL, IOUT = -1 mA ICL, IOUT = -2 mA 1 0.5 0 -40 -20 0 20 40 60 80 100 120 140 o Ambient Temperature ( C) Figure 27. VC Supply Current vs. Temperature Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 11 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com 7 Parameter Measurement Information 5.5 V 2 3 4 5 6 7 8 1 VE 16 VIN+ 5.5 V VEE-L 15 VINVCC1 1 FAULT 6 VOUT 11 7 VEE-L 10 NC GND1 8 VEE-P 9 5V 2 3 4 5 6 7 8 VIN- VEE-L VCC1 GND1 DESAT VCC2 15 14 12 RESET VC FAULT VOUT NC VEE-L 10 GND1 VEE-P 1 VIN+ VE 2 VIN- VEE-L 3 VCC1 4 GND1 5 RESET VC 6 FAULT VOUT 7 NC VEE-L 8 GND1 VEE-P ICC2 5V 0.1 F 2 3 4 5 6 7 8 VIN+ VE VIN- VEE-L VCC1 GND1 RESET DESAT VCC2 VC FAULT VOUT NC VEE-L GND1 VEE-P VCC2 30 V 11 0.1 F IOUT 9 1 16 15 14 0.1 F 5.5 V 0.1 F 13 4 0.1 F 5 12 11 VOUT 2 3 V1 Sweep 0.1 F VEE-L 15 DESAT 14 VCC2 13 RESET VC 12 FAULT VOUT 11 NC VEE-L 10 GND1 VEE-P 9 16 15 14 ICC2 13 IC 12 11 0.1 F 30 V 10 9 Figure 31. ICC2L, ICL Test Circuit V2 5.5 V 6 IFAULT 10 7 9 8 Figure 32. VIT(UVLO) Test Circuit 12 DESAT IC Figure 30. ICC2H, ICH Test Circuit 1 VIN- Figure 29. ICC1L Test Circuit 16 13 VE 16 GND1 5 VC 12 VIN+ VCC1 4 VCC2 13 RESET VE 2 DESAT 14 GND1 VIN+ 0.1 F 3 Figure 28. ICC1H Test Circuit 0.1 F ICC1 0.1 F ICC1 1 Submit Documentation Feedback VIN+ VE VIN- VEE-L VCC1 GND1 DESAT VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 15 14 13 12 11 30 V 0.1 F 10 9 Figure 33. IFH Test Circuit Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 Parameter Measurement Information (continued) 1 0.1 F 3V 2 3 4 5 0.4 V 6 IFAULT 7 8 VE VIN+ VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET FAULT VC 16 15 NC VEE-L GND1 VEE-P 5V 3 13 4 12 5 6 0.1 F 30 V 10 7 9 8 Figure 34. IFL Test Circuit 1 VE VIN+ VEE-L 3 VCC1 4 GND1 5 RESET VC 6 FAULT VOUT 7 NC VEE-L 10 8 GND1 VEE-P DESAT VCC2 5V 0.1 F 1 5V 2 3 4 5 6 7 8 VIN+ VINVCC1 GND1 VIN- VEE-L GND1 VOUT NC VEE-L GND1 VEE-P 2 4 5 12 VPULSE 0.1 F 4.7 F 6 IOUT 7 8 9 VE VEE-L DESAT VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 1 15 5V 0.1 F 14 4 0.1 F 5 30 V 11 10 2 3 13 12 16 15 14 13 VPULSE 12 30 V 11 10 0.1 F 4.7 F IOUT 9 VIN+ VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 15 14 13 0.1 F 12 11 10 IOUT 30 V 14 V 9 Figure 37. IOF Test Circuit 16 VOUT VC FAULT 13 11 VCC2 RESET 3 30 V DESAT VCC1 14 Figure 36. IOL Test Circuit 0.1 F VE 1 15 VIN- VIN+ Figure 35. IOH Test Circuit 16 2 2 14 11 VOUT 1 0.1 F 6 7 IOUT 9 8 Figure 38. VOH Test Circuit VIN+ VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 15 14 13 12 100 mA 0.1 F 30 V 11 VOUT 10 9 Figure 39. VOL Test Circuit Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 13 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com Parameter Measurement Information (continued) 1 0.1 F 5V 2 3 4 5 6 7 8 VIN+ VE VIN- VEE-L GND1 1 15 0.1 F 0.1 F 5V 2 3 V1 VCC2 RESET IE 14 DESAT VCC1 16 VC 13 12 5 0.1 F 11 FAULT VOUT NC VEE-L GND1 VEE-P 4 0.1 F V2 6 10 7 9 8 Figure 40. IEH Test Circuit 1 5V 0.1 F 2 3 4 5 6 7 8 VE VIN+ VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 15 1 0.1 F 5V 0.1 F 2 3 14 13 V1 IDESAT 4 0.1 F 12 5 3k V2 0.1 F 11 VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 IE 15 0.1 F 14 V1 13 0.1 F 12 0.1 F 11 V2 10 9 Figure 41. IEL Test Circuit 16 SWEEP VIN+ 6 SCOPE 7 10 100 pF 8 9 VIN+ VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 15 14 13 12 0.1 F 11 10 9 4.7 F 30 V 4.7 F 30 V 10 W 10 nF VCM Figure 42. ICHG, IDSCHG, VDSTH Test Circuit 1 5V 0.1 F 2 3 4 3k 5 6 SCOPE 100 pF 7 8 VIN+ VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P Figure 43. CMTI VFH Test Circuit 1 16 15 5V 0.1 F 2 14 3 13 4 12 11 10 9 5 3k 0.1 F 4.7 F 30 V 6 7 100 pF 10 W 8 10 nF VCM VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 15 14 13 12 SCOPE 0.1 F 11 10 9 10 W 10 nF VCM Figure 44. CMTI VFL Test Circuit 14 VIN+ Figure 45. CMTI VOH Test Circuit Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 Parameter Measurement Information (continued) 1 0.1 F 5V 2 3 4 5 3k 6 7 100 pF 8 VIN+ VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 1 VIN 15 2 GND1 14 3 13 12 5V SCOPE 0.1 F 11 10 4.7 F 3k 9 6 8 10 nF VEE-L DESAT VCC2 RESET 7 10 W VIN- GND1 5 30 V VE VCC1 4 0.1 F VIN+ VC FAULT VOUT NC VEE-L GND1 VEE-P 16 15 14 13 VOUT 12 0.1 F V1 4.7 F 11 10 W 10 10 nF 9 VCM Figure 46. CMTI VOL Test Circuit 1 VIN 2 3 4 5 6 5V 3k 0.1 F 7 8 VIN+ VE VIN- VEE-L VCC1 GND1 RESET DESAT VCC2 VC FAULT VOUT NC VEE-L GND1 VEE-P Figure 47. tPLH, tPHL, tr, tf Test Circuit 16 15 100 pF 12 0V VIN+ 50 % 0.1 F 14 0.1 F V1 DESAT 13 VIN- 50 % tr tf VOUT 0.1 F 4.7 F 90% V2 11 10 50% 10 W 10 nF 9 VOUT 10% tPLH Figure 48. tDESAT, tRESET Test Circuit tPHL Figure 49. VOUT Propagation Delay, Non-inverting Configuration A. VIN- tDESAT (FAULT ) tDESAT (10%) 50 % 50 % 7.2V VDESAT VIN+ VCC1 tDESAT (LOW) 50% tDESAT (90%) tr VOUT tf 90% 10% 90% FAULT 50 % 50 % 50% VOUT 10% tPLH tRESET (FAULT ) RESET 50% tPHL Figure 50. VOUT Propagation Delay, Inverting Configuration Figure 51. DESAT, VOUT, FAULT, RESET Delays Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 15 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The ISO5500 is an isolated gate driver for IGBTs and MOSFETs with power ratings of up to IC = 150 A and VCE = 600 V. Input TTL logic and output power stage are separated by a capacitive, silicon dioxide (SiO2), isolation barrier. The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET inputs, and FAULT alarm output. The power stage consists of power transistors to supply 2.5 A pullup and pulldown currents to drive the capacitive load of the external power transistors, as well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5500 also contains undervoltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and soft turnoff feature which ensures graceful reduction in IGBT current to zero when a short-circuit is detected. 8.2 Functional Block Diagram ISO5500 VREG VCC1 VCC2 - VIN+ UVLO + ISO - Barri er V INDELAY FAULT Gate Drive VC DESAT + DESAT - 12 .3V and 7.2 V Fault Logic Q1b Q1a Q4 VOUT Q S VE R RESET Q3 Q2b Q2a VEE-P GND1 VEE-L 16 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 8.3 Feature Description Table 1. Package Characteristics PARAMETER TEST CONDITIONS (1) UNIT 8.1 mm 0.012 mm L(I02) Minimum external tracking (creepage (1)) Shortest terminal to terminal distance across the package surface Minimum internal gap (internal clearance) Distance through the insulation Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 400 (2) RIO Isolation resistance Input to output, VIO = 500 V CIO Barrier capacitance input-to-output VIO = 0.4 sin (2ft), f = 1 MHz (2) CI Input capacitance to ground VI = VCC/2 + 0.4 sin (2 ft), f = 2 MHz, VCC = 5V (2) MAX mm Minimum air gap (clearance (1) TYP 8.3 L(I01) CTI ) MIN Shortest terminal to terminal distance through air V 12 1.25 pF 2 pF >10 Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.space Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the isolation glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase their specification. All pins on each side of the barrier tied together creating a two-terminal device 8.3.1 Insulation Characteristics for DW-16 Package Over recommended operating conditions (unless noted otherwise) PARAMETER VIORM TEST CONDITIONS SPECIFICATION Maximum working insulation voltage per DIN V VDE V 0884-10 (VDE V 0884-10) 679/480 After Input/Output safety test subgroup 2/3, VPR = 1.2 x VIORM, t = 10 sec, Partial discharge < 5 pC 816/576 Method a, After environmental tests subgroup 1, Input to output test voltage per DIN V VDE V VPR = 1.6 x VIORM, t = 10 sec (qualification) 0884-10 (VDE V 0884-10) Partial discharge < 5pC VPR VIOTM Transient overvoltage per DIN V VDE V 0884-10 (VDE V 0884-10) VISO Isolation voltage per UL 1577 RS Insulation resistance UNIT 1088/768 VPEAK/ VRMS Method b1, 100% Production test, VPR = 1.875 x VIORM, t = 1 sec Partial discharge < 5pC 1275/900 VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100% production) 6000/4243 VTEST = VISO, t = 60 sec (qualification) 6000/4243 VTEST = 1.2 x VISO, t = 1 sec (100% production) 7200/5092 VIO = 500 V at TS = 150C > 109 Pollution degree 2 8.3.2 Regulatory Information VDE CSA UL Certified according to DIN V VDE V 0884-10 (VDE V 0884-10) Approved under CSA Component Acceptance Notice 5A Recognized under 1577 Component Recognition Program Basic Insulation Maximum Transient Overvoltage, 6000 VPK Maximum Working Voltage, 680 VPK Basic and Reinforced Insulation per CSA 60950-1-07 and IEC 60950-1 (2nd Ed) Single Protection, 4243 VRMS Certificate Number: 40016131 Master Contract Number: 220991 File Number: E181974 (1) (1) Production tested 5092 VRMS for 1 second in accordance with UL 1577. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 17 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com 8.3.3 IEC 60664-1 Rating Table PARAMETER TEST CONDITIONS Basic Isolation Group SPECIFICATION Material Group Installation Classification II Rated Mains Voltage 300 VRMS I-IV Rated Mains Voltage 600 VRMS I-III 8.3.4 Isolation Lifetime at a Maximum Continuous Working Voltage PARAMETER Bipolar AC Voltage LIFETIME SPECIFICATION 20 years 679/480 25 years 657/465 50 years 601/425 UNIT VPEAK/VRMS 8.3.5 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS TS Safety Limiting Current TEST CONDITIONS MIN TYP MAX JA = 76C/W, VI = 3.6 V, TJ = 170C, TA = 25C 530 JA = 76C/W, VI = 5.5 V, TJ = 170C, TA = 25C 347 JA = 76C/W, VI = 30 V, TJ = 170C, TA = 25C 64 Case Temperature 150 UNIT mA C Safety Limiting Current - mA The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 600 500 VCC1 = 3.6V 400 300 VCC1 = 5.5V 200 VCC2 - VEE-P = 30 V 100 0 0 50 100 150 200 Case Temperature - oC Figure 52. DW-16 JC Thermal Derating Curve per DIN V VDE V 0884-10 (VDE V 0884-10) 18 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 8.3.6 Behavioral Model Figure 53 and Figure 54 show the detailed behavioral model of the ISO5500 for a non-inverting input configuration and its corresponding timing diagram for normal operation, fault condition, and Reset. +HV ISO5500 DESAT + 1 VIN+ PWM DIS - ISO CBLK 7.2V 270 A 2 VIN- 3 VCC1 DELAY 3.3V to 5V VCC2 - UVLO ISO - Barrie r C + 13 VREG 12.3V VC 12 Q1b 15V Q1a VOUT 11 6 FAULT I/P 14 FAULT Q S VE 16 Q3 Q2b 4,8 GND1 VREG Q2a 15V VEE-P VCC2 9 LOAD 5 RESET O/P R VEE-L 10,15 -HV Figure 53. ISO5500 Behavioral Model Normal Operation Fault Condition Reset VIN+ Normal Operation 5 ISO 4 7.2V VDESAT VOUT FAULT 3 lay De 2 1 DIS FAULT RESET 6 Figure 54. Complete Timing Diagram Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 19 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com 8.3.7 Power Supplies VCC1 and GND1 are the power supply input and output for the input side of the ISO5500. The supply voltage at VCC1 can range from 3 V up to 5.5 V with respect to GND1, thus supporting the direct interface to state-of-the-art 3.3 V low-power controllers as well as legacy 5 V controllers. VCC2, VEE-P and VEE-L are the power supply input and supply returns for the output side of the ISO5500. VEE-P is the supply return for the output driver and VEE-L is the return for the logic circuitry. With VEE-P as the main reference potential, VEE-L should always be directly connected to VEE-P. The supply voltage at VCC2 can range from 15 V up to 30 V with respect to VEE-P. A third voltage input, VE, serves as reference voltage input for the internal UVLO and DESAT comparators. VE also represents the common return path for the gate voltage of the external power device. The ISO5500 is designed for driving MOSFETs and IGBTs. Because MOSFETs do not require a negative gate-voltage, the voltage potential at VE with respect to VEE-P can range from 0 V for MOSFETs and up to 15 V for IGBTs. ISO5500 ISO5500 VCC2 VCC1 VCC2 +15 V 15V VC VCC1 +15 V VC 15 V-30 V GND1 Power Device Common VE 0 V-15 V GND1 ISOLATION 3 V - 5.5 V ISOLATION 3 V - 5.5 V Power Device Common VE 0 V-15 V -15 V 0-(-15 V) VEE-P VEE-P VEE-L VEE-L Figure 55. Power Supply Configurations The output supply configuration on the left uses symmetrical 15 V supplies for VCC2 and VEE-P with respect to VE. This configuration is mostly applied when deriving the output supply from the input supply via an isolated DCDC converter with symmetrical voltage outputs. The configuration on the right, having both supplies referenced to VEE-P, is found in applications where the device output supply is derived from the high-voltage IGBT supplies. 8.3.8 Control Signal Inputs The two digital, TTL control inputs, VIN+ and VIN-, allow for inverting and non-inverting control of the gate driver output. In the non-inverting configuration VIN+ receives the control input signal and VIN- is connected to GND1. In the inverting configuration VIN- is the control input while VIN+ is connected to VCC1. ISO5500 ISO5500 3 V - 5.5 V VCC1 PWM VIN+ VIN+ VCC1 VIN+ VCC1 3 V - 5.5 V GND1 GND1 VIN+ PWM VIN- ISOLATION VIN- ISOLATION VINVIN- GND1 VOUT VOUT Figure 56. Non-inverting (left) and Inverting (right) Input Configurations 20 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 8.3.9 Output Stage The output stage provides the actual IGBT gate drive by switching the output voltage pin, VOUT, between the most positive potential, typically VCC2, and the most negative potential, VEE-P. VCC2 ISO5500 VC VIN+ Q1b 15V Q1a 30V On VOUT VOUT Gate Drive Q1 Q3 Q2 VE Q3 Slow Off Q2 0V VGE Off Q1 Q2b +15V Q2a 15V VE VEE-P VE VGE -15V VEE-L Figure 57. Output Stage Design and Timing This stage consists of an upper transistor pair (Q1a and Q1b) turning the IGBT on, and a lower transistor pair (Q2a and Q2b) turning the IGBT off. Each transistor pair possesses a bipolar transistor for high current drive and a MOSFET for close-to-rail switching capability. An additional, weak MOSFET (Q3) is used to softly turn-off the IGBT in the event of a short circuit fault to prevent large di/dt voltage transients which potentially could damage the output circuitry. The output control signals, On, Off, and Slow-Off are provided by the gate-drive and fault-logic circuit which also includes a break-before-make function to prevent both transistor pairs from conducting at the same time. By introducing the reference potential for the IGBT emitter, VE, the final IGBT gate voltage, VGE, assumes positive and negative values with respect to VE. A positive VGE of typically 15 V is required to switch the IGBT well into saturation while assuring the survival of short circuit currents of up to 5-10 times the rated collector current over a time span of up to 10 s. Negative values of VE, ranging from a required minimum of -5 V up to a recommended -15 V, are necessary to keep the IGBT turned off and to prevent it from unintentional conducting due to noise transients, particularly during short circuit faults. As previously mentioned, MOSFETs do not require a negative gate-voltage and thus allow the VE-pin to be directly connected to VEE-P. The timing diagram in Figure 57 shows that during normal operation VOUT follows the switching sequence of VIN+ (here shown for the non-inverting input configuration), and only the Q1 and Q2 transistor pairs applying VCC2 and VEE-P potential to the VOUT-pin respectively. In the event of a short circuit fault, however, while the IGBT is actively driven, the Q1 pair is turned off and Q3 turns on to slowly reduce VOUT in a controlled manner down to a level of approximately 2 V above VEE-P. At this voltage level, the strong Q2 pair then conducts holding VOUT at VEE-P potential. 8.3.10 Undervoltage Lockout (UVLO) The Under Voltage Lockout feature prevents the application of insufficient gate voltage (VGE-ON) to the power device by forcing VOUT low (VOUT = VEE-P) during power-up and whenever else VCC2 - VE drops below 12.3 V. IGBTs and MOSFETs typically require gate voltages of VGE = 15 V to achieve their rated, low saturation voltage, VCES. At gate voltages below 13 V typically, their VCE-ON increases drastically, especially at higher collector currents. At even lower voltages, i.e. VGE < 10 V, an IGBT starts operating in the linear region and quickly overheats. Figure 58 shows the principle operation of the UVLO feature. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 21 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com VCC2 VCC2 - UVLO On 11.1V 2V VC + 12.3V 15V VIN+ Gate Drive 12.3V Q1b Q1a VOUT VGE VE VOUT Failsafe Low Q1 Q2 Q1 Q2 Q1 0V R PD Q2 Off Q2b 15V Q2a VEE-P ISO5500 VE +15V VE VGE VEE-L -15V Figure 58. Undervoltage Lockout (UVLO) Function Because VCC2 with respect to VE represents the gate-on voltage, VGE-ON = VCC2 - VE, the UVLO comparator compares VCC2 to a 12.3 V reference voltage that is also referenced to VE via the connection of the ISO5500 VEpin to the emitter potential of the power device. The comparator hysteresis is 1.2 V typical and the typical values for the positive and negative going input threshold voltages are VTH+ = 12.3 V and VTH- = 11.1 V. The timing diagram shows that at VCC2 levels below 2 V VOUT is 0 V. Because none of the internal circuitry operates at such low supply levels, an internal 100 k pull-down resistor is used to pull VOUT down to VEE-P potential. This initial weak clamping, known as failsafe-low output, strengthens with rising VCC2. Above 2 V the Q2-pair starts conducting gradually until VCC2 reaches 12.3 V at which point the logic states of the control inputs VIN+ and VIN- begin to determine the state of VOUT. Another UVLO event takes place should VCC2 drop slightly below 11 V while the IGBT is actively driven. At that moment the UVLO comparator output causes the gate-drive logic to turn off Q1 and turn on Q2. Now VOUT is clamped hard to VEE-P. This condition remains until VCC2 returns to above 12.3 V and normal operation commences. NOTE An Undervoltage Lockout does not indicate a Fault condition. 8.3.11 Desaturation Fault Detection (DESAT) The DESAT fault detection prevents IGBT destruction due to excessive collector currents during a short circuit fault. Short circuits caused by user misconnect, bad wiring, or overload conditions induced by the load can cause a rapid increase in IGBT current, leading to excessive power dissipation and heating. IGBTs become damaged when the current load approaches the saturation current of the device and the collector-emitter voltage, VCE, rises above the saturation voltage level, VCE-sat. The drastically increased power dissipation overheats and destroys the IGBT. To prevent damage to IGBT applications, the implemented fault detection slowly reduces the overcurrent in a controlled manner during the fault condition. 22 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 VCC2 VC ISO5500 15V DESAT + VIN+ DESAT - CBLK On Gate Drive 7.2V Q4 Q1a Q1b VOUT Dschg 7.2V VDESAT VCE Q4 VOUT VE Fault Off Slow Off Q3 Q2b 15V Q2a Fault VEE-P VEE-L Figure 59. DESAT Fault Detection and Protection The DESAT fault detection involves a comparator that monitors the IGBT's VCE and compares it to an internal 7.2 V reference. If VCE exceeds this reference voltage, the comparator causes the gate-drive and fault-logic to initiate a fault shutdown sequence. This sequence starts with the immediate generation of a fault signal, which is transmitted across the isolation barrier towards the Fault indicator circuit at the input side of the ISO5500. At the same time the fault logic turns off the power-pair Q1 and turns on the small discharge MOSFETs, Q3 and Q4. Q3 slowly discharges the IGBT gate voltage which causes the high short-circuit current through the IGBT to gradually decrease, thereby preventing large di/dt induced voltage transients. Q4 discharges the blanking capacitor. Once VOUT is sufficiently close to VEE-P potential (at approximately 2 V), the large Q2-pair turns on in addition to Q3 to clamp the IGBT gate to VEE-P. NOTE The DESAT detection circuit is only active when the IGBT is turned on. When the IGBT is turned off, and its VCE is at maximum, the fault detection is simply disabled to prevent false triggering of fault signals. 8.3.12 DESAT Blanking Time The DESAT fault detection must remain disabled for a short time period following the turn-on of the IGBT to allow its collector voltage to drop below the 7.2 V DESAT threshold. This time period, called the DESAT blanking time, tBLK, is controlled by an internal charge current of ICHG = 270 A, the 7.2 V DESAT threshold, VDSTH, and an external blanking capacitor, CBLK. The nominal blanking time with a recommended capacitor value of CBLK = 100 pF is calculated with: tBL K = CBL K VDSTH ICHG = 100 pF 7.2 V 270 A = 2.7 s (1) The capacitor value can be scaled slightly to adjust the blanking time. However, because the blanking capacitor and the DESAT diode capacitance build a voltage divider that attenuates large voltage transients at DESAT, CBLK values smaller than 100 pF are not recommended. The nominal blanking time also represents the ISO5500 maximum response time to a DESAT fault condition. If a short circuit condition exists prior to the turn-on of the IGBT, (causing the IGBT switching into a short) the soft shutdown sequence begins after approximately 3 s. However, if a short circuit condition occurs while the IGBT is already on, the response time is significantly shorter due to the parasitic parallel capacitance of the DESAT diode. The recommended value of 100 pF however, provides sufficient blanking and fault response times for most applications. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 23 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com The timing diagram in Figure 59 shows the DESAT function for both, normal operation and a short-circuit fault condition. The use of VIN+ as control input implies non-inverting input configuration. During normal operation VDESAT will display a small sawtooth waveform every time VIN+ goes high. The ramp of the sawtooth is caused by the internal current source charging the blanking capacitor. Once the IGBT collector has sufficiently dropped below the capacitor voltage, the DESAT diode conducts and discharges CBLK through the IGBT. In the event of a short circuit fault; however, high IGBT collector voltage prevents the diode from conducting and the voltage at the blanking capacitor continues to rise until it reaches the DESAT threshold. When the output of the DESAT comparator goes high, the gate-drive and fault-logic circuit initiates the soft shutdown sequence and also produces a Fault signal that is fed back to the input side of the ISO5500. 8.3.13 FAULT Alarm The Fault alarm unit consists of three circuit elements, a RS flip-flop to store the fault signal received from the gate-drive and fault-logic, an open-drain MOSFET output signaling the fault condition to the micro controller, and a delay circuit blocking the control inputs after the soft shutdown sequence of the IGBT has been completed. Figure 60 shows the ISO5500 in a non-inverting input configuration. Because the FAULT-pin is an open-drain output, it requires a pull-up resistor, RPU, in the order of 3.3 k to 10 k. The internal signals DIS, ISO, and FAULT represent the input-disable signal, the isolator output signal, and the fault feedback signal respectively. VCC1 3.3V ISO5500 VIN+ DIS ISO ISO ISO - Barrier VINRPU FAULT Q S Sh oc ort cu rs 4 FAULT 3 lay De DELAY I/P 5 VIN+ PWM C "IGBT On" 2 1 DIS FAULT R O/P RESET GND1 FAULT RESET 6 Figure 60. Fault Alarm Circuitry and Timing Sequence The timing diagram shows that the micro controller initiates an IGBT-on command by taking VIN+ high. After propagating across the isolation barrier ISO goes high, activating the output stage. 1. Upon a short circuit condition the gate-drive and fault-logic feeds back a fault signal (FAULT = high) which sets the RS-FF driving the FAULT output active-low. 2. After a delay of approximately 3 s, the time required to shutdown the IGBT, DIS becomes high and blocks the control inputs 3. This in turn drives ISO low 4. which, after propagating through the output fault-logic, drives FAULT low. At this time both flip-flop inputs are low and the fault signal is stored. 5. Once the failure cause has been removed the micro controller must set the control inputs into an "Outputlow" state before applying the Reset pulse. 6. Taking the RESET-input low resets the flip-flop, which removes the fault signal from the controller by pulling FAULT high and releases the control inputs by driving DIS low 24 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 8.4 Device Functional Modes Table 2. Function Table VIN+ VIN- UVLO (VCC2 - VE) DESAT DETECTED ON PIN 14 (DESAT) PIN 6 (FAULT) OUTPUT VOUT X X Active X X Low X X X Yes Low Low Low X X X X Low X High X X X Low High Low Not active No High High Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 25 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ISO5500 is an isolated gate driver for high power devices such as IGBTs and MOSFETs with power ratings of up to IC = 150 A and VCE = 600 V. It is intended for use in applications such as motor control, industrial inverters and switched-mode power supplies. In these applications, sophisticated PWM control signals are required to turn the power-devices on and off, which at the system level eventually may determine, for example, the speed, position, and torque of the motor or the output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a micro controller, and are at low voltage levels such as 3.3 V or 5.0 V. The gate controls required by the MOSFETs and IGBTs, on the other hand, are in the range of 15 V to 30 V, and need high current capability to be able to drive the large capacitive loads offered by those power transistors. Not only that, the gate drive needs to be applied with reference to the Emitter of the IGBT (Source for MOSFET), and by construction, the Emitter node in a gate drive system swings between 0 to the DC bus voltage, which is several 100s of volts in magnitude. The ISO5500 is thus used to level shift the incoming 3.3-V and 5.0-V control signals from the microcontroller to the 15-V to 30-V drive required by the power transistors while ensuring high-voltage isolation between the driver side and the microcontroller side. 9.2 Typical Application Figure 61 shows the typical application of a three-phase inverter using six ISO5500 isolated gate drivers. Threephase inverters are used for variable-frequency drives to control the operating speed of AC motors and for high power applications such as High-Voltage DC (HVDC) power transmission. The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5500 devices that are connected to one of the three load terminals. The operation of the three switches is coordinated so that one switch operates at each 60 degree point of the fundamental output waveform, thus creating a sixstep line-to-line output waveform. In this type of applications carrier-based PWM techniques are applied to retain waveform envelope and cancel harmonics. ISOLATION BARRIER PWM 3-PHASE INPUT 1 2 3 4 5 6 ISO 5500 ISO 5500 ISO 5500 ISO 5500 ISO 5500 ISO 5500 C M FAULT Figure 61. Typical Motor Drive Application 26 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 Typical Application (continued) 9.2.1 Design Requirements Unlike optocoupler based gate drivers which need external current drivers and biasing circuitry to provide the input control signals, the input control to the ISO5500 is TTL and can be directly driven by the microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a pullup resistor on the common drain FAULT output signal, and a high-voltage protection diode between the IGBT collector and the DESAT input. Further details are explained in the subsequent sections. 9.2.2 Detailed Design Procedure 9.2.2.1 Recommended ISO5500 Application Circuit The ISO5500 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 62 illustrates a typical gate drive implementation using the ISO5500. The four 0.1 F supply bypass capacitors provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, low current (20 mA) power supplies for VCC2 and VEE-P suffice. The 100 pF blanking capacitor disables DESAT detection during the off-to-on transition of the power device. The DESAT diode and its 100 series resistor are important external protection components for the fault detection circuitry. The 10 gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times. The open-drain fault output has a passive 3.3 k pull-up resistor and a 330pF filtering capacitor. In this application, the IGBT gate driver will shut down when a fault is detected and will not resume switching until the micro-controller applies a reset signal. 1 2 3 C 3.3V 3.3 k 0.1 F 4 5 6 330 pF 7 8 ISO5500 V IN+ V IN- VE VEE -L DESAT V CC1 GND1 V CC2 RESET FAULT VC VOUT NC VEE -L GND1 V EE-P 16 15 100 0.1 pF F 0.1 F DS (opt.) 100 14 D DESAT + 13 12 Q1 4.7 F + 15V VCE Rg 11 10 VF - 0.1 F Q2 15V 3-PHASE OUTPUT + 9 VCE - Figure 62. Recommended Application Circuit 9.2.2.2 FAULT Pin Circuitry The FAULT pin is an open-drain output requiring a 3.3 k pull-up resistor to provide logic high when FAULT is inactive. Because fast common mode transients can alter the FAULT-pin voltage during high state, a 330 pF capacitor connected between FAULT and GND1 is recommended to provide sufficient noise margin at the specified CMTI of 50 kV/s. The added capacitance does not increase the FAULT response time during a fault condition. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 27 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com Typical Application (continued) 1 2 3 5V C 3.3 kW 0.1 F 4 5 6 330 pF 7 8 ISO5500 VIN+ VINVCC1 GND1 RESET FAULT NC GND1 Figure 63. FAULT Pin Circuitry for High CMTI 9.2.2.3 Driving the Control Inputs The amount of common-mode transient immunity (CMTI) is primarily determined by the capacitive coupling from the high-voltage output circuit to the low-voltage input side of the ISO5500. For maximum CMTI performance, the digital control inputs, VIN+ and VIN-, must be actively driven by standard CMOS or TTL, push-pull drive circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5500 output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain configurations using pull-up resistors, must be avoided. 9.2.2.4 Local Shutdown and Reset In applications with local shutdown and reset, the FAULT output of each gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition. 1 2 3 C RF 4 5 6 7 8 VIN+ 1 ISO5500 2 VIN- 3 VCC1 C GND1 RF 4 5 RESET 6 FAULT 7 NC 8 GND1 VIN+ ISO5500 VINVCC1 GND1 RESET FAULT NC GND1 Figure 64. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right) 9.2.2.5 Global-Shutdown and Reset When configured for inverting operation, the ISO5500 can be configured to shutdown automatically in the event of a fault condition by tying the FAULT output to VIN+. For high reliability drives, the open drain FAULT outputs of multiple ISO5500 devices can be wired together forming a single, common fault bus for interfacing directly to the micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FAULT output disables all six gate drivers simultaneously; thereby, providing protection against further catastrophic failures. 28 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 Typical Application (continued) 1 2 3 C 4 5 6 7 8 to other RESETs to other FAULTs VIN+ ISO5500 VINVCC1 GND1 RESET FAULT NC GND1 Figure 65. Global Shutdown with Inverting Input Configuration 9.2.2.6 Auto-Reset Connecting RESET to the active control input (VIN+ for non-inverting, or VIN- for inverting operation) configures the ISO5500 for automatic reset capability. In this case, the gate control signal at VIN is also applied to the RESET input to reset the fault latch every switching cycle. During normal IGBT operation, asserting RESET low has no effect on the output. For a fault condition, however, the gate driver remains in the latched fault state until the gate control signal changes to the 'gate low' state and resets the fault latch. If the gate control signal is a continuous PWM signal, the fault latch will always be reset before VIN+ goes high again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next 'on' cycle. When the ISO5500 is configured for Auto Reset, the specified minimum FAULT signal pulse width is 3 s. 1 2 3 C 4 5 6 7 8 VIN+ 1 ISO5500 2 VIN- 3 VCC1 C GND1 4 5 RESET 6 FAULT 7 NC 8 GND1 VIN+ ISO5500 VINVCC1 GND1 RESET FAULT NC GND1 Figure 66. Auto Reset for Non-inverting and Inverting Input Configuration 9.2.2.7 Resetting Following a Fault Condition To resume normal switching operation following a fault condition (FAULT output low), the gate control signal must be driven into a 'gate low' state before asserting RESET low. This can be accomplished with a microcontroller, or an additional logic gate that synchronizes the RESET signal with the appropriate input signal. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 29 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com Typical Application (continued) 1 2 3 C 4 5 6 7 8 VIN+ 1 ISO5500 2 VIN- 3 VCC1 C 4 GND1 5 RESET 6 FAULT 7 NC 8 GND1 VIN+ ISO5500 VINVCC1 GND1 RESET FAULT NC GND1 Figure 67. Auto Reset with Prior Gate-low Assertion for Non-inverting and Inverting Input Configuration 9.2.2.8 DESAT Pin Protection Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial current out of the device. To limit this current below damaging levels, a 100 to 1 k resistor is connected in series with the DESAT diode. The added resistance neither alters the DESAT threshold nor the DESAT blanking time. Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of the DESAT input to VE potential at low voltage levels. ISO5500 VE VEE-L DESAT VCC2 VC VOUT 16 15 100 pF DS (opt.) RS 14 DDESAT - 13 12 15V Rg 11 VEE-L 10 VEE-P + VFW VFW-inst + 15V 9 Figure 68. DESAT Pin Protection with Series Resistor and Optional Schottky Diode 9.2.2.9 DESAT Diode and DESAT Threshold The DESAT diode's function is to conduct forward current, allowing sensing of the IGBT's saturated collector-toemitter voltage, VCESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the short transition time when the IGBT is switching, there is commonly a high dVCE/dt voltage ramp rate across the IGBT. This results in a charging current ICHARGE = CD-DESAT x dVCE/dt, charging the blanking capacitor. To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector voltage transients appear at DESAT attenuated by the ratio of 1+ CBLANK / CD-DESAT. Table 3 lists a number of fast-recovery diodes suitable for the use as DESAT diodes. Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the voltage at the DESAT-pin, VF + VCE = VDESAT, the VCE level, which triggers a fault condition, can be modified by adding multiple DESAT diodes in series: VCE-FAULT(TH) = 7.2 V - n x VF (where n is the number of DESAT diodes). 30 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 Typical Application (continued) When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be chosen. Table 3. Recommended DESAT Diodes PART NUMBER MANUFACTURER trr (ns) VRRM-max (V) PACKAGE STTH112 STM 75 1200 SMA, SMB, DO-41 59-04 (axial leaded) MUR100E Motorola 75 1000 MURS160T3 Motorola 75 600 Case 403A (SMD) UF4007 General Semi. 75 1000 DO-204AL (axial leaded) BYM26E Philips 75 1000 SOD64 (axial leaded) BYV26E Philips 75 1000 SOD57 (axial leaded) BYV99 Philips 75 600 SOD87 (axial leaded) 9.2.2.10 Determining the Maximum Available, Dynamic Output Power, POD-max The ISO5500 total power consumption of PD = 592 mW consists of the total input power, PID, the total output power, POD, and the output power under load, POL: PD = PID + POD + POL (2) PID = VCC1-max x ICC1-max = 5.5 V x 8.5 mA = 47 mW (3) POD = (VCC2 - VEE-P) x ICC2-q = 30 V x 14 mA = 420 mW (4) POL = PD - PID - POD = 592 mW - 47 mW - 420 mW = 125 mW (5) With: and: then: In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety of parameters: POL-WC = 0.5 fINP QG (VCC2 ae o ron-max roff-max - VEE-P ) c + / r + R r + R e on-max G off-max G o where * * * * * * * fINP = signal frequency at the control input VIN() QG = power device gate charge VCC2 = positive output supply with respect to VE VEE-P = negative output supply with respect to VE ron-max = worst case output resistance in the on-state: 4 roff-max = worst case output resistance in the off-state: 2.5 RG = gate resistor (6) Once RG is determined, Equation 6 is to be used to verify whether POL-WC < POL. Figure 69 shows a simplified output stage model for calculating POL-WC. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 31 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com ISO5500 VCC2 VC 15 V ron-max RG VOUT QG roff-max 15 V VEE-P Figure 69. Simplified Output Model for Calculating POL-WC 9.2.2.11 Determining Gate Resistor, RG The value of the gate resistor determines the peak charge and discharge currents, ION-PK and IOFF-PK. Due to the transient nature of these currents, their peak values only occur during the on-to-off and off-to-on transitions of the gate voltage. In order to calculate RG for the maximum peak current, ron and roff must be assumed zero. The resulting charge and discharge models are shown in Figure 70. ISO5500 ISO5500 VCC2 VCC2 VC VC 15 V 15 V V CC2 - VEE-P VOUT V CC2 - VEE-P Ion VOUT RG RG CG VE CG VE 15 V VEE-P Ioff 15 V VEE-P Figure 70. Simplified Gate Charge and Discharge Model 9.2.2.11.1 Off-to-On Transition In the off-state, the upper plate of the gate capacitance, CG, assumes a steady-state potential of -VEE-P with respect to VE. When turning on the power device, VCC2 is applied to VOUT and the voltage drop across RG results in a peak charge current of ION-PK = (VCC2 - VEE-P)/RG. Solving for RG then provides the necessary resistor value for a desired on-current via: V - VEE-P RG = CC2 ION-PK (7) 9.2.2.11.2 On-to-Off Transition When turning the power device off, the current and voltage relations are reversed but the equation for calculating RG remains the same. Once RG has been calculated, it is necessary to check whether the resulting, worst-case power consumption, POD-WC, (derived in Equation 6) is below the calculated maximum, POL = 125 mW (calculated in Equation 5). 32 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 9.2.2.12 Example The example below considers an IGBT drive with the following parameters: ION-PK = 2 A, QG = 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE-P = -5 V Applying Equation 7, the value of the gate resistor is calculated with 15V - ( - 5V) RG = = 10 2A (8) Then, calculating the worst-case output power consumption as a function of RG, using Equation 6 yields 4 2.5 ae o POL-WC = 0.5 20 kHz 650 nC (15 V - ( - 5V)) c + / = 63 mW e 4 + 10 2.5 + 10 o (9) Because POL-WC = 63 mW is well below the calculated maximum of POL = 125 mW, the resistor value of RG = 10 is fully suitable for this application. 9.2.2.13 Determining Collector Resistor, RC Despite equal charge and discharge currents, many power devices possess longer turn-off propagation and fall times than turn-on propagation and rise times. In order to compensate for the difference in switching times, it might be necessary to significantly reduce the charge current, ION-PK, versus the discharge current, IOFF-PK. Reducing ION-PK is accomplished by inserting an external resistor, RC, between the VC- pin and the VCC2- pin of the ISO5500. ISO5500 ISO5500 VCC2 VC VCC2 RC VC 15 V VOUT C2 - VC VE 15 V E- P Ion-pk VOUT RG VCC2 - VEE-P Ioff-pk RG CG VE CG VE 15 V 15 V VEE-P VEE-P Figure 71. Reducing ION-PK by Inserting Resistor RC Figure 71 (right) shows that during the on-transition, the (VCC2 - VEE-P) voltage drop occurs across the series resistance of RC + RG, thus reducing the peak charge current to: ION-PK = (VCC2 - VEE-P) /(RC + RG). Solving for RC provides: V - VEE-P RC = CC2 - RG ION-PK (10) To stay below the maximum output power consumption, RG must be calculated first via: RG = VCC2 - VEE-P IOFF-PK (11) and the necessary comparison of POL-WC versus POL must be completed. Once RG is determined, calculate RC for a desired on-current using Equation 10. Another method is to insert Equation 11 into Equation 10 and arriving at: aeI o RC = R G c OFF-PK - 1/ e ION-PK o (12) Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 33 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com 9.2.2.13.1 Example Reducing the peak charge current from the previous example to ION-PK = 1.5 A, requires a RC value of: ae 2A o RC = 10 c - 1/ = 3.33 e 1.5 A o (13) 9.2.2.14 Higher Output Current Using an External Current Buffer To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 72) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10 pair for up to 15 A maximum. ISO5500 VE VEE-L DESAT VCC2 VC 16 15 13 12 11 VOUT VEE-L VEE-P 100 pF 14 MJD44H11 or D44VH10 15 V 4.5 W 10 W 10 2.5 W 9 MJD45H11 or D45VH10 15 V Figure 72. Current Buffer for Increased Drive Current 9.2.3 Application Curve VCC2 - VEE = 30 V R G = 0 W, 5 V / div CL = 10 nF Time 125 ns / div Figure 73. Output Waveform 34 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 ISO5500 www.ti.com SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 10 Power Supply Recommendations To provide the large transient currents necessary during a switching transition on the gate driver output, 0.1-F bypass capacitors are recommended between input supply and ground (VCC1 and GND1), and between output supplies and ground (VCC2 and VE, VCC2 and VEE-P and VEE-P and VE). These capacitors are shown in Figure 62. These capacitors should be placed as close to the supply and ground pins as possible. 11 Layout 11.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 74). Layer stacking should be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and low-frequency signal layer. * Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the gate driver and the microcontroller and power transistors. Gate driver control input, Gate driver output VOUT and DESAT should be routed in the top layer. * Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for the return current flow. On the driver side, use VE as the ground plane. * Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2. On the gate-driver VEE-P and VCC2 can be used as power planes. They can share the same layer on the PCB as long as they are not connected together. * Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes, routing etc. see Application Note SLLA284, Digital Isolator Design Guide. 11.2 PCB Material Standard FR-4 epoxy-glass is recommended as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics. 11.3 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces , pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 74. Recommended Layer Stack Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 35 ISO5500 SLLSE64D - SEPTEMBER 2011 - REVISED JANUARY 2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: * ISO5500 Evaluation Module (EVM) User's Guide, SLLU136 * Digital Isolator Design Guide, SLLA284 12.2.1.1 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12.3 Trademarks All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SLLA353 -- Isolation Glossary. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 36 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: ISO5500 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) ISO5500DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO5500DW ISO5500DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO5500DW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO5500DWR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO5500DWR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height SMALL OUTLINE INTEGRATED CIRCUIT Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4040000-2/H PACKAGE OUTLINE DW0016B SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 14X 1.27 16 1 2X 8.89 10.5 10.1 NOTE 3 8 9 0.51 0.31 0.25 C A 16X B 7.6 7.4 NOTE 4 2.65 MAX B 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0.1 0 -8 1.27 0.40 DETAIL A (1.4) TYPICAL 4221009/B 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DW0016B SOIC - 2.65 mm max height SOIC SYMM SYMM 16X (2) 16X (1.65) SEE DETAILS 1 SEE DETAILS 1 16 16 16X (0.6) 16X (0.6) SYMM SYMM 14X (1.27) 14X (1.27) 9 8 9 8 R0.05 TYP R0.05 TYP (9.75) (9.3) HV / ISOLATION OPTION 8.1 mm CLEARANCE/CREEPAGE IPC-7351 NOMINAL 7.3 mm CLEARANCE/CREEPAGE LAND PATTERN EXAMPLE SCALE:4X METAL SOLDER MASK OPENING SOLDER MASK OPENING 0.07 MAX ALL AROUND METAL 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4221009/B 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DW0016B SOIC - 2.65 mm max height SOIC SYMM SYMM 16X (1.65) 16X (2) 1 1 16 16 16X (0.6) 16X (0.6) SYMM SYMM 14X (1.27) 14X (1.27) 9 8 9 8 R0.05 TYP R0.05 TYP (9.3) (9.75) IPC-7351 NOMINAL 7.3 mm CLEARANCE/CREEPAGE HV / ISOLATION OPTION 8.1 mm CLEARANCE/CREEPAGE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:4X 4221009/B 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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