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GND1

VIN+

VIN-

VCC1

DESAT

VCC2

FAULT

ISO5500

VREG

UVLO

DESAT

Gate

Drive

and

Fault

Logic

7.2V

12.3V

Q1a

Q1b

Q2aQ2b

VOUT

VEE-P

VEE-L

RESET

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ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

ISO5500 2.5-A Isolated IGBT, MOSFET Gate Driver

1 Features 3 Description

The ISO5500 is an isolated gate driver for IGBTs and

1• 2.5-A Maximum Peak Output Current MOSFETs with power ratings of up to IC= 150 A and

• Drives IGBTs up to IC= 150 A, VCE = 600 V VCE = 600 V. Input TTL logic and output power stage

• Capacitive Isolated Fault Feedback are separated by a capacitive, silicon dioxide (SiO2),

isolation barrier. When used in conjunction with

• CMOS/TTL Compatible Inputs isolated power supplies, the device blocks high

• 300-ns Maximum Propagation Delay voltage, isolates ground, and prevents noise currents

• Soft IGBT Turnoff from entering the local ground and interfering with or

damaging sensitive circuitry.

• Integrated Fail-Safe IGBT Protection

– High VCE (DESAT) Detection The device provides over-current protection (DESAT)

to an IGBT or MOSFET while an Undervoltage

– Undervoltage Lockout (UVLO) Protection With Lockout circuit (UVLO) monitors the output power

Hysteresis supply to ensure sufficient gate drive voltage. If the

• User Configurable Functions output supply drops below 12 V, the UVLO turns the

– Inverting, Noninverting Inputs power transistor off by driving the gate drive output to

a logic low state.

– Auto-Reset

– Auto-Shutdown For a DESAT fault, the ISO5500 initiates a soft

shutdown procedure that slowly reduces the

• Wide VCC1 Range: 3 V to 5.5 V IGBT/MOSFET current to zero while preventing large

• Wide VCC2 Range: 15 V to 30 V di/dt induced voltage spikes. A fault signal is then

• Operating Temperature: –40°C to 125°C transmitted across the isolation barrier, actively

driving the open-drain FAULT output low and

• Wide-Body SO-16 Package disabling the device inputs. The inputs are blocked as

• ±50-kV/us Transient Immunity Typical long as the FAULT-pin is low. FAULT remains low

• Safety and Regulatory Approvals: until the inputs are configured for an output low state,

– VDE 6000 VPK Basic Isolation per DIN V VDE followed by a logic low input on the RESET pin.

V 0884-10 (VDE V 0884-10) and DIN EN The ISO5500 is available in a 16-pin SOIC package

61010-1 and is specified for operating temperatures from

– 4243 VRMS Isolation for One Minute per UL –40°C to 125°C.

1577 Device Information(1)

– CSA Component Acceptance Notice #5A, IEC PART NUMBER PACKAGE BODY SIZE (NOM)

61010-1, and IEC 60950-1 End Equipment ISO5500 SOIC (16) 10.30 mm × 7.50 mm

Standards

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

2 Applications

• Isolated IGBT and MOSFET Drives in Functional Block Diagram

– Motor Control

– Motion Control

– Industrial Inverters

– Switched-Mode Power Supplies

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Table of Contents

8.3 Feature Description................................................. 17

1 Features.................................................................. 18.4 Device Functional Modes........................................ 25

2 Applications ........................................................... 19 Application and Implementation ........................ 26

3 Description............................................................. 19.1 Application Information............................................ 26

4 Revision History..................................................... 29.2 Typical Application ................................................. 26

5 Pin Configuration and Functions......................... 310 Power Supply Recommendations ..................... 35

6 Specifications......................................................... 411 Layout................................................................... 35

6.1 Absolute Maximum Ratings ...................................... 411.1 Layout Guidelines ................................................. 35

6.2 ESD Ratings.............................................................. 411.2 PCB Material......................................................... 35

6.3 Recommended Operating Conditions....................... 411.3 Layout Example .................................................... 35

6.4 Thermal Information.................................................. 512 Device and Documentation Support................. 36

6.5 Electrical Characteristics........................................... 512.1 Device Support...................................................... 36

6.6 Switching Characteristics.......................................... 612.2 Documentation Support ........................................ 36

6.7 Typical Characteristics.............................................. 712.3 Trademarks........................................................... 36

7 Parameter Measurement Information ................ 12 12.4 Electrostatic Discharge Caution............................ 36

8 Detailed Description............................................ 16 13 Mechanical, Packaging, and Orderable

8.1 Overview................................................................. 16 Information ........................................................... 36

8.2 Functional Block Diagram....................................... 16

4 Revision History

Changes from Revision C (June 2013) to Revision D Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1

• Added FAULT limits to Absolute Maximum Ratings .............................................................................................................. 4

Changes from Revision B (May 2013) to Revision C Page

• Changed VCE from1200 V to 600 V........................................................................................................................................ 1

• Added the Thermal Information table inside the data sheet below the Absolute Maximum Ratings table............................ 5

• Changed row VIORM and VPR specification from VIORM of 1200Vpk to 680 Vpk....................................................................... 17

• Changed 1200 VPK in the Regulatory Information table from 1200 VPK to 680 VPK ............................................................. 17

• Deleted last row of the IEC 60664-1 Rating Table............................................................................................................... 18

• Added Isolation Lifetime at a Maximum Continuous Working Voltage table........................................................................ 18

• Added Function Table under the Functional Block Diagram................................................................................................ 25

Changes from Revision A (July 2012) to Revision B Page

• Changed the Regulatory Approvals List................................................................................................................................. 1

• Changed the REGULATORY INFORMATION table, VDE Column From: File Number: pending To: File Number:

40016131.............................................................................................................................................................................. 17

• Changed the REGULATORY INFORMATION table, CSA Column From: File Number: pending To: File Number:

220991.................................................................................................................................................................................. 17

Changes from Original (September 2011) to Revision A Page

• Changed the device From: Product Preview To: Production................................................................................................. 1

Product Folder Links: ISO5500

VIN+ 1 16

VIN-

VCC1

GND1

RESET

FAULT

GND1

DESAT

VEE-L

VCC2

VEE-P

ISOLATION

VEE-L

VOUT

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

5 Pin Configuration and Functions

DW Package

16-Pin SOIC

Top View

Pin Functions

PIN I/O DESCRIPTION

NO. NAME

1 VIN+ I Noninverting gate drive voltage control input

2 VIN– I Inverting gate drive voltage control input

3 VCC1 Supply Positive input supply (3 V to 5.5 V)

4,8 GND1 Ground Input ground

5 RESET I FAULT reset input

6 FAULT O Open-drain output. Connect to 3.3k pullup resistor

7 NC NC Not connected

9 VEE-P Supply Most negative output-supply potential of the power output. Connect externally to pin 10.

Most negative output-supply potential of the logic circuitry. Pin 10 and 15 are internally connected.

10, 15 VEE-L Supply Connect at least pin 10 externally to pin 9. Pin 15 can be floating.

11 VOUT O Gate drive output voltage

12 VCSupply Gate driver supply. Connect to VCC2.

13 VCC2 Supply Most positive output supply potential

14 DESAT I Desaturation voltage input

16 VEGround Gate drive common. Connect to IGBT Emitter.

Product Folder Links: ISO5500

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Supply voltage, VCC1 –0.5 6 V

Total output supply voltage, VOUT(total) (VCC2 – VEE-P) –0.5 35 V

35 –

Positive output supply voltage, VOUT+ (VCC2 – VE) –0.5 V

(VE– VEE-P)

Negative output supply voltage, VOUT- (VE– VEE-P) –0.5 VCC2 V

DESAT VE– 0.5 VCC2

Voltage at V

VIN+, VIN–, RESET, FAULT –0.5 6

Peak gate drive output voltage Vo(peak) –0.5 VCC2 V

Collector voltage, VC–0.5 VCC2 V

Output current , IO(1) ±2.8 A

FAULT output current, IFL ±20 mA

Maximum junction temperature, TJ170 °C

Storage temperature, Tstg –65 150 °C

(1) Maximum pulse width = 10 μs, maximum duty cycle = 0.2%.

6.2 ESD Ratings VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000

Charged-device model (CDM), per JEDEC specification JESD22- ±1500

V(ESD) Electrostatic discharge V

C101(2)

Machine model JEDEC JESD22-A115-A ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VCC1 Supply voltage 3 5.5 V

VOUT(total) Total output supply voltage (VCC2 – VEE-P) 15 30 V

30 – (VE– V

VOUT+ Positive output supply voltage (VCC2 – VE) 15 VEE-P)

VOUT– Negative output supply voltage (VE– VEE-P) 0 15 V

VCCollector voltage VEE-P + 8 VCC2 V

tui Input pulse width 0.1 μs

tuiR RESET Input pulse width 0.1 μs

VIH High-level input voltage (VIN+, VIN–, RESET) 2 VCC V

VIL Low-level input voltage (VIN+, VIN–, RESET) 0 0.8 V

fINP Input frequency 520(1) kHz

VSUP_SR Supply Slew Rate (VCC1 or VCC2 – VEE-P)(2) 75 V/ms

TJJunction temperature –40 150 °C

TAAmbient temperature -40 25 125 °C

(1) If TA= 125°C, VCC1= 5.5 V, VCC2 = 30 V, RG= 10 Ω, CL= 1 nF

(2) If VCC1 skew is faster than 75 V/ms (especially for the falling edge) then VCC2 must be powered up after VCC1 and powered down before

VCC1 to avoid output glitches.

Product Folder Links: ISO5500

ISO5500

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SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

6.4 Thermal Information ISO5500

THERMAL METRIC(1) UNIT

DW (SOIC) 16

PINS

θJA Junction-to-ambient thermal resistance 76

θJCtop Junction-to-case (top) thermal resistance 34

θJB Junction-to-board thermal resistance 36 °C/W

ψJT Junction-to-top characterization parameter 8

ψJB Junction-to-board characterization parameter 35

TSHDN+ 185 °C

Thermal Shutdown

TSHDN- 173 °C

TSHDN-HYS Thermal Shutdown Hysteresis 12 °C

PDPower Dissipation See Equation 2 through Equation 6 592 mW

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

All typical values are at TA= 25°C, VCC1 = 5 V, VCC2 – VE= 30 V, VE– VEE-P = 0 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Quiescent 5.5 8.5

VI= VCC1 or 0 V, No load, See Figure 1,

ICC1 Supply current mA

Figure 2,Figure 28, and Figure 29

300 kHz 5.7 8.7

Quiescent 8.4 12

VI= VCC1 or 0 V, No load, See Figure 3

ICC2 Supply current mA

through Figure 5,Figure 30, and Figure 31

300 kHz 9 14

IOUT = 0, See Figure 27 and Figure 30 1.3

ICH High-level collector current mA

IOUT = –650 μA, See Figure 27 and Figure 30 1.9

ICL Low-level collector current See Figure 27 and Figure 31 0.4 mA

IEH VEHigh-level supply current See Figure 6 and Figure 40 –0.5 –0.3 mA

IEL VELow-level supply current See Figure 6 and Figure 41 –0.8 –0.53 mA

IIH High-level input leakage 10

IN from 0 to VCC μA

IIL Low-level input leakage –10

VFAULT = VCC1, no pull-up,

IFH High-level FAULT pin output current –10 10 μA

See Figure 33

IFL Low-level FAULT pin output current VFAULT = 0.4 V, no pull-up, See Figure 34 5 12 mA

VIT+(UVLO) Positive-going UVLO threshold voltage 11.6 12.3 13.5

VIT–(UVLO) Negative-going UVLO threshold voltage See Figure 32 11.1 12.4 V

VHYS (UVLO) UVLO Hysteresis voltage (VIT+ – VIT–) 0.7 1.2

VOUT = VCC2 – 4 V(1), See Figure 7 and –1 –1.6

Figure 35

IOH High-level output current A

VOUT = VCC2 – 15 V(2), See Figure 7 and –2.5

Figure 35

VOUT = VEE-P + 2.5 V(1), See Figure 8 and 1 1.8

Figure 36

IOL Low-level output current A

VOUT = VEE-P + 15 V(2), See Figure 8 and 2.5

Figure 36

VOUT – VEE-P = 14 V, See Figure 9 and

IOF Output-low fault current 90 140 230 mA

Figure 37

IOUT = –100 mA, See Figure 10,Figure 11 VC-1.5 VC-0.8

and Figure 38

VOH High-level output voltage V

IOUT = –650 μA, See Figure 10,Figure 11 and VC-0.15 VC-0.05

Figure 38

IOUT = 100 mA, See Figure 12,Figure 13 and

VOL Low-level output voltage 0.2 0.5 V

Figure 39

VDESAT = 0 V to 6 V, See Figure 14 and

ICHG Blanking capacitor charging current –180 –270 –380 μA

Figure 42

IDSCHG Blanking capacitor discharge current VDESAT = 8 V, See Figure 42 20 45 mA

(1) Maximum pulse width is 50 μs, maximum duty cycle is 0.5%

(2) Maximum pulse width is 10 μs, maximum duty cycle is 0.2%

Product Folder Links: ISO5500

( ) ( )

PHL-min CC1, CC2, A PLH-max CC1, CC2, A

P HL-ma x CC1, CC2, A PL H-m in CC1, CC2, A

min = t V V T t V V T

max = t V V T t V V T

i.e. -

( ) ( )

P H L-ma x C C 1, CC 2, A PH L -m in CC1, C C2, A

P LH -ma x C C 1, C C 2, A PL H -m in CC 1, C C 2, A

t V V T t V V T ,

t V V T t V V T

i.e. max

ì ü

é ù

ïë û ï

í ý

é ù

ï ï

ë û

î þ

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Electrical Characteristics (continued)

All typical values are at TA= 25°C, VCC1 = 5 V, VCC2 – VE= 30 V, VE– VEE-P = 0 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(VCC2 – VE) > VTH-(UVLO), See Figure 15 and

VDSTH DESAT threshold voltage 6.7 7.2 7.7 V

Figure 42

VI= VCC1 or 0 V, VCM at 1500 V,

CMTI Common mode transient immunity 25 50 kV/μS

See Figure 43 though Figure 46

6.6 Switching Characteristics

All typical values are at TA= 25°C, VCC1 = 5 V, VCC2 – VE= 30 V, VE– VEE-P = 0 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLH, tPHL Propagation Delay 150 200 300 ns

RG= 10 Ω, CG= 10 nF,

tsk-p Pulse Skew |tPHL – tPLH| 1.7 10 ns

50 % duty cycle, 10 kHz input,

VCC2 – VEE = 30 V,

tsk-pp Part-to-part skew(1) 45 ns

VE– VEE = 0 V, See Figure 16

tsk2-pp Part-to-part skew(2) –50 50 ns

through Figure 19,Figure 26,

Figure 47,Figure 49, and

trOutput signal rise time 55 ns

Figure 50

tfOutput signal fall time 10 ns

tDESAT (90%) DESAT sense to 90% VOUT delay 300 550 ns

RG= 10 Ω, CG= 10 nF,

tDESAT (10%) DESAT sense to 10% VOUT delay 1.8 2.3 μs

VCC2 – VEE-P = 30 V,

tDESAT (FAULT) DESAT sense to FAULT low output delay 290 550 ns

VE– VEE-P = 0 V, See Figure 20

DESAT sense to DESAT low propagation through Figure 25,Figure 48 and

tDESAT (LOW) 180 ns

delay Figure 51

tRESET (FAULT) RESET to high-level FAULT signal delay 3 8.2 13 μs

tUVLO (ON) UVLO to VOUT high delay 1ms ramp from 0 V to 30 V 4 μs

tUVLO (OFF) UVLO to VOUT low delay 1ms ramp from 30 V to 0 V 6 μs

Failsafe output delay time from input power

tFS 2.8 μs

loss

(1) tsk-pp is the maximum difference in same edge propagation delay times (either VIN+ to VOUT or VIN– to VOUT) between two devices

operating at the same supply voltage, same temperature, and having identical packages and test circuits.

(2) tsk2-pp is the propagation delay difference in high-to-low to low-to-high transition ( any of the combinations VIN+ to VOUT or VIN– to VOUT)

between two devices operating at the same supply voltage, same temperature, and having identical packages and test circuits.

Product Folder Links: ISO5500

-40 20 80 140

IEH, I - Supply Current (mA)

Ambient Temperature ( C)

-20 0 40 60 100 120

-0.7

-0.6

-0.5

-0.3

-0.8

-0.4

-0.2

-0.1

I , V - V = 0 V

EH E EE

I , V - V = 15 V

I , V - V = 0 V

I , V - V = 15 V

EH E EE

EL E EE

20 80

I - Supply Current (mA)

CC2

Load Capacitance (nF)

0 40 60 100

R = 10

f = 20 kHz

INP

VCC2

CC2

= 15 V

V = 30 V

-40 20 80 140

I - Supply Current (mA)

CC2

Ambient Temperature ( C)

-20 0 40 60 100 120

VCC2

CC2

= 15 V

V = 20 V

V = 30 V

CC2

50 200 300

I - Supply Current (mA)

CC2

Input Frequency (KHz)

0 100 150 250

No Load

VCC2

CC2

= 15 V

V = 20 V

V = 30 V

-40 20 80 140

I - Supply Current (mA)

CC1

Ambient Temperature ( C)

-20 0 40 60 100 120

V = 4.5 V

V = 5 V

V = 5.5 V

CC1

VCC1 = 3 V

V = 3.3 V

V = 3.6 V

CC1

50 200 300

I - Supply Current (mA)

CC1

Input Frequency (KHz)

0 100 150 250

VCC1

CC1

= 3.3 V

V = 5 V

ISO5500

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SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

6.7 Typical Characteristics

Figure 1. VCC1 Supply Current vs. Temperature Figure 2. VCC1 Supply Current vs. Frequency

Figure 3. VCC2 Supply Current vs. Temperature Figure 4. VCC2 Supply Current vs. Frequency

Figure 5. VCC2 Supply Current vs. Load Capacitance Figure 6. VESupply Current vs. Temperature

Product Folder Links: ISO5500

-40 20 80 140

V - Low Output Voltage (V)

Ambient Temperature ( C)

-20 0 40 60 100 120

0.1

0.15

0.35

0.2

0.25

0.3

IOUT = 100 mA

0.2 0.8 1.4

V - High Output Voltage (V)

Output Drive (A)Current

0 0.4 0.6 1

26.5

25.5

27.5

28.5

29.5

1.2 1.5

T = -40 C

T = 25 C

T = 125 C

5 20 30

I - Output Sink Current During

a Fault Condition (mA)

Output Voltage (V)

0 10 15 25

110

130

100

160

120

140

150

T = -40 C

T = 25 C

T = 125 C

-40 20 80 140

V - - High Output Voltage Drop (V)

OH VC

Ambient Temperature ( C)

-20 0 40 60 100 120

-1.5

-1.1

-1.3

0.1

-0.9

-0.5

-0.3

-0.7

-0.1

IOUT = -650 Am

I = -100 mA

OUT

-40 20 80 140

I - Output Drive Current (A)

Ambient Temperature ( C)

-20 0 40 60 100 120

-5

-3.5

-4.5

-2

-4

-3

-1.5

-1

VOUT C

OUT C

= V - 4 V

V = V - 15 V

-2.5

-0.5

-40 20 80 140

I - Output Sink Current (A)

Ambient Temperature ( C)

-20 0 40 60 100 120

VOUT

OUT

= 2.5 V

V = 15 V

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Typical Characteristics (continued)

Figure 7. Output Drive Current vs. Temperature Figure 8. Output Sink Current vs. Temperature

Figure 9. Output Sink Current During a Fault Condition Figure 10. High Output Voltage Drop vs. Temperature

vs. Output Voltage

Figure 11. High Output Voltage vs. Output Drive Current Figure 12. Low Output Voltage vs. Temperature

Product Folder Links: ISO5500

3 4.5

Propagation Delay (ns)

V Supply Voltage (V)

CC1

3.5 4 5 5.5

200

210

205

225

220

215

tPLH

tPHL

R = 10 ,

C = 10 nF

14 20 24 30

Propagation Delay (ns)

V Supply Voltage (V)

CC2

16 18 22 26 28

205

195

230

220

215

225

190

200

210

tPLH CC1

PHL CC1

PLH CC1

PHL CC1

at V = 3.3 V

t at V = 3.3 V

t at V = 5 V

R = 10 ,

C = 10 nF

-40 20 80 140

Propagation Delay (ns)

Ambient Temperature ( C)

-20 0 40 60 100 120

180

200

190

240

220

210

230

tPLH CC1

PHL CC1

PLH CC1

PHL CC1

at V = 3.3 V

t at V = 3.3 V

t at V = 5 V

R = 10 ,

C = 10 nF

-40 20 80 140

V - Desat Threshold (V)

DSTH

Ambient Temperature ( C)

-20 0 40 60 100 120

6.5

6.7

7.9

6.9

7.3

7.5

7.1

7.7

0.5 2

V - Low Output Voltage (V)

Output Sink Current (A)

0 1 1.5 2.5

T = -40 C

T = 25 C

T = 125 C

-40 20 80 140

I - Blanking Capacitor Charging

Current (mA)

CHG

Ambient Temperature ( C)

-20 0 40 60 100 120

-0.35

-0.31

-0.15

-0.29

-0.23

-0.21

-0.27

-0.17

-0.33

-0.25

-0.19

ISO5500

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SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

Typical Characteristics (continued)

Figure 13. Low Output Voltage vs. Output Sink Current Figure 14. Blanking Capacitance Charging Current vs.

Temperature

Figure 15. DESAT Threshold vs. Temperature Figure 16. Propagation Delay vs. Temperature

Figure 17. Propagation Delay vs. VCC1 Supply Voltage Figure 18. Propagation Delay vs. VCC2 Supply Voltage

Product Folder Links: ISO5500

0 20 50 100

Desat Sense to 10% Delay ( s)mVOUT

Load Capacitance (nF)

10 40 70 80 90

30 60

R = 10

VCC2

CC2

= 15 V

V = 30 V

-40 20 80 140

Desat Sense to Fault Low Delay (ns)

Ambient Temperature ( C)

-20 0 40 60 100 120

200

450

150

250

400

300

350

VCC2

CC2

= 15 V

V = 30 V

0 20 50 100

Desat Sense to 90% Delay (ns)VOUT

Load Capacitance (nF)

10 40 70 80 90

200

1600

600

800

1400

1000

30 60

400

1200

R = 10

VCC2

CC2

= 15 V

V = 30 V

-40 20 80 140

Desat Sense to 10% Delay ( s)mVOUT

Ambient Temperature ( C)

-20 0 40 60 100 120

0.5

2.5

1.5

R = 10 ,

C = 10 nF

VCC2

CC2

= 15 V

V = 30 V

0 30 50 100

Propagation Delay (ns)

Load Capacitance (nF)

10 20 40 60 70

600

200

1400

1200

1000

400

800

R = 10

80 90

tPLH CC1

PHL CC1

PLH CC1

PHL CC1

at V = 3.3 V

t at V = 3.3 V

t at V = 5 V

-40 20 80 140

Desat Sense to 90% Delay (ns)VOUT

Ambient Temperature ( C)

-20 0 40 60 100 120

200

450

250

150

300

400

350

R = 10 ,

C = 10 nF

VCC2

CC2

= 15 V

V = 30 V

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Typical Characteristics (continued)

Figure 19. Propagation Delay vs. Load Capacitance Figure 20. DESAT Sense to 90% VOUT Delay vs Temperature

Figure 21. DESAT Sense to 90% VOUT Delay vs Load Figure 22. DESAT Sense to 10% VOUT Delay vs Temperature

Capacitance

Figure 23. DESAT Sense to 10% VOUT Delay vs Load Figure 24. DESAT Sense to Fault Low Delay vs Temperature

Capacitance

Product Folder Links: ISO5500

-40 20 80 140

ICH, I - Supply Current (mA)

Ambient Temperature ( C)

-20 0 40 60 100 120

0.5

1.5

2.5

I , I = -500 A

CH OUT m

I , I = -1 mA

I , I = -2 mA

CH OUT

CL OUT

Time 125 ns / div

5 V / div

V - V = 30 V

R = 0 ,

C = 10 nF

CC2 EE

-40 20 80 140

Reset to Fault Delay ( s)m

Ambient Temperature ( C)

-20 0 40 60 100 120

6.5

5.5

8.5

7.5

9.5

VCC1 = 3 V

V = 3.3 V

V = 3.6 V

V = 4.5 V

V = 5 V

V = 5.5 V

CC1

ISO5500

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SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

Typical Characteristics (continued)

Figure 25. Reset to Fault Delay vs Temperature Figure 26. Output Waveform

Figure 27. VCSupply Current vs. Temperature

Product Folder Links: ISO5500

0.1

µF

5 V

0.1

µF

0.1

µF

VOUT

0.1

µF

Sweep

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

0.1

µF

5.5 V

IFAULT

30 V 0.1

µF

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

0.1

µF

5 V

30 V

ICC2

0.1

µ F

IOUT

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

30 V

ICC2

0.1

µF

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

0.1

µF

5.5 V

ICC1

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

0.1

µF

5.5 V

ICC1

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

7 Parameter Measurement Information

Figure 28. ICC1H Test Circuit Figure 29. ICC1L Test Circuit

Figure 30. ICC2H, ICH Test Circuit Figure 31. ICC2L, ICL Test Circuit

Figure 32. VIT(UVLO) Test Circuit Figure 33. IFH Test Circuit

Product Folder Links: ISO5500

30 V

0.1

µF

VOUT

IOUT

0.1

µF

5 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

0.1

µF

5 V

30 V

0.1

µF

100

VOUT

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

30 V 0.1

µF

4.7

µF

IOUT

VPULSE

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

30 V

0.1

µF

14 V

IOUT

0.1

µF

5 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

0.1

µF

3 V

0.4 V

IFAULT

30 V 0.1

µF

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

30 V

0.1

µF

4.7

µF

VPULSE

IOUT

0.1

µF

5 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

Parameter Measurement Information (continued)

Figure 34. IFL Test Circuit Figure 35. IOH Test Circuit

Figure 36. IOL Test Circuit Figure 37. IOF Test Circuit

Figure 38. VOH Test Circuit Figure 39. VOL Test Circuit

Product Folder Links: ISO5500

3 k

VCM

100 pF

SCOPE

0.1

µF

5 V

10 W

0.1

µF

4.7

µF 30 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

10 W

3 k

0.1

µF

VCM

100 pF

SCOPE

0.1

µF

5 V

4.7

µF 30 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

3 k

VCM

100 pF

SCOPE

0.1

µF

5 V

10 W

0.1

µF

4.7

µF 30 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

IDESAT

0.1

µF

0.1

µF

0.1

µF

SWEEP

0.1

µF

5 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

0.1

µF

0.1

µF

0.1

µF

0.1

µF

5 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

0.1

µF

5 V

0.1

µF

0.1

µF

0.1

µF

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Parameter Measurement Information (continued)

Figure 40. IEH Test Circuit Figure 41. IEL Test Circuit

Figure 42. ICHG, IDSCHG, VDSTH Test Circuit Figure 43. CMTI VFH Test Circuit

Figure 44. CMTI VFL Test Circuit Figure 45. CMTI VOH Test Circuit

Product Folder Links: ISO5500

VIN-

50 % 50 %

tPLH tPHL

90%

50%

10%

VOUT

VCC1

VIN+

VDESAT

VOUT

RESET

FAULT

tDESAT (90%)

tDESAT (LOW)

10%

90%

50%

50 %

tDESAT (10%)

tDESAT (FAULT )

50%

tRESET (FAULT )

7.2V

50 %

VIN+ 50 % 50 %

tPLH tPHL

90%

50%

10%

VOUT

0VVIN-

10 W

VOUT

0.1

µF

4.7

µF

0.1

µF

V1 0.1

µF

3 k

0.1

µF

5 V

VIN 100

DESAT

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

3 k

VCM

100 pF

0.1

µF

5 V

10 W

0.1

µF

SCOPE

4.7

µF 30 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

10 W

0.1

µF

VIN

VOUT

0.1

µF

4.7

µF

3 k

GND1

5 V

VIN+

VIN-

VCC1

GND1

DESAT

VEE-L

VCC2

VOUT

VEE-P

RESET

FAULT

VEE-L

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

Parameter Measurement Information (continued)

Figure 46. CMTI VOL Test Circuit Figure 47. tPLH, tPHL, tr, tfTest Circuit

Figure 48. tDESAT, tRESET Test Circuit Figure 49. VOUT Propagation Delay, Non-inverting

Configuration

Figure 50. VOUT Propagation Delay, Inverting Figure 51. DESAT, VOUT, FAULT, RESET Delays

Configuration

Product Folder Links: ISO5500

ISO - Barri er

DELAY

GND1

VIN+

VIN-

VCC1

DESAT

VCC2

FAULT

ISO5500

VREG

UVLO

DESAT

Gate

Drive

and

Fault

Logic

7.2V

12.3V

Q1a

Q1b

Q2aQ2b

VOUT

VEE-P

VEE-L

RESET

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

8 Detailed Description

8.1 Overview

The ISO5500 is an isolated gate driver for IGBTs and MOSFETs with power ratings of up to IC = 150 A and VCE

= 600 V. Input TTL logic and output power stage are separated by a capacitive, silicon dioxide (SiO2), isolation

barrier.

The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET

inputs, and FAULT alarm output. The power stage consists of power transistors to supply 2.5 A pullup and

pulldown currents to drive the capacitive load of the external power transistors, as well as DESAT detection

circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The capacitive isolation core

consists of transmit circuitry to couple signals across the capacitive isolation barrier, and receive circuitry to

convert the resulting low-swing signals into CMOS levels. The ISO5500 also contains undervoltage lockout

circuitry to prevent insufficient gate drive to the external IGBT, and soft turnoff feature which ensures graceful

reduction in IGBT current to zero when a short-circuit is detected.

8.2 Functional Block Diagram

Product Folder Links: ISO5500

ISO5500

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SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

8.3 Feature Description

Table 1. Package Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Shortest terminal to terminal distance

L(I01) Minimum air gap (clearance(1)) 8.3 mm

through air

Shortest terminal to terminal distance

L(I02) Minimum external tracking (creepage(1)) 8.1 mm

across the package surface

Minimum internal gap (internal clearance) Distance through the insulation 0.012 mm

CTI Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 400 V

RIO Isolation resistance Input to output, VIO = 500 V(2) >1012 Ω

CIO Barrier capacitance input-to-output VIO = 0.4 sin (2πft), f = 1 MHz(2) 1.25 pF

VI= VCC/2 + 0.4 sin (2πft), f = 2 MHz,

CIInput capacitance to ground 2 pF

VCC = 5V

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed circuit board do not reduce this distance.space

Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the isolation

glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase their specification.

(2) All pins on each side of the barrier tied together creating a two-terminal device

8.3.1 Insulation Characteristics for DW-16 Package

Over recommended operating conditions (unless noted otherwise)

PARAMETER TEST CONDITIONS SPECIFICATION UNIT

Maximum working insulation voltage per DIN

VIORM 679/480

V VDE V 0884-10 (VDE V 0884-10) After Input/Output safety test subgroup 2/3,

VPR = 1.2 x VIORM, t = 10 sec, 816/576

Partial discharge < 5 pC

Method a, After environmental tests subgroup 1,

Input to output test voltage per DIN V VDE V

VPR VPR = 1.6 × VIORM, t = 10 sec (qualification) 1088/768

0884-10 (VDE V 0884-10) VPEAK/

Partial discharge < 5pC VRMS

Method b1, 100% Production test,

VPR = 1.875 × VIORM, t = 1 sec 1275/900

Partial discharge < 5pC

Transient overvoltage per DIN V VDE V VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec

VIOTM 6000/4243

0884-10 (VDE V 0884-10) (100% production)

VTEST = VISO, t = 60 sec (qualification) 6000/4243

VISO Isolation voltage per UL 1577 VTEST = 1.2 × VISO, t = 1 sec (100% production) 7200/5092

RSInsulation resistance VIO = 500 V at TS= 150°C > 109Ω

Pollution degree 2

8.3.2 Regulatory Information

VDE CSA UL

Certified according to DIN V VDE V 0884-10 Approved under CSA Component Recognized under 1577 Component

(VDE V 0884-10) Acceptance Notice 5A Recognition Program

Basic Insulation Basic and Reinforced Insulation per CSA

Maximum Transient Overvoltage, 6000 VPK Single Protection, 4243 VRMS (1)

60950-1-07 and IEC 60950-1 (2nd Ed)

Maximum Working Voltage, 680 VPK

Certificate Number: 40016131 Master Contract Number: 220991 File Number: E181974

(1) Production tested ≥5092 VRMS for 1 second in accordance with UL 1577.

Product Folder Links: ISO5500

100

200

300

400

500

600

0 50 100 150 200

Case Temperature - C

Safety Limiting Current - mA

V - V = 30 V

CC2 EE-P

V = 3.6V

CC1

V = 5.5V

CC1

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

8.3.3 IEC 60664-1 Rating Table

PARAMETER TEST CONDITIONS SPECIFICATION

Basic Isolation Group Material Group II

Rated Mains Voltage ≤300 VRMS I-IV

Installation Classification Rated Mains Voltage ≤600 VRMS I-III

8.3.4 Isolation Lifetime at a Maximum Continuous Working Voltage

PARAMETER LIFETIME SPECIFICATION UNIT

20 years 679/480

Bipolar AC Voltage 25 years 657/465 VPEAK/VRMS

50 years 601/425

8.3.5 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.

A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate

sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system

failures.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

θJA = 76°C/W, VI= 3.6 V, TJ= 170°C, TA= 25°C 530

ISSafety Limiting Current θJA = 76°C/W, VI= 5.5 V, TJ= 170°C, TA= 25°C 347 mA

θJA = 76°C/W, VI= 30 V, TJ= 170°C, TA= 25°C 64

TSCase Temperature 150 °C

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum

Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the

application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the

Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount

Packages. The power is the recommended maximum input voltage times the current. The junction temperature is

then the ambient temperature plus the power times the junction-to-air thermal resistance.

Figure 52. DW-16 θJC Thermal Derating Curve per DIN V VDE V 0884-10 (VDE V 0884-10)

Product Folder Links: ISO5500

VIN+

VDESAT

VOUT

FAULT

RESET

7.2V

ISO

FAULT

DIS

Normal Operation Fault Condition Reset Normal Operation

Delay

270 μA

12.3V

FAULT

ISO - Barrie r

DELAY

ISO

UVLO

Q1a

Q1b

Q2aQ2b

GND1

VIN+

VIN-

VCC1 VC

VOUT

VEE-P

DESAT

VCC2

FAULT

RESET

VREG VCC2

VREG

ISO5500

15V

CBLK

7.2V

+HV

LOAD

-HV

I/P

O/P

PWM

μC

VEE-L 10,15

4,8

DIS

3.3V

15V

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

8.3.6 Behavioral Model

Figure 53 and Figure 54 show the detailed behavioral model of the ISO5500 for a non-inverting input

configuration and its corresponding timing diagram for normal operation, fault condition, and Reset.

Figure 53. ISO5500 Behavioral Model

Figure 54. Complete Timing Diagram

Product Folder Links: ISO5500

ISOLATION

ISO5500

VCC1

GND1

ISOLATION

3 V - 5.5 V

ISO5500

VIN+

VIN-

PWM

VIN-

VCC1

VIN+

VCC1

GND1

VIN+

VIN-

3 V - 5.5 V

PWM VIN-

VIN+

VOUT

GND1

VOUT

VCC1

GND1

VCC2

VEE-P

ISOLATION

3 V - 5.5 V

VCC2

ISOLATION

ISO5500 ISO5500

VCC1

GND1

Power Device

Common

15V 15 V-30 V

0 V-15 V

3 V - 5.5 V

+15 V

0-(-15 V)

+15 V

-15 V

VEE-L

VEE-P

VEE-L

0 V-15 V

Power Device

Common

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

8.3.7 Power Supplies

VCC1 and GND1 are the power supply input and output for the input side of the ISO5500. The supply voltage at

VCC1 can range from 3 V up to 5.5 V with respect to GND1, thus supporting the direct interface to state-of-the-art

3.3 V low-power controllers as well as legacy 5 V controllers.

VCC2, VEE-P and VEE-L are the power supply input and supply returns for the output side of the ISO5500. VEE-P is

the supply return for the output driver and VEE-L is the return for the logic circuitry. With VEE-P as the main

reference potential, VEE-L should always be directly connected to VEE-P. The supply voltage at VCC2 can range

from 15 V up to 30 V with respect to VEE-P.

A third voltage input, VE, serves as reference voltage input for the internal UVLO and DESAT comparators. VE

also represents the common return path for the gate voltage of the external power device. The ISO5500 is

designed for driving MOSFETs and IGBTs. Because MOSFETs do not require a negative gate-voltage, the

voltage potential at VEwith respect to VEE-P can range from 0 V for MOSFETs and up to 15 V for IGBTs.

Figure 55. Power Supply Configurations

The output supply configuration on the left uses symmetrical ±15 V supplies for VCC2 and VEE-P with respect to

VE. This configuration is mostly applied when deriving the output supply from the input supply via an isolated DC-

DC converter with symmetrical voltage outputs. The configuration on the right, having both supplies referenced to

VEE-P, is found in applications where the device output supply is derived from the high-voltage IGBT supplies.

8.3.8 Control Signal Inputs

The two digital, TTL control inputs, VIN+ and VIN–, allow for inverting and non-inverting control of the gate driver

output. In the non-inverting configuration VIN+ receives the control input signal and VIN– is connected to GND1. In

the inverting configuration VIN– is the control input while VIN+ is connected to VCC1.

Figure 56. Non-inverting (left) and Inverting (right) Input Configurations

Product Folder Links: ISO5500

VCC2

15V

Q1a

Q1b

Q2aQ2b

VOUT

VEE-P

Off

Slow

Off 15V

ISO5500

VGE

VIN+

VOUT

VGE

30V

-15V

+15V

Q1 Q2 Q1

Gate

Drive

VEE-L

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

8.3.9 Output Stage

The output stage provides the actual IGBT gate drive by switching the output voltage pin, VOUT, between the

most positive potential, typically VCC2, and the most negative potential, VEE-P.

Figure 57. Output Stage Design and Timing

This stage consists of an upper transistor pair (Q1a and Q1b) turning the IGBT on, and a lower transistor pair

(Q2a and Q2b) turning the IGBT off. Each transistor pair possesses a bipolar transistor for high current drive and

a MOSFET for close-to-rail switching capability.

An additional, weak MOSFET (Q3) is used to softly turn-off the IGBT in the event of a short circuit fault to

prevent large di/dt voltage transients which potentially could damage the output circuitry.

The output control signals, On, Off, and Slow-Off are provided by the gate-drive and fault-logic circuit which also

includes a break-before-make function to prevent both transistor pairs from conducting at the same time.

By introducing the reference potential for the IGBT emitter, VE, the final IGBT gate voltage, VGE, assumes

positive and negative values with respect to VE.

A positive VGE of typically 15 V is required to switch the IGBT well into saturation while assuring the survival of

short circuit currents of up to 5–10 times the rated collector current over a time span of up to 10 μs.

Negative values of VE, ranging from a required minimum of –5 V up to a recommended –15 V, are necessary to

keep the IGBT turned off and to prevent it from unintentional conducting due to noise transients, particularly

during short circuit faults. As previously mentioned, MOSFETs do not require a negative gate-voltage and thus

allow the VE-pin to be directly connected to VEE-P.

The timing diagram in Figure 57 shows that during normal operation VOUT follows the switching sequence of VIN+

(here shown for the non-inverting input configuration), and only the Q1 and Q2 transistor pairs applying VCC2 and

VEE-P potential to the VOUT-pin respectively.

In the event of a short circuit fault, however, while the IGBT is actively driven, the Q1 pair is turned off and Q3

turns on to slowly reduce VOUT in a controlled manner down to a level of approximately 2 V above VEE-P. At this

voltage level, the strong Q2 pair then conducts holding VOUT at VEE-P potential.

8.3.10 Undervoltage Lockout (UVLO)

The Under Voltage Lockout feature prevents the application of insufficient gate voltage (VGE-ON) to the power

device by forcing VOUT low (VOUT = VEE-P) during power-up and whenever else VCC2 – VEdrops below 12.3 V.

IGBTs and MOSFETs typically require gate voltages of VGE = 15 V to achieve their rated, low saturation voltage,

VCES. At gate voltages below 13 V typically, their VCE-ON increases drastically, especially at higher collector

currents. At even lower voltages, i.e. VGE < 10 V, an IGBT starts operating in the linear region and quickly

overheats. Figure 58 shows the principle operation of the UVLO feature.

Product Folder Links: ISO5500

VIN+

VOUT

VGE

-15V

+15V

Q1 Q2

VCC2

12.3V

Q2RPD

Failsafe

Low

11.1V

VCC2

12.3V Q1a

Q1b

Q2aQ2b

VOUT

15V

VGE

Off

Gate

Drive

UVLO

Q2Q1 Q1

ISO5500 VEE-P

VEE-L

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Figure 58. Undervoltage Lockout (UVLO) Function

Because VCC2 with respect to VErepresents the gate-on voltage, VGE-ON = VCC2 – VE, the UVLO comparator

compares VCC2 to a 12.3 V reference voltage that is also referenced to VEvia the connection of the ISO5500 VE-

pin to the emitter potential of the power device.

The comparator hysteresis is 1.2 V typical and the typical values for the positive and negative going input

threshold voltages are VTH+ = 12.3 V and VTH– = 11.1 V.

The timing diagram shows that at VCC2 levels below 2 V VOUT is 0 V. Because none of the internal circuitry

operates at such low supply levels, an internal 100 kΩpull-down resistor is used to pull VOUT down to VEE-P

potential. This initial weak clamping, known as failsafe-low output, strengthens with rising VCC2. Above 2 V the

Q2-pair starts conducting gradually until VCC2 reaches 12.3 V at which point the logic states of the control inputs

VIN+ and VIN– begin to determine the state of VOUT.

Another UVLO event takes place should VCC2 drop slightly below 11 V while the IGBT is actively driven. At that

moment the UVLO comparator output causes the gate-drive logic to turn off Q1 and turn on Q2. Now VOUT is

clamped hard to VEE-P. This condition remains until VCC2 returns to above 12.3 V and normal operation

commences.

NOTE

An Undervoltage Lockout does not indicate a Fault condition.

8.3.11 Desaturation Fault Detection (DESAT)

The DESAT fault detection prevents IGBT destruction due to excessive collector currents during a short circuit

fault. Short circuits caused by user misconnect, bad wiring, or overload conditions induced by the load can cause

a rapid increase in IGBT current, leading to excessive power dissipation and heating. IGBTs become damaged

when the current load approaches the saturation current of the device and the collector-emitter voltage, VCE,

rises above the saturation voltage level, VCE-sat. The drastically increased power dissipation overheats and

destroys the IGBT.

To prevent damage to IGBT applications, the implemented fault detection slowly reduces the overcurrent in a

controlled manner during the fault condition.

Product Folder Links: ISO5500

BLK DSTH

BLK

CHG

C V 100 pF 7.2 V

t = = = 2.7 μ s

I 270 μA

´ ´

VCC2

Gate

Drive

15V

7.2V Q1a

Q1b

Q2aQ2b

VOUT

VEE-P

Off

DESAT

Slow

Off

DESAT

CBLK

ISO5500

Fault

VCE

VIN+

Fault

VDESAT

VOUT

7.2V

VEE-L

Dschg

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

Figure 59. DESAT Fault Detection and Protection

The DESAT fault detection involves a comparator that monitors the IGBT’s VCE and compares it to an internal 7.2

V reference. If VCE exceeds this reference voltage, the comparator causes the gate-drive and fault-logic to initiate

a fault shutdown sequence. This sequence starts with the immediate generation of a fault signal, which is

transmitted across the isolation barrier towards the Fault indicator circuit at the input side of the ISO5500.

At the same time the fault logic turns off the power-pair Q1 and turns on the small discharge MOSFETs, Q3 and

Q4. Q3 slowly discharges the IGBT gate voltage which causes the high short-circuit current through the IGBT to

gradually decrease, thereby preventing large di/dt induced voltage transients. Q4 discharges the blanking

capacitor. Once VOUT is sufficiently close to VEE-P potential (at approximately 2 V), the large Q2-pair turns on in

addition to Q3 to clamp the IGBT gate to VEE-P.

NOTE

The DESAT detection circuit is only active when the IGBT is turned on. When the IGBT is

turned off, and its VCE is at maximum, the fault detection is simply disabled to prevent

false triggering of fault signals.

8.3.12 DESAT Blanking Time

The DESAT fault detection must remain disabled for a short time period following the turn-on of the IGBT to allow

its collector voltage to drop below the 7.2 V DESAT threshold. This time period, called the DESAT blanking time,

tBLK, is controlled by an internal charge current of ICHG = 270 μA, the 7.2 V DESAT threshold, VDSTH, and an

external blanking capacitor, CBLK.

The nominal blanking time with a recommended capacitor value of CBLK = 100 pF is calculated with:

(1)

The capacitor value can be scaled slightly to adjust the blanking time. However, because the blanking capacitor

and the DESAT diode capacitance build a voltage divider that attenuates large voltage transients at DESAT,

CBLK values smaller than 100 pF are not recommended. The nominal blanking time also represents the ISO5500

maximum response time to a DESAT fault condition.

If a short circuit condition exists prior to the turn-on of the IGBT, (causing the IGBT switching into a short) the soft

shutdown sequence begins after approximately 3 μs. However, if a short circuit condition occurs while the IGBT

is already on, the response time is significantly shorter due to the parasitic parallel capacitance of the DESAT

diode. The recommended value of 100 pF however, provides sufficient blanking and fault response times for

most applications.

Product Folder Links: ISO5500

FAULT

ISO - Barrier

DELAY

GND1

VIN+

VIN-

VCC1

FAULT

RESET

ISO5500

3.3V

µC

I/P

O/P

PWM

RPU

ISO

VIN+

ISO

FAULT

RESET

DIS

Delay

Short

occurs

“IGBT

On”

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

The timing diagram in Figure 59 shows the DESAT function for both, normal operation and a short-circuit fault

condition. The use of VIN+ as control input implies non-inverting input configuration.

During normal operation VDESAT will display a small sawtooth waveform every time VIN+ goes high. The ramp of

the sawtooth is caused by the internal current source charging the blanking capacitor. Once the IGBT collector

has sufficiently dropped below the capacitor voltage, the DESAT diode conducts and discharges CBLK through

the IGBT.

In the event of a short circuit fault; however, high IGBT collector voltage prevents the diode from conducting and

the voltage at the blanking capacitor continues to rise until it reaches the DESAT threshold. When the output of

the DESAT comparator goes high, the gate-drive and fault-logic circuit initiates the soft shutdown sequence and

also produces a Fault signal that is fed back to the input side of the ISO5500.

8.3.13 FAULT Alarm

The Fault alarm unit consists of three circuit elements, a RS flip-flop to store the fault signal received from the

gate-drive and fault-logic, an open-drain MOSFET output signaling the fault condition to the micro controller, and

a delay circuit blocking the control inputs after the soft shutdown sequence of the IGBT has been completed.

Figure 60 shows the ISO5500 in a non-inverting input configuration. Because the FAULT-pin is an open-drain

output, it requires a pull-up resistor, RPU, in the order of 3.3 kΩto 10 kΩ. The internal signals DIS, ISO, and

FAULT represent the input-disable signal, the isolator output signal, and the fault feedback signal respectively.

Figure 60. Fault Alarm Circuitry and Timing Sequence

The timing diagram shows that the micro controller initiates an IGBT-on command by taking VIN+ high. After

propagating across the isolation barrier ISO goes high, activating the output stage.

1. Upon a short circuit condition the gate-drive and fault-logic feeds back a fault signal (FAULT = high) which

sets the RS-FF driving the FAULT output active-low.

2. After a delay of approximately 3 μs, the time required to shutdown the IGBT, DIS becomes high and blocks

the control inputs

3. This in turn drives ISO low

4. which, after propagating through the output fault-logic, drives FAULT low.

At this time both flip-flop inputs are low and the fault signal is stored.

5. Once the failure cause has been removed the micro controller must set the control inputs into an "Output-

low" state before applying the Reset pulse.

6. Taking the RESET-input low resets the flip-flop, which removes the fault signal from the controller by pulling

FAULT high and releases the control inputs by driving DIS low

Product Folder Links: ISO5500

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

8.4 Device Functional Modes

Table 2. Function Table

UVLO DESAT DETECTED ON PIN 6 (FAULT)

VIN+ VIN- VOUT

(VCC2 – VE) PIN 14 (DESAT) OUTPUT

X X Active X X Low

X X X Yes Low Low

Low X X X X Low

X High X X X Low

High Low Not active No High High

Product Folder Links: ISO5500

µC

PWM

FAULT

3-PHASE

INPUT

ISO 5500

ISOLATIONBARRIER

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO5500 is an isolated gate driver for high power devices such as IGBTs and MOSFETs with power ratings

of up to IC = 150 A and VCE = 600 V. It is intended for use in applications such as motor control, industrial

inverters and switched-mode power supplies. In these applications, sophisticated PWM control signals are

required to turn the power-devices on and off, which at the system level eventually may determine, for example,

the speed, position, and torque of the motor or the output voltage, frequency and phase of the inverter. These

control signals are usually the outputs of a micro controller, and are at low voltage levels such as 3.3 V or 5.0 V.

The gate controls required by the MOSFETs and IGBTs, on the other hand, are in the range of 15 V to 30 V, and

need high current capability to be able to drive the large capacitive loads offered by those power transistors. Not

only that, the gate drive needs to be applied with reference to the Emitter of the IGBT (Source for MOSFET), and

by construction, the Emitter node in a gate drive system swings between 0 to the DC bus voltage, which is

several 100s of volts in magnitude.

The ISO5500 is thus used to level shift the incoming 3.3-V and 5.0-V control signals from the microcontroller to

the 15-V to 30-V drive required by the power transistors while ensuring high-voltage isolation between the driver

side and the microcontroller side.

9.2 Typical Application

Figure 61 shows the typical application of a three-phase inverter using six ISO5500 isolated gate drivers. Three-

phase inverters are used for variable-frequency drives to control the operating speed of AC motors and for high

power applications such as High-Voltage DC (HVDC) power transmission.

The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5500

devices that are connected to one of the three load terminals. The operation of the three switches is coordinated

so that one switch operates at each 60 degree point of the fundamental output waveform, thus creating a six-

step line-to-line output waveform. In this type of applications carrier-based PWM techniques are applied to retain

waveform envelope and cancel harmonics.

Figure 61. Typical Motor Drive Application

Product Folder Links: ISO5500

100 Ω

VIN+

VIN-

VCC1

GND1

DESAT

VEE -L

VCC2

VOUT

VEE -L

VEE-P

RESET

FAULT

15V

0.1

μF

0.1

μF

3.3V

μC

ISO5500

3.3

kΩ

330 pF

0.1

μF

100

DDESAT

VCE

3-PHASE

OUTPUT

0.1

μF

15V

4.7

μF

DS(opt.)

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

Typical Application (continued)

9.2.1 Design Requirements

Unlike optocoupler based gate drivers which need external current drivers and biasing circuitry to provide the

input control signals, the input control to the ISO5500 is TTL and can be directly driven by the microcontroller.

Other design requirements include decoupling capacitors on the input and output supplies, a pullup resistor on

the common drain FAULT output signal, and a high-voltage protection diode between the IGBT collector and the

DESAT input. Further details are explained in the subsequent sections.

9.2.2 Detailed Design Procedure

9.2.2.1 Recommended ISO5500 Application Circuit

The ISO5500 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open

drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 62 illustrates

a typical gate drive implementation using the ISO5500.

The four 0.1 μF supply bypass capacitors provide the large transient currents necessary during a switching

transition. Because of the transient nature of the charging currents, low current (20 mA) power supplies for VCC2

and VEE-P suffice. The 100 pF blanking capacitor disables DESAT detection during the off-to-on transition of the

power device. The DESAT diode and its 100 Ωseries resistor are important external protection components for

the fault detection circuitry. The 10 Ωgate resistor limits the gate charge current and indirectly controls the IGBT

collector voltage rise and fall times. The open-drain fault output has a passive 3.3 kΩpull-up resistor and a

330pF filtering capacitor. In this application, the IGBT gate driver will shut down when a fault is detected and will

not resume switching until the micro-controller applies a reset signal.

Figure 62. Recommended Application Circuit

9.2.2.2 FAULT Pin Circuitry

The FAULT pin is an open-drain output requiring a 3.3 kΩpull-up resistor to provide logic high when FAULT is

inactive.

Because fast common mode transients can alter the FAULT-pin voltage during high state, a 330 pF capacitor

connected between FAULT and GND1 is recommended to provide sufficient noise margin at the specified CMTI

of 50 kV/μs. The added capacitance does not increase the FAULT response time during a fault condition.

Product Folder Links: ISO5500

VIN+

VIN-

VCC1

GND1

RESET

FAULT

µC

ISO5500

7NC

GND1

VIN+

VIN-

VCC1

GND1

RESET

FAULT

µC

ISO5500

7NC

GND1

VIN+

VIN-

VCC1

GND1

RESET

FAULT

0.1

µF

5 V

µC

ISO5500

3.3

330 pF

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Typical Application (continued)

Figure 63. FAULT Pin Circuitry for High CMTI

9.2.2.3 Driving the Control Inputs

The amount of common-mode transient immunity (CMTI) is primarily determined by the capacitive coupling from

the high-voltage output circuit to the low-voltage input side of the ISO5500. For maximum CMTI performance, the

digital control inputs, VIN+ and VIN–, must be actively driven by standard CMOS or TTL, push-pull drive circuits.

This type of low-impedance signal source provides active drive signals that prevent unwanted switching of the

ISO5500 output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain

configurations using pull-up resistors, must be avoided.

9.2.2.4 Local Shutdown and Reset

In applications with local shutdown and reset, the FAULT output of each gate driver is polled separately, and the

individual reset lines are asserted low independently to reset the motor controller after a fault condition.

Figure 64. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)

9.2.2.5 Global-Shutdown and Reset

When configured for inverting operation, the ISO5500 can be configured to shutdown automatically in the event

of a fault condition by tying the FAULT output to VIN+. For high reliability drives, the open drain FAULT outputs of

multiple ISO5500 devices can be wired together forming a single, common fault bus for interfacing directly to the

micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FAULT

output disables all six gate drivers simultaneously; thereby, providing protection against further catastrophic

failures.

Product Folder Links: ISO5500

VIN+

VIN-

VCC1

GND1

RESET

FAULT

µC

ISO5500

7NC

GND1

VIN+

VIN-

VCC1

GND1

RESET

FAULT

µC

ISO5500

7NC

GND1

VIN+

VIN-

VCC1

GND1

RESET

FAULT

µC

ISO5500

7NC

GND1

to other

RESETs

to other

FAULTs

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

Typical Application (continued)

Figure 65. Global Shutdown with Inverting Input Configuration

9.2.2.6 Auto-Reset

Connecting RESET to the active control input (VIN+ for non-inverting, or VIN– for inverting operation) configures

the ISO5500 for automatic reset capability. In this case, the gate control signal at VIN is also applied to the

RESET input to reset the fault latch every switching cycle. During normal IGBT operation, asserting RESET low

has no effect on the output. For a fault condition, however, the gate driver remains in the latched fault state until

the gate control signal changes to the 'gate low' state and resets the fault latch.

If the gate control signal is a continuous PWM signal, the fault latch will always be reset before VIN+ goes high

again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next

'on' cycle. When the ISO5500 is configured for Auto Reset, the specified minimum FAULT signal pulse width is

3μs.

Figure 66. Auto Reset for Non-inverting and Inverting Input Configuration

9.2.2.7 Resetting Following a Fault Condition

To resume normal switching operation following a fault condition (FAULT output low), the gate control signal

must be driven into a 'gate low' state before asserting RESET low. This can be accomplished with a micro-

controller, or an additional logic gate that synchronizes the RESET signal with the appropriate input signal.

Product Folder Links: ISO5500

DESAT

VEE-L

VCC2

VOUT

VEE-P

15V

ISO5500

100

DDESAT

Rg+

15V

DS(opt.)

VFW-inst

VFW

VEE-L

VIN+

VIN-

VCC1

GND1

RESET

FAULT

µC

ISO5500

7NC

GND1

VIN+

VIN-

VCC1

GND1

RESET

FAULT

µC

7NC

GND1

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Typical Application (continued)

Figure 67. Auto Reset with Prior Gate-low Assertion for Non-inverting and Inverting Input Configuration

9.2.2.8 DESAT Pin Protection

Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes

of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial

current out of the device. To limit this current below damaging levels, a 100 Ωto 1 kΩresistor is connected in

series with the DESAT diode. The added resistance neither alters the DESAT threshold nor the DESAT blanking

time.

Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of

the DESAT input to VEpotential at low voltage levels.

Figure 68. DESAT Pin Protection with Series Resistor and Optional Schottky Diode

9.2.2.9 DESAT Diode and DESAT Threshold

The DESAT diode’s function is to conduct forward current, allowing sensing of the IGBT’s saturated collector-to-

emitter voltage, VCESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the

short transition time when the IGBT is switching, there is commonly a high dVCE/dt voltage ramp rate across the

IGBT. This results in a charging current ICHARGE = CD-DESAT x dVCE/dt, charging the blanking capacitor.

To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are

recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector

voltage transients appear at DESAT attenuated by the ratio of 1+ CBLANK / CD-DESAT.

Table 3 lists a number of fast-recovery diodes suitable for the use as DESAT diodes.

Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the

voltage at the DESAT-pin, VF+ VCE = VDESAT, the VCE level, which triggers a fault condition, can be modified by

adding multiple DESAT diodes in series: VCE-FAULT(TH) = 7.2 V – n x VF (where n is the number of DESAT

diodes).

Product Folder Links: ISO5500

( ) on-max off- max

OL-WC INP G CC2 EE-P

on-max G off-max G

r r

P = 0.5 f Q V V +

r + R r + R

æ ö

´ ´ ´ - ´ ç ÷

è ø

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

Typical Application (continued)

When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be

chosen.

Table 3. Recommended DESAT Diodes

PART NUMBER MANUFACTURER trr (ns) VRRM-max (V) PACKAGE

STTH112 STM 75 1200 SMA, SMB, DO-41

MUR100E Motorola 75 1000 59-04 (axial leaded)

MURS160T3 Motorola 75 600 Case 403A (SMD)

UF4007 General Semi. 75 1000 DO-204AL (axial leaded)

BYM26E Philips 75 1000 SOD64 (axial leaded)

BYV26E Philips 75 1000 SOD57 (axial leaded)

BYV99 Philips 75 600 SOD87 (axial leaded)

9.2.2.10 Determining the Maximum Available, Dynamic Output Power, POD-max

The ISO5500 total power consumption of PD= 592 mW consists of the total input power, PID, the total output

power, POD, and the output power under load, POL:

PD= PID + POD + POL (2)

With:PID = VCC1-max × ICC1-max = 5.5 V × 8.5 mA = 47 mW (3)

and: POD = (VCC2 – VEE-P) x ICC2-q = 30 V × 14 mA = 420 mW (4)

then:POL = PD– PID – POD = 592 mW – 47 mW – 420 mW = 125 mW (5)

In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety

of parameters:

where

• fINP = signal frequency at the control input VIN(±)

• QG= power device gate charge

• VCC2 = positive output supply with respect to VE

• VEE-P = negative output supply with respect to VE

• ron-max = worst case output resistance in the on-state: 4Ω

• roff-max = worst case output resistance in the off-state: 2.5Ω

• RG= gate resistor (6)

Once RG is determined, Equation 6 is to be used to verify whether POL-WC < POL.Figure 69 shows a simplified

output stage model for calculating POL-WC.

Product Folder Links: ISO5500

CC2 EE-P

ON-PK

V V

R =

VCC2

VOUT

VEE-P

ISO5500

15 V

Ion

VCC2 - VEE-P

VCC2

VOUT

VEE-P

ISO5500

15 V

Ioff

VCC2 - VEE-P

VEVE

VCC2

VOUT

VEE-P

ISO5500

15 V

ron-max

roff-max

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

Figure 69. Simplified Output Model for Calculating POL-WC

9.2.2.11 Determining Gate Resistor, RG

The value of the gate resistor determines the peak charge and discharge currents, ION-PK and IOFF-PK. Due to the

transient nature of these currents, their peak values only occur during the on-to-off and off-to-on transitions of the

gate voltage. In order to calculate RGfor the maximum peak current, ron and roff must be assumed zero. The

resulting charge and discharge models are shown in Figure 70.

Figure 70. Simplified Gate Charge and Discharge Model

9.2.2.11.1 Off-to-On Transition

In the off-state, the upper plate of the gate capacitance, CG, assumes a steady-state potential of –VEE-P with

respect to VE. When turning on the power device, VCC2 is applied to VOUT and the voltage drop across RGresults

in a peak charge current of ION-PK = (VCC2 – VEE-P)/RG. Solving for RGthen provides the necessary resistor value

for a desired on-current via:

(7)

9.2.2.11.2 On-to-Off Transition

When turning the power device off, the current and voltage relations are reversed but the equation for calculating

RGremains the same.

Once RGhas been calculated, it is necessary to check whether the resulting, worst-case power consumption,

POD-WC, (derived in Equation 6) is below the calculated maximum, POL = 125 mW (calculated in Equation 5).

Product Folder Links: ISO5500

OFF-PK

C G

ON-PK

R = R 1

æ ö

´ -

ç ÷

è ø

CC2 EE-P

OFF-PK

V V

R =

CC2 EE-P

C G

ON-PK

V V

R = R

VCC2

VOUT

VEE-P

ISO5500

15 V

RGCG

15 V

Ion-pk

VCC2-VEE-P

VCC2

VOUT

VEE-P

ISO5500

15 V

RGCG

15 V

Ioff-pk

VCC2 - VEE-P

VEVE

( )

OL-WC

4 Ω 2.5 Ω

P = 0.5 20 kHz 650 nC 15 V ( 5V) + = 63 mW

4 Ω + 10Ω 2.5 Ω + 10 Ω

æ ö

´ ´ ´ - - ´ ç ÷

è ø

15V ( 5V)

R = = 10 Ω

- -

ISO5500

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SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

9.2.2.12 Example

The example below considers an IGBT drive with the following parameters:

ION-PK =2A,QG= 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE-P = –5 V

Applying Equation 7, the value of the gate resistor is calculated with

(8)

Then, calculating the worst-case output power consumption as a function of RG, using Equation 6 yields

(9)

Because POL-WC = 63 mW is well below the calculated maximum of POL = 125 mW, the resistor value of RG=

10Ωis fully suitable for this application.

9.2.2.13 Determining Collector Resistor, RC

Despite equal charge and discharge currents, many power devices possess longer turn-off propagation and fall

times than turn-on propagation and rise times. In order to compensate for the difference in switching times, it

might be necessary to significantly reduce the charge current, ION-PK, versus the discharge current, IOFF-PK.

Reducing ION-PK is accomplished by inserting an external resistor, RC, between the VC- pin and the VCC2- pin of

the ISO5500.

Figure 71. Reducing ION-PK by Inserting Resistor RC

Figure 71 (right) shows that during the on-transition, the (VCC2 – VEE-P) voltage drop occurs across the series

resistance of RC+ RG, thus reducing the peak charge current to: ION-PK = (VCC2 – VEE-P) /(RC+ RG). Solving for RC

provides:

(10)

To stay below the maximum output power consumption, RGmust be calculated first via:

(11)

and the necessary comparison of POL-WC versus POL must be completed.

Once RGis determined, calculate RCfor a desired on-current using Equation 10.

Another method is to insert Equation 11 into Equation 10 and arriving at:

(12)

Product Folder Links: ISO5500

Time 125 ns / div

5 V / div

V - V = 30 V

R = 0 ,

C = 10 nF

CC2 EE

100 pF

10 W4.5 W

2.5 W

MJD44H11

D44VH10

MJD45H11

D45VH10

15 V

DESAT

VEE-L

VCC2

VOUT

VEE-P

ISO5500

VEE-L

2 A

R = 10 Ω 1 = 3.33 Ω

1.5 A

æ ö

´ -

ç ÷

è ø

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

9.2.2.13.1 Example

Reducing the peak charge current from the previous example to ION-PK = 1.5 A, requires a RCvalue of:

(13)

9.2.2.14 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in

Figure 72) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and

must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10

pair for up to 15 A maximum.

Figure 72. Current Buffer for Increased Drive Current

9.2.3 Application Curve

Figure 73. Output Waveform

Product Folder Links: ISO5500

10 mils

40 mils

FR-4

0r~ 4.5

Keep this

space free

from planes,

traces , pads,

and vias

Ground plane

Power plane

Low-speed traces

High-speed traces

ISO5500

www.ti.com

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

10 Power Supply Recommendations

To provide the large transient currents necessary during a switching transition on the gate driver output, 0.1-μF

bypass capacitors are recommended between input supply and ground (VCC1 and GND1), and between output

supplies and ground (VCC2 and VE, VCC2 and VEE-P and VEE-P and VE). These capacitors are shown in Figure 62.

These capacitors should be placed as close to the supply and ground pins as possible.

11 Layout

11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 74). Layer stacking should

be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and

low-frequency signal layer.

• Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of

their inductances) and allows for clean interconnects between the gate driver and the microcontroller and

power transistors. Gate driver control input, Gate driver output VOUT and DESAT should be routed in the top

layer.

• Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for

the return current flow. On the driver side, use VE as the ground plane.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in2. On the gate-driver VEE-P and VCC2 can be used as power planes. They can share

the same layer on the PCB as long as they are not connected together.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,

routing etc. see Application Note SLLA284,Digital Isolator Design Guide.

11.2 PCB Material

Standard FR-4 epoxy-glass is recommended as PCB material. FR-4 (Flame Retardant 4) meets the

requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower

dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-

extinguishing flammability-characteristics.

11.3 Layout Example

Figure 74. Recommended Layer Stack

Product Folder Links: ISO5500

ISO5500

SLLSE64D –SEPTEMBER 2011–REVISED JANUARY 2015

www.ti.com

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

•ISO5500 Evaluation Module (EVM) User’s Guide,SLLU136

•Digital Isolator Design Guide,SLLA284

12.2.1.1 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12.3 Trademarks

All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

SLLA353 -- Isolation Glossary.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: ISO5500

PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ISO5500DW ACTIVE SOIC DW 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO5500DW

ISO5500DWR ACTIVE SOIC DW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO5500DW

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2014

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ISO5500DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Oct-2014

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ISO5500DWR SOIC DW 16 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Oct-2014

Pack Materials-Page 2

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

DW 16 SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

4040000-2/H

www.ti.com

PACKAGE OUTLINE

TYP

10.63

9.97

2.65 MAX

14X 1.27

16X 0.51

0.31

8.89

TYP

0.33

0.10

0 - 8 0.3

0.1

(1.4)

0.25

GAGE PLANE

1.27

0.40

NOTE 3

10.5

10.1

BNOTE 4

7.6

7.4

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

116

0.25 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.500

www.ti.com

EXAMPLE BOARD LAYOUT

(9.75)

R0.05 TYP

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

(9.3)

14X (1.27)

R0.05 TYP

16X (1.65)

16X (0.6)

14X (1.27)

16X (2)

16X (0.6)

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

SYMM

SEE

DETAILS

SYMM

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL

SOLDER MASK

DEFINED

LAND PATTERN EXAMPLE

SCALE:4X

SYMM

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SEE

DETAILS

www.ti.com

EXAMPLE STENCIL DESIGN

R0.05 TYP

16X (1.65)

16X (0.6)

14X (1.27)

(9.75)

16X (2)

16X (0.6)

14X (1.27)

(9.3)

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

SYMM

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

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