AD8221ARMZ-RL - Analog Devices, Inc.

Precision Instrumentation Amplifier

AD8221

Rev. C

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Easy to use

Available in space-saving MSOP

Gain set with 1 external resistor (gain range 1 to 1000)

Wide power supply range: ±2.3 V to ±18 V

Temperature range for specified performance:

−40°C to +85°C

Operational up to 125°C1

Excellent AC specifications

80 dB minimum CMRR to 10 kHz (G = 1)

825 kHz, –3 dB bandwidth (G = 1)

2 V/µs slew rate

Low noise

8 nV/√Hz, @ 1 kHz, maximum input voltage noise

0.25 µV p-p input noise (0.1 Hz to 10 Hz)

High accuracy dc performance (AD8221BR)

90 dB minimum CMRR (G = 1)

25 µV maximum input offset voltage

0.3 µV/°C maximum input offset drift

0.4 nA maximum input bias current

APPLICATIONS

Weigh scales

Industrial process controls

Bridge amplifiers

Precision data acquisition systems

Medical instrumentation

Strain gages

Transducer interfaces

GENERAL DESCRIPTION

The AD8221 is a gain programmable, high performance

instrumentation amplifier that delivers the industry’s highest

CMRR over frequency in its class. The CMRR of instrumentation

amplifiers on the market today falls off at 200 Hz. In contrast,

the AD8221 maintains a minimum CMRR of 80 dB to 10 kHz

for all grades at G = 1. High CMRR over frequency allows the

AD8221 to reject wideband interference and line harmonics,

greatly simplifying filter requirements. Possible applications

include precision data acquisition, biomedical analysis, and

aerospace instrumentation.

CONNECTION DIAGRAM

–IN

OUT

REF

–V

+IN

TOP VIEW

AD8221

03149-001

Figure 1.

CMRR (dB)

100

110

120

FREQUENCY (Hz)

10010 1k 10k 100k

03149-002

AD8221

COMPETI

TOR 1

COMPETITOR 2

Figure 2. Typical CMRR vs. Frequency for G = 1

Low voltage offset, low offset drift, low gain drift, high gain

accuracy, and high CMRR make this part an excellent choice

in applications that demand the best dc performance possible,

such as bridge signal conditioning.

Programmable gain affords the user design flexibility. A single

resistor sets the gain from 1 to 1000. The AD8221 operates on

both single and dual supplies and is well suited for applications

where ±10 V input voltages are encountered.

The AD8221 is available in a low cost 8-lead SOIC and 8-lead

MSOP, both of which offer the industry’s best performance. The

MSOP requires half the board space of the SOIC, making it ideal

for multichannel or space-constrained applications.

Performance is specified over the entire industrial temperature

range of −40°C to +85°C for all grades. Furthermore, the AD8221

is operational from −40°C to +125°C1.

1 See Typical Performance Characteristics for expected operation from

85°C to 125°C.

AD8221

Rev. C | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Connection Diagram ....................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 17

Gain Selection ............................................................................. 18

Layout .......................................................................................... 18

Reference Terminal .................................................................... 19

Power Supply Regulation and Bypassing ................................ 19

Input Bias Current Return Path ............................................... 19

Input Protection ......................................................................... 19

RF Interference ........................................................................... 20

Precision Strain Gage ................................................................. 20

Conditioning ±10 V Signals for a +5 V Differential Input

ADC ............................................................................................. 20

AC-Coupled Instrumentation Amplifier ................................ 21

Die Information .............................................................................. 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

REVISION HISTORY

3/11—Rev. B to Rev. C

Added Pin Configuration and Function Descriptions Section .. 9

Added Die Information Section ................................................... 22

Updated Outline Dimensions ....................................................... 23

Changes to Ordering Guide .......................................................... 24

9/07—Rev. A to Rev. B

Changes to Features .......................................................................... 1

Changes to Table 1 Layout ............................................................... 3

Changes to Table 2 Layout ............................................................... 5

Changes to Figure 15 ...................................................................... 11

Changes to Figures 32 .................................................................... 13

Changes to Figure 33, Figure 34, and Figure 35 ......................... 14

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 22

11/03—Rev. 0 to Rev. A

Changes to Features .......................................................................... 1

Changes to Specifications Section .................................................. 4

Changes to Theory of Operation Section .................................... 13

Changes to Gain Selection Section............................................... 14

10/03—Revision 0: Initial Version

AD8221

Rev. C | Page 3 of 24

SPECIFICATIONS

VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.

Table 1.

AR Grade BR Grade

Parameter Conditions Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION RATIO

CMRR DC to 60 Hz with 1 kΩ

Source Imbalance

VCM = −10 V to +10 V

G = 1 80 90 dB

G = 10 100 110 dB

G = 100 120 130 dB

G = 1000 130 140 dB

CMRR at 10 kHz VCM = −10 V to +10 V

G = 1 80 80 dB

G = 10 90 100 dB

G = 100 100 110 dB

G = 1000 100 110 dB

NOISE RTI noise =

√eNI2 + (eNO/G)2

Voltage Noise, 1 kHz

Input Voltage Noise, eNI V

IN+, VIN−, VREF = 0 8 8 nV/√Hz

Output Voltage Noise, eNO 75 75 nV/√Hz

RTI f = 0.1 Hz to 10 Hz

G = 1 2 2 μV p-p

G = 10 0.5 0.5 μV p-p

G = 100 to 1000 0.25 0.25 μV p-p

Current Noise f = 1 kHz 40 40 fA/√Hz

f = 0.1 Hz to 10 Hz 6 6 pA p-p

VOLTAGE OFFSET1

Input Offset, VOSI V

S = ±5 V to ±15 V 60 25 μV

Over Temperature T = −40°C to +85°C 86 45 μV

Average TC 0.4 0.3 μV/°C

Output Offset, VOSO V

S = ±5 V to ±15 V 300 200 μV

Over Temperature T = −40°C to +85°C 0.66 0.45 mV

Average TC 6 5 μV/°C

Offset RTI vs. Supply (PSR) VS = ±2.3 V to ±18 V

G = 1 90 110 94 110 dB

G = 10 110 120 114 130 dB

G = 100 124 130 130 140 dB

G = 1000 130 140 140 150 dB

INPUT CURRENT

Input Bias Current 0.5 1.5 0.2 0.4 nA

Over Temperature T = −40°C to +85°C 2.0 1 nA

Average TC 1 1 pA/°C

Input Offset Current 0.2 0.6 0.1 0.4 nA

Over Temperature T = −40°C to +85°C 0.8 0.6 nA

Average TC 1 1 pA/°C

REFERENCE INPUT

RIN 20 20 kΩ

IIN V

IN+, VIN−, VREF = 0 50 60 50 60 μA

Voltage Range –VS +VS –VS +VS V

Gain to Output 1 ± 0.0001 1 ± 0.0001 V/V

AD8221

Rev. C | Page 4 of 24

AR Grade BR Grade

Parameter Conditions Min Typ Max Min Typ Max Unit

POWER SUPPLY

Operating Range V

= ±2.3 V to ±18 V ±2.3 ±18 ±2.3 ±18 V

Quiescent Current 0.9 1 0.9 1 mA

Over Temperature T = −40°C to +85°C 1 1.2 1 1.2 mA

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 1 825 825 kHz

G = 10 562 562 kHz

G = 100 100 100 kHz

G = 1000 14.7 14.7 kHz

Settling Time 0.01% 10 V step

G = 1 to 100 10 10 µs

G = 1000 80 80 µs

Settling Time 0.001% 10 V step

G = 1 to 100 13 13 µs

G = 1000 110 110 µs

Slew Rate G = 1 1.5 2 1.5 2 V/µs

G = 5 to 100 2 2.5 2 2.5 V/µs

GAIN G = 1 + (49.4 kΩ/R

)

Gain Range 1 1000 1 1000 V/V

Gain Error VOUT ± 10 V

G = 1 0.03 0.02 %

G = 10 0.3 0.15 %

G = 100 0.3 0.15 %

G = 1000 0.3 0.15 %

Gain Nonlinearity VOUT = −10 V to +10 V

G = 1 to 10 RL = 10 kΩ 3 10 3 10 ppm

G = 100 RL = 10 kΩ 5 15 5 15 ppm

G = 1000 RL = 10 kΩ 10 40 10 40 ppm

G = 1 to 100 R

= 2 kΩ 10 95 10 95 ppm

Gain vs. Temperature

G = 1 3 10 2 5 ppm/°C

G > 12 –50 –50 ppm/°C

INPUT

Input Impedance

Differential 100||2 100||2 GΩ||pF

Common Mode 100||2 100||2 GΩ||pF

Input Operating Voltage Range3VS = ±2.3 V to ±5 V –VS + 1.9 +VS − 1.1 –VS + 1.9 +VS − 1.1 V

Over Temperature T = −40°C to +85°C –VS + 2.0 +VS − 1.2 –VS + 2.0 +VS − 1.2 V

Input Operating Voltage Range VS = ±5 V to ±18 V –VS + 1.9 +VS − 1.2 –VS + 1.9 +VS − 1.2 V

Over Temperature T =−40°C to +85°C –VS + 2.0 +VS − 1.2 –VS + 2.0 +VS − 1.2 V

OUTPUT RL = 10 kΩ

Output Swing VS = ±2.3 V to ±5 V –VS + 1.1 +VS − 1.2 –VS + 1.1 +VS − 1.2 V

Over Temperature T = −40°C to +85°C –VS + 1.4 +Vs − 1.3 –VS + 1.4 +VS − 1.3 V

Output Swing VS = ±5 V to ±18 V –VS + 1.2 +VS − 1.4 –VS + 1.2 +VS − 1.4 V

Over Temperature T = –40°C to +85°C –VS + 1.6 +VS − 1.5 –VS + 1.6 +VS − 1.5 V

Short-Circuit Current 18 18 mA

AD8221

Rev. C | Page 5 of 24

AR Grade BR Grade

Parameter Conditions Min Typ Max Min Typ Max Unit

TEMPERATURE RANGE

Specified Performance –40 +85 –40 +85 °C

Operating Range4 –40 +125 –40 +125 °C

1 Total RTI VOS = (VOSI) + (VOSO/G).

2 Does not include the effects of external resistor RG.

3 One input grounded. G = 1.

4 See Typical Performance Characteristics for expected operation between 85°C to 125°C.

Table 2.

Parameter Conditions

ARM Grade

Unit Min Typ Max

COMMON-MODE REJECTION RATIO (CMRR)

CMRR DC to 60 Hz with 1 kΩ Source Imbalance VCM = −10 V to +10 V

G = 1 80 dB

G = 10 100 dB

G = 100 120 dB

G = 1000 130 dB

CMRR at 10 kHz VCM = –10 V to +10 V

G = 1 80 dB

G = 10 90 dB

G = 100 100 dB

G = 1000 100 dB

NOISE RTI noise = √eNI2 + (eNO/G)2

Voltage Noise, 1 kHz

Input Voltage Noise, e

IN+

, V

IN−

, V

REF

= 0 8 nV/√Hz

Output Voltage Noise, eNO 75 nV/√Hz

RTI f = 0.1 Hz to 10 Hz

G = 1 2 µV p-p

G = 10 0.5 µV p-p

G = 100 to 1000 0.25 µV p-p

Current Noise f = 1 kHz 40 fA/√Hz

f = 0.1 Hz to 10 Hz 6 pA p-p

VOLTAGE OFFSET1

Input Offset, V

OSI

= ±5 V to ±15 V 70 µV

Over Temperature T = −40°C to +85°C 135 µV

Average TC 0.9 µV/°C

Output Offset, VOSO VS = ±5 V to ±15 V 600 µV

Over Temperature T = −40°C to +85°C 1.00 mV

Average TC 9 µV/°C

Offset RTI vs. Supply (PSR) VS = ±2.3 V to ±18 V

G = 1 90 100 dB

G = 10 100 120 dB

G = 100 120 140 dB

G = 1000 120 140 dB

INPUT CURRENT

Input Bias Current 0.5 2 nA

Over Temperature T = −40°C to +85°C 3 nA

Average TC 3 pA/°C

Input Offset Current 0.3 1 nA

Over Temperature T = −40°C to +85°C 1.5 nA

Average TC 3 pA/°C

AD8221

Rev. C | Page 6 of 24

Parameter Conditions

ARM Grade

Unit Min Typ Max

REFERENCE INPUT

20 kΩ

IIN VIN+, VIN−, VREF = 0 50 60 µA

Voltage Range −VS +VS V

Gain to Output 1 ± 0.0001 V/V

POWER SUPPLY

Operating Range VS = ±2.3 V to ±18 V ±2.3 ±18 V

Quiescent Current 0.9 1 mA

Over Temperature T = −40°C to +85°C 1 1.2 mA

DYNAMIC RESPONSE

Small Signal –3 dB Bandwidth

G = 1 825 kHz

G = 10 562 kHz

G = 100 100 kHz

G = 1000 14.7 kHz

Settling Time 0.01% 10 V step

G = 1 to 100 10 µs

G = 1000 80 µs

Settling Time 0.001% 10 V step

G = 1 to 100 13 µs

G = 1000 110 µs

Slew Rate G = 1 1.5 2 V/µs

G = 5 to 100 2 2.5 V/µs

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 1000 V/V

Gain Error VOUT ± 10 V

G = 1 0.1 %

G = 10 0.3 %

G = 100 0.3 %

G = 1000 0.3 %

Gain Nonlinearity VOUT = −10 V to +10 V

G = 1 to 10 RL = 10 kΩ 5 15 ppm

G = 100 R

= 10 kΩ 7 20 ppm

G = 1000 RL = 10 kΩ 10 50 ppm

G = 1 to 100 RL = 2 kΩ 15 100 ppm

Gain vs. Temperature

G = 1 3 10 ppm/°C

G > 12 –50 ppm/°C

INPUT

Input Impedance

Differential 100||2 GΩ/pF

Common Mode 100||2 GΩ/pF

Input Operating Voltage Range3VS = ±2.3 V to ±5 V –VS + 1.9 +VS − 1.1 V

Over Temperature T = −40°C to +85°C –VS + 2.0 +VS − 1.2 V

Input Operating Voltage Range VS = ±5 V to ±18 V –VS + 1.9 +VS − 1.2 V

Over Temperature T = −40°C to +85°C –VS + 2.0 +VS − 1.2 V

OUTPUT RL = 10 kΩ

Output Swing VS = ±2.3 V to ±5 V –VS + 1.1 +VS − 1.2 V

Over Temperature T = −40°C to +85°C –VS + 1.4 +VS − 1.3 V

Output Swing VS = ±5 V to ±18 V –VS + 1.2 +VS − 1.4 V

Over Temperature T = −40°C to +85°C –VS + 1.6 +VS − 1.5 V

Short-Circuit Current 18 mA

AD8221

Rev. C | Page 7 of 24

Parameter Conditions

ARM Grade

Unit Min Typ Max

TEMPERATURE RANGE

Specified Performance −40 +85 °C

Operating Range4 −40 +125 °C

1 Total RTI VOS = (VOSI) + (VOSO/G).

2 Does not include the effects of external resistor RG.

3 One input grounded. G = 1.

4 See Typical Performance Characteristics for expected operation between 85°C to 125°C.

AD8221

Rev. C | Page 8 of 24

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±18 V

Internal Power Dissipation 200 mW

Output Short-Circuit Current Indefinite

Input Voltage (Common-Mode) ±VS

Differential Input Voltage ±VS

Storage Temperature Range −65°C to +150°C

Operating Temperature Range1−40°C to +125°C

1 Temperature range for specified performance is –40°C to +85°C. See Typical

Performance Characteristics for expected operation from 85°C to 125°C.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL CHARACTERISTICS

Specification for a device in free air.

Table 4.

Package θ

Unit

8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W

8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W

ESD CAUTION

AD8221

Rev. C | Page 9 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TOP VIEW

(Not t o Scale)

–IN

+IN

OUT

REF

–V

AD8221

03149-103

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN Negative Input Terminal.

2 RG Gain Setting Terminal. Place resistor across the RG pins to set the gain. G = 1 + (49.4 kΩ/RG).

3 RG Gain Setting Terminal. Place resistor across the RG pins to set the gain. G = 1 + (49.4 kΩ/RG).

4 +IN Positive Input Terminal.

5 −VS Negative Power Supply Terminal.

6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output.

7 VOUT Output Terminal.

8 +VS Positive Power Supply Terminal.

AD8221

Rev. C | Page 10 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.

200

400

600

800

1000

UNITS

1200

1400

1600

0–50–100–150 50 100 150

CMR (µV/V)

03149-003

Figure 4. Typical Distribution for CMR (G = 1)

300

600

900

1200

1500

UNITS

1800

2100

2400

0–20–40–60 20 40 60

INPUT OFFSET VOLTAGE (µV)

03149-004

Figure 5. Typical Distribution of Input Offset Voltage

500

1000

1500

2000

2500

3000

UNITS

0–0.5–1.0–1.5 0.5 1.0 1.5

INP UT BIAS CURRE NT (n A)

03149-005

Figure 6. Typical Distribution of Input Bias Current

500

1000

1500

2000

2500

3000

3500

UNITS

0–0.3–0.6–0.9 0.3 0.6 0.9

INP UT OFFS E T CURRENT (n A)

03149-006

Figure 7. Typical Distribution of Input Offset Current

–15

–10

–5

INPUT COMMON-MODE VOLTAGE (V)

–5 0–15 –10 510 15

OUTPUT VOLTAGE (V)

03149-007

= ±5V

= ±15V

Figure 8. Input Common-Mode Range vs. Output Voltage, G = 1

–15

–10

–5

INPUT COMMON-MODE VOLTAGE (V)

–5 0–15 –10 510 15

OUTPUT VOLTAGE (V)

03149-008

VS = ±5V

VS = ±15V

Figure 9. Input Common-Mode Range vs. Output Voltage, G = 100

AD8221

Rev. C | Page 11 of 24

0.40

0.45

0.50

0.55

0.60

0.65

INP UT BIAS CURRE NT (nA)

0.70

0.75

0.80

–5 0–15 –10 510 15

COMMON-MODE VOLTAGE (V)

03149-009

= ±5V

= ±15V

Figure 10. IBIAS vs. CMV

0.25

0.50

0.75

1.00

1.25

CHANGE IN INPUT OFFSET VOLTAGE (µV)

1.50

1.75

2.00

0.10.01 110

WARM-UP TIME (min)

03149-010

Figure 11. Change in Input Offset Voltage vs. Warm-Up Time

–5

–4

–3

–2

–1

INP UT CURRENT ( nA)

–40 –20 020 40 60 80 100 120 140

TEMPERATURE (°C)

03149-011

INP UT BIAS CURRE NT

VS = ± 15V

INP UT OFF S E T CURRENT

Figure 12. Input Bias Current and Offset Current vs. Temperature

100

120

POSIT I VE PSRR (dB)

140

160

180

0.1 110 100 1k 10k 100k 1M

FREQUENCY (Hz)

03149-012

GAIN = 1

GAIN = 10

GAIN = 100

GAIN = 1000

Figure 13. Positive PSRR vs. Frequency, RTI (G = 1 to 1000)

100

120

NEGAT I VE PSRR (dB)

140

160

180

0.1 110 100 1k 10k 100k 1M

FREQUENCY (Hz)

03149-013

GAIN = 1

GAIN = 10

GAIN = 100

GAIN = 1000

Figure 14. Negative PSRR vs. Frequency, RTI (G = 1 to 1000)

TOTAL DRIF T 25° C – 85°C RT I (µ V )

100

10k

100k

1k 10k10 100 100k 1M 10M

SO URCE RE S ISTANCE (Ω)

03149-014

BEST AVAILABLE FET

INP UT IN- AM P G AIN = 1

BEST AVAILABLE FET

INP UT IN- AM P G AIN = 1000

AD8221 GAIN = 1

AD8221 GAIN = 1000

Figure 15. Total Drift vs. Source Resistance

AD8221

Rev. C | Page 12 of 24

–30

–20

–10

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

GAIN (d B)

03149-015

GAIN = 1000

GAIN = 100

GAIN = 10

GAIN = 1

Figure 16. Gain vs. Frequency

100

CMRR (dB)

120

140

160

0.1 110 100 1k 10k 100k 1M

FREQUENCY (Hz)

03149-016

GAIN = 1000

GAIN = 100

GAIN = 10

GAIN = 1

Figure 17. CMRR vs. Frequency, RTI

100

CMRR (dB)

120

140

160

0.1 110 100 1k 10k 100k 1M

FREQUENCY (Hz)

03149-017

GAIN = 1000

GAIN = 100

GAIN = 10

GAIN = 1

Figure 18. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance

–100

–80

–60

–40

–20

100

CMR ( µV/V)

–40 –20 020 40 60 80 100 120 140

TEMPERATURE ( °C)

03149-018

Figure 19. CMR vs. Temperature

–VS +0

+0.4

+0.8

+1.2

+1.6

+2.0

+2.4

–1.6

–2.0

–2.4

–1.2

–0.8

–0.4

+VS –0

INP UT VOLTAGE LIMIT (V)

REFERRED TO SUPPLY VOLTAGES

SUPPLY VOLTAGE (±V)

50 10 15 20

03149-019

Figure 20. Input Voltage Limit vs. Supply Voltage, G = 1

–V

+0.4

+0.8

+1.2

+1.6

+2.0

–1.6

–2.0

–1.2

–0.8

–0.4

–0

OUTPUT VOLTAGE SWI NG (V)

REFERRED TO SUPPLY VOLTAGES

SUPP

LY VOLTAGE (±V)

50 10 15 20

03149-020

= 10kΩ

= 2kΩ

= 10kΩ

= 2kΩ

Figure 21. Output Voltage Swing vs. Supply Voltage, G = 1

AD8221

Rev. C | Page 13 of 24

OUTPUT VOLTAGE SWI NG (V p -p )

LOAD RESISTANCE (Ω)

101100 1k 10k

03149-021

VS = ±15V

Figure 22. Output Voltage Swing vs. Load Resistance

–V

–3

–2

–1

–0

OUTPUT VOLTAGE SWI NG (V)

REFERRED TO SUPPLY VOLTAGES

0 1 2 3 4 5 6 7 8 9 10 11 12

OUTPUT CURRE NT (mA)

03149-022

SOURCING

SINKING

Figure 23. Output Voltage Swing vs. Output Current, G = 1

–10 –8 –6 –4 –2 0246810

VS = ±15V

03149-023

ERRO R ( 1ppm/DI V )

OUTPUT VOLTAGE (V)

Figure 24. Gain Nonlinearity, G = 1, RL = 10 kΩ

VS = ±15V

03149-024

–10 –8 –6 –4 –2 0246810

ERRO R ( 10ppm/DI V )

OUTPUT VOLTAGE (V)

Figure 25. Gain Nonlinearity, G = 100, RL = 10 kΩ

VS = ±15V

03149-025

–10 –8 –6 –4 –2 0246810

ERRO R ( 100ppm/DI V )

OUTPUT VOLTAGE (V)

Figure 26. Gain Nonlinearity, G = 1000, RL = 10 kΩ

VOLTAGE NOISE RTI (nV/ Hz)

100

110 100 1k 10k 100k

FREQUENCY (Hz)

03149-026

GAIN = 1

GAIN = 1000

BW LIMIT

GAIN = 10

GAIN = 100

GAIN = 1000

Figure 27. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000)

AD8221

Rev. C | Page 14 of 24

1s/DIV2µV/DIV

03149-027

Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)

1s/DIV0.1µV/DIV

03149-028

Figure 29. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)

CURRENT NOIS E ( f A/ Hz)

100

FREQUENCY (Hz)

101100 1k 10k

03149-029

Figure 30. Current Noise Spectral Density vs. Frequency

1s/DIV5pA/DIV

03149-030

Figure 31. 0.1 Hz to 10 Hz Current Noise

OUTPUT VOLTAGE (V p-p )

FREQUENCY (Hz)

1k 100k10k 1M

03149-031

GAIN = 1 GAIN = 10, 100, 1000

= ±15V

Figure 32. Large Signal Frequency Response

20µs/DIV

0.002%/DIV 7.9µs T O 0. 01%

8.5µs TO 0.001%

5V/DIV

03149-032

Figure 33. Large Signal Pulse Response and Settling Time (G = 1), 0.002%/DIV

AD8221

Rev. C | Page 15 of 24

20µs/DIV

4.9µs TO 0.01%

5.6µs TO 0.001%

5V/DIV

03149-033

0.002%/DIV

Figure 34. Large Signal Pulse Response and Settling Time (G = 10),

0.002%/DIV

20µs/DIV

10.3µs TO 0. 01%

13.4µs TO 0. 001%

5V/DIV

03149-034

0.002%/DIV

Figure 35. Large Signal Pulse Response and Settling Time (G = 100),

0.002%/DIV

200µs/DIV

83µs TO 0.01%

112µs TO 0.001%

5V/DIV

03149-035

0.002%/DIV

Figure 36. Large Signal Pulse Response and Settling Time (G = 1000),

0.002%/DIV

4µs/DIV

20mV/DIV

03149-036

Figure 37. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF

4µs/DIV

20mV/DIV

03149-037

Figure 38. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF

10µs/DIV

20mV/DIV

03149-038

Figure 39. Small Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF

AD8221

Rev. C | Page 16 of 24

100µs/DIV

20mV/DIV

03149-039

Figure 40. Small Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF

SETTLING TIME (µs)

OUTPUT VOLTAGE STEP SIZE (V)

50 10 15 20

03149-040

SETTLED TO 0.01%

SETTLED TO 0.001%

Figure 41. Settling Time vs. Step Size (G = 1)

SETTLING TIME (µs)

100

1000

GAIN

1100

10 1000

03149-041

SETTLED TO 0.001%

SETTLED TO 0.01%

Figure 42. Settling Time vs. Gain for a 10 V Step

AD8221

Rev. C | Page 17 of 24

THEORY OF OPERATION

C1 C2

+VS

+IN–IN

–VS

10kΩ

400Ω400Ω

10kΩREF

OUTPUT

IB COMPENSATIONIB COMPENSATION

+VS

–VS

–V

+VS

I I

R1 24.7kΩ24.7kΩ

–VS

+VS

–VS

A2A1

03149-042

Figure 43. Simplified Schematic

The AD8221 is a monolithic instrumentation amplifier based

on the classic 3-op amp topology. Input transistors Q1 and Q2

are biased at a fixed current so that any differential input signal

forces the output voltages of A1 and A2 to change accordingly.

A signal applied to the input creates a current through RG, R1,

and R2, such that the outputs of A1 and A2 deliver the correct

voltage. Topologically, Q1, A1, R1 and Q2, A2, R2 can be

viewed as precision current feedback amplifiers. The amplified

differential and common-mode signals are applied to a

difference amplifier that rejects the common-mode voltage

but amplifies the differential voltage. The difference amplifier

employs innovations that result in low output offset voltage as

well as low output offset voltage drift. Laser-trimmed resistors

allow for a highly accurate in-amp with gain error typically less

than 20 ppm and CMRR that exceeds 90 dB (G = 1).

Using superbeta input transistors and an IB compensation

scheme, the AD8221 offers extremely high input impedance,

low IB, low IB drift, low IOS, low input bias current noise, and

extremely low voltage noise of 8 nV/√Hz.

The transfer function of the AD8221 is

GkΩ4.49

1+=

Users can easily and accurately set the gain using a single

standard resistor.

Because the input amplifiers employ a current feedback

architecture, the gain-bandwidth product of the AD8221

increases with gain, resulting in a system that does not suffer

from the expected bandwidth loss of voltage feedback

architectures at higher gains.

To maintain precision even at low input levels, special attention

was given to the design and layout of the AD8221, resulting in

an in-amp whose performance satisfies the most demanding

applications.

A unique pinout enables the AD8221 to meet a CMRR

specification of 80 dB at 10 kHz (G = 1) and 110 dB at 1 kHz

(G = 1000). The balanced pinout, shown in Figure 44, reduces

the parasitics that had, in the past, adversely affected CMRR

performance. In addition, the new pinout simplifies board

layout because associated traces are grouped together. For

example, the gain setting resistor pins are adjacent to the

inputs, and the reference pin is next to the output.

–IN

OUT

REF

–V

+IN

TOP VIEW

AD8221

03149-043

Figure 44. Pinout Diagram

AD8221

Rev. C | Page 18 of 24

GAIN SELECTION

Placing a resistor across the RG terminals set the gain of

AD8221, which can be calculated by referring to Table 6 or

by using the gain equation.

kΩ4.49

−

Table 6. Gains Achieved Using 1% Resistors

1% Standard Table Value of R

(Ω) Calculated Gain

49.9 k 1.990

12.4 k 4.984

5.49 k 9.998

2.61 k 19.93

1.00 k 50.40

499 100.0

249 199.4

100 495.0

49.9 991.0

The AD8221 defaults to G = 1 when no gain resistor is used.

Gain accuracy is determined by the absolute tolerance of RG.

The TC of the external gain resistor increases the gain drift of

the instrumentation amplifier. Gain error and gain drift are kept

to a minimum when the gain resistor is not used.

LAYOUT

Careful board layout maximizes system performance. Traces

from the gain setting resistor to the RG pins should be kept as

short as possible to minimize parasitic inductance. To ensure

the most accurate output, the trace from the REF pin should

either be connected to the local ground of the AD8221, as shown

in Figure 47, or connected to a voltage that is referenced to the

local ground of the AD8221.

Common-Mode Rejection

One benefit of the high CMRR over frequency of the AD8221 is

that it has greater immunity to disturbances, such as line noise

and its associated harmonics, than do typical instrumentation

amplifiers. Typically, these amplifiers have CMRR fall-off at

200 Hz; common-mode filters are often used to compensate for

this shortcoming. The AD8221 is able to reject CMRR over a

greater frequency range, reducing the need for filtering.

A well implemented layout helps to maintain the high CMRR

over frequency of the AD8221. Input source impedance and

capacitance should be closely matched. In addition, source

resistance and capacitance should be placed as close to the

inputs as permissible.

Grounding

The output voltage of the AD8221 is developed with respect to

the potential on the reference terminal. Care should be taken to

tie REF to the appropriate local ground.

In mixed-signal environments, low level analog signals need to

be isolated from the noisy digital environment. Many ADCs

have separate analog and digital ground pins. Although it is

convenient to tie both grounds to a single ground plane, the

current traveling through the ground wires and PC board may

cause hundreds of millivolts of error. Therefore, separate analog

and digital ground returns should be used to minimize the

current flow from sensitive points to the system ground. An

example layout is shown in Figure 45 and Figure 46.

03149-044

Figure 45. Top Layer of the AD8221-EVAL

03149-045

Figure 46. Bottom Layer of the AD8221-EVAL

AD8221

Rev. C | Page 19 of 24

REFERENCE TERMINAL

As shown in Figure 43, the reference terminal, REF, is at one

end of a 10 kΩ resistor. The output of the instrumentation

amplifier is referenced to the voltage on the REF terminal; this

is useful when the output signal needs to be offset to a precise

midsupply level. For example, a voltage source can be tied to the

REF pin to level-shift the output so that the AD8221 can interface

with an ADC. The allowable reference voltage range is a function

of the gain, input, and supply voltage. The REF pin should not

exceed either +VS or –VS by more than 0.5 V.

For best performance, source impedance to the REF terminal

should be kept low, because parasitic resistance can adversely

affect CMRR and gain accuracy.

POWER SUPPLY REGULATION AND BYPASSING

A stable dc voltage should be used to power the instrumentation

amplifier. Noise on the supply pins can adversely affect

performance. Bypass capacitors should be used to decouple

the amplifier.

A 0.1 µF capacitor should be placed close to each supply pin.

As shown in Figure 47, a 10 µF tantalum capacitor can be used

further away from the part. In most cases, it can be shared by

other precision integrated circuits.

AD8221

+VS

+IN

–IN

LOAD

REF

0.1µF 10µF

–VS

VOUT

03149-046

Figure 47. Supply Decoupling, REF, and Output Referred to Local Ground

INPUT BIAS CURRENT RETURN PATH

The input bias current of the AD8221 must have a return path

to common. When the source, such as a thermocouple, cannot

provide a return current path, one should be created, as shown

in Figure 48.

+VS

REF

TRANSFORMER

THERMOCOUPLE

–VS

AD8221

REF

–V

AD8221

CAPACITOR COUP LED

REF

–V

AD8221

HIGH-PASS

= 2πRC

03149-047

Figure 48. Creating an IBIAS Path

INPUT PROTECTION

All terminals of the AD8221 are protected against ESD, 1 kV

Human Body Model. In addition, the input structure allows for

dc overload conditions below the negative supply, −VS. The

internal 400 Ω resistors limit current in the event of a negative

fault condition. However, in the case of a dc overload voltage

above the positive supply, +VS, a large current flows directly

through the ESD diode to the positive rail. Therefore, an external

resistor should be used in series with the input to limit current

for voltages above +Vs. In either scenario, the AD8221 can

safely handle a continuous 6 mA current, I = VIN/REXT for

positive overvoltage and I = VIN/(400 Ω + REXT) for negative

overvoltage.

For applications where the AD8221 encounters extreme

overload voltages, as in cardiac defibrillators, external series

resistors, and low leakage diode clamps, such as BAV199Ls,

FJH1100s, or SP720s should be used.

AD8221

Rev. C | Page 20 of 24

RF INTERFERENCE

RF rectification is often a problem when amplifiers are used in

applications where there are strong RF signals. The disturbance

can appear as a small dc offset voltage. High frequency signals

can be filtered with a low-pass RC network placed at the input

of the instrumentation amplifier, as shown in Figure 49. The

filter limits the input signal bandwidth according to the following

relationship:

)2(π2

Diff

CCR

FilterFreq +

CM RC

FilterFreq π2

where CD ≥ 10CC.

AD8221

+15V

+IN

–IN

0.1µF 10µF

10µF

0.1µF

REF

OUT

–15V

499Ω

10nF

1nF

03149-048

4.02kΩ

Figure 49. RFI Suppression

CD affects the difference signal, and CC affects the common-

mode signal. Values of R and CC should be chosen to minimize

RFI. Mismatch between the R × CC at the positive input and the

R × CC at the negative input degrades the CMRR of the AD8221.

By using a value of CD one magnitude larger than CC, the effect

of the mismatch is reduced, and therefore, performance is

improved.

PRECISION STRAIN GAGE

The low offset and high CMRR over frequency of the AD8221

make it an excellent candidate for bridge measurements. As

shown in Figure 50, the bridge can be directly connected to

the inputs of the amplifier.

+5V

+2.5V

03149-049

10µF 0.1µF

AD8221

+IN

–IN

350Ω

350Ω350Ω

350Ω

–

Figure 50. Precision Strain Gage

CONDITIONING ±10 V SIGNALS FOR A +5 V

DIFFERENTIAL INPUT ADC

There is a need in many applications to condition ±10 V signals.

However, many of today’s ADCs and digital ICs operate on

much lower, single-supply voltages. Furthermore, new ADCs

have differential inputs because they provide better common-

mode rejection, noise immunity, and performance at low supply

voltages. Interfacing a ±10 V, single-ended instrumentation

amplifier to a +5 V, differential ADC can be a challenge.

Interfacing the instrumentation amplifier to the ADC requires

attenuation and a level shift. A solution is shown in Figure 51.

+12V

+IN

–IN

0.1µF

10µF

0.1µF

10µF

–12V

1kΩ

+2.5V

1kΩ

REF R5

499Ω

10kΩ

470pF

+12V

0.1µF

–12V

+12V

+5V +5V

0.1µF

10nF

0.1µF

–12V

+12V

0.1µF

–12V

27.4Ω

220µF

10µF 0.1µF 22µF

+5V 2.5V

220nF 10nF

AD8221

AD8022

OP27

AD8022

AD7723

VIN(+) AV

AGND DGND REF1 REF2

VIN(–)

AD780

GND

OUT

03149-050

(½)

Figure 51. Interfacing to a Differential Input ADC

AD8221

Rev. C | Page 21 of 24

In this topology, an OP27 sets the reference voltage of the

AD8221. The output signal of the instrumentation amplifier is

taken across the OUT pin and the REF pin. Two 1 kΩ resistors

and a 499 Ω resistor attenuate the ±10 V signal to +4 V. An

optional capacitor, C1, can serve as an antialiasing filter. An

AD8022 is used to drive the ADC.

This topology has five benefits. In addition to level-shifting and

attenuation, very little noise is contributed to the system. Noise

from R1 and R2 is common to both of the inputs of the ADC

and is easily rejected. R5 adds a third of the dominant noise and

therefore makes a negligible contribution to the noise of the

system. The attenuator divides the noise from R3 and R4. Likewise,

its noise contribution is negligible. The fourth benefit of this

interface circuit is that the acquisition time of the AD8221 is

reduced by a factor of 2. With the help of the OP27, the AD8221

only needs to deliver one-half of the full swing; therefore, signals

can settle more quickly. Lastly, the AD8022 settles quickly,

which is helpful because the shorter the settling time, the

more bits that can be resolved when the ADC acquires data.

This configuration provides attenuation, a level-shift, and a

convenient interface with a differential input ADC while

maintaining performance.

AC-COUPLED INSTRUMENTATION AMPLIFIER

Measuring small signals that are in the noise or offset of the

amplifier can be a challenge. Figure 52 shows a circuit that can

improve the resolution of small ac signals. The large gain

reduces the referred input noise of the amplifier to 8 nV/√Hz.

Thus, smaller signals can be measured because the noise floor is

lower. DC offsets that would have been gained by 100 are

eliminated from the output of the AD8221 by the integrator

feedback network.

At low frequencies, the OP1177 forces the output of the AD8221 to

0 V. Once a signal exceeds fHIGH-PASS, the AD8221 outputs the

amplified input signal.

AD8221

OP1177

15.8kΩ

+IN

–IN

0.1µF

10µF10µF

REF C

1µF

–V

499Ω

2πRC

HIGH-PASS

03149-051

Figure 52. AC-Coupled Circuit

AD8221

Rev. C | Page 22 of 24

DIE INFORMATION

Die size: 1575 μm × 2230 μm

Die thickness: 381 μm

To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting

Pad 2A and Pad 2B in parallel to one end of RG and Pad 3A and Pad 3B in parallel to the other end of RG. For unity gain applications

where RG is not required, Pad 2A and Pad 2B must be bonded together as well as the Pad 3A and Pad 3B.

03149-104

LOGO

Figure 53. Bond Pad Diagram

Table 7. Bond Pad Information

Pad No. Mnemonic

Pad Coordinates1

X (μm) Y (μm)

1 −IN –379 +951

2A RG –446 +826

2B RG –615 +474

3A RG –619 +211

3B RG –490 –190

4 +IN –621 –622

5 −VS +635 –823

6 REF +649 –339

7 VOUT +612 +84

8 +VS +636 +570

1 The pad coordinates indicate the center of each pad, referenced to the center of the die. The die orientation is indicated by the logo, as shown in Figure 53.

AD8221

Rev. C | Page 23 of 24

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-187-AA

6°

0°

0.80

0.55

0.40

0.65 BSC

0.40

0.25

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.10

0.23

0.09

3.20

3.00

2.80

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

10-07-2009-B

Figure 54. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DES

IGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

012407-A

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099) 45°

8°

0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

8 5

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

6.20 (0.2441)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

AD8221

Rev. C | Page 24 of 24

ORDERING GUIDE

Model1

Temperature Range for

Specified Performance

Operating2

Package Description

Temperature Range

Package

Option Branding

AD8221AR –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N R-8

AD8221AR-REEL –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8

AD8221AR-REEL7 –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8

AD8221ARZ –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N R-8

AD8221ARZ-R7 –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8

AD8221ARZ-RL –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8

AD8221ARM –40°C to +85°C –40°C to +125°C 8-Lead MSOP RM-8 JLA

AD8221ARM-REEL –40°C to +85°C –40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 JLA

AD8221ARM REEL7 –40°C to +85°C –40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 JLA

AD8221ARMZ –40°C to +85°C –40°C to +125°C 8-Lead MSOP RM-8 JLA#

AD8221ARMZ-R7 –40°C to +85°C –40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 JLA#

AD8221ARMZ-RL –40°C to +85°C –40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 JLA#

AD8221BR –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N R-8

AD8221BR-REEL –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8

AD8221BR-REEL7 –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8

AD8221BRZ –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N R-8

AD8221BRZ-R7 –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8

AD8221BRZ-RL –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8

AD8221AC-P7 –40°C to +85°C –40°C to +125°C Die

1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.

2 See Typical Performance Characteristics for expected operation from 85°C to 125°C.

registered trademarks are the property of their respective owners.

D03149–0–3/11(C)