SLCS115E - DECEMBER 1986 - REVISED JULY 2003 D Very Low Power . . . 110 W Typ at 5 V D Fast Response Time . . . tPLH = 2.5 s Typ D, JG, P, OR PW PACKAGE (TOP VIEW) With 5-mV Overdrive 1OUT 1IN - 1IN + GND D Single Supply Operation: 8 2 7 3 6 4 5 VDD 2OUT 2IN - 2IN + FK PACKAGE (TOP VIEW) NC 1OUT NC VDD NC description The TLC193 and TLC393 consist of dual independent micropower voltage comparators designed to operate from a single supply. They are functionally similar to the LM393 but uses one-twentieth the power for similar response times. The open-drain MOS output stage interfaces to a variety of loads and supplies. For a similar device with a push-pull output configuration (see the TLC3702 data sheet). 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 NC GND NC NC 1IN - NC 1IN + NC Texas Instruments LinCMOS process offers superior analog performance to standard CMOS processes. Along with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and low bias currents, the LinCMOS process offers extremely stable input offset voltages, even with differential input stresses of several volts. This characteristic makes it possible to build reliable CMOS comparators. NC 2OUT NC 2IN - NC 2IN+ NC D TLC393C . . . 3 V to 16 V TLC393I . . . 3 V to 16 V TLC393Q . . . 4 V to 16 V TLC393M . . . 4 V to 16 V TLC193M . . . 4 V to 16 V On-Chip ESD Protection 1 NC - No internal connection symbol (each comparator) IN + OUT IN - The TLC393C is characterized for operation over the commercial temperature range of TA = 0C to 70C. The TLC393I is characterized for operation over the extended industrial temperature range of TA = -40C to 85C. The TLC393Q is characterized for operation over the full automotive temperature range of TA = -40C to 125C. The TLC193M and TLC393M are characterized for operation over the full military temperature range of TA = -55C to 125C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. Copyright 1986-2003, Texas Instruments Incorporated !" #!$% &"' &! #" #" (" " ") !" && *+' &! # ", &" " "%+ %!&" ", %% #""' * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 1 SLCS115D - DECEMBER 1986 - REVISED JULY 2003 AVAILABLE OPTIONS PACKAGES TA VIOmax at 25C 0C to 70C SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP (PW) 5 mV TLC393CD -- -- TLC393CP TLC393CPWLE - 40C to 85C 5 mV TLC393ID -- -- TLC393IP TLC393IPWLE - 40C to 125C 5 mV TLC393QD -- -- -- -- - 55C to 125C 5 mV TLC393MD TLC193MFK TLC193MJG TLC393MP -- The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC393CDR). schematic OUT OPEN-DRAIN CMOS OUTPUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 16 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Total supply current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range: TLC393C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLC393I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C TLC393Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C TLC393M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C TLC193M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN -. DISSIPATION RATING TABLE PACKAGE 2 TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING D 725 mW 5.8 mW/C 464 mW 377 mW 145 mW FK 1375 mW 11.0 mW/C 880 mW 715 mW 275 mW JG 1050 mW 8.4 mW/C 672 mW 546 mW 210 mW P 1000 mW 8.0 mW/C 640 mW 520 mW -- PW 525 mW 4.2 mW/C 336 mW 273 mW -- * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * SLCS115E - DECEMBER 1986 - REVISED JULY 2003 recommended operating conditions TLC393C Supply voltage, VDD Common-mode input voltage, VIC MIN NOM 3 5 -0.2 Low-level output current, IOL Operating free-air temperature, TA UNIT MAX 16 V VDD - 1.5 20 V mA 70 C 0 electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Inp t offset voltage Input oltage IIO Inp t offset ccurrent Input rrent TEST CONDITIONS VIC = VICRmin, VDD = 5 V to 10 V, V See Note 3 TLC393C TA MIN 25C VICR Common mode inp Common-mode inputt voltage oltage range kSVR Common-mode Common mode rejection ratio Supply-voltage Su ly voltage rejection ratio VIC = 2.5 25V 1 70C VIC = 2.5 25V 0C to 70C VIC = VICRmin VDD = 5 V to 10 V Lo le el o tp t voltage oltage Low-level output VID = -1 1 V, V IOL = 6 mA IOH High le el o High-level output tp t ccurrent rrent VID = 1 V, V 0.3 Supply current (both comparators) Outputs low, low No load 0 to VDD - 1 0 to VDD - 1.5 nA V 84 70C 84 0C 84 25C 85 70C 85 0C 85 25C 300 70C dB dB 400 650 mV 0.8 40 nA 1 A 22 40 70C 25C nA pA 0.6 25C 25C VO = 5 V pA 5 70C VOL IDD 5 mV 25C CMMR 1.4 UNIT 6.5 25C Inp t bias current Input c rrent MAX 0C to 70C 25C IIB TYP 0C to 70C 50 A All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 3 SLCS115D - DECEMBER 1986 - REVISED JULY 2003 recommended operating conditions TLC393I Supply voltage, VDD Common-mode input voltage, VIC MIN NOM 3 5 16 V - 0.2 VDD - 1.5 20 V mA - 40 85 C Low-level output current, IOL Operating free-air temperature, TA UNIT MAX electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) TEST CONDITIONS PARAMETER VIO Inp t offset voltage Input oltage IIO Inp t offset ccurrent Input rrent VIC = VICRmin, VDD = 5 V to 10 V, V See Note 3 TLC393I TA MIN 25C Common mode inp Common-mode inputt voltage oltage range 1 85C VIC = 2.5 25V kSVR Common-mode Common mode rejection ratio Supply-voltage Su ly voltage rejection ratio -40C to 85C VIC = VICRmin VDD = 5 V to 10 V VOL Lo le el o tp t voltage oltage Low-level output VID = -1 1 V, V IOL = 6 mA IOH High le el o High-level output tp t ccurrent rrent VID = 1 V, V 1 IDD Supply current (both comparators) Outputs low, low No load 0 to VDD - 1 0 to VDD - 1.5 85C 84 - 40C 84 25C 85 85C 85 - 40C 84 25C 300 85C * * dB 400 mV 0.8 40 nA 1 A 22 40 85C -40C to 85C POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 dB 700 All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V. 4 nA V 84 25C nA pA 2 25C 25C VO = 5 V pA 5 85C 25C CMMR 5 mV 25C VICR 1.4 UNIT 7 25C Inp t bias current Input c rrent MAX -40C to 85C VIC = 2.5 25V IIB TYP 65 A SLCS115E - DECEMBER 1986 - REVISED JULY 2003 recommended operating conditions TLC393Q MIN NOM Supply voltage, VDD 4 5 Common-mode input voltage, VIC 0 Low-level output current, IOL Operating free-air temperature, TA UNIT MAX 16 V VDD - 1.5 20 V mA 125 C -40 electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Inp t offset voltage Input oltage IIO Inp t offset ccurrent Input rrent TEST CONDITIONS VIC = VICRmin, VDD = 5 V to 10 V, V See Note 4 TLC393Q TA MIN 25C VICR Common mode inp Common-mode inputt voltage oltage range kSVR Common-mode Common mode rejection ratio Supply-voltage Su ly voltage rejection ratio VIC = 2.5 25V 1 125C VIC = 2.5 25V -40C to 125C VIC = VICRmin VDD = 5 V to 10 V Lo le el o tp t voltage oltage Low-level output VID = -1 1 V, V IOL = 6 mA IOH High le el o High-level output tp t ccurrent rrent VID = 1 V, V 15 Supply current (both comparators) Outputs low, low No load 0 to VDD - 1 0 to VDD - 1.5 125C 84 -40C 84 25C 85 125C 84 -40C 84 25C 300 125C dB dB 400 800 mV 0.8 40 nA 1 A 22 40 125C -40C to 125C nA V 84 25C nA pA 30 25C 25C VO = 5 V pA 5 125C VOL IDD 5 mV 25C CMMR 1.4 UNIT 10 25C Inp t bias current Input c rrent MAX -40C to 125C 25C IIB TYP 90 A All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 4: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V (with a 2.5-k load to VDD). * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 5 SLCS115D - DECEMBER 1986 - REVISED JULY 2003 recommended operating conditions TLC193M, TLC393M MIN NOM Supply voltage, VDD 4 5 Common-mode input voltage, VIC 0 Low-level output current, IOL Operating free-air temperature, TA UNIT MAX 16 V VDD - 1.5 20 V mA 125 C -55 electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) TEST CONDITIONS PARAMETER VIO Inp t offset voltage Input oltage IIO Inp t offset ccurrent Input rrent VIC = VICRmin, VDD = 5 V to 10 V, V See Note 4 TLC193M, TLC393M TA MIN 25C Common mode inp Common-mode inputt voltage oltage range 1 125C VIC = 2.5 25V kSVR Common-mode Common mode rejection ratio Supply-voltage Su ly voltage rejection ratio -55C to 125C VIC = VICRmin VDD = 5 V to 10 V VOL Lo le el o tp t voltage oltage Low-level output VID = -1 1 V, V IOL = 6 mA IOH High le el o High-level output tp t ccurrent rrent VID = 1 V, V 15 IDD Supply current (both comparators) Outputs low, low No load 0 to VDD - 1 0 to VDD - 1.5 125C 84 -55C 84 25C 85 125C 84 -55C 84 25C 300 125C dB dB 400 800 mV 0.8 40 nA 1 A 22 40 125C -55C to 125C nA V 84 25C nA pA 30 25C 25C VO = 5 V pA 5 125C 25C CMMR 5 mV 25C VICR 1.4 UNIT 10 25C Inp t bias current Input c rrent MAX -55C to 125C VIC = 2.5 25V IIB TYP 90 A All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 4: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V (with a 2.5-k load to VDD). 6 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * SLCS115E - DECEMBER 1986 - REVISED JULY 2003 switching characteristics, VDD = 5 V, TA = 25C (see Figure 3) PARAMETER TEST CONDITIONS TLC393C, TLC393I TLC393Q, TLC193M, TLC393M MIN tPLH tPHL tf f = 10 kH kHz, CL = 15 pF Propagation Pro agation delay time, low low-to-high-level to high level out output ut Fall time, output 4.5 Overdrive = 5 mV 2.5 Overdrive = 10 mV 1.7 Overdrive = 20 mV 1.2 Overdrive = 40 mV 1.1 VI = 1.4-V step at IN + Overdrive = 2 mV 1.1 Overdrive = 5 mV 2.1 f = 10 kH kHz, CL = 15 pF Propagation Pro agation delay time, high high-to-low-level to low level out output ut TYP Overdrive = 2 mV UNIT MAX s 3.6 Overdrive = 10 mV 1.3 Overdrive = 20 mV 0.85 Overdrive = 40 mV 0.55 VI = 1.4-V step at IN + f = 10 kHz, Overdrive = 50 mV CL = 15 pF 0.10 s 22 ns PARAMETER MEASUREMENT INFORMATION The TLC393 contains a digital output stage which, if held in the linear region of the transfer curve, can cause damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternatives for testing parameters such as input offset voltage, common-mode rejection ratio, etc., are suggested. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. 5V + Applied VIO Limit 1V 5.1 k 5.1 k + - - Applied VIO Limit VO VO -4V (a) VIO WITH VIC = 0 V (b) VIO WITH VIC = 4 V Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 7 SLCS115D - DECEMBER 1986 - REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but opposite in polarity, to the input offset voltage, the output changes states. Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1A generates a triangular waveform of approximately 20-mV amplitude. U1B acts as a buffer, with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by U1C through the voltage divider formed by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. The voltage divider formed by R9 and R10 provides an increase in input offset voltage by a factor of 100 to make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be 1% or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device. VDD U1B 1/4 TLC274CN + Buffer C2 1 F U1C 1/4 TLC274CN R6 5.1 k - - C3 0.68 F R5 1.8 k, 1% DUT R4 47 k - R7 1 M + VIO (X100) R1 240 k - + R8 1.8 k, 1% U1A 1/4 TLC274CN C4 0.1 F C1 0.1 F + Triangle Generator R10 100 , 1% R3 100 k R9 10 k, 1% R2 10 k Figure 2. Circuit for Input Offset Voltage Measurement 8 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * Integrator SLCS115E - DECEMBER 1986 - REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION Propagation delay time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Propagation delay time, low-to-high-level output, is measured from the leading edge of the input pulse, while propagation delay time, high-to-low-level output, is measured from the trailing edge of the input pulse. Propagation delay time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3) so that the circuit is just at the transition point. Then a low signal, for example, 105 mV or 5 mV overdrive, causes the output to change state. VDD 50 1V Input Offset Voltage Compensation Adjustment 1 F 5.1 k Pulse Generator DUT 10 10 Turn CL (see Note A) 1 k -1V 0.1 F TEST CIRCUIT Overdrive Overdrive Input Low-to-HighLevel Output Input 100 mV 100 mV 90% 90% High-to-LowLevel Output 50% 10% 50% 10% tf tr tPHL tPLH VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3. Propagation Delay, Rise Time, and Fall Time Circuit and Voltage Waveforms * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 9 SLCS115D - DECEMBER 1986 - REVISED JULY 2003 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO IIB Input offset voltage Distribution 4 Input bias current vs Free-air temperature 5 CMRR Common-mode rejection ratio vs Free-air temperature 6 kSVR Supply-voltage rejection ratio vs Free-air temperature 7 VOL Lo le el o Low-level output tp t voltage oltage vs Low-level Low level output out ut current vs Free-air temperature 8 9 IOH Lo le el output Low-level o tp t current c rrent vs High-level High level output out ut voltage vs Free-air temperature 10 11 IDD S ppl current Supply c rrent vs Su Supply ly voltage vs Free-air temperature 12 13 tPLH tPHL Low-to-high level output propagation delay time vs Supply voltage 14 High-to-low level output propagation delay time vs Supply voltage 15 Low-to-high-level output response Low-to-high level output propagation delay time 16 High-to-low level output response High-to-low level output propagation delay time 17 Fall time vs Supply voltage 18 tf INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE DISTRIBUTION OF INPUT OFFSET VOLTAGE 90 Number of Units 80 70 60 50 40 30 20 10 0 -5 CC CCCC E CCCC E E CCC CCE E CCCC E C CE CCE CCE E C E EEC CCCC E E C E EEC EE CCCC E E C E EEC EE C CCCC E C CE E EE C EEEE CCCC E C CE E EE C EEEE C EE CCCC EEEE CEEE CC CCEECEECE 10 VDD = 5 V VIC = 2.5 V TA = 25C -4 -3 -2 -1 0 1 2 3 4 VDD = 5 V VIC = 2.5 V IIB - Input Bias Current - nA 100 1 0.1 0.01 0.001 25 5 50 75 100 TA - Free-Air Temperature - C VIO - Input Offset Voltage - mV Figure 4 Figure 5 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 10 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 125 SLCS115E - DECEMBER 1986 - REVISED JULY 2003 TYPICAL CHARACTERISTICS SUPPLY VOLTAGE REJECTION RATIO vs FREE-AIR TEMPERATURE COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE 90 89 kSVR - Supply Voltage Rejection Ratio - dB 90 VDD = 5 V CMRR - Common-Mode Rejection Ratio - dB 88 87 86 85 84 83 82 81 80 -75 -50 -25 0 25 50 75 100 89 88 87 86 85 84 83 82 81 80 -75 125 VDD = 5 V to 10 V -50 -25 25 50 75 100 125 TA - Free-Air Temperature - C TA - Free-Air Temperature - C Figure 7 Figure 6 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 1.5 600 TA = 25C 4V VOL - Low-Level Output Voltage - mV VOL - Low-Level Output Voltage - V 0 1.25 VDD = 3 V 1 5V 0.75 10 V 0.5 0.25 VDD = 16 V 0 0 2 4 6 8 10 12 14 16 18 VDD = 5 V IOL = 6 mA 500 400 300 200 100 0 -75 20 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C IOL - Low-Level Output Current - mA Figure 9 Figure 8 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 11 SLCS115D - DECEMBER 1986 - REVISED JULY 2003 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT CURRENT vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 1000 I OH - High-Level Output Current - nA I OH - High-Level Output Current - nA 1000 TA = 125C 100 TA = 85C TA = 70C 10 TA = 25C 1 VDD = VOH = 5 V 100 10 1 VOH = VDD 0.1 25 0.1 0 2 4 6 8 10 12 14 16 50 100 125 TA - Free-Air Temperature - C VOH - High-Level Output Voltage - V Figure 11 Figure 10 SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 40 50 Outputs Low No Loads 45 TA = - 55C 35 VDD = 5 V No Load TA = - 40C 40 IDD - Supply Current -A I DD - Supply Current - A 75 35 TA = 25C 30 25 TA = 85C 20 TA = 125C 15 30 25 Outputs Low 20 15 10 10 0 Outputs High 5 5 0 2 4 6 8 10 12 14 0 -75 16 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C VDD - Supply Voltage - V Figure 13 Figure 12 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 12 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 125 SLCS115E - DECEMBER 1986 - REVISED JULY 2003 TYPICAL CHARACTERISTICS LOW-TO-HIGH-LEVEL OUTPUT RESPONSE TIME vs SUPPLY VOLTAGE HIGH-TO-LOW-LEVEL OUTPUT RESPONSE TIME vs SUPPLY VOLTAGE 5 CL = 15 pF RL = 5.1 k (pullup to VDD) TA = 25C 5 CL = 15 pF RL = 5.1 k (pullup to VDD) TA = 25C 4.5 t PHL - High-to-Low Level Output Propagation Delay Time - s t PLH - Low-to-High-Level Output Propagation Delay Time - s 6 Overdrive = 2 mV 4 5 mV 3 10 mV 2 20 mV 40 mV 1 4 3.5 Overdrive = 2 mV 3 2.5 5 mV 2 1.5 10 mV 1 20 mV 0.5 40 mV 0 0 2 4 6 8 10 12 14 0 16 0 2 4 VDD - Supply Voltage - V 12 14 16 HIGH-TO-LOW-LEVEL OUTPUT PROPAGATION DELAY FOR VARIOUS INPUT OVERDRIVES 5 40 mV 20 mV 10 mV 5 mV 2 mV VO - Output Voltage - V VO - Output Voltage - V 10 Figure 15 LOW-TO-HIGH-LEVEL OUTPUT PROPAGATION DELAY FOR VARIOUS INPUT OVERDRIVES 40 mV 20 mV 10 mV 5 mV 2 mV 0 0 100 Differential Input Voltage - mV Differential Input Voltage - mV 8 VDD - Supply Voltage - V Figure 14 5 6 VDD = 5 V CL = 15 pF RL = 5.1 k (pullup to VDD) TA = 25C 0 0 1 2 3 4 VDD = 5 V CL = 15 pF RL = 5.1 k (pullup to VDD) TA = 25C 100 0 0 5 1 2 3 4 5 tPHL - High-to-Low-Level Output Propagation Delay Time - s tPLH - Low-to-High-Level Output Propagation Delay Time - s Figure 16 Figure 17 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 13 SLCS115D - DECEMBER 1986 - REVISED JULY 2003 TYPICAL CHARACTERISTICS OUTPUT FALL TIME vs SUPPLY VOLTAGE 60 50 CL = 100 pF t f - Fall Time -ns 40 50 pF 30 15 pF 20 50-mV Overdrive RL = 5.1 k (pullup to VDD) TA = 25C 10 0 0 2 4 6 8 10 12 14 16 VDD - Supply Voltage - V Figure 18 APPLICATION INFORMATION The input should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device will not be damaged as long as the input current is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within the common-mode range. For example, at 25C with VDD = 5 V, both inputs must remain between -0.2 V and 4 V to assure proper device operation. To assure reliable operation, the supply should be decoupled with a capacitor (0.1-F) positioned as close to the device as possible. The TLC393 has internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices, as exposure to ESD may result in the degradation of the device parametric performance. Table of Applications FIGURE 14 Pulse-width-modulated motor speed controller 19 Enhanced supply supervisor 20 Two-phase nonoverlapping clock generator 21 Micropower switching regulator 28 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * SLCS115E - DECEMBER 1986 - REVISED JULY 2003 APPLICATION INFORMATION 12 V 12 V SN75603 Half-H Driver DIR 5V EN C2 (see Note A) 5.1 k + 5.1 k 100 k + 10 k 5V - 10 k 1/2 TLC393 Motor C1 0.01 F (see Note B) - 1/2 TLC393 12 V DIR SN75604 Half-H Driver 10 k 5V 10 k Motor Speed Control Potentiometer EN 5V Direction Control S1 SPDT NOTES: A. The recommended minimum capacitance is 10 F to eliminate common ground switching noise. B. Adjust C1 for change in oscillator frequency. Figure 19. Pulse-Width-Modulated Motor Speed Controller * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 15 SLCS115D - DECEMBER 1986 - REVISED JULY 2003 APPLICATION INFORMATION 5V 12 V VCC 12-V Sense 3.3 k RESIN - 5V 10 k 5.1 k + 1 k SENSE TL7705A RESET To P Reset 1/2 TLC393 REF CT GND 2.5 V 12 V 1 F CT (see Note B) 5.1 k + VUNREG (see Note A) To P Interrupt Early Power Fail R1 - 1/2 TLC393 R2 Monitors 5-VDC Rail Monitors 12-VDC Rail Early Power Fail Warning (R1 +R2) R2 B. The value of CT determines the time delay of reset. NOTES: A. V UNREG + 2.5 Figure 20. Enhanced Supply Supervisor 16 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * SLCS115E - DECEMBER 1986 - REVISED JULY 2003 APPLICATION INFORMATION 12 V 12 V R1 100 (see Note B) R2 5 k (see Note C) 5.1 k - 5.1 k - 12 V 1OUT + 1/2 TLC393 12 V 100 k + 1/2 TLC393 100 k 22 k 5.1 k C1 0.01 F (see Note A) - 2OUT 100 k + 1/2 TLC393 R3 100 k (see Note B) 12 V 1OUT 2OUT NOTES: A. Adjust C1 for a change in oscillator frequency where: 1/f = 1.85(100 k)C1 B. Adjust R1 and R3 to change duty cycle C. Adjust R2 to change deadtime Figure 21. Two-Phase Nonoverlapping Clock Generator * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 17 PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 5962-9555101NXDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 1 TBD Call TI Call TI TBD Call TI Call TI A42 5962-9555101QPA ACTIVE CDIP JG 8 TLC193MFKB OBSOLETE LCCC FK 20 TLC193MJGB ACTIVE CDIP JG 8 1 TBD TLC393CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type N / A for Pkg Type TLC393CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) TLC393CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CPWLE OBSOLETE TSSOP PW 8 TLC393CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Call TI Samples (Requires Login) 5962-9555101NXD TBD (3) Call TI PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2011 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC393IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC393IPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393IPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393IPWLE OBSOLETE TSSOP PW 8 TLC393IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393MD OBSOLETE SOIC D 8 TBD Call TI Call TI TLC393MP OBSOLETE PDIP P 8 TBD Call TI Call TI TLC393QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC393QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Call TI Samples (Requires Login) TLC393IDG4 TBD (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2011 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC393 : * Automotive: TLC393-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing 5962-9555101NXDR SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 12.0 Q1 D 8 2500 330.0 12.4 6.4 5.2 2.1 W Pin1 (mm) Quadrant TLC393CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC393CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 TLC393CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC393IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC393IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC393QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 5962-9555101NXDR SOIC D 8 2500 367.0 367.0 35.0 TLC393CDR SOIC D 8 2500 340.5 338.1 20.6 TLC393CPSR SO PS 8 2000 367.0 367.0 38.0 TLC393CPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC393IDR SOIC D 8 2500 340.5 338.1 20.6 TLC393IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC393QDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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