F280040PMQR - TEXAS INSTRUMENTS - Datasheet.Directory

Si590/591

1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)

(10 MHZ TO 810 MHZ)

Features

Applications

Description

The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL

circuitry

to provide a low ji tter clock a t high freque ncies. The Si590/ 591 supports any

frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique

crystal is required for each output frequency, the Si590/591 uses one fixed

crystal to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The

Si590/591 IC based XO is factory configurable for a wide variety of user

specifications including frequency, supply voltage, output format, and

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminatin g lon g lead times associated with custom oscillators.

Functional Block Diagram

Available with any-frequency output

frequencies from 10 to 810 MHz

3rd generation DSPLL® with superior

jitter performance: 1 ps max jitter

Better frequency stability than SAW-

based oscillators

Internal fundamental mode crystal

ensures high reliability

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry Standard 5x7 and

3.2x5 mm packages

Pb-free/RoHS-compliant

–40 to +85 ºC operating

temperature range

SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video

Test and measurement

Storage

FPGA/ASIC clock generation

Fixed

Frequency

Any-rate

10–810 MHz

DSPLL®

Clock

Synthesis

VDD CLK+CLK–

GND

17 k *

*Note: Output Enable High/Low Options Av ailable – See Ordering Information



Ordering Information:

See page 8.

Pin Assignments:

See page 7.

(Top View)

Si5602

4GND

VDD

CLK+

CLK–

4GND

VDD

CLK

4GND

VDD

CLK+

CLK–

Si590 (LVDS/LVPECL/CML)

Si590 (CMOS)

Si591 (LVDS/LVPECL/CML)

Si590/591

2 Rev. 1.2

TABLE OF CONTENTS

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4. Package Outline Drawing: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

5. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

6. Package Outline Drawing: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

7. PCB Land Pattern: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

8. Si590/Si591 Top Marking: 5x7mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

9. Si590/Si591 Top Marking: 3.2 x 5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Si590/591

Rev. 1.2 3

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Units

Supply Voltage1VDD 3.3 V op tio n 2.97 3.3 3.63 V2.5 V option 2.25 2.5 2.75

1.8 V option 1.71 1.8 1.89

Supply Current IDD Output enabled

LVPECL

CML

LVDS

CMOS

—

110

100

125

110

100

Tristate mode — 60 75

Output Enable (OE)2VIH 0.75 x VDD ——

VIL ——0.5

Operating Temperature Range TA–40 — 85 ºC

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 8 for further details.

2. OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k  pull-d own resistor to

GND for output enable active low. See 3. "Ordering Informa tion" on page 8.

Table 2. CLK± Output Frequency Characteristics

Parameter Symbol Test Condition Min Typ Max Units

Nominal Frequency1,2 fOLVPECL/LVDS/CML 10 — 810 MHz

CMOS 10 — 160

Initial Accuracy fiMeasured at +25 °C at time of

shipping — ±1.5 — ppm

Total Stability Note 3, second option code “D” — — ±20 ppm

Note 3, second option code “C” — — ±30 ppm

Note 4, second option code “B” — — ±50 ppm

Note 4, second option code “A” — — ±100 ppm

Temperature Stability second option code “D” — — ±7 ppm

second option code “C” — — ±20 ppm

second option code “B” — — ±25 ppm

second option code “A” — — ±50 ppm

Powerup Time5tOSC ——10ms

Notes:

1. See Section 3. "Ordering Information" on page 8 for further details.

2. Specified at time of order by part number.

3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See

3. "Ordering Information" on page 8.

4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See

3. "Ordering Information" on page 8.

5. Time from powerup or tristate mode to fO.

Si590/591

4 Rev. 1.2

Table 3. CLK± Output Levels and Symmetry

Parameter Symbol Test Condition Min Typ Max Units

LVPECL Output Option1VOmid-level VDD – 1.42 — VDD – 1.25 V

VOD swing (diff) 1.1 —1.9 VPP

VSE swing (single-ended) 0.55 —0.95 VPP

LVDS Output Option2VOmid-level 1.125 1.20 1.275 V

VOD swing (diff) 0.5 0.7 0.9 VPP

CML Output Option2

VO2.5/3.3 V option mid-level — VDD – 1.30 — V

1.8 V option mid-level — VDD – 0.36 —

VOD 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP

1.8 V option swing (diff) 0.35 0.425 0.50

CMOS Output Option3VOH 0.8 x VDD —VDD V

VOL ——0.4

Rise/Fall time (20/80%) tR, tFLVPECL/LVDS/CML — — 350 ps

CMOS with CL=15pF — 2 — ns

Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff)

LVDS: 1.25 V (diff)

CMOS: VDD/2 45 — 55 %

Notes:

1. 50  to VDD – 2.0 V.

2. Rterm = 100  (differential).

3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3V, 6mA for V

DD = 2.5V, 3mA for V

DD = 1.8 V.

Table 4. CLK± Output Phase Jitter

Parameter Symbol Test Condition Min Typ Max Units

Phase Jitter (RMS)1

for 50 MHz < FOUT < 810 MHz

(LVPECL/LVDS/CML)

J12 kHz to 20 MHz — 0.5 1.0 ps

Phase Jitter (RMS)1

(LVPECL/LVDS/CML) J12 kHz to 20 MHz,

155.52 MHz output frequency —0.40.7ps

Phase Jitter (RMS)2

for 50 MHz < FOUT < 160 MHz

(CMOS)

J12 kHz to 20 MHz — 0.6 1.0 ps

Notes:

1. Refer to AN256 for further information.

2. Single-ended CMOS output phase jitter measured using 33  series termination into 50  phase noise test equipment.

3.3 V supply voltage option only.

Si590/591

Rev. 1.2 5

Table 5. CLK± Output Period Jitter

Parameter Symbol Test Condition Min Typ Max Units

Period Jitter* JPER RMS — — 3 ps

Peak-to-Peak — — 35

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 6. Environmental Compliance and Package Information

Parameter Conditions/Test Method

Mechanical Shock MIL-STD-883, Method 2002

Mechanical Vibration MIL-STD-883, Method 2007

Solderability MIL-STD-883, Method 2003

Gross and Fine Leak MIL-STD-883, Method 1014

Resistance to Solder Heat MIL-STD-883, Method 2036

Contact Pads Gold over Nickel

Table 7. Thermal Characteristics

(Typical values TA=25ºC, V

DD =3.3V)

Parameter Symbol Test Condition Min Typ Max Unit

5x7mm, The rmal Re sistance Junct i on to

Ambient JA Still Air — 84.6 — °C/W

5x7mm, The rmal Re sistance Junct i on to

Case JC Still Air — 38.8 — °C/W

3.2x5mm, Thermal Resistance Junction to

Ambient JA Still Air — 31.1 — °C/W

3.2x5mm, Thermal Resistance Junction to

Case JC Still Air — 13.3 — °C/W

Ambient Temperature TA–40 — 85 °C

Junction Temper a tur e TJ——125°C

Si590/591

6 Rev. 1.2

Table 8. Absolute Maximum Ratings1

Parameter Symbol Rating Units

Maximum Op er at ing Tem p er at ur e TAMAX 85 ºC

Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V

Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V

Input Voltage (any input pin) VI–0.5 to VDD + 0.3 V

Storage Temperature TS–55 to +125 ºC

ESD Sensitivity (HBM, per JESD22-A114) ESD 2500 V

Soldering Tem p er at ur e (Pb -f re e pr of ile)2TPEAK 260 ºC

Soldering Temperature Time @ TPEAK (Pb-free profile)2tP20–40 seconds

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Fu nctional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at

www.silabs.com/VCXO for further information, including soldering profiles.

Si590/591

Rev. 1.2 7

2. Pin Descriptions

Table 9. Pinout for Si590 Series

Pin Symbol LVDS/LVPECL/CML Function CMOS Function

1OE* No connection

Make no external connection to this pin Output enable

2OE* Output enable No connection

Make no external connection to this pin

3 GND Electrical and Case Ground Electrical and Case Ground

4 CLK+ Oscillator Output Oscillator Output

5 CLK– Complementary Output No connection

Make no external connection to this pin

DD Power Supply Voltage Power Supply Voltage

*Note: OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pulldown resistor to

GND for output enable active low. See 3. "Ordering Informa tion" on page 8.

Table 10. Pinout for Si591 Series

Pin Symbol LVDS/LVPECL/CML Function

1 OE* Output enable

2No connection

Make no external connection to this pin No connection

Make no external connection to this pin

3 GND Electrical and Case Ground

4 CLK+ Oscillator Output

5 CLK– Complemen tary outp ut

DD Power Supply Voltage

*Note: OE pin incl udes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pulldown resistor to

GND for output enable active low. See 3. "Ordering Information" on page 8.

4GND

VDD

CLK

(Top View)

4GND

VDD

CLK+

CLK–

4GND

VDD

CLK+

CLK–

Si590

LVDS/LVPECL/CML Si590

CMOS Si591

LVDS/LVPECL/CML

Si590/591

8 Rev. 1.2

3. Ordering Information

The Si590/591 XO supports a variety of options including frequency, temperature stability, output format, and VDD.

Specific device configurations are programmed into the Si590/591 at time of shipment. Configurations can be

specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based

part number configuration utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and

click “Custo miz e” in th e product table. T he Si5 9 0 an d Si 591 XO series are supplied in an industry-standard, RoHS

compliant, 6-pad, 5 x 7 mm and 3.2 x 5 mm packages. The Si591 Series supports an alternate OE pinout (pin #1)

for LVPECL, LVDS, and CML output formats. See Tables 9 and 10 for the pinout differences between the Si590

and Si591 series.

Figure 1. Part Number Convention

59x XXXXMXXX

1st Option Code

VDD Output Format Output En ab le Polarity

A3.3LVPECL High

B 3.3 LV DS High

C 3.3 CMOS High

D3.3CML High

E2.5LVPECL High

F 2.5 LVDS High

G 2.5 CMOS High

H2.5CML High

J 1.8 CMOS High

K1.8CML High

M 3.3 LVPECL Low

N 3.3 LVDS Low

P3.3CMOS Low

Q3.3CML Low

R 2.5 LVPECL Low

S 2.5 LVDS Low

T2.5CMOS Low

U2.5CML Low

V1.8CMOS Low

W1.8CML Low

Note:

CMOS available to 160 MHz.

D G R

Frequency (e.g., 148M352 is 148.352 MHz)

Available frequency range is 10 to 810 M Hz. T h e p osition of “M” shifts

to denote higher or lower freque ncies. If the freq ue ncy of interest

req u ires gre ater t han 6 digit reso lutio n, a six digit cod e will be

assigned for the specific frequency.

Tap e and Reel P ackaging

Blank = Co il Tape

Operating Tem p Range (° C)

G –40 to +85°C

Part Revision Letter

590 or 591 XO

Product Family

E xam ple P/N: 590BB148M352DGR is a 5 x 7 XO in a 6 pad package. T he fr eq uency is 148.352 M Hz, with a 3.3 V supply, LVDS output, and

Output En ab le active high po larity. Overall stability is specifed as ±50 ppm . T h e device is specified for –40 to +85 °C ambient temperature

range operation and is shipped in tape and reel format.

2nd Option Cod e

Cod e Pac kage T otal Stablilit y (p pm , m a x, ±) Te mper atur e St ablility (p pm , max, ±)

A 5x7 mm 100 50

B 5x7 mm 50 25

C 5 x7 mm 30 20

D 5 x7 m m 20 7

E 3.2x5 mm 100 50

F 3.2x5 mm 50 25

G 3.2x5 mm 30 20

Si590/591

Rev. 1.2 9

4. Package Outline Drawing: 5 x 7 mm, 6-pin

Figure 2 illustrates the package details for the 5 x 7 mm Si590/591. Table 11 lists the values for the dimensions

shown in the illustration.

Figure 2. Si590/591 Outline Diagram

Table 11. Package Diagram Dimensions (mm)

Dimension Min Nom Max

A 1.50 1.65 1.80

b 1.30 1.40 1.50

c 0.50 0.60 0.70

D 5.00 BSC

D1 4.30 4.40 4.50

e 2.54 BSC

E 7.00 BSC

E1 6.10 6.20 6.30

H 0.55 0.65 0.75

L 1.17 1.27 1.37

L1 0.05 0.10 0.15

p 1.80 — 2.60

R 0.70 REF

aaa 0.15

bbb 0.15

ccc 0.10

ddd 0.10

eee 0.05

Si590/591

10 Rev. 1.2

5. PCB Land Pattern: 5 x 7 mm, 6-pin

Figure 3 illustrates the 6-pin PCB land pattern for the 5 x 7 mm Si590/591. Table 12 lists the values for the

dimensions shown in the illustration.

Figure 3. Si590/591 PCB Land Pattern

Table 12. PCB Land Pattern Dimensions (mm)

Dimension (mm)

C1 4.20

E2.54

X1 1.55

Y1 1.95

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between

the solder mask and the metal pad is to be 60 µm minimum, all the way around

the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls

should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

Si590/591

Rev. 1.2 11

6. Package Outline Drawing: 3.2 x 5 mm, 6-pin

Figure illustrates the package details for the 3.2 x 5 mm Si590/591. Table 13 lists the values for the dimensions

shown in the illustration.

Figure 4. Si590/591 Outline Diagram

Table 13. Package Diagram Dimensions (mm)

Dimension Min Nom Max Dimension Min Nom Max

A 1.02 1.17 1.32 E1 2.85 BSC

A1 0.99 1.10 1.21 E2 1.91 BSC

A2 0.5 BSC L 0.35 0.45 0.55

A3 0.30 BSC L2 0.05 0.10 0.15

b0.54

0.64 0.74 R1 0.10 REF

B1 0.35 0.45 0.55 aaa 0.15

D 5.00 BSC bbb 0.15

D1 4.65 BSC ccc 0.08

D2 3.38 BSC ddd 0.10

e 1.27 BSC eee 0.05

E 3.20 BSC

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

Si590/591

12 Rev. 1.2

7. PCB Land Pattern: 3.2 x 5 mm, 6-pin

Figure 5 illustrates the 6-pin PCB land pattern for the 3.2 x 5 mm Si590/591. Table 14 lists the values for the

dimensions shown in the illustration.

Figure 5. Si590/591 PCB Land Pattern

Table 14. PCB Land Pattern Dimensions (mm)

Dimension (mm)

C1 2.91

E1.27

X1 0.80

Y1 1.10

Notes:

General

1. All dimensions shown are in mi llimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines .

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition

(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil ape rture to land pad size shoul d be 1: 1.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for

Small Body Components.

Si590/591

Rev. 1.2 13

8. Si590/Si591 Top Marking: 5 x 7 mm

Figure 6 illustrates the mark specification for the 5 x 7 mm Si590/Si591. Table 15 lists the line information.

Figure 6. Top Mark Specification

Table 15. Si59x Top Mark Description

Line Position Description

1 1–10 “SiLabs”+ Part Family Number, 59x (First 3 characters in p art number where x = 0

indicates a 590 device and x = 1 indicates a 591 device)

2 1–10 Si590, Si591: Option1 + Option2 + Freq(7) + Temp

Si590/Si591 w/ 8-dig it resolution: Option1 + Option2 + ConfigNum(6) + Temp

3 Trace Code

Position 1 Pin 1 orientation mark (dot)

Position 2 Product Revision (D)

Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)

Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site

Position 10 “+” to indicate Pb-Free and RoHS-compliant



Si590/591

14 Rev. 1.2

9. Si590/Si591 Top Marking: 3.2x5mm

Figure 7 illustrates the mark specification for the 3.2 x 5 mm Si590/Si591. Table 1 6 lists the line information.

Figure 7. Top Mark Specification

Table 16. Si59x Top Mark Description

Line Position Description

1 1–5 “Si”+ Part Family Num ber, 59x (First 3 characters in p art numb er where x = 0 indi-

cates a 590 device and x = 1 indicates a 591 device)

6–8 Crystal trace code (3 alp ha n ume ric ch ar ac te rs assigned by assemb ly site )

2 1–9 Si590, Si591: Option1 + Option2 + Freq(7)

Si590/Si591 w/ 8-dig it resolution: Option1 + Option2 + ConfigNum(6)

3 Trace Code

Position 1 Pin 1 orientation mark (dot)

Position 2 Product Revision (D)

Position 3–5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions)

Position 6–7 Year (last two digits of year), to be assigned by assembly site (ex: 20017 = 17)

Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site

Si590/591

Rev. 1.2 15

REVISION HISTORY

Revision 1.2

June, 2018

Changed “Trays” to “Coil Tape” in 3. "Ordering Information" on page 8.

Revision 1.1

December, 2017

Added 3.2 x 5 mm package.

Revision 1.0

Updated 2.5 V/3.3 V and 1.8 V CML output level specifications in Table 3 on page 4.

Updated Si590/591 devices to support frequencies up to 810 MHz for LVPECL, LVDS, and CML outputs.

Separate d 1.8 V, 2.5 V/3.3 V supply voltage. specifications for CML output in Table 3 on page 4.

Updated Note 1 of Table 4 on page 4 to refer to AN256.

Updated Table 4 on page 4.

Updated phase jitter specification.

Updated Table 6 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows.

Updated Figure 3 and Table 15 on page 13 to reflect specific marking information.

Added Table 7, “Thermal Characteristics,” on page 5.

Rearranged sections to conform to new quality standard.

Revision 0.4

Added ±7 ppm temperature stability ordering option in Table 4 on page 4 and Figure 1 on page 8.

Revision 0.3

Updated Table 4 on page 4 by adding the 155.51 MHz “Phase Jitter (RMS) (LVPECL/LVDS/CML)” row.

Updated and clarified Table 6 on page 5 to correct typos and include the “Moisture Sensitivity Level” and

“Contact Pads” rows.

Corrected BSC value in rows D and E in Table 11 on page 9.

Revision 0.25

Total Stability Maximum changed to ±30 in Table 2 on page 3.

Total Stability Maximum changed to ±30 in Figure 1 on page 8.

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