HI-506A, HI-507A HI-508A, HI-509A S E M I C O N D U C T O R August 1997 16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection Features Description * Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . 70VP-P The HI-506A, HI-507A, HI-508A and HI-509A are analog multiplexers with active overvoltage protection. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with 15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1k of resistance under this condition. These features make the HI-506A, HI-507A, HI-508A and HI-509A ideal for use in systems where the analog inputs originate from external equipment, or separately powered circuitry. All devices are fabricated with 44V dielectrically isolated CMOS technology. The HI-506A is a single 16 channel multiplexer, the HI-507A is an 8-Channel differential multiplexer, the HI-508A is a single 8 channel multiplexer and the HI-509A is a differential 4-Channel multiplexer. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521. * No Channel Interaction During Overvoltage * Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V * Fail Safe with Power Loss (No Latch-Up) * Break-Before-Make Switching * Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . 15V * Access Time 500ns * Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW Applications * Data Acquisition Systems * Industrial Controls * Telemetry Ordering Information PART NUMBER TEMP. RANGE (oC) HI1-0506A-2 -55 to 125 28 Ld CERDIP F28.6 HI1-0506A-5 0 to 75 28 Ld CERDIP F28.6 HI1-0506A-8 -55 to 125 + 160 Hour Burn-In 28 Ld CERDIP F28.6 HI3-0506A-5 0 to 75 28 Ld PDIP E28.6 HI1-0507A-8 -55 to 125 + 160 Hour Burn-In 28 Ld CERDIP F28.6 HI3-0507A-5 0 to 75 28 Ld PDIP E28.6 HI1-0508A-7 0 to 75 + 96 Hour Burn-In 16 Ld CERDIP F16.3 HI1-0508A-8 -55 to 125 + 160 Hour Burn-In 16 Ld CERDIP F16.3 HI3-0508A-5 +0 to 75 16 Ld PDIP E16.3 HI1-0509A-2 -55 to 125 16 Ld CERDIP F16.3 HI1-0509A-5 0 to 75 16 Ld CERDIP F16.3 HI1-0509A-7 0 to 75 + 96 Hour Burn-In 16 Ld CERDIP F16.3 HI1-0509A-8 -55 to 125 + 160 Hour Burn-In 16 Ld CERDIP F16.3 HI3-0509A-5 0 to 75 16 Ld PDIP E16.3 PACKAGE PKG. NO. The HI-506A/507A devices are available in a 28 lead Plastic or Ceramic DIP and the HI-508A/509A devices are available in a 16 lead Plastic or Ceramic DIP package. The HI-50XA are offered in industrial/commercial and military grades, additional Hi-Rel screening including 160 hour burn-in is specified by the "8" suffix. For MIL-STD-883 compliant parts, request the HI-546/883, HI-547/883, HI-548/883 or HI-549/883 data sheets. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 11-70 File Number 3143.1 HI-506A, HI-507A, HI-508A, HI-509A Pinouts HI1-506A (CERDIP) HI3-506A (PDIP) TOP VIEW +VSUPPLY 1 HI1-507A (CERDIP) HI3-507A (PDIP) TOP VIEW 28 OUT +VSUPPLY 1 28 OUT A NC 2 27 -VSUPPLY NC 3 26 IN 8 NC 3 26 IN 8A IN 16 4 25 IN 7 IN 8B 4 25 IN 7A IN 15 5 24 IN 6 IN 7B 5 24 IN 6A IN 14 6 23 IN 5 IN 6B 6 23 IN 5A IN 13 7 22 IN 4 IN 5B 7 22 IN 4A IN 12 8 21 IN 3 IN 4B 8 21 IN 3A IN 11 9 20 IN 2 IN 3B 9 20 IN 2A IN 10 10 19 IN 1 IN 2B 10 19 IN 1A 18 ENABLE IN 1B 11 18 ENABLE IN 9 11 OUT B 2 27 -VSUPPLY GND 12 17 ADDRESS A0 GND 12 17 ADDRESS A0 VREF 13 16 ADDRESS A1 VREF 13 16 ADDRESS A1 ADDRESS A3 14 15 ADDRESS A2 NC 14 15 ADDRESS A2 HI1-508A (CERDIP) HI3-508A (PDIP) TOP VIEW HI1-509A (CERDIP) HI3-509A (PDIP) TOP VIEW A0 1 16 A1 A0 1 ENABLE 2 15 A2 ENABLE 2 16 A1 15 GND -VSUPPLY 3 14 GND -VSUPPLY 3 14 +VSUPPLY IN 1 4 13 +VSUPPLY IN 1A 4 13 IN 1B IN 2 5 12 IN 5 IN 2A 5 12 IN 2B IN 3 6 11 IN 6 IN 3A 6 11 IN 3B IN 4 7 10 IN 7 IN 4A 7 10 IN 4B OUT 8 9 IN 8 OUT A 8 11-71 9 OUT B HI-506A, HI-507A, HI-508A, HI-509A Functional Diagrams HI-506A HI-507A OUT 1K IN 1 OUT A 1K IN 1A 1K 1K IN 2 IN 8A OUT B 1K DECODER/ DRIVER IN 1B 1K IN 16 1K DECODER/ DRIVER IN 8B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF DIGITAL INPUT PROTECTION LEVEL SHIFT VREF A0 A1 A2 A3 EN A1 A2 EN DIGITAL INPUT PROTECTION HI-508A VREF A0 HI-509A OUT A 1K OUT 1K IN 1A IN 1 1K 1K IN 2 IN 4A OUT B 1K DECODER/ DRIVER IN 1B 1K IN 8 1K DECODER/ DRIVER IN 4B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT A0 A1 A2 EN OVERVOLTAGE CLAMP AND SIGNAL ISOLATION DIGITAL INPUT PROTECTION 5V REF LEVEL SHIFT A0 A1 EN DIGITAL INPUT PROTECTION 11-72 HI-506A, HI-507A, HI-508A, HI-509A Schematic Diagrams ADDRESS INPUT BUFFER AND LEVEL SHIFTER TTL REFERENCE CIRCUIT V+ R10 R9 Q1 VREF Q4 D3 GND LEVEL SHIFTER V+ OVERVOLTAGE PROTECTION P P P N R2 P P P P R5 V+ R3 N LEVEL SHIFTED ADDRESS TO DECODE N N R8 N N N N N V- V- GND ADD IN ADDRESS DECODER +V P P P R7 R6 D1 P R4 D2 R1 200 P P P A0 OR A0 A1 OR A1 A2 OR A2 A3 OR A3 P P P N N N TO P-CHANNEL DEVICE OF THE SWITCH N N TO N-CHANNEL DEVICE OF THE SWITCH N N ENABLE DELETE A3 OR A3 INPUT FOR HI-507A AND HI-509A V- 11-73 N HI-506A, HI-507A, HI-508A, HI-509A Schematic Diagrams (Continued) MULTIPLEX SWITCH FROM DECODE OVERVOLTAGE PROTECTION N V+ Q5 P R11 1K D7 D6 D4 D5 N IN OUT N Q6 VP FROM DECODE 11-74 HI-506A, HI-507A, HI-508A, HI-509A Absolute Maximum Ratings Thermal Information VSUPPLY(+) to VSUPPLY(-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V VSUPPLY(+) to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V VSUPPLY(-) to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V Digital Input Overvoltage +VEN , +VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V -VEN , -VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V or 20mA, Whichever Occurs First Analog Signal Overvoltage +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +20V -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -20V Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA Pulsed at 1ms, 10% Duty Cycle (Max) Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) 28 Ld CERDIP Package (HI-506A, HI-507A) . . . . . . . . . . . . . 55 18 16 Ld CERDIP Package (HI-508A, HI-509A) . . . . . . . . . . . . . 85 32 28 Ld PDIP Package (HI-506A, HI-507A) . . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package (HI-508A, HI-509A) . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Ranges HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . . -55oC to 125oC HI-506A/507A/508A/509A-5, -7 . . . . . . . . . . . . . . . . 0oC to 75 oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = +4V; VAL (Logic Level Low) = +0.8V, Unless Otherwise Specified. For Test Conditions, Consult Performance Curves PARAMETER HI-50XA-2, -8 HI-50XA-5, -7 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 0.5 - - 0.5 - s Full - - 1.0 - - 1.0 s 25 25 80 - 25 80 - ns SWITCHING CHARACTERISTICS Access Time, tA (Note 2) Break-Before-Make Delay, tOPEN (Note 2) Enable Delay (ON), tON(EN) (Note 2) Enable Delay (OFF), tOFF(EN) (Note 2) 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns Settling Time to 0.1%, tS (HI-506A and HI-507A) 25 - 1.2 - - 1.2 - s Settling Time to 0.01%, tS (HI-506A and HI-507A) 25 - 3.5 - - 3.5 - s Settling Time to 0.1%, tS (HI-508A and HI-509A) 25 - 1.2 - - 1.2 - s Settling Time to 0.01%, tS (HI-508A and HI-509A) 25 - 3.5 - - 3.5 - s "Off Isolation" (Note 7) 25 50 68 - 50 68 - dB Channel Input Capacitance, CS(OFF) 25 - 12 - - 12 - pF Channel Output Capacitance, CD(OFF) (HI-506A) 25 - 52 - - 52 - pF Channel Output Capacitance, CD(OFF) (HI-507A) 25 - 30 - - 30 - pF Channel Output Capacitance, CD(OFF) (HI-508A) 25 - 25 - - 25 - pF Channel Output Capacitance, CD(OFF) (HI-509A) 25 - 12 - - 12 - pF Digital Input Capacitance, CA 25 - 10 - - 10 - pF Input to Output Capacitance, CDS(OFF) 25 - 0.1 - - 0.1 - pF Input Low Threshold, TTL Drive, VAL (Note 2) Full - - +0.8 - - +0.8 V Input High Threshold, VAH (Notes 2, 9) Full +4.0 - - +4.0 - - V DIGITAL INPUT CHARACTERISTICS 11-75 HI-506A, HI-507A, HI-508A, HI-509A Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = +4V; VAL (Logic Level Low) = +0.8V, Unless Otherwise Specified. For Test Conditions, Consult Performance Curves (Continued) HI-50XA-2, -8 HI-50XA-5, -7 PARAMETER TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Input Leakage Current (High or Low), IA (Notes 2, 6) Full - - 1.0 - - 1.0 A MOS Drive, VAL , HI-506A/HI-507A (Note 10) 25 - - 0.8 - - 0.8 V MOS Drive, VAH , HI-506A/HI-507A (Note 10) 25 6.0 - - 6.0 - - V Full -15 - +15 -15 - +15 V ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VS (Note 2) On Resistance, rON , (Notes 2, 3) Off Input Leakage Current, IS(OFF) (Notes 2, 4) Off Output Leakage Current, ID(OFF) (Notes 2, 4) 25 - 1.2 1.5 - 1.5 1.8 k Full - 1.5 1.8 - 1.8 2.0 k 25 - 0.03 - - 0.03 - nA Full - - 50 - - 50 nA 25 - 0.1 - - 0.1 - nA HI-506A Full - - 300 - - 300 nA HI-507A Full - - 200 - - 200 nA HI-508A Full - - 200 - - 200 nA HI-509A Full - - 100 - - 100 nA 25 - 4.0 - - 4.0 - nA Full - - 2.0 - - - A 25 - 0.1 - - 0.1 - nA HI-506A Full - - 300 - - 300 nA HI-507A Full - - 200 - - 200 nA HI-508A Full - - 200 - - 200 nA HI-509A Full - - 100 - - 100 nA Full - - 50 - - 50 nA Current, I+, Pin 1 (Notes 2, 8) Full - 1.5 2.0 - 1.5 2.0 mA Current, I+, HI-508A/HI-509A (Notes 2, 8) Full - 1.5 2.4 - 1.5 2.0 mA Current, I-, Pin 27 (Notes 2, 8) Full - 0.02 1.0 - 0.02 1.0 mA Power Dissipation, PD Full - 7.5 - - 7.5 - mW With Input Overvoltage Applied, ID(OFF) (Note 5) On Channel Leakage Current, ID(ON) (Notes 2, 4) Differential Off Output Leakage Current, IDIFF, (HI-507A, HI-509A Only) POWER REQUIREMENTS NOTES: 2. 100% tested for Dash 8. Leakage currents not tested at -55oC. 3. VOUT = 10V, IOUT = +100A. 4. 10nA is the practical lower limit for high speed measurement in the production test environment. 5. Analog Overvoltage = 33V. 6. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 7. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 8. VEN , VA = 0V or 4V. 9. To drive from DTL/TTL Circuits, 1k pull-up resistors to +5V supply are recommended. 10. VREF = +10V. 11-76 HI-506A, HI-507A, HI-508A, HI-509A Typical Performance Curves and Test Circuits TA = 25oC, VSUPPLY = 15V, VAH = +4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified -100A V2 IN OUT VIN V2 rON = 100A FIGURE 1A. TEST CIRCUIT 1.4 1.2 1.1 TA = 25oC 1.0 TA = -55oC 0.9 0.8 0.7 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.6 -10 -8 -6 -4 -2 0 +2 +4 ANALOG INPUT (V) +6 +8 +10 125oC TO -55oC VIN = +5V 1.5 5 6 7 8 9 10 11 12 13 14 SUPPLY VOLTAGE (V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA LEAKAGE CURRENT 10nA OFF OUTPUT CURRENT ID(OFF) +0.8V EN ON LEAKAGE CURRENT ID(ON) OUT 1nA A 10pA 10V OFF INPUT LEAKAGE CURRENT IS(OFF) 100pA 25 50 75 100 TEMPERATURE (oC) 125 FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) (NOTE 1) 11-77 ID(OFF) ON RESISTANCE (k) NORMALIZED RESISTANCE (REFERRED TO VALUE AT 15V) TA = 125oC 1.3 10V 15 HI-506A, HI-507A, HI-508A, HI-509A Typical Performance Curves and Test Circuits TA = 25oC, VSUPPLY = 15V, VAH = +4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) OUT OUT IS(OFF) A A +0.8V EN 10V A0 A1 ID(ON) EN 10V 10V 10V +2.4V FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 1) FIGURE 2D. ID(On) TEST CIRCUIT (NOTE 1) NOTE: 1. Two measurements per channel: 10V and +10V. (Two measurements per device for ID(OFF) 10V and +10V.) FIGURE 2. LEAKAGE CURRENTS ANALOG INPUT CURRENT (mA) 18 6 ANALOG INPUT CURRENT (IIN) 15 5 12 4 9 3 6 2 OUTPUT OFF LEAKAGE CURRENT ID(OFF) 3 0 15 18 21 24 27 30 33 1 36 OUTPUT OFF LEAKAGE CURRENT (nA) 7 A IIN A ID(OFF) VIN 0 ANALOG INPUT OVERVOLTAGE (V) FIGURE 3A. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS FIGURE 3B. TEST CIRCUIT FIGURE 3. OVERVOLTAGE CHARACTERISTICS 14 -55oC SWITCH CURRENT (mA) 12 10 25oC 125oC 8 6 VIN 4 A 2 0 0 2 4 6 8 10 12 14 VOLTAGE ACROSS SWITCH (V) FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4B. TEST CIRCUIT FIGURE 4. ON CHANNEL CURRENT 11-78 HI-506A, HI-507A, HI-508A, HI-509A Typical Performance Curves and Test Circuits TA = 25oC, VSUPPLY = 15V, VAH = +4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) +15V/+10V +V IN 1 HI-506A A2 IN 2 THRU A1 IN 7/IN 15 6 10V/5V A3 VSUPPLY = 15V 4 VV A 50 VSUPPLY = 10V A0 2 IN 8/IN 16 EN +4V GND OUT -V 1K 10K 100K TOGGLE FREQUENCY (Hz) 1M 10V/ 10 M 5V 14 pF -ISUPPLY A 0 SUPPLY CURRENT (mA) +ISUPPLY A 8 10M -15V/-10V Similar connection for HI-507A/HI-508A/HI-509A FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 5B. TEST CIRCUIT FIGURE 5. SUPPLY CURRENTS +15V 900 A3 VA 50 A1 600 HI-506A A0 500 IN 16 EN +4V 10V IN 2 THRU IN 7/IN 15 A2 700 +V IN 1 GND ACCESS TIME (ns) VREF VREF = OPEN FOR LOGIC HIGH LEVEL 6V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V 800 10V OUT -V 400 -15V 300 3 4 5 6 7 9 10 11 12 8 LOGIC LEVEL (HIGH) (V) 13 14 15 Similar connection for HI-507A/HI-580A/HI-509A FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 6B. TEST CIRCUIT FIGURE 6. ACCESS TIME Switching Waveforms VAH = 4.0V ADDRESS DRIVE (VA) VA INPUT 2V/DIV. 1/ V 2 AH 0V +10V OUTPUT 90% OUTPUT A 5V/DIV. -10V tA 200ns/DIV. FIGURE 7A. FIGURE 7B. FIGURE 7. ACCESS TIME 11-79 PROBE 10 k 50 pF HI-506A, HI-507A, HI-508A, HI-509A A3 HI-506A A2 A3 +5V IN 1 HI-506A A2 IN 1 A1 IN 2 THRU IN 7/IN 15 IN 8 /IN 16 IN 2 THRU VA 50 +4.0V A1 IN 7/IN 15 A0 IN 8/IN 16 A0 VOUT OUT EN OUT EN GND -VA 50pF 1k +10V Similar connection for HI-507A/HI-508A/HI-509A 50 GND 50pF 1k Similar connection for HI-507A//HI-508A/HI-509A FIGURE 8A. FIGURE 9A. VAH = 4.0V VAH = 4.0V 50% 50% ADDRESS DRIVE (VA) 0V 0V OUTPUT 90% OUTPUT 90% 50% 50% tON(EN) tOFF(EN) tOPEN FIGURE 8B. FIGURE 9B. VA INPUT 2V/DIV. 16 ON 1 ON 1 ON OUTPUT 0.5V/DIV. IN 1 THRU IN 16 OFF OUTPUT 2V/DIV. 100ns/DIV. 100ns/DIV. FIGURE 8C. FIGURE 9C. FIGURE 8. BREAK-BEFORE-MAKE DELAY FIGURE 9. ENABLE DELAY tON(EN) , tOFF(EN) 11-80 HI-506A, HI-507A, HI-508A, HI-509A Truth Tables HI-506A HI-508A A3 A2 A1 A0 EN "ON" CHANNEL A2 A1 A0 EN "ON" CHANNEL X X X X L None X X X L None L L L L H 1 L L L H 1 L L L H H 2 L L H H 2 L L H L H 3 L H L H 3 L L H H H 4 L H H H 4 L H L L H 5 H L L H 5 L H L H H 6 H L H H 6 L H H L H 7 H H L H 7 L H H H H 8 H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 A1 A0 EN "ON" CHANNEL PAIR H H L L H 13 X X L None H H L H H 14 L L H 1 H H H L H 15 L H H 2 H H H H H 16 H L H 3 H H H 4 HI-509A HI-507A A2 A1 A0 EN "ON" CHANNEL PAIR X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 11-81 HI-506A, HI-507A, HI-508A, HI-509A Die Characteristics DIE DIMENSIONS: WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 159 mils x 83.9 mils x 19 mils METALLIZATION: TRANSISTOR COUNT: Type: CuAl Thickness: 16kA 2kA 485 PROCESS: SUBSTRATE POTENTIAL (NOTE): CMOS-DI -VSUPPLY PASSIVATION: Silox: 12kA 2kA Nitride: 3.5kA 1kA NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-506A EN (18) A0 (17) A1 A2 (16) (15) HI-507A A3 VREF (14) (13) GND (12) EN (18) A0 (17) A1 A2 (16) (15) NC VREF (14) (13) GND (12) IN 1 (19) IN 9 (11) IN 1A (19) IN 2 (20) IN 10 (10) IN 2A (20) IN 3 (21) IN 11 (9) IN 3A (21) IN 3B (9) IN 4 (22) IN 12 (8) IN 4A (22) IN 4B (8) IN 5 (23) IN 6 (24) IN 13 (7) IN 14 (6) IN 5A (23) IN 6A (24) IN 5B (7) IN 6B (6) IN 7 (25) IN 15 (5) IN 7A (25) IN 7B (5) IN 8 (26) IN 16 (4) IN 8A (26) IN 8B (4) V- (27) OUT (28) +V (1) NC (2) V- (27) 11-82 IN 1B (11) IN 2B (10) OUT A (28) +V (1) OUT B(2) HI-506A, HI-507A, HI-508A, HI-509A Die Characteristics DIE DIMENSIONS: WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 108 mils x 83 mils METALLIZATION: TRANSISTOR COUNT: Type: CuAl Thickness: 16kA 2kA 253 PROCESS: SUBSTRATE POTENTIAL (NOTE): CMOS-DI -VSUPPLY PASSIVATION: Silox: 12kA 2kA Nitride: 3.5kA 1kA NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-508A IN 6 (11) IN 7 IN 8 (10) (9) HI-509A OUT (8) IN 4 IN 3 (7) (6) IN 3B IN 4B OUT B (11) (10) (9) OUT A (8) IN 4A IN 3A (7) (6) IN 5 (12) IN 2 (5) IN 2B (12) IN 2A (5) +V (13) GND (14) IN 1 (4) -V (3) IN 1B (13) +V (14) IN 1A (4) -V (3) A2 (15) A1 (16) A0 (1) GND (15) EN (2) 11-83 A1 (16) A0 (1) EN (2)