HI3-0508A-5 - Harris Semiconductor

SEMICONDUCTOR

11-70

Features

• Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . 70VP-P

• No Channel Interaction During Overvoltage

• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . .44V

• Fail Safe with Po wer Loss (No Latc h-Up)

• Break-Before-Make Switching

• Analog Signal Range. . . . . . . . . . . . . . . . . . . . . . . ±15V

• Access Time 500ns

• Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW

Applications

• Data Acquisition Systems

• Industrial Controls

• Telemetry

Ordering Information

Description

The HI-506A, HI-507A, HI-508A and HI-509A are analog

multiplexers with active overvoltage protection. Analog

input le vels may greatly exceed either power supply without

damaging the device or disturbing the signal path of other

channels. Active protection circuitry assures that signal

ﬁdelity is maintained even under fault conditions that would

destroy other multiplexers. Analog inputs can withstand

constant 70VP-P levels with ±15V supplies. Digital inputs

will also sustain continuous faults up to 4V greater than

either supply. In addition, signal sources are protected from

short circuiting should multiplexer supply loss occur. Each

input presents 1kΩ of resistance under this condition.

These features make the HI-506A, HI-507A, HI-508A and

HI-509A ideal for use in systems where the analog inputs

originate from external equipment, or separately powered

circuitry. All devices are fabricated with 44V dielectrically

isolated CMOS technology. The HI-506A is a single 16

channel multiplexer, the HI-507A is an 8-Channel differen-

tial multiplexer, the HI-508A is a single 8 channel multi-

plexer and the HI-509A is a differential 4-Channel

multiplexer. If input overvoltage protection is not needed

the HI-506/507/508/509 multiplexers are recommended.

For further information see Application Notes AN520 and

AN521.

The HI-506A/507A devices are available in a 28 lead Plas-

tic or Ceramic DIP and the HI-508A/509A devices are avail-

able in a 16 lead Plastic or Ceramic DIP package.

The HI-50XA are offered in industrial/commercial and

military grades, additional Hi-Rel screening including 160

hour burn-in is speciﬁed by the “8” sufﬁx. For MIL-STD-883

compliant parts, request the HI-546/883, HI-547/883,

HI-548/883 or HI-549/883 data sheets.

PART

NUMBER TEMP. RANGE

(oC) PACKAGE PKG.

NO.

HI1-0506A-2 -55 to 125 28 Ld CERDIP F28.6

HI1-0506A-5 0 to 75 28 Ld CERDIP F28.6

HI1-0506A-8 -55 to 125 + 160

Hour Burn-In 28 Ld CERDIP F28.6

HI3-0506A-5 0 to 75 28 Ld PDIP E28.6

HI1-0507A-8 -55 to 125 + 160

Hour Burn-In 28 Ld CERDIP F28.6

HI3-0507A-5 0 to 75 28 Ld PDIP E28.6

HI1-0508A-7 0 to 75 + 96 Hour

Burn-In 16 Ld CERDIP F16.3

HI1-0508A-8 -55 to 125 + 160

Hour Burn-In 16 Ld CERDIP F16.3

HI3-0508A-5 +0 to 75 16 Ld PDIP E16.3

HI1-0509A-2 -55 to 125 16 Ld CERDIP F16.3

HI1-0509A-5 0 to 75 16 Ld CERDIP F16.3

HI1-0509A-7 0 to 75

+ 96 Hour Burn-In 16 Ld CERDIP F16.3

HI1-0509A-8 -55 to 125 + 160

Hour Burn-In 16 Ld CERDIP F16.3

HI3-0509A-5 0 to 75 16 Ld PDIP E16.3

August 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

HI-506A, HI-507A

HI-508A, HI-509A

16-Channel, 8-Channel, Differential 8-Channel and Differential

4-Channel, CMOS Analog MUXs with Active Overvoltage Protection

11-71

Pinouts

HI1-506A (CERDIP)

HI3-506A (PDIP)

TOP VIEW

HI1-507A (CERDIP)

HI3-507A (PDIP)

TOP VIEW

HI1-508A (CERDIP)

HI3-508A (PDIP)

TOP VIEW

HI1-509A (CERDIP)

HI3-509A (PDIP)

TOP VIEW

+VSUPPLY

IN 16

IN 15

IN 14

IN 13

IN 12

IN 11

IN 10

IN 9

GND

VREF

ADDRESS A3

OUT

IN 8

IN 7

IN 6

IN 5

IN 3

IN 1

ENABLE

ADDRESS A0

ADDRESS A1

ADDRESS A2

-VSUPPLY

IN 4

IN 2

+VSUPPLY

OUT B

IN 8B

IN 7B

IN 6B

IN 5B

IN 4B

IN 3B

IN 2B

IN 1B

GND

VREF

OUT A

IN 8A

IN 7A

IN 6A

IN 5A

IN 3A

IN 1A

ENABLE

ADDRESS A0

ADDRESS A1

ADDRESS A2

-VSUPPLY

IN 4A

IN 2A

ENABLE

-VSUPPLY

IN 1

IN 2

IN 3

OUT

IN 4

GND

+VSUPPLY

IN 5

IN 6

IN 7

IN 8

ENABLE

-VSUPPLY

IN 1A

IN 2A

IN 3A

OUT A

IN 4A

+VSUPPLY

IN 1B

IN 2B

IN 3B

IN 4B

OUT B

GND

HI-506A, HI-507A, HI-508A, HI-509A

11-72

Functional Diagrams

HI-506A HI-507A

HI-508A HI-509A

DECODER/

DRIVER

† † † †

OUT

IN 1

IN 2

IN 16

PROTECTION A0A1A2A3

†

† DIGITAL INPUT

LEVEL

SHIFT

REF

VREF

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

DECODER/

DRIVER

† † †

OUT

IN 1A

IN 8A

IN 1B

PROTECTION A0A1A2

†

† DIGITAL INPUT

LEVEL

SHIFT

REF

VREF

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

IN 8B

OUT

DECODER/

DRIVER

† † †

OUT

IN 1

IN 2

IN 8

PROTECTION A0A1A2

†

† DIGITAL INPUT

LEVEL

SHIFT

REF

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

DECODER/

DRIVER

† †

OUT

IN 1A

IN 4A

IN 1B

PROTECTION A0A1

†

† DIGITAL INPUT

LEVEL

SHIFT

REF

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

IN 4B

OUT

HI-506A, HI-507A, HI-508A, HI-509A

11-73

Schematic Diagrams

ADDRESS INPUT BUFFER AND LEVEL SHIFTER

ADDRESS DECODER

LEVEL SHIFTER

VREF

ADD

P P

LEVEL

SHIFTED

ADDRESS

TTL REFERENCE

CIRCUIT

V+

R10

GND

OVERVOLTAGE

PROTECTION

200

V-

Ω

V+

GND

V+

V-

DECODE

R5 R7

A0 OR A0

TO N-CHANNEL

DEVICE OF

THE SWITCH

A1 OR A1

A2 OR A2

A3 OR A3

ENABLE

PP PP P P

V-

TO P-CHANNEL

DEVICE OF

THE SWITCH

DELETE A3 OR A3INPUT

FOR HI-507A AND HI-509A

HI-506A, HI-507A, HI-508A, HI-509A

11-74

MULTIPLEX SWITCH

Schematic Diagrams

(Continued)

FROM DECODE

V+

OUT

FROM DECODE

OVERVOLTAGE PROTECTION

R11

V-

D7 D4 D5

HI-506A, HI-507A, HI-508A, HI-509A

11-75

Absolute Maximum Ratings Thermal Information

VSUPPLY(+) to VSUPPLY(-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V

VSUPPLY(+) to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V

VSUPPLY(-) to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V

Digital Input Overvoltage

+VEN, +VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V

-VEN, -VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V

or 20mA, Whichever Occurs First

Analog Signal Overvoltage

+VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +20V

-VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -20V

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40mA

Pulsed at 1ms, 10% Duty Cycle (Max)

Operating Conditions

Temperature Ranges

HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . . -55oC to 125oC

HI-506A/507A/508A/509A-5, -7 . . . . . . . . . . . . . . . . 0oC to 75 oC

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

28 Ld CERDIP Package

(HI-506A, HI-507A) . . . . . . . . . . . . . 55 18

16 Ld CERDIP Package

(HI-508A, HI-509A) . . . . . . . . . . . . . 85 32

28 Ld PDIP Package

(HI-506A, HI-507A) . . . . . . . . . . . . . 60 N/A

16 Ld PDIP Package

(HI-508A, HI-509A) . . . . . . . . . . . . . 100 N/A

Maximum Junction Temperature

CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Speciﬁcations Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = +4V; VAL (Logic Lev el Lo w) = +0.8V,

Unless Otherwise Speciﬁed. For Test Conditions, Consult Performance Curves

PARAMETER TEMP

(oC)

HI-50XA-2, -8 HI-50XA-5, -7

UNITSMIN TYP MAX MIN TYP MAX

SWITCHING CHARACTERISTICS

Access Time, tA (Note 2) 25 - 0.5 - - 0.5 - µs

Full - - 1.0 - - 1.0 µs

Break-Before-Make Delay, tOPEN (Note 2) 25 25 80 - 25 80 - ns

Enable Delay (ON), tON(EN) (Note 2) 25 - 300 500 - 300 - ns

Full - - 1000 - - 1000 ns

Enable Delay (OFF), tOFF(EN) (Note 2) 25 - 300 500 - 300 - ns

Full - - 1000 - - 1000 ns

Settling Time to 0.1%, tS (HI-506A and HI-507A) 25 - 1.2 - - 1.2 - µs

Settling Time to 0.01%, tS (HI-506A and HI-507A) 25 - 3.5 - - 3.5 - µs

Settling Time to 0.1%, tS (HI-508A and HI-509A) 25 - 1.2 - - 1.2 - µs

Settling Time to 0.01%, tS (HI-508A and HI-509A) 25 - 3.5 - - 3.5 - µs

“Off Isolation” (Note 7) 25 50 68 - 50 68 - dB

Channel Input Capacitance, CS(OFF) 25-12- -12-pF

Channel Output Capacitance, CD(OFF) (HI-506A) 25 - 52 - - 52 - pF

Channel Output Capacitance, CD(OFF) (HI-507A) 25 - 30 - - 30 - pF

Channel Output Capacitance, CD(OFF) (HI-508A) 25 - 25 - - 25 - pF

Channel Output Capacitance, CD(OFF) (HI-509A) 25 - 12 - - 12 - pF

Digital Input Capacitance, CA25-10- -10-pF

Input to Output Capacitance, CDS(OFF) 25 - 0.1 - - 0.1 - pF

DIGITAL INPUT CHARACTERISTICS

Input Low Threshold, TTL Drive, VAL (Note 2) Full - - +0.8 - - +0.8 V

Input High Threshold, VAH (Notes 2, 9) Full +4.0 - - +4.0 - - V

HI-506A, HI-507A, HI-508A, HI-509A

11-76

Input Leakage Current (High or Low), IA(Notes 2, 6) Full - - 1.0 - - 1.0 µA

MOS Drive, VAL, HI-506A/HI-507A (Note 10) 25 - - 0.8 - - 0.8 V

MOS Drive, VAH, HI-506A/HI-507A (Note 10) 25 6.0 - - 6.0 - - V

ANALOG CHANNEL CHARACTERISTICS

Analog Signal Range, VS (Note 2) Full -15 - +15 -15 - +15 V

On Resistance, rON, (Notes 2, 3) 25 - 1.2 1.5 - 1.5 1.8 kΩ

Full - 1.5 1.8 - 1.8 2.0 kΩ

Off Input Leakage Current, IS(OFF) (Notes 2, 4) 25 - 0.03 - - 0.03 - nA

Full - - 50 - - 50 nA

Off Output Leakage Current, ID(OFF) (Notes 2, 4) 25 - 0.1 - - 0.1 - nA

HI-506A Full - - 300 - - 300 nA

HI-507A Full - - 200 - - 200 nA

HI-508A Full - - 200 - - 200 nA

HI-509A Full - - 100 - - 100 nA

With Input Overvoltage Applied, ID(OFF) (Note 5) 25 - 4.0 - - 4.0 - nA

Full - - 2.0 - - - µA

On Channel Leakage Current, ID(ON) (Notes 2, 4) 25 - 0.1 - - 0.1 - nA

HI-506A Full - - 300 - - 300 nA

HI-507A Full - - 200 - - 200 nA

HI-508A Full - - 200 - - 200 nA

HI-509A Full - - 100 - - 100 nA

Differential Off Output Leakage Current, IDIFF,

(HI-507A, HI-509A Only) Full - - 50 - - 50 nA

POWER REQUIREMENTS

Current, I+, Pin 1 (Notes 2, 8) Full - 1.5 2.0 - 1.5 2.0 mA

Current, I+, HI-508A/HI-509A (Notes 2, 8) Full - 1.5 2.4 - 1.5 2.0 mA

Current, I-, Pin 27 (Notes 2, 8) Full - 0.02 1.0 - 0.02 1.0 mA

Power Dissipation, PDFull - 7.5 - - 7.5 - mW

NOTES:

2. 100% tested for Dash 8. Leakage currents not tested at -55oC.

3. VOUT = ±10V, IOUT = +100µA.

4. 10nA is the practical lower limit for high speed measurement in the production test environment.

5. Analog Overvoltage = ±33V.

6. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC.

7. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS, f = 100kHz.

8. VEN, VA = 0V or 4V.

9. To drive from DTL/TTL Circuits, 1kΩ pull-up resistors to +5V supply are recommended.

10. VREF = +10V.

Electrical Speciﬁcations Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = +4V; VAL (Logic Lev el Lo w) = +0.8V,

Unless Otherwise Speciﬁed. For Test Conditions, Consult Performance Curves (Continued)

PARAMETER TEMP

(oC)

HI-50XA-2, -8 HI-50XA-5, -7

UNITSMIN TYP MAX MIN TYP MAX

HI-506A, HI-507A, HI-508A, HI-509A

11-77

T ypical P erformance Curves and T est Circuits

TA = 25oC, VSUPPLY = ±15V, V AH = +4V, V AL = 0.8V, VREF = Open,

Unless Otherwise Speciﬁed

FIGURE 1A. TEST CIRCUIT

FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY

VOLTAGE

FIGURE 1. ON RESISTANCE

FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) (NOTE 1)

-100µA

OUTIN

VIN rON = V2

100µA

-10 ANALOG INPUT (V)

ON RESISTANCE (kΩ)

-8 +2 +4 +6 +8 +10-6 -4 -2 0

1.4

1.3

1.2

1.1

1.0

0.9

0.8

TA = 125oC

TA = 25oC

TA = -55oC

0.7

0.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

NORMALIZED RESISTANCE

(REFERRED TO VALUE AT ±15V)

±7±8±9±10 ±11 ±12 ±13 ±14 ±15

SUPPLY VOLTAGE (V)

±5±6

125oC TO -55oC

VIN = +5V

100nA

10nA

1nA

100pA

10pA

LEAKAGE CURRENT

25 50 75 100 125

TEMPERATURE (oC)

OFF OUTPUT

CURRENT

ID(OFF)

OFF INPUT

LEAKAGE CURRENT

IS(OFF)

ON LEAKAGE

CURRENT

ID(ON)

ID(OFF)

±10V

+0.8V

OUT

10V

HI-506A, HI-507A, HI-508A, HI-509A

11-78

FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 1) FIGURE 2D. ID(On) TEST CIRCUIT (NOTE 1)

NOTE:

1. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V.)

FIGURE 2. LEAKAGE CURRENTS

FIGURE 3A. ANALOG INPUT OVER V OLTAGE CHARA CTERISTICS FIGURE 3B. TEST CIRCUIT

FIGURE 3. OVERVOLTAGE CHARACTERISTICS

FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4B. TEST CIRCUIT

FIGURE 4. ON CHANNEL CURRENT

T ypical P erformance Curves and T est Circuits

TA = 25oC, VSUPPLY = ±15V, V AH = +4V, V AL = 0.8V, VREF = Open,

Unless Otherwise Speciﬁed (Continued)

10V

±10V

+0.8V

OUT

IS(OFF)

OUT

ID(ON)

±10V ±10V

+2.4V

A0A1

±15 ±18 ±21 ±24 ±27 ±30 ±33 ±36

ANALOG INPUT OVERVOLTAGE (V)

ANALOG INPUT CURRENT (mA)

OUTPUT OFF LEAKAGE CURRENT (nA)

ANALOG INPUT

CURRENT (IIN)

OUTPUT OFF LEAKAGE

CURRENT ID(OFF)

±VIN

AIIN ID(OFF)

0±2±4±6±8±10 ±12 ±14

±14

±12

±10

±8

±6

±4

±2

VOLTAGE ACROSS SWITCH (V)

SWITCH CURRENT (mA)

-55oC25oC

125oC

±VIN

HI-506A, HI-507A, HI-508A, HI-509A

11-79

FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 5B. TEST CIRCUIT

FIGURE 5. SUPPLY CURRENTS

FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 6B. TEST CIRCUIT

FIGURE 6. ACCESS TIME

Switching Waveforms

FIGURE 7A. FIGURE 7B.

FIGURE 7. ACCESS TIME

T ypical P erformance Curves and T est Circuits

TA = 25oC, VSUPPLY = ±15V, V AH = +4V, V AL = 0.8V, VREF = Open,

Unless Otherwise Speciﬁed (Continued)

01K TOGGLE FREQUENCY (Hz)

SUPPLY CURRENT (mA)

10K 100K 1M 10M

VSUPPLY = ±10V

VSUPPLY = ±15V

+15V/+10V

-V

IN 1

IN 2

IN 8/IN 16

OUT

10 14

MΩpF

50Ω

VVA

+4V GND

-15V/-10V

A-ISUPPLY

+ISUPPLY

±10V/±5V

THRU

IN 7/IN 15

HI-506A†

†Similar connection for HI-507A/HI-508A/HI-509A

10V/

900

700

500

300 3

ACCESS TIME (ns)

LOGIC LEVEL (HIGH) (V)

579 151311

800

600

400

468101214

REF = OPEN FOR LOGIC HIGH LEVEL ≤ 6V

VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V ±10V

+15V

-V

IN 1

IN 2 THRU

IN 16

OUT

10 50

kΩpF

50Ω

+4V GND

-15V

10V

IN 7/IN 15

HI-506A†

†Similar connection for HI-507A/HI-580A/HI-509A

PROBE

VREF

1/2 VAH

VAH = 4.0V

90%

+10V

OUTPUT

-10V

ADDRESS

DRIVE (VA)

200ns/DIV.

VA INPUT

2V/DIV.

OUTPUT A

5V/DIV.

HI-506A, HI-507A, HI-508A, HI-509A

11-80

FIGURE 8A.

FIGURE 8B.

FIGURE 8C.

FIGURE 8. BREAK-BEFORE-MAKE DELAY

IN 1

IN 2 THRU

IN 8/IN 16

OUT

50pF

1kΩ

VOUT

50Ω

+4.0V

GND

IN 7/IN 15

HI-506A†

†Similar connection for HI-507A/HI-508A/HI-509A

+5V

50% 50%

VAH = 4.0V

OUTPUT

ADDRESS

DRIVE (VA)

tOPEN

1 ON 16 ON

VA INPUT

2V/DIV.

OUTPUT

0.5V/DIV.

100ns/DIV.

FIGURE 9A.

FIGURE 9B.

FIGURE 9C.

FIGURE 9. ENABLE DELAY tON(EN), tOFF(EN)

IN 1

IN 2 THRU

IN 8 /IN 16

OUT

50pF

-VAGND 1kΩ

+10V

IN 7/IN 15

HI-506A†

†Similar connection for HI-507A//HI-508A/HI-509A

50Ω

VAH = 4.0V

OUTPUT

tOFF(EN)

tON(EN)

90%

50%

90%

IN 1 THRU

IN 16 OFF

OUTPUT

2V/DIV.

1 ON

100ns/DIV.

HI-506A, HI-507A, HI-508A, HI-509A

11-81

Truth Tables

HI-506A

A3A2A1A0EN “ON” CHANNEL

XXXXL None

LLLLH 1

LLLHH 2

LLHLH 3

LLHHH 4

LHLLH 5

LHLHH 6

LHHLH 7

LHHHH 8

HLLLH 9

HLLHH 10

HLHLH 11

HLHHH 12

HHLLH 13

HHLHH 14

HHHLH 15

HHHHH 16

HI-507A

A2A1A0EN “ON” CHANNEL

PAIR

X X X L None

LLLH 1

LLHH 2

LHLH 3

LHHH 4

HLLH 5

HLHH 6

HHLH 7

HHHH 8

HI-508A

A2A1A0EN “ON” CHANNEL

X X X L None

LLLH 1

LLHH 2

LHLH 3

LHHH 4

HLLH 5

HLHH 6

HHLH 7

HHHH 8

HI-509A

A1A0EN “ON” CHANNEL

PAIR

X X L None

LLH 1

LHH 2

HLH 3

HHH 4

HI-506A, HI-507A, HI-508A, HI-509A

11-82

Die Characteristics

DIE DIMENSIONS:

159 mils x 83.9 mils x 19 mils

METALLIZATION:

Type: CuAl

Thickness: 16kÅ±2kÅ

SUBSTRATE POTENTIAL (NOTE):

-VSUPPLY

PASSIVATION:

Silox: 12kÅ±2kÅ

Nitride: 3.5kÅ±1kÅ

WORST CASE CURRENT DENSITY:

1.4 x 105 A/cm2

TRANSISTOR COUNT:

485

PROCESS:

CMOS-DI

NO TE: The substrate appears resistive to the -VSUPPLY terminal, therefore it ma y be left ﬂoating (Insulating Die Mount) or it may be mounted

on a conductor at -VSUPPLY potential.

Metallization Mask Layouts

HI-506A HI-507A

IN 9

IN 10

IN 11

IN 12

IN 13

IN 14

IN 15

IN 16

V- (27) +V (1) NC (2)

IN 1

IN 2

IN 3

IN 4

IN 5

IN 6

IN 7

IN 8

EN A0A1A2VREF GND

(18) (17) (16) (15) (13) (12)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26) (4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

OUT (28)

(14)

IN 1B

IN 2B

IN 3B

IN 4B

IN 5B

IN 6B

IN 7B

IN 8B

V- (27) +V (1) OUT B(2)

IN 1A

IN 2A

IN 3A

IN 4A

IN 5A

IN 6A

IN 7A

IN 8A

EN A0A1A2NC VREF GND

(18) (17) (16) (15) (14) (13) (12)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26) (4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

OUT A (28)

HI-506A, HI-507A, HI-508A, HI-509A

11-83

Die Characteristics

DIE DIMENSIONS:

108 mils x 83 mils

METALLIZATION:

Type: CuAl

Thickness: 16kÅ±2kÅ

SUBSTRATE POTENTIAL (NOTE):

-VSUPPLY

PASSIVATION:

Silox: 12kÅ±2kÅ

Nitride: 3.5kÅ±1kÅ

WORST CASE CURRENT DENSITY:

1.4 x 105 A/cm2

TRANSISTOR COUNT:

253

PROCESS:

CMOS-DI

NO TE: The substrate appears resistive to the -VSUPPLY terminal, therefore it ma y be left ﬂoating (Insulating Die Mount) or it may be mounted

on a conductor at -VSUPPLY potential.

Metallization Mask Layouts

HI-508A HI-509A

IN 6 IN 7 IN 8 OUT IN 4 IN 3

IN 1

IN 2

-V

A2EN

IN 5

GND

(11) (10) (9) (8) (7) (6)

(12)

(13)

(14)

(5)

(4)

(3)

(15) (16) (1) (2)

IN 3B IN 4BOUT B OUT A IN 4AIN 3A

IN 1A

IN 2A

-V

GND EN

IN 2B

IN 1B

(11) (10) (9) (8) (7) (6)

(12)

(13)

(14)

(5)

(4)

(3)

(15) (16) (1) (2)

HI-506A, HI-507A, HI-508A, HI-509A