18-Bit Register
fax id: 7031
CY74FCT16823T
CY74FCT162823T
Cypress Semiconductor Corporation • 39 01 North First Street • San Jo se • CA 95134 • 408-943-2600
August 1994 - Revised March 19, 199 7
1CY74FCT162823T
Features
• Low power, pin compatible replacement for ABT
functions
• FCT-E speed at 4.4 ns
• Power-off disable outputs permits live insertion
• Edge-rate con trol circuitry for significantly improved
noise c h aracteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mi l pi tch) and SSOP (25-mil pitch)
packages
• Extended c ommercial r an ge of −40°C to +85°C
•V
CC = 5V ± 10%
CY74FCT16823T Feature s:
• 64 mA sink curre nt, 32 mA source current
• Typical VOLP (grou nd bounce) <1.0V at VCC = 5V,
TA = 25°C
CY74FCT162823T Features:
• Balanced output drivers: 24 mA
• Reduced s ystem switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25°C
Functional Description
The CY74FCT16823T and the CY74FCT162823T 18-bit bu s
interface register are designed for use in high-speed,
low-power systems needing wide registers and parity. 18-bit
operation is achieved by connecting the control lines of the two
9-bit registers. Flow-thro ugh pinout and small shrink packag-
ing aids in simplifying board layout. The outputs are designed
with a power-off disable feature to allow live insertion of
boards.
The CY74FCT16823T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162823T has 24-mA balanced output drivers
with curr ent limiting resistors in the outputs. This re duces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162823T is i deal for driving transmission lines.
Logic Block Diagrams
C
Pin Configuration
D
R
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
1CLR
34
SSOP/TSSOP
Top View
13
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
1CLR
1D1
1OE
1OE
1Q1
1Q2
GND
VCC
GND
FCT16823-1
1CLK
1CLKEN
1Q1
TO 8 OTHER CHANNELS
GND
1D1
1D2
1D3
1D4
1CLK
GND
1D5
1D6
1D7
1D9
VCC
GND
2D1
2D2
2D4
GND
2D5
2D6
2D7
2D8
VCC
2CLK
1CLKEN
25
26
27
28
49
50
51
52
53
54
55
56
1D8
2D3
2D9
2CLKEN
C
D
R
2CLR
2D2
2OE
2CLK
2CLKEN
2Q1
TO 8 OTHER CHANNELS
1Q3
1Q4
1Q5
1Q7
1Q8
1Q9
1Q6
14
2Q1
2Q2
2Q3
2Q4
2Q6
2Q7
2Q8
2Q5
2Q9
GND
VCC
GND
2OE
2CLR
FCT16823-2 FCT16823-3
CY74FCT16823T
CY74FCT162823T
2
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature .....................................−55°C to +125°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
DC Input Voltage.................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 t o +120 mA
Power Dissipation. ..... ............ ..... ............ ..... ............ ..... .1.0W
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-8 83, Method 3015)
Notes:
1. H = HIGH Voltage Level.
L = LOW Voltage Level.
X = Don’t Care.
Z = HIGH Impedance.
=LOW-to-HIGH transition.
2. Output level before indicated steady-state input conditions were established.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage lev el, preferably either VCC or ground.
Pin Description
Name Description
DData Inputs
CLK Clock Inputs
CLKEN Clock E nable Inputs (Active LOW)
CLR Asynchronous Clear Inputs (Acti ve LOW)
OE Output Enable Inputs (Active LOW)
QThree-State Outputs
Function Table[1]
Inputs Outputs
OE CLR CLKEN CLK D Q Function
H X X X X Z High Z
L L X X X L Clear
L H H X X Q[2] Hold
H H L L Z Load
H H L H Z
L H L L L
L H L H H
Operating Range
Range Ambient
Temperature VCC
Commercial −40°C to +85°C 5V ± 10%
CY74FCT16823T
CY74FCT162823T
3
Electrical Characteristics Over the Operating Rang e
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
VHInput Hysteresis[6] 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V
IIH Inpu t HIGH Current VCC=Max., VI=VCC ±1µA
IIL Input LOW Current VCC=Max., VI=GND ±1µA
IOZH High Impedance Output Current
(Three-State Output pins) VCC=Max., VOUT=2.7V ±1µA
IOZL High Impedance Output Current
(Three-State Output pins) VCC=Max., VOUT=0.5V ±1µA
IOS Short Circuit Curre nt[7] VCC=Max., VOUT=GND −80 −140 −200 mA
IOOutput Drive Current[7] VCC=Max., VOUT=2.5V −50 −180 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[8] 1µA
Output Drive Characteristics for CY74 FCT16823T
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VOH Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V
VCC=Min., IOH=−15 mA 2.4 3.5
VCC=Min., IOH=−32 mA 2.0 3.0
VOL Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V
Output Drive Characteristics for CY74 FCT162823T
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
IODL Output LOW Voltage[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
IODH Output HIGH Voltage[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA
VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V
VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V
Capacitance[9] (TA = +25°C, f = 1.0 MHz)
Parameter Description Test Conditions Typ.[5] Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6.0 pF
COUT Out put Capacitance VOUT = 0V 5.5 8.0 pF
Notes:
5. Typical v alues are at VCC= 5.0V, TA= +25°C ambient.
6. This input is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed tes t apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational val ues. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any se quence of parameter
tests, IOS tests should be performed last.
8. Tested at +25°C.
9. This parameter is guaranteed but not tested.
CY74FCT16823T
CY74FCT162823T
4
Power Supply Characteristics
Parameter Description Test Conditions[10] Min. Typ.[5] Max. Unit
ICC Quiescent P ower Supply
Current VCC=Max. VIN<0.2V
VIN>VCC−0.2V — 5 500 µA
∆ICC Quiescent P ower Supply
Current (TTL input s HIGH) VCC=Max. VIN=3.4V[11] —0.5 1.5 mA
ICCD Dynami c Power Supply
Current[12] VCC=Max.,
One Input Toggling,
50% Duty Cycle,
Outputs Open,
OE=CLKEN=GND
VIN=VCC or
VIN=GND —75 120 µA/
MHz
ICTotal Power Supply Current[13] VCC=Max.,
f0=10 MHz,
50% Duty Cycle,
Outputs Open,
One Bit Toggling,
OE=CLKEN=GND
at f1=5 MHz
VIN=VCC or
VIN=GND —0.8 1.7 mA
VIN=3.4V or
VIN=GND —1.3 3.2
VCC=Max.,
at f1=2.5 MHz,
50% Duty Cycle,
Outputs Open,
Eighteen Bits Toggling,
OE=CLKEN=GND
f0=10 MHz
VIN=VCC or
VIN=GND —4.2 7.1[14]
VIN=3.4V or
VIN=GND —9.2 22.1[14]
Notes:
10. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
12. This parameter is not directly testable, but is derived for use in Total Power Suppl y calculatio ns.
13. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current fo r a TTL HIGH input (VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are i n milliamps and all frequencies are in megahertz.
14. Values for these conditions are examples of the ICC formula. These limits are guara nteed but not tested.
CY74FCT16823T
CY74FCT162823T
5
Switching Characteristics Over the Operating Range[15]
CY74FCT16823AT
CY74FCT162823AT CY74FCT16823BT
CY74FCT162823BT
Parameter Description Condition[16] Min. Max. Min. Max. Unit Fig.No.[16]
tPLH
tPHL Pro pagation Del a y
CLK to Q CL=50 pF
RL=500Ω1.5 10.0 1.5 7.5 ns 1, 5
CL=300 pF[17]
RL=500Ω1.5 20.0 1.5 15.0
tPHL Pr opagation Delay
CLR to Q CL=50 pF
RL=500Ω1.5 14.0 1.5 9.0 ns 1, 5
tPZH
tPZL Output Enable Tim e
OE to Q CL=50 pF
RL=500Ω1.5 12.0 1.5 8.0 ns 1, 7, 8
CL=300 pF[17]
RL=500Ω1.5 23.0 1.5 15.0
tPHZ
tPLZ Output Disable Time
OE to Q CL=5 pF[17]
RL=500Ω1.5 7.0 1.5 6.5 ns 1, 7, 8
CL=50 pF
RL=500Ω1.5 8.0 1.5 7.5
tSU Set-U p Time
HIGH or LOW, D to CLK CL=50 pF
RL=500Ω3.0 — 3.0 — ns 4
tHHold Time
HIGH or LOW, D to CLK 1.5 — 1.5 — ns 4
tSU Set-U p Time
HIGH or LOW, CLKEN to CLK 3.0 — 3.0 — ns 9
tHHold Time HIGH or LOW
CLKEN to CLK 0.0 — 0.0 — ns 9
tWCLK Pulse Width
HIGH or LOW 6.0 — 6.0 — ns 5
tWCLR Pulse Width LOW 6.0 — 6.0 — ns 5
tREM Recovery Time
CLR to CLK 6.0 — 6.0 — ns 6
tSK(O) Output Skew[18] —0.5 — 0.5 ns —
Switching Characteristics Over the Operating Range[15]
CY74FCT16823CT
CY74FCT162823CT CY74FCT16823ET
CY74FCT162823ET
Parameter Description Condition[16] Min. Max. Min. Max. Unit Fig.No.[16]
tPLH
tPHL Propagation Delay
CLK to Q CL=50 pF
RL=500Ω1.5 6.0 1.5 4.4 ns 1, 5
CL=3 00 pF [17]
RL=500Ω1.5 12.5 1.5 8.0
tPHL Pro pagation Delay
CLR to Q CL=50 pF
RL=500Ω1.5 6.1 1.5 4.4 ns 1, 5
tPZH
tPZL Outp ut Enable Time
OE to Q CL=5 0 pF
RL=500Ω1.5 5.5 1.5 4.4 ns 1, 7, 8
CL=3 00 pF [17]
RL=500Ω1.5 12.5 1.5 9.0
tPHZ
tPLZ Output Disable Time
OE to Q CL=5 pF[17]
RL=500Ω1.5 5.2 1.5 3.6 ns 1, 7, 8
CL=5 0 pF
RL=500Ω1.5 6.5 1.5 3.6
CY74FCT16823T
CY74FCT162823T
6
Document #: 38- 00385-B
tSU Set-Up Time
HIGH or LOW, D to C LK CL=5 0 pF
RL=500Ω2.0 — 1.5 — ns 4
tHHold Time
HIGH or LOW, D to C LK 1.5 — 0.0 — ns 4
tSU Set-Up Time
HIGH or LOW, CLKEN to CLK 3.0 — 2.5 — ns 9
tHHol d Tim e HIGH or LOW
CLKEN to CLK 0.0 — 0.0 — ns 9
tWCLK Pulse Width
HIGH or LOW 3.3 — 3.3 — ns 5
tWCLR Pulse Width LO W 3.3 — 3.0 — ns 5
tREM Recovery Time
CLR to CLK 6.0 — 3.0 — ns 6
tSK(O) Output Skew[18] —0.5 — 0.5 ns —
Notes:
15. Minimum limits are guaranteed but not tested on Propagation Delays.
16. See “Parameter Measurement Information” in the General Information section.
17. These limits are guaranteed but not tested.
18. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
Switching Characteristics Over the Operating Range[15] (conti nued)
CY74FCT16823CT
CY74FCT162823CT CY74FCT16823ET
CY74FCT162823ET
Parameter Description Condition[16] Min. Max. Min. Max. Unit Fig.No.[16]
Ordering Inform ation CY74FCT16823
Speed
(ns) Order ing Code Package
Name Package Type Operating
Range
4.4 CY74FCT16823ETPAC Z56 56-Lead (2 40-Mil) TSSOP Commercial
CY74FCT16823ETPVC O56 56-Lead (300-Mil) SSOP
6.0 CY74FCT16823CTPAC Z56 56-Lead (2 40-Mil) TSSOP Commercial
CY74FCT16823CTPVC O56 56-Lead (300-Mil) SSOP
7.5 CY74FCT16823BTPAC Z56 56-Lead (240-Mil) TSSOP Commercial
CY74FCT16823BTPVC O56 56-Lead (300-Mil) SSOP
10.0 CY74FCT16823ATPAC Z56 56-Lead (240- Mil) TSSOP Commercial
CY74FCT16823ATPVC O56 56-Lead (300-Mil) SSOP
Ordering Inform ation CY74FCT162823
Speed
(ns) Order ing Code Package
Name Package Type Operating
Range
4.4 CY74FCT162823ETPAC Z56 56-Lead ( 240-Mil) TSSOP Commercial
CY74FCT162823ETPVC O56 56-Lead (300-Mil) SSOP
6.0 CY74FCT162823CTPAC Z56 56-Lead ( 240-Mil) TSSOP Commercial
CY74FCT162823CTPVC O56 56-Lead (300-Mil) SSOP
7.5 CY74FCT162823BTPAC Z56 56-Lead (240-Mil) TSSOP Commercial
CY74FCT162823BTPVC O56 56-Lead (300-Mil) SSOP
10.0 CY74FCT162823ATPAC Z56 56-Lead (240-Mil) TSSOP Commercial
CY74FCT162823ATPVC O56 56-Lead (300-Mil) SSOP
CY74FCT16823T
CY74FCT162823T
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cypress Semi conductor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may rea sonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
