Altera Corporation 6–49
June 2006 Stratix GX Device Handbook, Volume 1
DC & Switching Characteristics
3.3-V LVTTL 4 mA 1,993 2,097 2,411 ps
8 mA 1,773 1,866 2,145 ps
12 mA 1,553 1,635 1,879 ps
16 mA 1,493 1,572 1,807 ps
24 mA 1,423 1,498 1,722 ps
2.5-V LVTTL 2 mA 2,631 2,768 3,182 ps
8 mA 2,051 2,159 2,482 ps
12 mA 1,941 2,043 2,349 ps
16 mA 1,901 2,001 2,300 ps
1.8-V LVTTL 2 mA 4,632 4,873 5,604 ps
8 mA 3,542 3,728 4,287 ps
12 mA 3,472 3,655 4,203 ps
1.5-V LVTTL 2 mA 6,620 6,964 8,008 ps
4 mA 6,040 6,355 7,307 ps
8 mA 5,570 5,862 6,740 ps
GTL 1,191 1,255 1,442 ps
GTL+ 1,231 1,297 1,90 ps
3.3-V PCI 1,111 1,171 1,346 ps
3.3-V PCI-X 1.0 1,111 1,171 1,346 ps
Compact PCI 1,111 1,171 1,346 ps
AGP 1×1,311 1,381 1,587 ps
AGP 2×1,311 1,381 1,587 ps
CTT 1,391 1,465 1,684 ps
SSTL-3 class I 1,431 1,507 1,732 ps
SSTL-3 class II 1,291 1,360 1,563 ps
SSTL-2 class I 1,912 2,013 2,314 ps
SSTL-2 class II 1,832 1,929 2,218 ps
SSTL-18 class I 3,097 3,260 3,748 ps
SSTL-18 class II 2,867 3,018 3,470 ps
1.5-V HSTL class I 4,916 5,174 5,950 ps
1.5-V HSTL class II 4,726 4,975 5,721 ps
1.8-V HSTL class I 3,247 3,417 3,929 ps
1.8-V HSTL class II 3,257 3,428 3,941 ps
Table 6–76. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2)
I/O Standard
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Max Min Max Min Max