ESURGENT Data Sheet S E M I C O N D U C T O R CLC1020 General Description FEATURES n 127A supply current n 2.1MHz gain bandwidth n Input voltage range with 5V supply: -0.4V to 4.3V n Output voltage range with 5V supply: 0.01V to 4.99V n 2.7V/s slew rate n 0.7pA bias current n 0.1mV input offset voltage n No crossover distortion n Fully specified at 2.7V and 5V supplies n Pb-free TSOT-5 The COMLINEAR CLC1020 is a single channel, high-performance, voltage feedback amplifier. The CLC1020 provides 2.1MHz gain bandwidth product and 2.7V/s slew rate making it well suited for high-performance battery powered-systems. This COMLINEAR high-performance amplifier also offers low input offset voltage and low bias current. The COMLINEAR CLC1020 consumes only 127A supply current and is designed to operate from a supply range of 2.7V to 5.5V (1.35 to 2.75). The input voltage range extends 400mV below the negative rail and 700mV below the positive rail. The CLC1020 amplifier operates over the extended temperature range of -40C to +125C. The CLC1020 is packaged in the space saving TSOT-5 package. The TSOT-5 package is pin compatible with the SOT23-5 package. APPLICATIONS n Portable/battery-powered applications n Mobile communications, cell phones, pagers n ADC buffer n Active filters n Portable test instruments n Medical Equipment n Portable medical instrumentation Typical Performance Examples Vout vs. Vcm Slew Rate vs. Supply Voltage 1B.R Vin = 1Vpp Ordering Information Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CLC1020IST5X TSOT-5 Yes Yes -40C to +85C Reel Moisture sensitivity level for all parts is MSL-1. (c) 2018 Resurgent Semiconductor, LLC 1 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier General Purpose, Rail to Rail Output Amplifier Rail to Rail Amplifiers Rev 1B.R Data Sheet CLC1020 Pin Assignments CLC1020 Pin Configuration +IN -IN 2 3 +VS + - 4 OUT Pin Name Description 1 +IN Output 2 -VS Negative supply 3 -IN Positive input 4 OUT Negative input 5 +VS Positive supply CLC1020 General Purpose, Rail to Rail Output Amplifier -V S 5 1 Pin No. 1B.R (c) 2018 Resurgent Semiconductor, LLC 2 / 15 Rev 1B.R Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Min Supply Voltage Input Voltage Range Continuous Output Current Max CLC1020 General Purpose, Rail to Rail Output Amplifier Parameter Unit 7 V -VS-0.4V +VS V Output is protected against momentary short circuit Reliability Information Parameter Min Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 5-Lead TSOT Typ -65 Max Unit 150 150 260 C C C 215 C/W Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air. ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) TSOT-5 2kV 2kV Recommended Operating Conditions Parameter Min Operating Temperature Range Supply Voltage Range -40 2.7 Typ Max Unit +85 5.5 C V 1B.R (c) 2018 Resurgent Semiconductor, LLC 3 / 15 Rev 1B.R Data Sheet Electrical Characteristics at +2.7V TA = 25C, Vs = +2.7V, Rf = 10k, RL=10k to VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response Gain Bandwidth Product VOUT=0.2Vpp, CL = 200 pF, RL = 10k, G=11 2 MHz UGBW Unity Gain Bandwidth BWSS -3dB Bandwidth VOUT = 0.2Vpp , RL = 10k, G=1 1.6 MHz VOUT = 0.2Vpp, RL = 10k, G=2 836 BWLS kHz Large Signal Bandwidth VOUT = 2Vpp, RL = 10k, G=2 540 kHz Gm Gain Margin G=1 22 dB m Phase Margin G=1 82 Time Domain Response tR , tS Rise and Fall Time VOUT = 2V step, RL = 10k 840 ns tS Settling Time to 0.1% VOUT =2Vpp, RL = 10k 1.6 s OS Overshoot VOUT=2Vpp, RL = 10k 5.5 % SR Slew Rate VOUT=2Vpp, RL = 10k 2.3 V/s -61 dBc -70 dBc Distortion/Noise Response HD2 2nd Harmonic Distortion 2Vpp, 10kHz, RL = 10k HD3 3rd Harmonic Distortion 2Vpp, 10kHz, RL = 10k THD Total Harmonic Distortion 2Vpp, 10kHz, G=1, RL = 10k en Input Voltage Noise 0.094 % f=100Hz 54 nV/Hz f=1kHz 30 nV/Hz f=10kHz 17 nV/Hz DC Performance VIO Input Offset Voltage 0.53 mV dVIO Average Drift 2.1 V/C Ib Input Bias Current 0.5 pA Ios Input Offset Current 0.1 pA PSRR Power Supply Rejection Ratio IS Supply Current DC 73 dB 111 A Input Characteristics Input Resistance Non-inverting Input 29 G CIN Input Capacitance Non-inverting 2.4 pF CMIR Common Mode Input Range For VCM50dB -0.4 to 2.0 V CMRR Common Mode Rejection Ratio DC , Vcm=0V to 1.7V 70.5 dB RL = 2k 0.02 to 2.63 V RL = 10k 0.01 to 2.68 V Sourcing, VOUT = 0V, G=1 18 mA Sinking, VOUT = 2.7V, G=1 58 mA 1B.R RIN Output Characteristics VOUT ISC Output Voltage Swing Short-Circuit Output Current Notes: 1. 100% tested at 25C (c) 2018 Resurgent Semiconductor, LLC 4 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier GBWP Rev 1B.R Data Sheet Electrical Characteristics at +5V TA = 25C, Vs = +5V, Rf = 10k, RL=10k to VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response Gain Bandwidth Product VOUT=0.2Vpp, CL = 200pF, RL = 10k, G=11 2.1 MHz UGBW Unity Gain Bandwidth BWSS -3dB Bandwidth VOUT = 0.2Vpp , RL = 10k, G=1 1.8 MHz VOUT = 0.2Vpp, RL = 10k, G=2 907 BWLS kHz Large Signal Bandwidth VOUT = 2Vpp, RL = 10k, G=2 576 Hz Gm Gain Margin G=1 18 dB m Phase Margin G=1 90 Time Domain Response tR , tS Rise and Fall Time VOUT =2V step, RL = 10k 670 ns tS Settling Time to 0.1% VOUT =2Vpp, RL = 10k 1.6 s OS Overshoot VOUT=2Vpp, RL = 10k 5.9 % SR Slew Rate VOUT=4Vpp, RL = 10k 2.7 V/s -67 dBc dBc Distortion/Noise Response HD2 2nd Harmonic Distortion VOUT=2Vpp, 10kHz, RL = 10k HD3 3rd Harmonic Distortion VOUT=2Vpp, 10kHz, RL = 10k -68 THD Total Harmonic Distortion VOUT=2Vpp, 10kHz, RL = 10k 0.057 % en Input Voltage Noise f=100Hz 57 nV/Hz f=1kHz 30 nV/Hz f=100kHz 18 nV/Hz DC Performance VIO Input Offset Voltage(1) 0.1 dVIO Average Drift 1.1 Ib Input Bias Current (1) Ios Input Offset Current 0.1 pA PSRR Power Supply Rejection Ratio (1) DC 60 73 dB AOL Open-Loop Gain (1) VOUT = VS / 2 70 122 dB IS Supply Current per channel 0.7 (1) (1) 127 6 mV V/C 250 170 pA A Input Characteristics Input Resistance Non-inverting Input 40 G CIN Input Capacitance Non-inverting Input 2.2 pF CMIR Common Mode Input Range For VCM50dB CMRR Common Mode Rejection Ratio (1) DC , Vcm= 0V to 4V 4.2 1B.R RIN -0.3 -0.4 to 4.3 V 60 67 RL = 2k 4.93 4.96 to 0.02 0.04 V RL = 10k (1) 4.97 4.99 to 0.01 0.02 V Sourcing, VOUT = 0V, G=1 30 69 mA Sinking, VOUT = 5V, G=1 80 150 mA dB Output Characteristics VOUT ISC Output Voltage Swing Short-Circuit Output Current Notes: 1. 100% tested at 25C (c) 2018 Resurgent Semiconductor, LLC 5 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier GBWP Rev 1B.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, VS = +5V, Rf = Rg =10k, RL = 10k to VS/2, G = 2; unless otherwise noted. Non-Inverting Freq. Resp. +5V Non-Inverting Freq. Resp. +2.7V Inverting Freq. Resp. +2.7V Non-Inverting Non-Inverting Non-Inverting Small Small Small Signal Signal Signal Pulse Pulse Pulse Response Response Response Inverting Freq. Resp. +5V Freq. Resp. vs. CL RL=1k +5V Freq. Resp. vs. CL RL=1k +2.7V 1B.R (c) 2018 Resurgent Semiconductor, LLC 6 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier Rev 1B.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, VS = +5V, Rf = Rg =10k, RL = 10k to VS/2, G = 2; unless otherwise noted. Freq. Resp. vs. CL RL=1M +5V Freq. Resp. vs. RL +5V Freq. Small Resp. Signal vs. RL Pulse +2.7V Non-Inverting Non-Inverting Non-Inverting Small Small Signal Signal Pulse Pulse Response Response Response Large Signal Freq. Resp. +5V Large Signal Freq. Resp. +2.7V 1B.R (c) 2018 Resurgent Semiconductor, LLC 7 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier Freq. Resp. vs. CL RL=1M +2.7V Rev 1B.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, VS = +5V, Rf = Rg =10k, RL = 10k to VS/2, G = 2; unless otherwise noted. Vin = 1Vpp 1B.R -3db BW vs Output Amplitude +5V -3db BW vs Output Amplitude +2.7V Slew Rate vs. Signal Supply Voltage Non-Inverting Non-Inverting Non-Inverting Small Small Small Signal Signal Pulse Pulse Pulse Response Response Response Open Loop Gain & Phase vs. Temp +5V (c) 2018 Resurgent Semiconductor, LLC 8 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier Open Loop Gain & Phase vs. Freq. +2.7V Open Loop Gain & Phase vs. Freq. +5V Rev 1B.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, VS = +5V, Rf = Rg =10k, RL = 10k to VS/2, G = 2; unless otherwise noted. CMRR vs. Freq. PSRR vs. Freq. THD Freq.Pulse Non-Inverting Non-Inverting Non-Inverting Small Small Smallvs. Signal Signal Signal Pulse Pulse Response Response Response Input Voltage Noise vs. Freq. Output Impedance vs. Freq. Large Signal Pulse Response 1B.R ) s/div) (c) 2018 Resurgent Semiconductor, LLC 9 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier Rev 1B.R Data Sheet Typical Performance Characteristics - Continued TA = 25C, VS = +5V, Rf = Rg =10k, RL = 10k to VS/2, G = 2; unless otherwise noted. VIO vs. CMR +5V VIO vs. CMR 2.7V VIO vs. Supply Voltage vs.Signal VCM +5V Non-Inverting Non-Inverting Non-InvertingVSmall Small Small Signal Signal Pulse Pulse Pulse Response Response Response OUT 1B.R Output Swing vs. Supply Voltage Input Current vs. Temperature (c) 2018 Resurgent Semiconductor, LLC 10 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier Rev 1B.R Data Sheet Application Information +Vs General Description +Vs Input 0.1uF + CLC1020 General Purpose, Rail to Rail Output Amplifier The CLC1020 is a single supply, general purpose, voltagefeedback amplifier fabricated on a CMOS process. The CLC1020 offers 2.1MHz gain bandwidth product, 2.7V/s slew rate, and only 127A supply current. It features a rail to rail output stage and is unity gain stable. The common mode input range extends to 400mV below ground and to 700mV below Vs. Exceeding these values will not cause phase reversal. However, if the input voltage exceeds the rails by more than 0.5V, the input ESD devices will begin to conduct. The output will stay at the rail during this overdrive condition. The output stage is short circuit protected and offers "soft" saturation protection that improves recovery time. Figures 1, 2, and 3 illustrate typical circuit configurations for noninverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. Figure 4 shows the typical non-inverting gain circuit for single supply applications 6.8uF Output - RL 0.1uF 6.8uF -Vs G=1 Figure 3. Unity Gain Circuit +Vs 6.8F + In + - 6.8F 0.1F Out Rf Rg Input 0.1F + Output 0.1F RL Rf 6.8F Power Dissipation G = 1 + (Rf/Rg) -Vs Figure 1. Typical Non-Inverting Gain Circuit +Vs R1 Input Rg 6.8F 0.1F + Output 0.1F 6.8F -Vs RL Rf Power dissipation should not be a factor when operating under the stated 2k load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond its intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction temperature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation. TJunction = TAmbient + (JA x PD) G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg Figure 2. Typical Inverting Gain Circuit (c) 2018 Resurgent Semiconductor, LLC Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by 11 / 15 Rev 1B.R 1B.R Rg Figure 4. Single Supply Non-Inverting Gain Circuit Data Sheet the supplies. PD = Psupply - Pload Input + Supply power is calculated by the standard power equation. - Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Rloadeff in Figure 3 would be calculated as: RL || (Rf + Rg) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSUPPLY. Load power can be calculated as above with the desired signal amplitudes using: Rg Figure 5. Addition of RS for Driving Capacitive Loads For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLC1020 and will typically recover in less than 5us from an overdrive condition. Figure 6 shows the CLC1020 in an overdriven condition. 3 (VLOAD)RMS = VPEAK / 2 2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff 1 VS = +/-2.5V RL = 10k AV+2_+25C Amplitude (V) Output Signal PDYNAMIC = (VS+ - VLOAD)RMS x ( ILOAD)RMS Input Signal 0 1B.R The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: RL -1 -2 Assuming the load is referenced in the middle of the power rails or Vsupply/2. -3 0 20 40 60 80 100 Time (s) The CLC1020 is short circuit protected. However, this may not guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. Figure 6. Overdrive Recovery Layout Considerations Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 5. (c) 2018 Resurgent Semiconductor, LLC General layout and supply bypassing play major roles in high frequency performance. Resurgent Semiconductor has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: 12 / 15 CLC1020 General Purpose, Rail to Rail Output Amplifier Power delivered to a purely resistive load is: Output CL Rf Psupply = Vsupply x IRMS supply Vsupply = VS+ - VS- Rs Rev 1B.R Data Sheet Include 6.8F and 0.1F ceramic capacitors for power supply decoupling Place the 6.8F capacitor within 0.75 inches of the power CLC1020 General Purpose, Rail to Rail Output Amplifier pin Place the 0.1F capacitor within 0.1 inches of the power pin Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Minimize all trace lengths to reduce series inductances Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # CEB004 Figure 8. CEB004 Top View Products CLC1020 in TSOT Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 7-11. These evaluation boards are built for dual supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. +Vs 1B.R 2. Use C3 (6.8F) and C4 (0.1F), if the -VS pin of the amplifier is not directly connected to the ground plane. 6.8uF Figure 9. CEB004 Bottom View Input Rin 5 1 + 0.1uF Output 4 3 2 Rg Rout RL 0.1uF Rf 6.8uF -Vs Figure 7. CEB004 Schematic (c) 2018 Resurgent Semiconductor, LLC 13 / 15 Rev 1B.R Data Sheet Mechanical Dimensions TSOT-5 Package 2.80 4 0.215 0.265 R0. 150 1.50 1.70 2.60 3.00 (RE F) 3 0.30 0.50 DETAIL "A " 0.03 0.20 0.84 0.90 0.30 0.50 0.45 GAUGE PLANE 0.25 BSC 0 ~ 8 1 CLC1020 General Purpose, Rail to Rail Output Amplifier 5 1.00MAX 0.95BSC 0.00 0.10 SEE DETAIL "A " NOTES: 1.ALL DIMENSIONS ARE IN MILLIMETERS. 2.PACKAGE LENGTH DOES NOT INCLUDE INTERLEAD FALSH OR PROTRUSION 3.PACKAGE WIDTH DOES NOTINCLUDE INTERLEAD FALSH OR PROTRUSION. 4.LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5.DRAWING CONFROMS TO JEDEC MO-193, VARIATION AA. 6.DRAWING IS NOT TO SCALE. 1B.R (c) 2018 Resurgent Semiconductor, LLC 14 / 15 Rev 1B.R Data Sheet Revision History Revision July 2018 Description Updated to Resurgent Semiconductor. CLC1020 General Purpose, Rail to Rail Output Amplifier 1B.R Date 1B.R For Further Assistance: ESURGENT S E M I C O N D U C T O R www.resurgentsemi.net NOTICE Resurgent Semiconductor reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. Resurgent Semiconductor assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. Resurgent Semiconductor does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Resurgent Semiconductor receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of Resurgent Semiconductor is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of Resurgent Semiconductor is prohibited. (c) 2018 Resurgent Semiconductor, LLC 15 / 15 Rev 1B.R