TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
CMOS/EEPROM/EPROM Technologies on a
Single Device
– Mask-ROM Devices for High-Volume
Production
– One-Time-Programmable (OTP) EPROM
Devices for Low-Volume Production
– Reprogrammable EPROM Devices for
Prototyping Purposes
D
Internal System Memory Configurations
– On-Chip Program Memory Versions
– ROM: 4K to 48K Bytes
– EPROM: 16K to 48K Bytes
– ROM-less
– Data EEPROM: 256 or 512 Bytes
– Static RAM: 256 to 3.5K Bytes
– External Memory/Peripheral Wait States
– Precoded External Chip-Select Outputs
in Microcomputer Mode
D
Flexible Operating Features
– Low-Power Modes: STANDBY and HALT
– Commercial, Industrial, and Automotive
Temperature Ranges
– Clock Options
– Divide-by-4 (0.5 MHz – 5 MHz SYSCLK)
– Divide-by-1 (2 MHz – 5 MHz SYSCLK)
Phase-Locked Loop (PLL)
– Supply Voltage (VCC): 5 V ± 10%
D
Eight-Channel 8-Bit Analog-to-Digital
Converter 1 (ADC1)
D
Two 16-Bit General-Purpose Timers
D
On-Chip 24-Bit Watchdog Timer
D
Two Communication Modules
– Serial Communications Interface 1 (SCI1)
– Serial Peripheral Interface (SPI)
D
Flexible Interrupt Handling
D
TMS370 Series Compatibility
D
CMOS/Package/TTL-Compatible I/O Pins
– 64-Pin Plastic and Ceramic Shrink
Dual-In-Line Packages/44 Bidirectional,
9 Input Pins
– 68-Pin Plastic and Ceramic Leaded Chip
Carrier Packages/46 Bidirectional,
9 Input Pins
– All Peripheral Function Pins Are
Software Configurable for Digital I/O
D
Workstation/PC-Based Development
System
– C Compiler and C Source Debugger
– Real-Time In-Circuit Emulation
– Extensive Breakpoint/Trace Capability
– Software Performance Analysis
– Multi-Window User Interface
– Microcontroller Programmer
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FN/FZ PACKAGE
(TOP VIEW)
VSS1
B7
C2
C1
MC
C0
B6
T2AIC1/CR
SCICLK
SCIRXD
SCITXD
XTAL2/CLKIN
XTAL1
C3
C4
C5
C6
C7
SPISOMI
SPICLK
SPISIMO
T1IC/CR
T1PWM
T1EVT
9876543
10
11
12
13
14
15
16
B5
B0
B4
B3
B2
B1
D0/CSE2/OCF
VCC2
VSS2
VCC1
2 1 6867 66 65 6463 62 61
27 28 2930 3132 3334 35 3637 38 39 4041 42 43
VCC3
VSS3
VCC1
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCC2
VSS2
A0
A1
A2
A3
A4
A5
A6
A7
T2AEVT
T2AIC2/PWM
INT1
INT2
INT3
D1/CSH3
D2/CSH2
D3/SYSCLK
D4/R/W
D5/CSPF
D6/CSH1/EDS
D7/CSE1/WAIT
RESET
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
JN/NM PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
B5
B6
B7
C0
MC
C1
C2
VSS1
C3
C4
C5
C6
C7
AN0
A0
A1
A2
A3
A4
A5
A6
A7
T2AEVT
T2AIC2/PWM
T2AIC1/CR
SCICLK
SCIRXD
SCITXD
XTAL2/CLKIN
XTAL1
VCC1
VCC3
B4
B3
B2
B1
B0
D0/CSE2/OCF
VSS1
VCC1
D1/CSH3
D3/SYSCLK
D4/R/W
D6 / CSH1 / EDS
D7/CSE1/WAIT
RESET
INT1
INT2
INT3
SPISOMI
SPISIMO
SPICLK
T1IC/CR
T1PWM
AN7
T1EVT
VSS1
AN6
AN5
AN4
AN3
AN1
AN2
VSS3
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Descriptions
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN
ÁÁ
ÁÁ
†
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
‡
ÁÁÁÁÁ
ÁÁÁÁÁ
NAME
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ALTERNATE
FUNCTION
ÁÁÁ
ÁÁÁ
SDIP
(64)
ÁÁÁ
ÁÁÁ
LCC
(68)
ÁÁ
ÁÁ
I/O
†
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DESCRIPTION
‡
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
A0
A1
A2
A3
A4
A5
A6
A7
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
15
16
17
18
19
20
21
22
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
17
18
19
20
21
22
23
24
ÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Single-chip mode: Port A is a general-purpose bidirectional I/O port.
Expansion mode: Port A can be individually programmed as the external
bidirectional data bus (DATA0–DATA7).
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
B0
B1
B2
B3
B4
B5
B6
B7
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
60
61
62
63
64
1
2
3
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
65
66
67
68
1
2
3
4
ÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Single-chip mode: Port B is a general-purpose bidirectional I/O port.
Expansion mode: Port B can be individually programmed as the low-order address
output bus (ADDR0–ADDR7).
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
C0
C1
C2
C3
C4
C5
C6
C7
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
4
6
7
9
10
11
12
13
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
5
7
8
10
11
12
13
14
ÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Single-chip mode: Port C is a general-purpose bidirectional I/O port.
Expansion mode: Port C can be individually programmed as the high-order address
output bus (ADDR8–ADDR15).
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT1
INT2
INT3
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
NMI
—
—
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
50
49
48
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
52
51
50
ÁÁ
Á
Á
Á
Á
ÁÁ
I
I/O
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
External (nonmaskable or maskable) interrupt/general-purpose input pin
External maskable interrupt input/general-purpose bidirectional pin
External maskable interrupt input/general-purpose bidirectional pin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
E0
E1
E2
E3
E4
E5
E6
E7
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
14
34
35
36
37
38
39
42
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
36
37
38
39
40
41
42
43
ÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ADC1 analog input (AN0–AN7) or positive reference pins (AN1–AN7)
Port E can be individually programmed as general-purpose input pins if not used
as ADC1 analog input or positive reference input.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
VCC3
VSS3
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
32
33
ÁÁÁ
Á
Á
Á
ÁÁÁ
34
35
ÁÁ
Á
Á
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ADC1 positive-supply voltage and optional positive-reference input pin
ADC1 ground reference pin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RESET
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
51
ÁÁÁ
Á
Á
Á
ÁÁÁ
53
ÁÁ
Á
Á
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
System reset bidirectional pin. RESET, as an input, initializes the microcontroller;
as open-drain output, RESET indicates an internal failure was detected by the
watchdog or oscillator fault circuit.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
MC
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
5
ÁÁÁ
Á
Á
Á
ÁÁÁ
6
ÁÁ
Á
Á
ÁÁ
I
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode control (MC) pin. MC enables EEPROM write-protection override (WPO)
mode, also EPROM VPP.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
XTAL2/CLKIN
XTAL1
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
29
30
ÁÁÁ
Á
Á
Á
ÁÁÁ
31
32
ÁÁ
Á
Á
ÁÁ
I
O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Internal oscillator crystal input/external clock source input
Internal oscillator output for crystal
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
31, 57
ÁÁÁ
ÁÁÁ
33,
61
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Positive supply voltage
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
—
ÁÁÁ
ÁÁÁ
15,63
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Positive supply voltage
†I = input, O = output
‡Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Descriptions (Continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN
ÁÁ
ÁÁ
†
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
‡
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
NAME
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ALTERNATE
FUNCTION
ÁÁÁ
Á
Á
Á
ÁÁÁ
SDIP
(64)
ÁÁÁ
Á
Á
Á
ÁÁÁ
LCC
(68)
ÁÁ
ÁÁ
ÁÁ
I/O
†
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DESCRIPTION
‡
ÁÁÁÁÁ
ÁÁÁÁÁ
VSS1
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
8,
58,40
ÁÁÁ
ÁÁÁ
9
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground reference for digital logic
ÁÁÁÁÁ
ÁÁÁÁÁ
VSS2
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
—
ÁÁÁ
ÁÁÁ
16,62
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground reference for digital I/O logic
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
FUNCTION
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Single-chip mode: Port D is a general-purpose bidirectional I/O port. Each of
the port D pins can be individually configured as a general-purpose I/O pin,
p
rimary memory control signal (function A) or secondary memory control
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
A
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
B
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
primary
memory
control
signal
(function
A)
,
or
secondary
memory
control
signal (function B). All chip selects are independent and can be used for
memory bank switching. Refer to Table 1 for function A memory accesses.
ÁÁÁÁÁ
ÁÁÁÁÁ
D0
ÁÁÁ
ÁÁÁ
CSE2
ÁÁÁÁ
ÁÁÁÁ
OCF
ÁÁÁ
ÁÁÁ
59
ÁÁÁ
ÁÁÁ
64
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O pin A: Chip select eighth output 2 goes low during memory accesses
I/O pin B: Opcode fetch goes low during the opcode fetch memory cycle.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
D1
ÁÁÁ
Á
Á
Á
ÁÁÁ
CSH3
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁ
Á
Á
Á
ÁÁÁ
56
ÁÁÁ
Á
Á
Á
ÁÁÁ
60
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O pin A: Chip select half output 3 goes low during memory accesses.
I/O pin B: Reserved
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
D2
ÁÁÁ
Á
Á
Á
ÁÁÁ
CSH2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁ
Á
Á
Á
ÁÁÁ
—
ÁÁÁ
Á
Á
Á
ÁÁÁ
59
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O pin A: Chip select half output 2 goes low during memory accesses.
I/O pin B: Reserved
ÁÁÁÁÁ
D3
ÁÁÁ
SYSCLK
ÁÁÁÁ
SYSCLK
ÁÁÁ
55
ÁÁÁ
58
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O pin A, B: Internal clock signal is 1/1 (PLL) or 1/4 XTAL2/CLKIN frequency .
ÁÁÁÁÁ
ÁÁÁÁÁ
D4
ÁÁÁ
ÁÁÁ
R/W
ÁÁÁÁ
ÁÁÁÁ
R/W
ÁÁÁ
ÁÁÁ
54
ÁÁÁ
ÁÁÁ
57
ÁÁ
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O pin A, B: Read/write output pin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
D5
ÁÁÁ
Á
Á
Á
ÁÁÁ
CSPF
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁ
Á
Á
Á
ÁÁÁ
—
ÁÁÁ
Á
Á
Á
ÁÁÁ
56
ÁÁ
ÁÁ
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I /O pin A: Chip select peripheral output for peripheral file goes low during
memory accesses.
I/O pin B: Reserved
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
D6
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
CSH1
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
EDS
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
53
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
55
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O pin A: Chip select half output 1 goes low during memory accesses.
I/O pin B: External data strobe output goes low during memory accesses from
external memory and has the same timings as the five chip selects.
ÁÁÁÁÁ
ÁÁÁÁÁ
D7
ÁÁÁ
ÁÁÁ
CSE1
ÁÁÁÁ
ÁÁÁÁ
WAIT
ÁÁÁ
ÁÁÁ
52
ÁÁÁ
ÁÁÁ
54
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O pin A: Chip select eighth output goes low during memory accesses.
I/O pin B: Wait input pin extends bus signals.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCITXD
SCIRXD
SCICLK
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
SCIIO1
SCIIO2
SCIIO3
ÁÁÁ
Á
Á
Á
ÁÁÁ
28
27
26
ÁÁÁ
Á
Á
Á
ÁÁÁ
30
29
28
ÁÁ
ÁÁ
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SCI transmit data output pin/general-purpose bidirectional pin (see Note 1)
SCI receive data input pin/general-purpose bidirectional pin
SCI bidirectional serial clock pin/general-purpose bidirectional pin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1IC/CR
T1PWM
T1EVT
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
T1IO1
T1IO2
T1IO3
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
44
43
41
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
46
45
44
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T imer1 input capture/counter reset input pin/general-purpose bidirectional
pin
T imer1 pulse-width-modulation (PWM) output pin/general-purpose
bidirectional pin
T imer1 external event input pin/general-purpose bidirectional pin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AIC1/CR
T2AIC2/PWM
T2AEVT
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
T2AIO1
T2AIO2
T2AIO3
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
25
24
23
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
27
26
25
ÁÁ
ÁÁ
ÁÁ
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Timer2A input capture 1/counter reset input pin/general-purpose bidirectional
pin
T imer2A input capture 2/PWM output pin/general-purpose bidirectional pin
T imer2A external event input pin/general-purpose bidirectional pin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPISOMI
SPISIMO
SPICLK
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
SPIIO1
SPIIO2
SPIIO3
ÁÁÁ
Á
Á
Á
ÁÁÁ
47
46
45
ÁÁÁ
Á
Á
Á
ÁÁÁ
49
48
47
ÁÁ
ÁÁ
ÁÁ
I/O
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SPI slave output pin, master input pin/general-purpose bidirectional pin
SPI slave input pin, master output pin/general-purpose bidirectional pin
SPI bidirectional serial clock pin/general-purpose bidirectional pin
†I = input, O = output
‡Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK.
NOTE 1: The three-pin configuration SCI is referred to as SCI1.
Table 1. Function A: Memory Accesses Locations for ‘x5x Devices
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
FUNCTION A
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
‘X50, ‘X52, ‘X53, AND ‘X56
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
‘X58
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
‘X59
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
CSEx
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
2000h – 3FFFh (8K bytes)
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
A000h – BFFFh (8K bytes)
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
E000h – EFFFh (4K bytes)
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
CSHx
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
8000h – FFFFh (32K bytes)
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
C000h – FFFFh (16K bytes)
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
F000h – FFFFh (4K bytes)
ÁÁÁÁÁÁÁÁÁ
CSPF
ÁÁÁÁÁÁÁÁÁ
10C0h – 10FFh (64 bytes)
ÁÁÁÁÁÁÁÁÁ
10C0h – 10FFh (64 bytes)
ÁÁÁÁÁÁÁÁÁ
10C0h – 10FFh (64 bytes)
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
Program Memory
ROM: 4K, 8K, 12K, 16K,
32K, or 48K Bytes
EPROM: 16K, 32K, or
48K Bytes
VSS1
VCC1
RESET
MCXTAL2/
CLKIN
XTAL1INT3INT2INT1
E0–E7
or
AN0–AN7
VCC2
VSS2
Data EEPROM
0, 256, or 512 Bytes
RAM
256, 512, 1K, 1.5K, or
3.5K Bytes
CPU
Port D†
Port C
Port B
Watchdog
Timer 1
Timer 2A
Serial
Communications
Interface 1
Serial
Peripheral
Interface
Analog-to-Digital
Converter 1
System Control
Clock Options:
Divide-by-4 or
Divide-by-1(PLL)
T1PWM
T1EVT
T1IC/CR
T2AIC2/PWM
T2AEVT
T2AIC1/CR
SCICLK
SCITXD
SCIRXD
SPICLK
SPISIMO
SPISOMI
VSS3
VCC3
Port A
Interrupts
8/6888
Memory Expansion
Data
Address LSbyte
Address MSbyte
Control
†For the 64-pin devices, there are only six pins for port D.
description
The TMS370Cx5x family of single-chip 8-bit microcontrollers provides cost-effective real-time system control
through integration of advanced peripheral function modules and various on-chip memory configurations. The
TMS370Cx5x family presently consists of twenty-one devices which are grouped into seven main sub-families:
the TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and
SE370C75x.
The TMS370Cx5x family of devices is implemented using high-performance silicon-gate CMOS EPROM and
EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of
CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the
TMS370Cx5x devices attractive in system designs for automotive electronics, industrial motor control,
computer peripheral control, telecommunications, and consumer application. Table 2 provides a memory
configuration overview of the TMS370Cx5x devices.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
Table 2. Memory Configurations
DEVICE
PROGRAM
MEMORY
(BYTES)
OFF-CHIP
MEMORY
EXP (BYTES)
DATA MEMORY
(BYTES) OPERATING
MODES PACKAGES
68 PIN PLCC/CLCC, OR
64 PIN PSDIP/CSDIP
ROM EPROM
EXP
.
(BYTES)
RAM EEPROM µC†µP†
64
PIN
PSDIP/CSDIP
TMS370Cx50: TMS370C050, TMS370C150, TMS370C250, AND TMS370C350
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C050A
ÁÁÁ
ÁÁÁ
4K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
256
ÁÁÁÁ
ÁÁÁÁ
256
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C150A
ÁÁÁ
ÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
56K
ÁÁÁ
ÁÁÁ
256
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
—
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C250A
ÁÁÁ
ÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
56K
ÁÁÁ
ÁÁÁ
256
ÁÁÁÁ
ÁÁÁÁ
256
ÁÁÁ
ÁÁÁ
—
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C350A
ÁÁÁ
ÁÁÁ
4K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
256
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
TMS370Cx52: TMS370C052, TMS370C352, AND TMS370C452
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C052A
ÁÁÁ
ÁÁÁ
8K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
256
ÁÁÁÁ
ÁÁÁÁ
256
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
ÁÁÁÁÁÁÁÁ
TMS370C352A
ÁÁÁ
8K
ÁÁÁÁ
—
ÁÁÁÁÁ
112K
ÁÁÁ
256
ÁÁÁÁ
—
ÁÁÁ
√
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C452A‡
ÁÁÁ
ÁÁÁ
8K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
256
ÁÁÁÁ
ÁÁÁÁ
256
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC
TMS370Cx53: TMS370C353
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C353A
ÁÁÁ
ÁÁÁ
12K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
1.5K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC
TMS370Cx56: TMS370C056, TMS370C156, TMS370C256, TMS370C356, TMS370C456, AND TMS370C756
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C056A
ÁÁÁ
ÁÁÁ
16K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
512
ÁÁÁÁ
ÁÁÁÁ
512
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C156A
ÁÁÁ
ÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
56K
ÁÁÁ
ÁÁÁ
512
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
—
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C256A
ÁÁÁ
ÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
56K
ÁÁÁ
ÁÁÁ
512
ÁÁÁÁ
ÁÁÁÁ
512
ÁÁÁ
ÁÁÁ
—
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C356A
ÁÁÁ
ÁÁÁ
16K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
512
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
ÁÁÁÁÁÁÁÁ
TMS370C456A‡
ÁÁÁ
16K
ÁÁÁÁ
—
ÁÁÁÁÁ
112K
ÁÁÁ
512
ÁÁÁÁ
512
ÁÁÁ
√
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
FN – PLCC
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C756A
ÁÁÁ
ÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
16K
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
512
ÁÁÁÁ
ÁÁÁÁ
512
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
TMS370Cx58: TMS370C058, TMS370C358, AND TMS370C758
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C058A
ÁÁÁ
ÁÁÁ
32K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
64K
ÁÁÁ
ÁÁÁ
1K
ÁÁÁÁ
ÁÁÁÁ
256
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C358A
ÁÁÁ
ÁÁÁ
32K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
64K
ÁÁÁ
ÁÁÁ
1K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
TMS370C758A,
TMS370C758B
ÁÁÁ
Á
Á
Á
ÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
32K
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
64K
ÁÁÁ
Á
Á
Á
ÁÁÁ
1K
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
256
ÁÁÁ
Á
Á
Á
ÁÁÁ
√
ÁÁÁ
Á
Á
Á
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
FN – PLCC / NM –PSDIP
TMS370Cx59: TMS370C059 AND TMS370C759
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C059A§
ÁÁÁ
ÁÁÁ
48K
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
20K
ÁÁÁ
ÁÁÁ
3.5K
ÁÁÁÁ
ÁÁÁÁ
256
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C759A§
ÁÁÁ
ÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
48K
ÁÁÁÁÁ
ÁÁÁÁÁ
20K
ÁÁÁ
ÁÁÁ
3.5K
ÁÁÁÁ
ÁÁÁÁ
256
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FN – PLCC
EPROM DEVICE: SE370C756, SE370C758, and SE370C759
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
SE370C756A¶
ÁÁÁ
ÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
16K
ÁÁÁÁÁ
ÁÁÁÁÁ
112K
ÁÁÁ
ÁÁÁ
512
ÁÁÁÁ
ÁÁÁÁ
512
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FZ – CLCC / JN –CSDIP
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
SE370C758A¶,
SE370C758B¶
ÁÁÁ
Á
Á
Á
—
ÁÁÁÁ
Á
ÁÁ
Á
32K
ÁÁÁÁÁ
Á
ÁÁÁ
Á
64K
ÁÁÁ
Á
Á
Á
1K
ÁÁÁÁ
Á
ÁÁ
Á
256
ÁÁÁ
Á
Á
Á
√
ÁÁÁ
Á
Á
Á
√
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
FZ – CLCC / JN –CSDIP
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
SE370C759A§¶
ÁÁÁ
ÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
48K
ÁÁÁÁÁ
ÁÁÁÁÁ
20K
ÁÁÁ
ÁÁÁ
3.5K
ÁÁÁÁ
ÁÁÁÁ
256
ÁÁÁ
ÁÁÁ
√
ÁÁÁ
ÁÁÁ
√
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
FZ – CLCC
†µC – Microcomputer mode
µP – Microprocessor mode
‡TMS370C45x support ROM memory security. Refer to the program ROM section.
§Only operate up to 3 MHz SYSCLK
¶System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
The suffix letter (A or B) appended to the device names shown in the device column of Table 2 indicates the
configuration of the device. ROM or an EPROM devices have different configurations as indicated in Table 3.
ROM devices with the suffix letter A are configured through a programmable contact during manufacture.
Table 3. Suffix Letter Configuration
DEVICE†WA TCHDOG TIMER CLOCK LOW-POWER MODE
EPROM A Standard Divide-by-4 (Standard oscillator) Enabled
EPROM B Hard Divide-by-1 (PLL) Enabled
Standard
ROM A Hard Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled
Simple
ROM-less A Standard Divide-by-4 Enabled
†Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.
Unless otherwise noted, the terms TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58,
TMS370Cx59, and SE370C75x refer to the individual devices listed in Table 2 and described in this data sheet.
All TMS370Cx5x devices contain the following on-chip peripheral modules:
D
Eight-channel, 8-bit analog-to-digital converter 1 (ADC1)
D
Serial communications interface 1 (SCI1)
D
Serial peripheral interface (SPI)
D
One 24-bit general-purpose watchdog timer
D
Two 16-bit general-purpose timers (one with an 8-bit prescaler)
TMS370C756, TMS370C758, and TMS370C759 are one-time programmable (OTP) devices that are available
in plastic packages. This microcomputer is effective to use for immediate production updates for other members
of the TMS370Cx5x family or for low-volume production runs when the mask charge or cycle time for low-cost
mask ROM devices is not practical.
The SE370C756, SE370C758, and SE370C759 have windowed ceramic packages to allow reprogramming of
the program EPROM memory during the development/prototyping phase of design. The SE370C75x devices
allow quick updates to breadboards and prototype systems while iterating initial designs.
The TMS370Cx5x family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no
instructions are executed). In the ST ANDBY mode, the internal oscillator and the general-purpose timer remain
active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral
configuration bits throughout both low-power modes.
The TMS370Cx5x features advanced register-to-register architecture that allows direct arithmetic and logical
operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to
the contents of register 47 and store the result in register 47). The TMS370Cx5x family is fully
instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller
family.
The SPI and the two operational modes of the SCI1 give three methods of serial communications. The SCI1
allows standard RS-232-C communications interface between other common data transmission equipment,
while the SPI gives high-speed communications between simpler shift-register type devices, such as display
drivers, ADC1 converter, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
For large memory applications, the TMS370Cx5x family provides an external bus with non-multiplexed address
and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system
implementations. W ait-state support facilitates performance matching among the CPU, external memory, and
the peripherals. All pins associated with memory expansion interface are individually software configurable for
general purpose digital input/output (I/O) pins when operating in the microcomputer mode.
The TMS370Cx5x family provides the system designer with very economical, efficient solution to real-time
control applications. The TMS370 family extended development system (XDS) and compact development
tool (CDT) solve the challenge of efficiently developing the software and hardware required to design the
TMS370Cx5x into an ever-increasing number of complex applications. The application source code can be
written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family
XDS development tools communicate through a standard RS-232-C interface with an existing personal
computer. This allows the use of the personal computer editors and software utilities already familiar to the
designer. The TMS370 family XDS emphasizes ease-of-use through extensive use of menus and screen
windowing so that a system designer with minimal training can begin developing software. Precise real-time
in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware
implementation as well as reduced time-to-market cycle.
The TMS370Cx5x family together with the TMS370 family XDS/22, CDT370, design kit, starter kit, software
tools, the SE370C75x reprogrammable devices, comprehensive product documentation, and customer support
provide a complete solution to the needs of the system designer.
modes
The TMS370Cx5x has four operating modes, two basic modes with each mode having two memory
configurations. The basic operating modes are the microcomputer and microprocessor modes, which are
selected by the voltage level applied to the dedicated MC pin two cycles before RESET goes inactive. The two
memory configurations then are selected through software programming of the internal system configuration
registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion,
microprocessor without internal program memory, and microprocessor with internal program memory. These
modes are described in the following list.
D
Microcomputer single chip mode:
– Operates as a self-contained microcomputer with all memory and peripherals on-chip.
– Maximizes the general-purpose I/O capability for real-time control applications.
D
Microcomputer with external expansion mode:
– Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM,
EPROM, and data EEPROM) remains active.
– Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port
control, to become external memory as follows:
– Port A: 8-bit data memory
– Port B and C: 16-bit address memory
– Port D: 8-bit control memory (pin not used as function A or B can be configured as I/O)
– Utilizes the pins available (not used for address, data, or control memory) as general-purpose
input/output by programming them individually.
– Lowers the system cost by not requiring an external address/data latch (address memory and data
memory are nonmultiplexed).
XDS and CDT are trademarks of Texas Instruments Incorporated.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
modes (continued)
– Reduces external interface decode logic by using the precoded chip select outputs that provide direct
memory/peripheral chip select or chip enable functions.
– Function A maps up to 112K bytes of external memory into the address space by using CSE1, CSE2,
CSH1, CSH2, and CSH3 as memory-bank selects under software control.
– Function B maps up to 40K bytes of external memory into the address space by using EDS under
software control.
D
Microprocessor without internal program memory mode:
– Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses
for interface to external memory and peripherals.
– On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled.
– Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations.
D
Microprocessor with internal program memory mode:
– Configured as the microprocessor without internal program memory mode with respect to the external
bus interface.
– Application program in external memory enables the internal program ROM or EPROM to be active in
the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control
register accomplishes this.)
memory/peripheral wait operation
The TMS370Cx5x enhances interface flexibility by providing W AIT-state support, decoupling the cycle time of
the CPU from the read/write access of the external memory or peripherals. External devices can extend the
read/write accesses indefinitely by placing an active low on the W AIT-input pin. The CPU continues to wait as
long as WAIT remains active.
Programmable automatic wait-state generation also is provided by the TMS370Cx5x on-chip bus controller.
Following a hardware reset, the TMS370Cx5x is configured to add one wait state to all external bus transactions
and memory and peripheral accesses automatically, thus making every external access a minimum of three
system-clock cycles. The designer can disable the automatic wait-state generation if the AUTOW AIT DISABLE
bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended
independently to four system clock cycles if the PF AUTO W AIT bit in SCCR0 is set to one. Programmable wait
states can be used in conjunction with the external WAIT pin. In applications where the external device
read/write access can interface with the TMS370Cx5x CPU using one wait state, the automatic wait-state
generation can eliminate external WAIT interface logic, lowering system cost.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU
The CPU used on TMS370Cx5x devices is the high-performance 8-bit TMS370 CPU module. The ’x5x
implements an efficient register-to-register architecture that eliminates the conventional accumulator
bottleneck. The complete ’x5x instruction set is summarized in Table 23. Figure 1 illustrates the CPU registers
and memory blocks.
0000h
0200h
0400h
1000h
10C0h
1100h
1F00h
Interrupts and Reset Vectors;
Trap Vectors
0600h
FFFFh
0
RAM (Includes 256-Byte Registers File)
015 Program Counter
7Legend:
Z=Zero
IE1=Level1 interrupts Enable
C=Carry
V=Overflow
N=Negative
IE2=Level2 interrupts Enable
IE1IE2ZNC
01234567
V
Status Register (ST)
Stack Pointer (SP)
R0(A)
R1(B)
R3
R127
0000h
0001h
0002h
007Fh
R255
0003h
R2
00FFh
Reserved†
16K-Byte ROM/EPROM (4000h–7FFFh)
1E00h
0100h
0E00h
12K-Byte ROM (5000h–7FFFh)
8K-Byte ROM (6000h–7FFFh)
32K-Byte ROM/EPROM (2000h–9FFFh)
48K-Byte ROM/EPROM (2000h–DFFFh)
Memory Expansion
2000h
4000h
5000h
6000h
7000h
7FC0h
8000h
A000h
E000h
256-Byte RAM (0000h–00FFh)
512-Byte RAM (0000h–01FFh)
1K-Byte RAM (0000h–03FFh)
1.5K-Byte RAM (0000h–05FFh)
3.5K-Byte RAM (0000h–0DFFh)
Peripheral File
Peripheral Exp
Reserved†
512-Byte (1E00h–1FFFh)
Data EEPROM
256-Byte (1F00h–1FFFh)
4K-Byte ROM (7000h–7FFFh)
†Reserved means the address space is reserved for future expansion.
Figure 1. Programmer’s Model
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU (continued)
The ’x5x CPU architecture provides the following components:
D
CPU registers:
– A stack pointer that points to the last entry in the memory stack
– A status register that monitors the operation of the instructions and contains the global-interrupt-enable
bits
– A program counter (PC) that points to the memory location of the next instruction to be executed
D
A memory map that includes :
– 256-, 512-, 1K-, 1.5K-, or 3.5K-byte general-purpose RAM that can be used for data-memory storage,
program instructions, general-purpose register , or the stack (can be located only in the first 256 bytes)
– A peripheral file that provides access to all internal peripheral modules, system-wide control functions,
and EEPROM/EPROM programming control
– 256- or 512-byte EEPROM module that provides in-circuit programmability and data retention in
power-off conditions
– 4K-, 8K-, 12K-, 16K-, 32K-, or 48K-byte ROM or 16K-, 32K-, or 48K-byte EPROM program memory
stack pointer (SP)
The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. Typically the stack
is used to store the return address on subroutine calls as well as the status-register contents during interrupt
sequences.
The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed
onto the stack and decrements after data is popped from the stack. The stack can be located only in the first
256 bytes of the on-chip RAM memory.
status register (ST)
The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes
four status bits (condition flags) and two interrupt-enable bits:
D
The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,
the conditional-jump instructions) use these status bits to determine program flow.
D
The two interrupt-enable bits control the two interrupt levels.
The ST register, status bit notation, and status bit definitions are shown in Table 4.
Table 4. Status Registers
ÁÁÁÁÁ
ÁÁÁÁÁ
7
ÁÁÁÁÁ
ÁÁÁÁÁ
6
ÁÁÁÁÁ
ÁÁÁÁÁ
5
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁ
ÁÁÁÁÁ
2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
C
ÁÁÁÁÁ
ÁÁÁÁÁ
N
ÁÁÁÁÁ
ÁÁÁÁÁ
Z
ÁÁÁÁÁ
ÁÁÁÁÁ
V
ÁÁÁÁÁ
ÁÁÁÁÁ
IE2
ÁÁÁÁÁ
ÁÁÁÁÁ
IE1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
RW-0
ÁÁÁÁÁ
ÁÁÁÁÁ
RW-0
ÁÁÁÁÁ
ÁÁÁÁÁ
RW-0
ÁÁÁÁÁ
ÁÁÁÁÁ
RW-0
ÁÁÁÁÁ
ÁÁÁÁÁ
RW-0
ÁÁÁÁÁ
ÁÁÁÁÁ
RW-0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
R = read, W = write, 0 = value after reset
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU (continued)
program counter (PC)
The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These
registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address.
The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH
(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is
loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of
6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).
Memory
Program Counter (PC)
60 00
PCH PCL
60
00
0000h
7FFEh
7FFFh
Figure 2. Program Counter After Reset
memory map
The TMS370Cx5x architecture is based on the Von Neuman architecture, where the program memory and data
memory share a common address space. All peripheral input/output is memory mapped in this same common
address space. In the expansion mode, external memory peripherals are also memory-mapped into this
common address. As shown in Figure 3, the TMS370Cx5x provides a 16 bit-address range to access internal
or external RAM, ROM, data EEPROM, EPROM input/output pins, peripheral functions, and system-interrupt
vectors.
The peripheral file contains all input/output port control, on- and off-chip peripheral status and control, EPROM,
EEPROM programming, and system-wide control functions. The peripheral file consists of 256 contiguous
addresses located from 1000h to 10FFh. The 256 contiguous addresses are divided logically into 16 peripheral
file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral
control and data information is passed. The TMS370Cx5x has its on-chip peripherals and system control
assigned to peripheral file frames 1 through 7, addresses 1010h through 107Fh.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map (continued)
Reset 7FFEh–7FFFh
Interrupt 1 7FFCh–7FFDh
Interrupt 2 7FFAh–7FFBh
Interrupt 3 7FF8h–7FF9h
Serial Peripheral I/F 7FF6h–7FF7h
Timer 1 7FF4h–7FF5h
Serial Comm I/F RX 7FF2h–7FF3h
Serial Comm I/F TX 7FF0h–7FF1h
Timer 2A 7FEEh–7FEFh
ADC1 7FECh–7FEDh
7FE0h–7FFBh
Reserved†
7FC0h–7FDFh
Trap 15–0
Vectors
Peripheral File Control
Registers
Reserved†1080h–108Fh
ADC1 Peripheral
Control 1070h–107Fh
Timer 2A Peripheral
Control 1060h–106Fh
SCI1 Peripheral
Control 1050h–105Fh
Timer 1 Peripheral
Control 1040h–104Fh
SPI Peripheral
Control 1030h–103Fh
Digital Port Control 1020h–102Fh
System Control 1010h–101Fh
1000h–100Fh
Reserved†
External
Reserved†
Ò
Ò
Ò
ŠŠ
ŠŠ
ŠŠ
ÒÒ
ÒÒ
ÒÒ
Š
Š
Š
ÒÒ
ÒÒ
ÒÒ
Š
Š
Š
ŠŠ
ŠŠ
ŠŠ
ÒÒ
ÒÒ
ÒÒ
10C0h
7FC0h
Memory Expansion
48K-Byte ROM
(2000h–DFFFh)
32K-Byte ROM
(2000h–9FFFh)
Interrupts and
Reset Vectors;
Trap Vectors
4K-Byte ROM
(7000h–7FFFh)
8K-Byte ROM
(6000h–7FFFh)
12K-Byte ROM
(5000h–7FFFh)
16K-Byte ROM
(4000h–7FFFh)
256-Byte Data
EEPROM
(1F00h–1FFFh)
512K-Byte Data
EEPROM
(1E00h–1FFFh)
Reserved†
Peripheral Expansion
Peripheral File
Reserved†
3.5K-Byte RAM
(0000h–0DFFh)
1.5K-Byte RAM
(0000h–05FFh)
1K-Byte RAM
(0000h–03FFh)
512-Byte RAM
(0000h–01FFh)
256-Byte RAM
(0000h–00FFh)
(Register File/Stack)
0000h
0100h
0200h
0400h
0E00h
1000h
1100h
1E00h
1F00h
2000h
4000h
6000h
7000h
8000h
A000h
E000h
FFFFh
0600h
5000h
Ú
Ú
Ú
Ú
Ú
ÛÛ
ÛÛ
ÛÛ
Ü
Ü
Ü
’X50
Ò
Ò
ŠŠ
ŠŠ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
Ú
Ú
Ú
ÛÛ
ÛÛ
ÛÛ
ÛÛ
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Microprocessor Mode¶
’X52
’X53
’X56
’X58
’X59
Reserved†
External
Reserved†
ÒÒ
ÒÒ
ÒÒ
ÒÒ
ÒÒ
Š
Š
Š
Š
Š
Š
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
’X50
ÒÒ
ÒÒ
Š
Š
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
Ú
Ú
Ú
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
Microprocessor With
Internal Program
Memory
’X52
’X53
’X56
’X58
’X59
Reserved†
External
Reserved†
Reserved†
Reserved†
’X59’X58’X56’X53’X52
Microcomputer
Mode With External
Expansion
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
Û
Û
Û
Û
ÚÚ
ÚÚ
ÚÚ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
Š
Š
ÒÒ
ÒÒ
’X50
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
Û
Û
Û
Û
Û
Û
Û
Û
Û
Û
Û
Û
Û
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
Š
Š
Š
Š
Š
Š
ÒÒ
ÒÒ
ÒÒ
ÒÒ
ÒÒ
5000h
ÒÒ
ÒÒ
ÒÒ
ÒÒ
ÒÒ
ŠŠ
ŠŠ
ŠŠ
ŠŠ
ŠŠ
ŠŠ
Ù
Ù
Ù
Ù
Ù
Ù
Ù
Ù
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Ü
’X50
0600h
ÒÒ
ÒÒ
ŠŠ
ŠŠ
Ù
Ù
Ù
Ù
Ù
Ù
ÚÚ
ÚÚ
ÚÚ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
Ü
Ü
Ü
Ü
Ü
Ü
Ü
Microcomputer
Single Chip Mode
FFFFh
E000h
A000h
8000h
7000h
6000h
4000h
2000h
1F00h
1E00h
1100h
10C0h
1000h
0E00h
0400h
0200h
0100h
0000h
’X52
’X53
’X56
’X58
’X59
Not Available‡
Not Avail-
able‡
(N/A)
Reserved†
ÒÒ
ÙÙ
ŠŠ
ÚÚ
ÛÛ
ÜÜ
On-Chip For TMS370Cx59 Devices
On-Chip For TMS370Cx58 Devices
On-Chip For TMS370Cx56 Devices
On-Chip For TMS370Cx53 Devices
On-Chip For TMS370Cx52 Devices
On-Chip For TMS370Cx50 Devices
Ü
Ü
ÛÛ
ÛÛ
ÚÚ
ÚÚ
Ù
Ù
ÒÒ
ÒÒ
ŠŠ
ŠŠ
ÜÜ
ÜÜ
Û
Û
ÚÚ
ÚÚ
ÙÙ
ÙÙ
ÒÒ
ÒÒ
Š
Š
ÜÜ
ÜÜ
ÛÛ
ÛÛ
Ú
Ú
ÙÙ
ÙÙ
ÒÒ
ÒÒ
Š
Š
Ü
Ü
ÛÛ
ÛÛ
Ú
Ú
ÙÙ
ÙÙ
Ò
Ò
ŠŠ
ŠŠ
N/A‡N/A‡N/A‡
External
External§External
External§
External§
†Reserved = the address space is reserved for future expansion.
‡Not available (N/A) = address space unavailable in the mode illustrated.
§Precoded chip select outputs available on external expansion bus.
¶Microprocessor mode is designed for ROM-less devices (’x50 and ’x56). ROM and EPROM devices can also be used in this mode but all on-chip
memory is ignored. Figure 3. TMS370Cx5x Memory Map
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
RAM/register file (RF)
Locations within RAM address space can serve as either register file or general-purpose read/write memory,
program memory, or stack instructions. The TMS370Cx50 and TMS370Cx52 devices contain 256 bytes of
internal RAM, mapped beginning at location 0000h and continuing through location 00FFh which is shown in
Table 5 along with other ’x5x devices.
Table 5. RAM Memory Map
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
‘x50 and ‘x52
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
‘x56
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
‘x58
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
‘x53
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
‘x59
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RAM Size
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
256 Bytes
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
512 Bytes
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1K Bytes
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1.5K Bytes
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.5K Bytes
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Memory Mapped
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0000h – 00FFh
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0000h – 01FFh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0000h – 03FFh
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0000h – 05FFh
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0000h – 0DFFh
The first 256 bytes of RAM (0000h – 00FFh) are register files, R0 through R255 (see Figure 1). The first two
registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A
or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer
is contained in register B. Registers A and B are the only registers cleared on reset.
peripheral file (PF)
The TMS370Cx5x control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the PF directly. These
instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal
designator or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at
address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 6
shows the TMS370Cx5x peripheral files.
Table 6. TMS370Cx5x Peripheral File Address map
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
ADDRESS RANGE
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
PERIPHERAL FILE
DESIGNATOR
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DESCRIPTION
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1000h–100Fh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P000–P00F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved for factory test
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1010h–101Fh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P010–P01F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
System and EEPROM/EPROM control registers
ÁÁÁÁÁÁÁ
1020h–102Fh
ÁÁÁÁÁÁÁ
P020–P02F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Digital I/O port control registers
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1030h–103Fh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P030–P03F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Serial peripheral interface registers
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1040h–104Fh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P040–P04F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T imer 1 registers
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1050h–105Fh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P050–P05F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Serial communication interface 1 registers
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1060h–106Fh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P060–P06F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T imer 2A registers
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1070h–107Fh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P070–P07F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Analog-to-digital converter 1 registers
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1080h–10BFh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P080–P0BF
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
10C0h–10FFh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
P0C0–P0FF
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
External peripheral control
data EEPROM
The TMS370Cx56 devices contain 512 bytes of data EEPROM, which are memory mapped beginning at
location 1E00h and continuing through location 1FFFh as shown in Table 7 along with other ‘x5x devices.
Table 7. Data-EEPROM Memory Map
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
‘x50, ‘x52, ‘x58, and ‘x59
ÁÁÁÁÁÁÁÁÁÁÁ
‘x56
ÁÁÁÁÁÁÁ
‘X53
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Data-EEPROM Size
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
256 Bytes
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
512 Bytes
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
None
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Memory Mapped
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
1F00h–1FFFh
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
1E00h–1FFFh
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
None
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
data EEPROM (continued)
Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the
write-protection register (WPR). Programming algorithm examples are available in the
TMS370 Family User’ s
Guide
(literature number SPNU127) or the
TMS370 Family Data Manual
(literature number SPNS014B). The
data EEPROM features include the following:
D
Programming:
– Bit, byte, and block write/erase modes
– Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.
– Control register: Data EEPROM programming is controlled by the data EEPROM control register
(DEECTL) located in the PF frame beginning at location P01A.
– In-circuit programming capability: There is no need to remove the device to program it.
D
Write-protection: Writes to the data EEPROM are disabled during the following conditions:
– Reset: All programming of the data EEPROM module is halted.
– Write protection active: There is one write-protect bit per 32-byte EEPROM block.
– Low-power mode operation
D
Write protection can be overridden by applying 12 V to MC.
Table 8 shows the memory map of the control registers.
Table 8. Data EEPROM and Program EPROM Control Registers Memory Map
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ADDRESS
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
SYMBOL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NAME
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P014
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
EPCTLH
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Program EPROM control register – high array
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P015–P016
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P017
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
INT1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
External interrupt 1 control register
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P018
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
INT2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
External interrupt 2 control register
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P019
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
INT3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
External interrupt 3 control register
ÁÁÁÁÁÁÁÁ
P01A
ÁÁÁÁÁÁÁÁ
DEECTL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Data EEPROM control register
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P01B
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P01C
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
EPCTLM
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Program EPROM control register – middle array
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P01D
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P01E
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
EPCTLL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Program EPROM control register – low array
For the 16K-byte EPROM device, program memory is controlled by P01C; for the 32K-byte EPROM device,
the program memory is controlled by P01C and P01E; for the 48K-byte EPROM device, the program memory
is controlled by P014, P01C, and P01E.
program EPROM
The ‘370C756 consists of a 16K-byte array of EPROM at address locations 4000h through 7FFFh. The
‘370C758 consists of 32K bytes made up of two 16K-byte arrays of EPROM; the first 16K-bytes array is located
at address locations 2000h through 5FFFh, and the second 16K byte array is located at address locations 6000h
through 9FFFh. The ’370C759 consists of 48K bytes that is made up of three 16K byte arrays of EPROM; the
first 16K bytes array is located at address locations 2000h through 5FFFh, the second 16K-byte array is located
at address locations 6000h through 9FFFh, the third 16K-byte array is located at address locations A000h
through DFFFh (see Figure 3).
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
program EPROM (continued)
The EPROM memory map in Table 9 expresses the following:
D
The programming control register for program EPROM (EPCTLM) for 16K-byte EPROM is located at
address 101Ch (P01C).
D
For the 32K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the
second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C).
D
For the 48K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the
second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C); the third 16K-byte array is
controlled by EPCTLH, located at 1014h (P014).
Table 9. EPROM Memory Map
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
’756
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
’758
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
’759
ÁÁÁÁÁ
ÁÁÁÁÁ
EPROM size
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
16K Bytes
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
32K Bytes
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
48K Bytes
ÁÁÁÁÁ
ÁÁÁÁÁ
Memory Mapped
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
16K
4000h–7FFFh
ÁÁÁÁÁ
ÁÁÁÁÁ
First 16K
2000h–5FFFh
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Second 16K
6000h–9FFFh
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
First 16K
2000h–5FFFh
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Second 16K
6000h–9FFFh
ÁÁÁÁÁ
ÁÁÁÁÁ
Third 16K
A000h–DFFFh
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Contol Registers
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
EPCTLM
P01C
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
EPCTLL
P01E
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
EPCTLM
P01C
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
EPCTLL
P01E
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
EPCTLM
P01C
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
EPCTLH
P014
Reading the program-EPROM modules is identical to reading other internal memory . During programming, the
EPROM is controlled by the EPCTL. The program EPROM modules’ features include:
D
Programming
– In-circuit programming capability if VPP is applied to MC
– Control register: Program EPROM programming is controlled by the program EPROM control registers
(EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 8.
– Programming one EPROM module while executing the other
D
Write protection: Writes to the program EPROM are disabled under the following conditions:
– Reset: All programming to the EPROM module is halted.
– Low-power modes
– 13 V not applied to MC
program ROM
The program ROM consists of 4K to 48K bytes of mask-programmable ROM. The program ROM is used for
permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device
fabrication. ROM security is a feature of the ‘45x devices, which inhibits reading of the data using the
programmer.
Table 10. ROM Memory Map†
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
‘x50
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
‘x52
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
‘x53
ÁÁÁÁÁ
ÁÁÁÁÁ
‘x56
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
‘x58
ÁÁÁÁÁ
ÁÁÁÁÁ
‘x59
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ROM Size
ÁÁÁÁÁ
ÁÁÁÁÁ
4K Bytes
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
8K Bytes
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
12K Bytes
ÁÁÁÁÁ
ÁÁÁÁÁ
16K Bytes
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
32K Bytes
ÁÁÁÁÁ
ÁÁÁÁÁ
48K Bytes
ÁÁÁÁÁÁ
Memory Mapped
ÁÁÁÁÁ
7000h – 7FFFh
ÁÁÁÁÁÁ
6000h – 7FFFh
ÁÁÁÁÁÁ
5000h – 7FFFh
ÁÁÁÁÁ
4000h – 7FFFh
ÁÁÁÁÁÁ
3000h – 9FFFh
ÁÁÁÁÁ
2000h – DFFFh
†Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI), and addresses 7FECh through 7FFFh are reserved for
interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh.
TI is a trademark of Texas Instruments Incorporated.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
system reset
The system-reset operation ensures an orderly start-up sequence for the TMS370Cx5x CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
internally generated, while one (RESET) is controlled externally. These actions are as follows:
D
Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key
register, or if the re-initialization does not occur before the watchdog timer timeout . See the
TMS370 User’s
Guide
(literature number SPNU127) or the
TMS370 Family Data Manual
(literature number SPNS014B)
for more information.
D
Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See
the
TMS370 User ’s Guide
(literature number SPNU127) or the
TMS370 Family Data Manual
(literature
number SPNS014B) for more information.
D
External RESET Pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the
TMS370 User’s Guide
(literature number SPNU127) or the
TMS370 Family Data Manual
(literature number
SPNS014B) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x5x device to reset external system components. Additionally, if a cold-start condition
(VCC is off for several hundred milliseconds) occurs, oscillator failure occurs, or RESET pin is held low, then the
reset logic holds the device in a reset state for as long as these actions are active.
After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag
(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source
of the reset. A reset does not clear these flags. Table 11 lists the reset sources.
Table 11. Reset Sources
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
REGISTER
ÁÁÁÁÁ
ÁÁÁÁÁ
ADDRESS
ÁÁÁÁÁ
ÁÁÁÁÁ
PF
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT NO.
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
CONTROL BIT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
SOURCE OF RESET
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
SCCR0
ÁÁÁÁÁ
ÁÁÁÁÁ
1010h
ÁÁÁÁÁ
ÁÁÁÁÁ
P010
ÁÁÁÁÁ
ÁÁÁÁÁ
7
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
COLD START
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Cold (power-up)
ÁÁÁÁÁÁ
SCCR0
ÁÁÁÁÁ
1010h
ÁÁÁÁÁ
P010
ÁÁÁÁÁ
4
ÁÁÁÁÁÁÁÁÁ
OSC FLT FLAG
ÁÁÁÁÁÁÁÁÁ
Oscillator out of range
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
T1CTL2
ÁÁÁÁÁ
ÁÁÁÁÁ
104Ah
ÁÁÁÁÁ
ÁÁÁÁÁ
P04A
ÁÁÁÁÁ
ÁÁÁÁÁ
5
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
WD OVRFL INT FLAG
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
W atchdog timer timeout
Once a reset is activated, the following sequence of events occurs:
1. The CPU registers initialize: ST = 00h, SP = 01h (reset state).
2. Registers A and B initialize to 00h (no other RAM is changed).
3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
5. Program execution begins with an opcode fetch from the address pointed to by the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode
fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state. During RESET, the two basic operating modes which are the
microcomputer and microprocessor modes can be selected by applying the desired voltage level to the
dedicated MC pin two cycles before RESET goes inactive (refer to page 7 for operating modes description).
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
interrupts
The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of
the status register.
Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is configured selectively on either the high- or
low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.
The TMS370Cx5x has nine hardware system interrupts (plus RESET) as shown in Table 12. Each system
interrupt has a dedicated vector located in program memory through which control is passed to the interrupt
service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt
sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the
associated PF. Each interrupt source FLAG bit is individually readable for software polling or determining which
interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in
Figure 4.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
interrupts (continued)
TIMER 2A
CPU
NMI
Logic
Enable
IE1
IE2 Level 1 INT
Level 2 INT
T2A PRI Priority
Overflow
Compare1
Ext Edge
Compare2
Input Capture 1
Input Capture 2
EXT INT 3
INT3 PRI
INT 3
STATUS REG
EXT INT1
INT1 PRI
INT1
SPI INT
SPI PRI
SPI
EXT INT 2
INT2 PRI
INT 2
AD INT
AD PRI
A/D
TIMER 1
T1 PRI
Overflow
Compare1
Ext Edge
Compare2
Input Capture 1
Watchdog
SCI INT
RX
BRKDT
RXRDY
TX
TXRDY
TXPRI RXPRI
Figure 4. Interrupt Control
On-chip peripheral functions generate six of the system interrupts. Three external interrupts also are supported.
Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers
in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling
edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or
non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or
global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should
be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts
INT2 and INT3 can be software configured as general purpose input/output pins if the interrupt function is not
required (INT1 can be similarly configured as an input pin). Table 12 shows the interrupt vector sources,
corresponding addresses, and hardware priorities.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
interrupts (continued)
Table 12. Hardware System Interrupts
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
INTERRUPT SOURCE
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
INTERRUPT FLAG
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
SYSTEM
INTERRUPT
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
VECTOR
ADDRESS
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
PRIORITY†
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
External RESET
W atchdog overflow
Oscillator fault detect
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
COLD START
WD OVRFL INT FLAG
OSC FLT FLAG
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
RESET‡
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
7FFEh, 7FFFh
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
1
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
External INT1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
INT1 FLAG
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INT1‡
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
7FFCh, 7FFDh
ÁÁÁÁÁ
ÁÁÁÁÁ
2
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
External INT2
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
INT2 FLAG
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INT2‡
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
7FFAh, 7FFBh
ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
External INT3
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
INT3 FLAG
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INT3‡
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
7FF8h, 7FF9h
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
SPI RX/TX complete
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
SPI INT FLAG
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
SPIINT
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
7FF6h, 7FF7h
ÁÁÁÁÁ
ÁÁÁÁÁ
5
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
T imer 1 overflow
T imer 1 compare 1
T imer 1 compare 2
T imer 1 external edge
T imer 1 input capture 1
W atchdog overflow
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
T1EDGE INT FLAG
T1IC1 INT FLAG
WD OVRFL INT FLAG
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
T1INT§
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
7FF4h, 7FF5h
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
6
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
SCI RX data register full
SCI RX break detect
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
RXRDY FLAG
BRKDT FLAG
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RXINT‡
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
7FF2h,7FF3h
ÁÁÁÁÁ
ÁÁÁÁÁ
7
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
SCI TX data register empty
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
TXRDY FLAG
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TXINT
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
7FF0h, 7FF1h
ÁÁÁÁÁ
ÁÁÁÁÁ
8
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
T imer 2A overflow
T imer 2A compare 1
T imer 2A compare 2
T imer 2A external edge
T imer 2A input capture 1
T imer 2A input capture 2
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
T2A OVRFL INT FLAG
T2AC1 INT FLAG
T2AC2 INT FLAG
T2AEDGE INT FLAG
T2AIC1 INT FLAG
T2AIC2 INT FLAG
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
T2AINT
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
7FEEh, 7FEFh
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
9
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
A/D conversion complete
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
AD INT FLAG
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ADINT
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
7FECh, 7FEDh
ÁÁÁÁÁ
ÁÁÁÁÁ
10
†Relative priority within an interrupt level
‡Releases microcontroller from STANDBY and HALT low-power modes.
§Releases microcontroller from STANDBY low-power mode.
privileged operation and EEPROM write-protection override
The TMS370Cx5x family has significant flexibility to enable the designer to software-configure the system and
peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation
ensures the integrity of the system configuration, once it is defined for an application. Following a hardware
reset, the TMS370Cx5x operates in the privileged mode, where all peripheral file registers have unrestricted
read/write access, and the application program configures the system during the initialization sequence
following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set
to 1 to enter the nonprivileged mode; disabling write operations to specific configuration control bits within the
peripheral file. Table 13 displays the system configuration bits that are write-protected during the nonprivileged
mode and must be configured by software prior to exiting the privileged mode.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
privileged operation and EEPROM write-protection override (continued)
Table 13. Privileged Bits
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
REGISTER†
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
CONTROL BIT
ÁÁÁÁ
ÁÁÁÁ
NAME
ÁÁÁÁÁ
ÁÁÁÁÁ
LOCATION
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
CONTROL
BIT
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁ
SCCRO
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
P010.5
P010.6
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
PF AUTOWAIT
OSC POWER
ÁÁÁÁ
ÁÁÁÁ
SCCR1
ÁÁÁÁÁ
ÁÁÁÁÁ
P011.2
P011.4
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
MEMORY DISABLE
AUTOWAIT DISABLE
ÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
ÁÁÁÁ
SCCR2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
P012.0
P012.1
P012.3
P012.4
P012.6
P012.7
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
PWRDWN/IDLE
HALT/STANDBY
ÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
ÁÁÁÁ
SPIPRI
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
P03F.5
P03F.6
P03F.7
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
SPI ESPEN
SPI PRIORITY
SPI STEST
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁ
SCIPRI
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
P05F.4
P05F.5
P05F.6
P05F.7
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
SCI ESPEN
SCIRX PRIORITY
SCITX PRIORITY
SCI STEST
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁ
T1PRI
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
P04F.6
P04F.7
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
T1 PRIORITY
T1 STEST
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁ
T2APRI
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
P06F.6
P06F.7
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
T2A PRIORITY
T2A STEST
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁ
ADPRI
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
P07F.5
P07F.6
P07F.7
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
AD ESPEN
AD PRIORITY
AD STEST
†The privileged bits are shown in a bold typeface in Table 15.
The write-protect override (WPO) mode provides an external hardware method for overriding the
write-protection registers of data EEPROM on the TMS370Cx5x. The WPO mode is entered by applying a 12-V
input to MC after RESET input goes high (logic 1). The high voltage on MC during the WPO mode is not the
programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages are
generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data
EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC
pin (normally not available in the end application except in a service or diagnostic environment).
low-power and IDLE modes
The TMS370Cx5x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time when the mask is manufactured.
The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The
HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.
In the ST ANDBY mode (HAL T/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial
communications interface remain active. System processing is suspended until a qualified interrupt (hardware
RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial
communications interface 1) is detected.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
low-power and IDLE modes (continued)
In the HALT mode (HALT/STANDBY = 1), the TMS370Cx5x is placed in its lowest power consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level
on the receive pin of the serial communications interface 1) is detected. The low-power mode selection bits are
summarized in Table 14.
Table 14. Low-Power/Idle Control Bits
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
POWER-DOWN CONTROL BITS
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
PWRDWN/IDLE
(SCCR2.6)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
HALT/STANDBY
(SCCR2.7)
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
MODE SELECTED
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
STANDBY
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
HALT
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
IDLE
X = don’t care
When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6–7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.
To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI is generated always, regardless of the interrupt enable flags.
The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status
registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the
STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.
clock modules
The ‘x5x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard
oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of
a TMS370 microcontroller. The ‘x5x ROM-masked devices offer both options to meet system engineering
requirements. Only one of the two clock options is allowed on each ROM device. The ‘75xA EPROM has only
the standard divide-by-4, while the ‘75xB EPROM has the divide-by-1.
The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with
no added cost.
The divide-by-1 provides a 1-to-1 match of the external resonator frequency to the internal system clock
(SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external
resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock
module then divides the resulting signal by four to provide the four-phased internal system clock signals. The
resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows
Divide-by-4 option : SYSCLK
+
external resonator frequency
4
+
CLKIN
4
Divide-by-1 option : SYSCLK
+
external resonator frequency
4
4
+
CLKIN
The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of
low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators.
The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a
steeper decay of emissions produced by the oscillator.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
system configuration registers
Table 15 contains system configuration and control functions and registers for controlling EEPROM
programming. The privileged bits are shown in a bold typeface and shaded.
Table 15. Peripheral File Frame 1: System Configuration Registers
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
PF
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 7
ÁÁÁÁ
ÁÁÁÁ
BIT 6
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 5
ÁÁÁÁ
ÁÁÁÁ
BIT 4
ÁÁÁÁ
ÁÁÁÁ
BIT 3
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 2
ÁÁÁÁ
ÁÁÁÁ
BIT 1
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 0
ÁÁÁÁ
ÁÁÁÁ
REG
ÁÁÁ
Á
Á
Á
ÁÁÁ
P010
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
COLD
START OSC
POWER PF AUTO
WAIT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
OSC FLT
FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
MC PIN
WPO
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
MC PIN
DATA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
µP/µC
MODE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCCR0
ÁÁÁ
ÁÁÁ
P011
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—AUTOWAIT
DISABLE
ÁÁÁÁ
ÁÁÁÁ
—MEMORY
DISABLE
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
SCCR1
ÁÁÁ
Á
Á
Á
ÁÁÁ
P012 HALT/
STANDBY PWRDWN/
IDLE
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—BUS
STEST CPU
STEST
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—INT1
NMI PRIVILEGE
DISABLE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCCR2
ÁÁÁ
ÁÁÁ
P013 Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P014
ÁÁÁÁÁ
ÁÁÁÁÁ
BUSY
ÁÁÁÁ
ÁÁÁÁ
VPPS
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
W0
ÁÁÁÁÁ
ÁÁÁÁÁ
EXE
ÁÁÁÁ
ÁÁÁÁ
EPCTLH
ÁÁÁ
Á
Á
Á
ÁÁÁ
P015
to
P016 Reserved
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P017
ÁÁÁÁÁ
ÁÁÁÁÁ
INT1
FLAG
ÁÁÁÁ
ÁÁÁÁ
INT1
PIN DATA
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
INT1
POLARITY
ÁÁÁÁ
ÁÁÁÁ
INT1
PRIORITY
ÁÁÁÁÁ
ÁÁÁÁÁ
INT1
ENABLE
ÁÁÁÁ
ÁÁÁÁ
INT1
ÁÁÁ
Á
Á
Á
ÁÁÁ
P018
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT2
FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
PIN DATA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
DATA DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
DATA OUT
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT2
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
PRIORITY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT2
ENABLE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P019
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT3
FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT3
PIN DATA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT3
DATA DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT3
DATA OUT
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT3
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT3
PRIORITY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT3
ENABLE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT3
ÁÁÁ
P01A
ÁÁÁÁÁ
BUSY
ÁÁÁÁ
—
ÁÁÁÁÁ
—
ÁÁÁÁ
—
ÁÁÁÁ
—
ÁÁÁÁÁ
AP
ÁÁÁÁ
W1W0
ÁÁÁÁÁ
EXE
ÁÁÁÁ
DEECTL
ÁÁÁ
ÁÁÁ
P01B Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P01C
ÁÁÁÁÁ
ÁÁÁÁÁ
BUSY
ÁÁÁÁ
ÁÁÁÁ
VPPS
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
W0
ÁÁÁÁÁ
ÁÁÁÁÁ
EXE
ÁÁÁÁ
ÁÁÁÁ
EPCTLM
ÁÁÁ
ÁÁÁ
P01D Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P01E
ÁÁÁÁÁ
ÁÁÁÁÁ
BUSY
ÁÁÁÁ
ÁÁÁÁ
VPPS
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
W0
ÁÁÁÁÁ
ÁÁÁÁÁ
EXE
ÁÁÁÁ
ÁÁÁÁ
EPCTLL
ÁÁÁ
ÁÁÁ
P01F Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
digital port control registers
Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 16 lists the specific
addresses, registers, and control bits within this peripheral file frame.
Table 16. Peripheral File Frame 2: Digital Port Control Registers
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
PF
ÁÁÁÁ
ÁÁÁÁ
BIT 7
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 6
ÁÁÁÁ
ÁÁÁÁ
BIT 5
ÁÁÁÁ
ÁÁÁÁ
BIT 4
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 3
ÁÁÁÁ
ÁÁÁÁ
BIT 2
ÁÁÁÁ
ÁÁÁÁ
BIT 1
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 0
ÁÁÁÁ
ÁÁÁÁ
REG
ÁÁÁ
ÁÁÁ
P020
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
APORT1
ÁÁÁ
ÁÁÁ
P021
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port A Control Register 2
ÁÁÁÁ
ÁÁÁÁ
APORT2
ÁÁÁ
ÁÁÁ
P022
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port A Data
ÁÁÁÁ
ÁÁÁÁ
ADATA
ÁÁÁ
ÁÁÁ
P023
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port A Direction
ÁÁÁÁ
ÁÁÁÁ
ADIR
ÁÁÁ
ÁÁÁ
P024
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
BPORT1
ÁÁÁ
P025
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port B Control Register 2
ÁÁÁÁ
BPORT2
ÁÁÁ
ÁÁÁ
P026
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port B Data
ÁÁÁÁ
ÁÁÁÁ
BDATA
ÁÁÁ
ÁÁÁ
P027
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port B Direction
ÁÁÁÁ
ÁÁÁÁ
BDIR
ÁÁÁ
ÁÁÁ
P028
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
CPORT1
ÁÁÁ
ÁÁÁ
P029
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port C Control Register 2
ÁÁÁÁ
ÁÁÁÁ
CPORT2
ÁÁÁ
ÁÁÁ
P02A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port C Data
ÁÁÁÁ
ÁÁÁÁ
CDATA
ÁÁÁ
ÁÁÁ
P02B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port C Direction
ÁÁÁÁ
ÁÁÁÁ
CDIR
ÁÁÁ
ÁÁÁ
P02C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port D Control Register 1
ÁÁÁÁ
ÁÁÁÁ
DPORT1
ÁÁÁ
ÁÁÁ
P02D
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port D Control Register 2†
ÁÁÁÁ
ÁÁÁÁ
DPORT2
ÁÁÁ
P02E
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port D Data
ÁÁÁÁ
DDATA
ÁÁÁ
ÁÁÁ
P02F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port D Direction
ÁÁÁÁ
ÁÁÁÁ
DDIR
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
†To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
digital port control registers (continued)
Table 17. Port Configuration Register Setup
INPUT OUTPUT FUNCTION A FUNCTION B
(µP MODE)
PORT PIN XPORT1 = 0†
XPORT2 = 0
XDATA = y
XDIR = 0
XPORT1 = 0†
XPORT2 = 0
XDATA = q
XDIR = 1
XPORT1 = 0†
XPORT2 = 1
XDATA = x
XDIR = x
XPORT1 = 1†
XPORT2 = 1
XDATA = x
XDIR = x
A0–7 Data In y Data Out q Data Bus Reserved
B0–7 Data In y Data Out q Low ADDR Reserved
C0–7 Data In y Data Out q Hi ADDR Reserved
D
0
1
2
3
4
5
6
7
Data In y Data Out q
CSE2
CSH3
CSH2
SYSCLK
R/W
CSPF
CSH1
CSE1
OCF
—
—
SYSCLK
R/W
—
EDS
WAIT
XPORT1 = 1
XPORT2 =0
XDATA = x
XDIR = x
Not defined
†DPORT only
timer 1 module
The programmable timer 1 (T1) module of the TMS370Cx5x provides the designer with the enhanced timer
resources required to perform realtime system control. The T1 module contains the general-purpose timer and
the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock
sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input capture and
compare) for special timer function control. The T1 module includes three external device pins that can be used
for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. T1 module is
shown in Figure 5.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
T1IC/CR Edge
Select
16-Bit
Counter
T1EVT
MUX
MUX
16-Bit
Register
T1PWM
PWM
Toggle
16
16-Bit
WatchdogCounter
(Aux. Timer)
Interrupt
Logic
Capt/Comp
16-Bit
Register
Compare
Interrupt
Logic
8-Bit
Prescaler
Figure 5. Timer 1 Block Diagram
D
Three T1 I/O pins:
– T1IC/CR: T1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin
– T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin
– T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin
D
Two operation modes:
– Dual-compare mode: Provides PWM signal
– Capture/compare mode: Provides input capture pin
D
One 16-bit general-purpose resettable counter
D
One 16-bit compare register with associated compare logic
D
One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a
capture or compare register
D
One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if
watchdog feature is not needed.
D
Prescaler/clock sources that determine one of eight clock sources for general-purpose timer
D
Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T1IC/CR)
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
D
Interrupts that can be generated on the occurrence of:
– A capture
– A compare equal
– A counter overflow
– An external edge detection
D
Sixteen T1 module control registers located in the PF frame, beginning at address P040
Table 18 shows the T1 module control register.
Table 18. T1 Module Register Memory Map
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
PF
ÁÁÁÁ
ÁÁÁÁ
BIT 7
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 6
ÁÁÁÁ
ÁÁÁÁ
BIT 5
ÁÁÁÁ
ÁÁÁÁ
BIT 4
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 3
ÁÁÁÁ
ÁÁÁÁ
BIT 2
ÁÁÁÁ
ÁÁÁÁ
BIT 1
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 0
ÁÁÁÁ
ÁÁÁÁ
REG
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Capture/Compare
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
P040
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T1 Counter MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁÁ
ÁÁÁÁ
T1CNTR
ÁÁÁÁ
ÁÁÁÁ
P041
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T1 Counter LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
P042
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compare Register MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁÁ
ÁÁÁÁ
T1C
ÁÁÁÁ
ÁÁÁÁ
P043
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compare Register LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
P044
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture/Compare Register MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁÁ
ÁÁÁÁ
T1CC
ÁÁÁÁ
ÁÁÁÁ
P045
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture/Compare Register LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
P046
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
W atchdog Counter MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁÁ
ÁÁÁÁ
WDCNTR
ÁÁÁÁ
ÁÁÁÁ
P047
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
W atchdog Counter LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
P048
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
W atchdog Reset Key
ÁÁÁÁÁ
Bit 0
ÁÁÁÁ
WDRST
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
P049
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
WD OVRFL
TAP SEL†
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
WD
INPUT
SELECT2†
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
WD
INPUT
SELECT1†
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
WD
INPUT
SELECT0†
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
T1
INPUT
SELECT2
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
T1
INPUT
SELECT1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1 INPUT
SELECT0
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
T1CTL1
ÁÁÁÁ
ÁÁÁÁ
P04A
ÁÁÁÁ
ÁÁÁÁ
WD OVRFL
RST ENA†
ÁÁÁÁÁ
ÁÁÁÁÁ
WD OVRFL
INT ENA
ÁÁÁÁ
ÁÁÁÁ
WD OVRFL
INT FLAG
ÁÁÁÁ
ÁÁÁÁ
T1 OVRFL
INT ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
T1 OVRFL
INT FLAG
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
T1 SW
RESET
ÁÁÁÁ
ÁÁÁÁ
T1CTL2
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Dual-Compare
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
P04B
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EDGE
INT FLAG
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1C2
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1C1
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EDGE
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1C2
INT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1C1
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1CTL3
ÁÁÁÁ
ÁÁÁÁ
P04C
ÁÁÁÁ
ÁÁÁÁ
T1
MODE = 0
ÁÁÁÁÁ
ÁÁÁÁÁ
T1C1
OUT ENA
ÁÁÁÁ
ÁÁÁÁ
T1C2
OUT ENA
ÁÁÁÁ
ÁÁÁÁ
T1C1
RST ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
T1CR
OUT ENA
ÁÁÁÁ
ÁÁÁÁ
T1EDGE
POLARITY
ÁÁÁÁ
ÁÁÁÁ
T1CR
RST ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
T1EDGE
DET ENA
ÁÁÁÁ
ÁÁÁÁ
T1CTL4
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Capture/Compare
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
P04B
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EDGE
INT FLAG
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1C1
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EDGE
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1C1
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1CTL3
ÁÁÁÁ
ÁÁÁÁ
P04C
ÁÁÁÁ
ÁÁÁÁ
T1
MODE = 1
ÁÁÁÁÁ
ÁÁÁÁÁ
T1C1
OUT ENA
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
T1C1
RST ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
T1EDGE
POLARITY
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
T1EDGE
DET ENA
ÁÁÁÁ
ÁÁÁÁ
T1CTL4
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Capture/Compare
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
P04D
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1EVT
DATA IN
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EVT
DATA OUT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EVT
FUNCTION
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1EVT
DATA DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1PC1
ÁÁÁÁ
ÁÁÁÁ
P04E
ÁÁÁÁ
ÁÁÁÁ
T1PWM
DATA IN
ÁÁÁÁÁ
ÁÁÁÁÁ
T1PWM
DATA OUT
ÁÁÁÁ
ÁÁÁÁ
T1PWM
FUNCTION
ÁÁÁÁ
ÁÁÁÁ
T1PWM
DATA DIR
ÁÁÁÁÁ
ÁÁÁÁÁ
T1IC/CR
DATA IN
ÁÁÁÁ
ÁÁÁÁ
T1IC/CR
DATA OUT
ÁÁÁÁ
ÁÁÁÁ
T1IC/CR
FUNCTION
ÁÁÁÁÁ
ÁÁÁÁÁ
T1IC/CR
DATA DIR
ÁÁÁÁ
ÁÁÁÁ
T1PC2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
P04F T1 STEST T1
PRIORITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1PRI
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
†Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT
SELECT2 bits are ignored.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
The T1 capture/compare mode block diagram is illustrated in Figure 6. The annotations on the diagram identify
the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,
bit 0, in the T1CTL2 register.
T1CTL4.2
16
Compare=
Edge
Select
T1IC/CR
T1EDGE POLARITY
T1EDGE DET ENA
Prescale
Clock
Source
16-Bit
Counter
MSB
LSB
T1CNTR.15-0
Reset
T1C1
RST ENA
T1 SW
RESET
T1CTL2.0
T1CTL4.4
T1PC2.3-0
T1CTL4.0
T1EDGE INT FLAG
T1EDGE INT ENA
T1CTL3.7
T1CTL3.2
T1 OVRFL INT FLAG
T1 OVRFL INT ENA
T1CTL2.3
T1CTL2.4
T1C1 INT FLAG
T1C1 INT ENA
T1CTL3.5
T1CTL3.0
T1C1
OUT ENA
T1PWM
T1CTL4.6
Toggle
T1PC2.7-4
16-Bit
Capt/CompMSB
LSB
Register
T1CC.15-0
T1C.15-0
16-Bit
Compare MSB
LSB
Register
T1 PRIORITY
ÏÏÏÏ
T1PRI.6
Level 1 Int
Level 2 Int
0
1
Figure 6. Capture/Compare Mode
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
The T1 dual-compare mode block diagram is illustrated in Figure 7. The annotations on the diagram identify
the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,
bit 0, in the T1CTL2 register.
T1CTL4.1
T1CTL4.4
Prescaler
Clock
Source
16-Bit
Counter
16-Bit
16
Compare=
Compare=
Reset
T1C1
RST ENA
T1 SW
RESET
Edge
Select
T1EDGE DET ENA
Output
Enable
Capt/Comp
Register MSB
LSB
MSB
LSB
T1CR OUT ENA
T1IC/CR
T1EDGE POLARITY
Toggle
16-Bit
Compare MSB
LSB
Register
T1CC.15-0
T1C1 INT FLAG
T1CTL3.0
T1CTL3.5
T1C1 INT ENA
T1C2 INT FLAG
T1CTL3.1
T1CTL3.6
T1C2 INT ENA
T1 OVRFL INT FLAG
T1CTL2.4
T1CTL2.3
T1 OVRFL INT ENA
T1EDGE INT FLAG
T1CTL3.2
T1CTL3.7
T1EDGE INT ENA
T1 PRIORITY
T1C2 OUT ENA
T1C1 OUT ENA
T1CTL4.3
T1CTL4.6
T1CTL4.5
T1PWM
T1PC2.7-4
T1PRI.6
T1C.15-0
T1CNTR.15-0
T1CTL2.0
T1CR
RST ENA
T1PC2.3-0
T1CTL4.0
T1CTL4.2
Level 1 Int
Level 2 Int
0
1
Figure 7. Dual-Compare Mode
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
The TMS370Cx5x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be
software-programmed as an event counter , pulse accumulator, or interval timer if the watchdog function is not
desired. The WD function is to monitor software and hardware operation and to implement a system reset when
the WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect
value). The WD can be configured as one of the three mask options: standard watchdog, hard watchdog, or
simple counter.
D
Standard watchdog configuration (see Figure 8) – for ’C75xA EPROM and mask-ROM devices
– Watchdog mode
– Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK
– A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct
value is written.
– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter
overflows
– A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a
system reset
– Non-watchdog mode
– Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer
16-Bit
W atchdog Counter
Reset
Prescaler
Clock
W atchdog Reset Key
WD OVRFL
TAP SEL WD OVRFL
RST ENA
System Reset
T1CTL1.7
WDRST.7-0
WDCNTR.15-0
T1CTL2.7
T1CTL2.5
WD OVRFL
INT ENA
Interrupt
T1CTL2.6
WD OVRFL
INT FLAG
Figure 8. Standard Watchdog
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
D
Hard watchdog configuration (see Figure 9) – for ‘C75xB EPROM and mask-ROM devices
– Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK.
– A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct
value is written.
– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter
overflows
– Automatic activation of the WD timer upon power-up reset
– INT1 is enabled as nonmaskable interrupt during low-power modes
– A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a
system reset
16-Bit
W atchdog Counter
Reset
Prescaler
Clock
W atchdog Reset Key
WD OVRFL
TAP SEL System Reset
T1CTL1.7
WDRST.7-0
WDCNTR.15-0
T1CTL2.5
WD OVRFL
INT FLAG
Figure 9. Hard Watchdog
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
D
Simple-counter configuration (see Figure 10) – for mask-ROM devices only
– The simple counter can be configured as an event counter, pulse accumulator, or an interval timer
16-Bit
W atchdog Counter
Reset
Prescaler
Clock
W atchdog Reset Key
WD OVRFL
TAP SEL
T1CTL1.7
WDRST.7-0
WDCNTR.15-0
T1CTL2.5
WD OVFL
INT FLAG
WD OVRFL
INT ENA
Interrupt
T1CTL2.6
Figure 10. Simple Counter
timer 2A module
The 16-bit general-purpose timer 2A (T2A) module is composed of a 16-bit resettable counter , 16-bit compare
register with associated compare logic, 16-bit capture register , and a 16-bit register that functions as a capture
register in one mode and as a compare register in the other mode. The T2A module adds an additional timer
that provides an event count, input capture, and compare functions. The T2A module includes three external
device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2A module is
shown in Figure 11.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 2A module (continued)
16–Bit
Register
16
INT
Logic
Capt/Comp
16–Bit
Capture
Edge
Detect
T2AEVT
PWM
Toggle T2AIC2/PWM
(Dual-Compare Mode)
Edge
Detect
T2AIC1/CR
T2AIC2/PWM
Register
16–Bit
Register
Compare
16–Bit
Counter
Clock
Select
(Dual-Capture Mode)
Figure 11. Timer 2A Block Diagram
The T2A module features include the following:
D
Three T2A I/O pins:
– T2AIC1/CR: T2A input-capture 1/counter-reset input pin, or general-purpose bidirectional I/O pin
– T2AIC2/PWM: T2A input-capture 2 /pulse-width-modulation (PWM) output pin, or general-purpose
bidirectional I/O pin
– T2AEVT: Timer 2A event-input pin, or general-purpose bidirectional I/O pin
D
Two operational modes:
– Dual-compare mode: Provides PWM signal
– Dual-capture mode: Provides input-capture pin
D
One 16-bit general-purpose resettable counter
D
One 16-bit compare register with associated compare logic
D
One 16-bit capture register with associated capture logic
D
One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a
capture or compare register
D
T2A clock sources can be any of the following:
– System clock
– No clock (the counter is stopped)
– External clock synchronized to the system clock (event counter)
– System clock while external input is high (pulse accumulation)
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 2A module (continued)
D
Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T2AIC1/CR)
D
Interrupts that can be generated on the occurrence of:
– A compare equal to dedicated compare register
– A compare equal to capture-compare register
– A counter overflow
– An external edge 1 detection
– An external edge 2 detection
D
Fourteen T2A module-control registers: Located in the PF frame beginning at address P060
The T2A module-control registers are illustrated in Table 19.
Table 19. Timer 2A Module Register Memory Map
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
PF
ÁÁÁÁ
ÁÁÁÁ
BIT 7
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 6
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 5
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 4
ÁÁÁÁ
ÁÁÁÁ
BIT 3
ÁÁÁÁ
ÁÁÁÁ
BIT 2
ÁÁÁÁ
ÁÁÁÁ
BIT 1
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 0
ÁÁÁ
ÁÁÁ
REG
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Dual-Capture
ÁÁÁ
ÁÁÁ
ÁÁÁ
P060
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T2A Counter MSbyte
ÁÁÁÁÁ
Bit 8
ÁÁÁ
T2ACNTR
ÁÁÁ
ÁÁÁ
P061
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T2A Counter LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
T2ACNTR
ÁÁÁ
ÁÁÁ
P062
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compare Register MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁ
ÁÁÁ
T2AC
ÁÁÁ
ÁÁÁ
P063
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compare Register LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
T2AC
ÁÁÁ
ÁÁÁ
P064
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture/Compare Register MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁ
ÁÁÁ
T2ACC
ÁÁÁ
ÁÁÁ
P065
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture/Compare Register LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
T2ACC
ÁÁÁ
ÁÁÁ
P066
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture Register 2 MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁ
ÁÁÁ
T2AIC
ÁÁÁ
ÁÁÁ
P067
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture Register 2 LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
T2AIC
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06A
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2A OVRFL
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A
OVRFL INT
FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A
INPUT
SELECT1
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A INPUT
SELECT0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2A SW
RESET
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2ACTL1
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Dual-Compare
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P06B
ÁÁÁÁ
ÁÁÁÁ
T2AEDGE1
INT FLAG
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AC2
INT FLAG
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AC1
INT FLAG
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
T2AEDGE1
INT ENA
ÁÁÁÁ
ÁÁÁÁ
T2AC2
INT ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AC1
INT ENA
ÁÁÁ
ÁÁÁ
T2ACTL2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06C
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A
MODE = 0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AC1
OUT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AC2
OUT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AC1
RST ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
OUT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
RST ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AEDGE1
DET ENA
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2ACTL3
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Dual-Capture
ÁÁÁ
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06B
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
INT FLAG
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AEDGE2
INT FLAG
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AC1
INT FLAG
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE2
INT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AC1
INT ENA
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2ACTL2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06C
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A
MODE = 1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AC1
RST ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE2
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE2
DET ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AEDGE1
DET ENA
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2ACTL3
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Dual-Capture
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06D
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEVT
DATA IN
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEVT
DATA OUT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEVT
FUNCTION
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AEVT
DATA DIR
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2APC1
ÁÁÁ
ÁÁÁ
P06E
ÁÁÁÁ
ÁÁÁÁ
T2AIC2/PWM
DATA IN
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AIC2/PWM
DATA OUT
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AIC2/PWM
FUNCTION
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AIC2/PWM
DATA DIR
ÁÁÁÁ
ÁÁÁÁ
T2AIC1/CR
DATA IN
ÁÁÁÁ
ÁÁÁÁ
T2AIC1/CR
DATA OUT
ÁÁÁÁ
ÁÁÁÁ
T2AIC1/CR
FUNCTION
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AIC1/CR
DATA DIR
ÁÁÁ
ÁÁÁ
T2APC2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06F T2A STEST T2A
PRIORITY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2APRI
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 2A module (continued)
The T2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify
the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,
bit 0, in the T2ACTL2 register.
T2AC.15-0
T2ACTL2.1
T2ACTL3.2
T2ACTL3.1
T2ACTL3.5
T2ACTL3.3
Clock
Source
16-Bit
Counter
16-Bit
16
Compare=
Compare=
Reset
T2AC1
RST ENA
T2A SW
RESET
Edge 1
Select
T2AEDGE1 DET ENA
Output
Enable
Capt/Comp
Register MSB
LSB
MSB
LSB
T2AEDGE1
OUT ENA
T2AIC1/CR
T2AEDGE1 POLARITY
Toggle
16-Bit
Compare MSB
LSB
Register
T2ACC.15-0
T2AC1 INT FLAG
T2ACTL2.0
T2ACTL2.5
T2AC1 INT ENA
T2AC2 INT FLAG
T2ACTL2.6
T2AC2 INT ENA
T2A OVRFL INT FLAG
T2ACTL1.4
T2ACTL1.3
T2A OVRFL INT ENA
T2AEDGE1 INT FLAG
T2ACTL2.2
T2ACTL2.7
T2AEDGE1 INT ENA
T2A PRIORITY
T2AC2 OUT ENA
T2AC1 OUT ENA
T2ACTL3.6
T2AIC2/PWM
T2APC2.7-4
T2APRI.6
T2ACNTR.15-0
T2ACTL1.0 T2ACTL3.4
T2AEDGE1
RST ENA
T2APC2.3-0
T2ACTL3.0
Level 1 Int
Level 2 Int
0
1
Figure 12. Dual-Compare Mode
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 2A module (continued)
The T2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram identify
the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,
bit 0, in the T2ACTL2 register.
0
Capt/Comp
T2APC2.3–0
Compare =
Clock
Source
16-Bit
Counter
MSB
LSB
T2ACNTR.15–0
Reset
T2AC1
RST ENA
T2ACTL1.0
T2ACTL3.4
T2ACTL2.6
T2ACTL2.1
T2ACTL2.7 T2ACTL2.2
T2ACTL2.5
T2ACTL2.0
16-Bit
MSB
LSB
Register 1
T2ACC.15–0
T2AC.15–0
16-Bit
Compare MSB
LSB
Register
T2A PRIORITY
Level 1 Int
Level 2 Int
1
T2ACTL1.3 T2ACTL1.4
16-Bit
Capture MSB
LSB
Register 2
T2AIC.15–0
Edge 2
Select
T2AIC2/PWM
T2APC2.7–4 T2ACTL3.1
Edge1
Select
T2AIC1/CR
T2ACTL3.3
T2ACTL3.2
T2ACTL3.0
16
T2AEDGE1 POLARITY
T2AEDGE1 DET ENA
T2AEDGE2 DET ENA
T2AEDGE2 POLARITY
T2AC1 INT FLAG
T2AC1 INT ENA
T2A OVRFL INT FLAG
T2A OVRFL INT ENA
T2AEDGE1 INT FLAG
T2AEDGE1 INT ENA
T2AEDGE2 INT ENA
T2AEDGE2 INT FLAG
T2APRI.6
T2A SW
RESET
Figure 13. Dual-Capture Mode
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial peripheral interface (SPI) module
The SPI is a high-speed, synchronous, serial I/O port that allows a serial bit stream of programmed length
(1 to 8 bits) to be shifted into, and out of, the device at a programmable bit-transfer rate.The SPI is used normally
for communications between the microcontroller and external peripherals or another microcontroller. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display drivers,
and analog-to-digital converters. The master/slave operation of the SPI supports multi-device communications.
The SPI module features include the following:
D
Three external pins:
– SPISOMI: SPI slave output/master input pin or general purpose bidirectional I/O pin
– SPISIMO: SPI slave input/master output pin or general purpose bidirectional I/O pin
– SPICLK: SPI serial clock pin or general purpose bidirectional I/O pin
D
Two operational modes: master and slave
D
Baud rate: Eight different programmable rates
– Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK
SPI BAUD RATE
+
SYSCLK
2
2b
– Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK.
For maximum slave SPI BAUD RATE < SYSCLK/8
where b = bit rate in SPICCR.5-3 (range 0–7)
D
Data word format: one to eight data bits
D
Simultaneous receive and transmit operation (transmit function can be disabled in software)
D
T ransmitter and receiver operations are accomplished through either interrupt driven or polled algorithms.
D
Seven SPI module control registers located in control register frame beginning at address P030h
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial peripheral interface (SPI) module (continued)
The SPI module control registers are illustrated in Table 20.
Table 20. SPI Module Control Register Memory Map
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
PF
ÁÁÁÁ
ÁÁÁÁ
BIT 7
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 6
ÁÁÁÁ
ÁÁÁÁ
BIT 5
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 4
ÁÁÁÁ
ÁÁÁÁ
BIT 3
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 2
ÁÁÁÁ
ÁÁÁÁ
BIT 1
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 0
ÁÁÁ
ÁÁÁ
REG
ÁÁÁ
ÁÁÁ
P030
ÁÁÁÁ
ÁÁÁÁ
SPI SW
RESET
ÁÁÁÁÁ
ÁÁÁÁÁ
CLOCK
POLARITY
ÁÁÁÁ
ÁÁÁÁ
SPI BIT
RATE2
ÁÁÁÁÁ
ÁÁÁÁÁ
SPI BIT
RATE1
ÁÁÁÁ
ÁÁÁÁ
SPI BIT
RATE0
ÁÁÁÁÁ
ÁÁÁÁÁ
SPI
CHAR2
ÁÁÁÁ
ÁÁÁÁ
SPI
CHAR1
ÁÁÁÁÁ
ÁÁÁÁÁ
SPI
CHAR0
ÁÁÁ
ÁÁÁ
SPICCR
ÁÁÁ
Á
Á
Á
ÁÁÁ
P031
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RECEIVER
OVERRUN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPI INT
FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
MASTER/
SLAVE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
TALK
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPI INT
ENA
ÁÁÁ
ÁÁ
Á
ÁÁÁ
SPICTL
ÁÁÁ
Á
Á
Á
ÁÁÁ
P032
to
P036 Reserved
ÁÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁÁ
ÁÁÁ
P037
ÁÁÁÁ
ÁÁÁÁ
RCVD7
ÁÁÁÁÁ
ÁÁÁÁÁ
RCVD6
ÁÁÁÁ
ÁÁÁÁ
RCVD5
ÁÁÁÁÁ
ÁÁÁÁÁ
RCVD4
ÁÁÁÁ
ÁÁÁÁ
RCVD3
ÁÁÁÁÁ
ÁÁÁÁÁ
RCVD2
ÁÁÁÁ
ÁÁÁÁ
RCVD1
ÁÁÁÁÁ
ÁÁÁÁÁ
RCVD0
ÁÁÁ
ÁÁÁ
SPIBUF
ÁÁÁ
ÁÁÁ
P038 Reserved
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P039
ÁÁÁÁ
ÁÁÁÁ
SDAT7
ÁÁÁÁÁ
ÁÁÁÁÁ
SDAT6
ÁÁÁÁ
ÁÁÁÁ
SDAT5
ÁÁÁÁÁ
ÁÁÁÁÁ
SDAT4
ÁÁÁÁ
ÁÁÁÁ
SDAT3
ÁÁÁÁÁ
ÁÁÁÁÁ
SDAT2
ÁÁÁÁ
ÁÁÁÁ
SDAT1
ÁÁÁÁÁ
ÁÁÁÁÁ
SDAT0
ÁÁÁ
ÁÁÁ
SPIDAT
ÁÁÁ
Á
Á
Á
ÁÁÁ
P03A
to
P03C Reserved
ÁÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P03D
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SPICLK
DATA IN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPICLK
DATA OUT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SPICLK
FUNCTION
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPICLK
DATA DIR
ÁÁÁ
ÁÁ
Á
ÁÁÁ
SPIPC1
ÁÁÁ
ÁÁÁ
P03E
ÁÁÁÁ
ÁÁÁÁ
SPISIMO
DATA IN
ÁÁÁÁÁ
ÁÁÁÁÁ
SPISIMO
DATA OUT
ÁÁÁÁ
ÁÁÁÁ
SPISIMO
FUNCTION
ÁÁÁÁÁ
ÁÁÁÁÁ
SPISIMO
DATA DIR
ÁÁÁÁ
ÁÁÁÁ
SPISOMI
DATA IN
ÁÁÁÁÁ
ÁÁÁÁÁ
SPISOMI
DATA OUT
ÁÁÁÁ
ÁÁÁÁ
SPISOMI
FUNCTION
ÁÁÁÁÁ
ÁÁÁÁÁ
SPISOMI
DATA DIR
ÁÁÁ
ÁÁÁ
SPIPC2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P03F SPI
STEST SPI
PRIORITY SPI
ESPEN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁ
ÁÁ
Á
ÁÁÁ
SPIPRI
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial peripheral interface (SPI) module (continued)
The SPI block diagram is illustrated in Figure 14.
SPIBUF Buffer
Register
SPIDAT
Data Register
SPIBUF.7-0
State Control
SPI CHAR
SPI BIT RATE
CLOCK POLARITY
SPI INT FLAG
SPICTL.6
SPIINT ENA
SPICTL.0
RECEIVER
OVERRUN
8
SPIDAT.7-0 SPICTL.1
TALK
201
3
4
5
SPICCR.2-0
SPICCR.5-3
System
Clock
SPICCR.6
SPICLK
MASTER/SLAVE†
SPICTL.7
Level 2 INT
SPIPRI.6
1
SPIPC2.7-4
SPISIMO
SPICTL.2
SPIPC1.3-0
SPISOMI
SPIPC2.3-0
Level 1 INT
0
†The diagram is shown in slave mode.
Figure 14. SPI Block Diagram
serial communications interface 1 (SCI1) module
The TMS370x5x devices include a serial communications interface (SCI1) module. The SCI1 module supports
digital communications between the TMS370 devices and other asynchronous peripherals and uses the
standard non-return-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and
each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in
the full duplex mode. T o ensure data integrity, the SCI1 checks received data for break detection, parity, overrun,
and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a
16-bit baud-select register.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial communications interface 1 (SCI1) module (continued)
Features of the SCI1 module include:
D
Three external pins:
– SCITXD: SCI transmit output pin or general-purpose bidirectional I/O pin
– SCIRXD: SCI receive input pin or general-purpose bidirectional I/O pin
– SCICLK: SCI bidirectional serial clock pin, or general-purpose bidirectional I/O pin
D
Two communications modes: asynchronous and isosynchronous†
D
Baud rate: 64K different programmable rates
– Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK
ASYNCHRONOUS BAUD
+
SYSCLK
(BAUD REG
)
1)
32
– Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK
ISOSYNCHRONOUS BAUD
+
SYSCLK
(BAUD REG
)
1)
2
D
Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– One or two stop bits
D
Four error-detection flags: parity, overrun, framing, and break detection
D
Two wake-up multiprocessor modes: Idle-line and address bit
D
Half or full-duplex operation
D
Double-buffered receive and transmit functions
D
Interrupt driven or polled algorithms with status flags accomplish transmitter (TX) and receiver (RX)
operations.
– Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX
EMPTY flag (transmitter shift register is empty)
– Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR monitoring four interrupt conditions
– Separate enable bits for transmitter and receiver interrupts
– NRZ (non return-to-zero) format
D
Eleven SCI1 module control registers are located in control register frame beginning at address P050h.
†Isosynchronous = Isochronous
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial communications interface 1 (SCI1) module (continued)
The SCI1 module control registers are illustrated in Table 21.
Table 21. SCI1 Module Control Register Memory Map
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
PF
ÁÁÁÁÁ
BIT 7
ÁÁÁÁ
BIT 6
ÁÁÁÁÁ
BIT 5
ÁÁÁÁ
BIT 4
ÁÁÁÁ
BIT 3
ÁÁÁÁÁ
BIT 2
ÁÁÁÁ
BIT 1
ÁÁÁÁÁ
BIT 0
ÁÁÁÁ
REG
ÁÁÁ
Á
Á
Á
ÁÁÁ
P050
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
STOP BITS
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
EVEN/ODD
PARITY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
PARITY
ENABLE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ASYNC/
ISOSYNC
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ADDRESS/
IDLE WUP
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCI CHAR2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCI CHAR1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCI CHAR0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCICCR
ÁÁÁ
Á
Á
Á
ÁÁÁ
P051
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCI SW
RESET
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
CLOCK
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
TXWAKE
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SLEEP
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
TXENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RXENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCICTL
ÁÁÁ
ÁÁÁ
P052
ÁÁÁÁÁ
ÁÁÁÁÁ
BAUDF
(MSB)
ÁÁÁÁ
ÁÁÁÁ
BAUDE
ÁÁÁÁÁ
ÁÁÁÁÁ
BAUDD
ÁÁÁÁ
ÁÁÁÁ
BAUDC
ÁÁÁÁ
ÁÁÁÁ
BAUDB
ÁÁÁÁÁ
ÁÁÁÁÁ
BAUDA
ÁÁÁÁ
ÁÁÁÁ
BAUD9
ÁÁÁÁÁ
ÁÁÁÁÁ
BAUD8
ÁÁÁÁ
ÁÁÁÁ
BAUD MSB
ÁÁÁ
Á
Á
Á
ÁÁÁ
P053
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BAUD7
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD6
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BAUD5
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD4
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD3
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BAUD2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BAUD0
(LSB)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD LSB
ÁÁÁ
ÁÁÁ
P054
ÁÁÁÁÁ
ÁÁÁÁÁ
TXRDY
ÁÁÁÁ
ÁÁÁÁ
TX EMPTY
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
SCI TX
INT ENA
ÁÁÁÁ
ÁÁÁÁ
TXCTL
ÁÁÁ
Á
Á
Á
ÁÁÁ
P055
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RX
ERROR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RXRDY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BRKDT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
FE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
OE
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
PE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RXWAKE
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCI RX
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RXCTL
ÁÁÁ
ÁÁÁ
P056
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P057
ÁÁÁÁÁ
ÁÁÁÁÁ
RXDT7
ÁÁÁÁ
ÁÁÁÁ
RXDT6
ÁÁÁÁÁ
ÁÁÁÁÁ
RXDT5
ÁÁÁÁ
ÁÁÁÁ
RXDT4
ÁÁÁÁ
ÁÁÁÁ
RXDT3
ÁÁÁÁÁ
ÁÁÁÁÁ
RXDT2
ÁÁÁÁ
ÁÁÁÁ
RXDT1
ÁÁÁÁÁ
ÁÁÁÁÁ
RXDT0
ÁÁÁÁ
ÁÁÁÁ
RXBUF
ÁÁÁ
ÁÁÁ
P058
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
P059
ÁÁÁÁÁ
TXDT7
ÁÁÁÁ
TXDT6
ÁÁÁÁÁ
TXDT5
ÁÁÁÁ
TXDT4
ÁÁÁÁ
TXDT3
ÁÁÁÁÁ
TXDT2
ÁÁÁÁ
TXDT1
ÁÁÁÁÁ
TXDT0
ÁÁÁÁ
TXBUF
ÁÁÁ
Á
Á
Á
ÁÁÁ
P05A
P05B
P05C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P05D
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCICLK
DATA IN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCICLK
DATA OUT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCICLK
FUNCTION
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCICLK
DATA DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCIPC1
ÁÁÁ
Á
Á
Á
ÁÁÁ
P05E
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCITXD
DATA IN
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCITXD
DATA OUT
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCITXD
FUNCTION
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCITXD
DATA DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCIRXD
DATA IN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCIRXD
DATA OUT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCIRXD
FUNCTION
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCIRXD
DATA DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCIPC2
ÁÁÁ
ÁÁÁ
P05F SCI STEST SCITX
PRIORITY SCIRX
PRIORITY SCI
ESPEN
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
SCIPRI
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
The SCI1 module block diagram is illustrated in Figure 15.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial communications interface 1 (SCI1) module (continued)
RXCTL.4–2
FE OE PE
RX ERROR
SCICTL.3
TXWAKE
SCICCR.6 SCICCR.5
EVEN/ODD ENABLE
PARITY
Frame Format and Mode
WUT
TXBUF.7–0
Transmit Data
Buffer Reg.
TXSHF Reg.
TXCTL.7
TXCTL.6
TXRDY
TX EMPTY
SCI TX Interrupt
TXCTL.0
TXENA
8
SCICTL.4
BAUD MSB. 7–0
Baud Rate
MSbyte Reg.
BAUD LSB. 7–0
Baud Rate
LSbyte Reg.
CLOCK
SCICTL.1
SCITXD
SCI TX INT ENA
RXCTL.7
ERR
RXSHF Reg.
RXCTL.1
8
Receive Data
Buffer Reg.
RXBUF.7–0
RXENA
RXCTL.6
RXCTL.5
RXRDY
BRKDT
SCI RX Interrupt
RXCTL.0
SCI RX INT ENA
ÏÏÏ
ÏÏÏ
SCIPRI.6
ÏÏÏÏ
ÏÏÏÏ
SCIPRI.5
Level 1 INT
Level 2 INT
Level 1 INT
Level 2 INT
SCITX PRIORITY
SCIRX PRIORITY
SCITXD
SCIPC2.7–4
SCICLK
SCIPC1.3–0
SCIRXD SCIRXD
SCIPC2.3–0
SCICTL.0
RXWAKE
1
SYSCLK
0
1
0
1
Figure 15. SCI1 Block Diagram
analog-to-digital converter 1 (ADC1) module
The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal
sample-and-hold circuitry . The module has eight multiplexed analog input channels that allow the processor to
convert the voltage levels from up to eight different sources. The ADC1 module features include the following:
D
Minimum conversion time: 32.8 µs at 5-MHz SYSCLK
D
Ten external pins:
– Eight analog input channels (AN0–AN7), any of which can be software configured as digital inputs
(E0–E7) if not needed as analog channels
– AN1–AN7 can also be configured as positive-input voltage reference.
–V
CC3: A/D module high-voltage reference input
–V
SS3: A/D module low-voltage reference input
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 1 (ADC1) module (continued)
D
The ADDATA register, which contains the digital result of the last ADC1 conversion
D
ADC1 operations can be accomplished through either interrupt driven or polled algorithms.
D
Six ADC1 module control registers are located in the control-register frame beginning at address 1070h.
The ADC1 module control registers are illustrated in Table 22.
Table 22. ADC1 Module Control Register Memory Map
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
PF
ÁÁÁÁ
ÁÁÁÁ
BIT 7
ÁÁÁÁ
ÁÁÁÁ
BIT 6
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 5
ÁÁÁÁ
ÁÁÁÁ
BIT 4
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 3
ÁÁÁÁ
ÁÁÁÁ
BIT 2
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 1
ÁÁÁÁ
ÁÁÁÁ
BIT 0
ÁÁÁÁ
ÁÁÁÁ
REG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
P070
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
CONVERT
START
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SAMPLE
START
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
REF VOLT
SELECT2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
REF VOLT
SELECT1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
REF VOLT
SELECT0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
AD INPUT
SELECT2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
AD INPUT
SELECT1
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
AD INPUT
SELECT0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ADCTL
ÁÁÁÁ
ÁÁÁÁ
P071
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
AD READY
ÁÁÁÁÁ
ÁÁÁÁÁ
AD INT
FLAG
ÁÁÁÁ
ÁÁÁÁ
AD INT
ENA
ÁÁÁÁ
ÁÁÁÁ
ADSTAT
ÁÁÁÁ
ÁÁÁÁ
P072
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
A-to-D Conversion Data Register
ÁÁÁÁ
ÁÁÁÁ
ADDATA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
P073
to
P07C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
P07D
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port E Data Input Register
ÁÁÁÁ
ÁÁÁÁ
ADIN
ÁÁÁÁ
ÁÁÁÁ
P07E
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port E Input Enable Register
ÁÁÁÁ
ÁÁÁÁ
ADENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
P07F AD STEST AD
PRIORITY AD ESPEN
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ADPRI
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 1 (ADC1) module (continued)
The ADC1 module block diagram is illustrated in Figure 16.
ADCTL.5–3
5 4 3
ADENA.0
REF VOLTS SELECT
ADCTL.2–0
2 1 0
AD INPUT SELECT
ADIN.0
Port E Input
ENA 0 Port E Data
AN 0
AN0
ADENA.1 ADIN.1
Port E Input
ENA 1 Port E Data
AN 1
AN1
ADENA.2 ADIN.2
Port E Input
ENA 2 Port E Data
AN 2
AN2
ADENA.3 ADIN.3
Port E Input
ENA 3 Port E Data
AN 3
AN3
ADENA.4 ADIN.4
Port E Input
ENA 4 Port E Data
AN 4
AN4
ADENA.5 ADIN.5
Port E Input
ENA 5 Port E Data
AN 5
AN5
ADENA.6 ADIN.6
Port E Input
ENA 6 Port E Data
AN 6
AN6
ADENA.7 ADIN.7
Port E Input
ENA 7 Port E Data
AN 7
AN7
VCC3
VSS3
ADCTL.6
SAMPLE
START
ADCTL.7
CONVERT
START
ADDATA.7–0
A-to-D
Conversion
Data Register
ADSTAT.2
AD READY
AD PRIORITY
ADPRI.6
0
1
Level 1 INT
Level 2 INT
AD INT FLAG
ADSTAT.1
AD INT ENA
ADSTAT.0
ADC1
Figure 16. ADC1 Block Diagram
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
instruction set overview
Table 23 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the
‘370Cx5x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode
while the numbers at the left side of the table represent the least significant nibble. The instruction of these two
opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.
For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes
in eight SYSCLK cycles.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•45
Table 23. TMS370 Family Opcode/Instruction Map†
MSN
01 2 3 4 5 6 7 8 9 A B C D E F
0JMP
#ra
2/7
INCW
#ra,Rd
3/11
MOV
Ps,A
2/8
CLRC /
TST A
1/9
MOV
A,B
1/9
MOV
A,Rd
2/7
TRAP
15
1/14
LDST
n
2/6
1JN
ra
2/5
MOV
A,Pd
2/8
MOV
B,Pd
2/8
MOV
Rs,Pd
3/10
MOV
Ps,B
2/7
MOV
B,Rd
2/7
TRAP
14
1/14
MOV
#ra[SP],A
2/7
2JZ
ra
2/5
MOV
Rs,A
2/7
MOV
#n,A
2/6
MOV
Rs,B
2/7
MOV
Rs,Rd
3/9
MOV
#n,B
2/6
MOV
B,A
1/8
MOV
#n,Rd
3/8
MOV
Ps,Rd
3/10
DEC
A
1/8
DEC
B
1/8
DEC
Rd
2/6
TRAP
13
1/14
MOV
A,*ra[SP]
2/7
3JC
ra
2/5
AND
Rs,A
2/7
AND
#n,A
2/6
AND
Rs,B
2/7
AND
Rs,Rd
3/9
AND
#n,B
2/6
AND
B,A
1/8
AND
#n,Rd
3/8
AND
A,Pd
2/9
AND
B,Pd
2/9
AND
#n,Pd
3/10
INC
A
1/8
INC
B
1/8
INC
Rd
2/6
TRAP
12
1/14
CMP
*n[SP],A
2/8
4JP
ra
2/5
OR
Rs,A
2/7
OR
#n,A
2/6
OR
Rs,B
2/7
OR
Rs,Rd
3/9
OR
#n,B
2/6
OR
B,A
1/8
OR
#n,Rd
3/8
OR
A,Pd
2/9
OR
B,Pd
2/9
OR
#n,Pd
3/10
INV
A
1/8
INV
B
1/8
INV
Rd
2/6
TRAP
11
1/14
extend
inst,2
opcodes
L
S
N
5JPZ
ra
2/5
XOR
Rs,A
2/7
XOR
#n,A
2/6
XOR
Rs,B
2/7
XOR
Rs,Rd
3/9
XOR
#n,B
2/6
XOR
B,A
1/8
XOR
#n,Rd
3/8
XOR
A,Pd
2/9
XOR
B,Pd
2/9
XOR
#n,Pd
3/10
CLR
A
1/8
CLR
B
1/8
CLR
Rn
2/6
TRAP
10
1/14
N
6JNZ
ra
2/5
BTJO
Rs,A,ra
3/9
BTJO
#n,A,ra
3/8
BTJO
Rs,B,ra
3/9
BTJO
Rs,Rd,ra
4/11
BTJO
#n,B,ra
3/8
BTJO
B,A,ra
2/10
BTJO
#n,Rd,ra
4/10
BTJO
A,Pd,ra
3/11
BTJO
B,Pd,ra
3/10
BTJO
#n,Pd,ra
4/11
XCHB
A
1/10
XCHB A /
TST B
1/10
XCHB
Rn
2/8
TRAP
9
1/14
IDLE
1/6
7JNC
ra
2/5
BTJZ
Rs.,A,ra
3/9
BTJZ
#n,A,ra
3/8
BTJZ
Rs,B,ra
3/9
BTJZ
Rs,Rd,ra
4/11
BTJZ
#n,B,ra
3/8
BTJZ
B,A,ra
2/10
BTJZ
#n,Rd,ra
4/10
BTJZ
A,Pd,ra
3/10
BTJZ
B,Pd,ra
3/10
BTJZ
#n,Pd,ra
4/11
SWAP
A
1/11
SWAP
B
1/11
SWAP
Rn
2/9
TRAP
8
1/14
MOV
#n,Pd
3/10
8JV
ra
2/5
ADD
Rs,A
2/7
ADD
#n,A
2/6
ADD
Rs,B
2/7
ADD
Rs,Rd
3/9
ADD
#n,B
2/6
ADD
B,A
1/8
ADD
#n,Rd
3/8
MOVW
#16,Rd
4/13
MOVW
Rs,Rd
3/12
MOVW
#16[B],Rpd
4/15
PUSH
A
1/9
PUSH
B
1/9
PUSH
Rd
2/7
TRAP
7
1/14
SETC
1/7
9JL
ra
2/5
ADC
Rs,A
2/7
ADC
#n,A
2/6
ADC
Rs,B
2/7
ADC
Rs,Rd
3/9
ADC
#n,B
2/6
ADC
B,A
1/8
ADC
#n,Rd
3/8
JMPL
lab
3/9
JMPL
*Rp
2/8
JMPL
*lab[B]
3/11
POP
A
1/9
POP
B
1/9
POP
Rd
2/7
TRAP
6
1/14
RTS
1/9
AJLE
ra
2/5
SUB
Rs,A
2/7
SUB
#n,A
2/6
SUB
Rs,B
2/7
SUB
Rs,Rd
3/9
SUB
#n,B
2/6
SUB
B,A
1/8
SUB
#n,Rd
3/8
MOV
& lab,A
3/10
MOV
*Rp,A
2/9
MOV
*lab[B],A
3/12
DJNZ
A,#ra
2/10
DJNZ
B,#ra
2/10
DJNZ
Rd,#ra
3/8
TRAP
5
1/14
RTI
1/12
BJHS
ra
2/5
SBB
Rs,A
2/7
SBB
#n,A
2/6
SBB
Rs,B
2/7
SBB
Rs,Rd
3/9
SBB
#n,B
2/6
SBB
B,A
1/8
SBB
#n,Rd
3/8
MOV
A, & lab
3/10
MOV
A, *Rp
2/9
MOV
A,*lab[B]
3/12
COMPL
A
1/8
COMPL
B
1/8
COMPL
Rd
2/6
TRAP
4
1/14
PUSH
ST
1/8
†All conditional jumps (opcodes 01–0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ
instructions have a relative address as the last operand.
L
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
T
emp
l
ate
R
e
l
ease
D
ate:
7
–
11
–
94
46 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•
Table 23. TMS370 Family Opcode/Instruction Map† (Continued)
MSN
01 2 3 4 5 6 7 8 9 A B C D E F
CJNV
ra
2/5
MPY
Rs,A
2/46
MPY
#n,A
2/45
MPY
Rs,B
2/46
MPY
Rs,Rd
3/48
MPY
#n,B
2/45
MPY
B,A
1/47
MPY
#n,Rs
3/47
BR
lab
3/9
BR
*Rp
2/8
BR
*lab[B]
3/11
RR
A
1/8
RR
B
1/8
RR
Rd
2/6
TRAP
3
1/14
POP
ST
1/8
L
S
DJGE
ra
2/5
CMP
Rs,A
2/7
CMP
#n,A
2/6
CMP
Rs,B
2/7
CMP
Rs,Rd
3/9
CMP
#n,B
2/6
CMP
B,A
1/8
CMP
#n,Rd
3/8
CMP
& lab,A
3/11
CMP
*Rp,A
2/10
CMP
*lab[B],A
3/13
RRC
A
1/8
RRC
B
1/8
RRC
Rd
2/6
TRAP
2
1/14
LDSP
1/7
S
NEJG
ra
2/5
DAC
Rs,A
2/9
DAC
#n,A
2/8
DAC
Rs,B
2/9
DAC
Rs,Rd
3/11
DAC
#n,B
2/8
DAC
B,A
1/10
DAC
#n,Rd
3/10
CALL
lab
3/13
CALL
*Rp
2/12
CALL
*lab[B]
3/15
RL
A
1/8
RL
B
1/8
RL
Rd
2/6
TRAP
1
1/14
STSP
1/8
FJLO
ra
2/5
DSB
Rs,A
2/9
DSB
#n,A
2/8
DSB
Rs,B
2/9
DSB
Rs,Rd
3/11
DSB
#n,B
2/8
DSB
B,A
1/10
DSB
#n,Rd
3/10
CALLR
lab
3/15
CALLR
*Rp
2/14
CALLR
*lab[B]
3/17
RLC
A
1/8
RLC
B
1/8
RLC
Rd
2/6
TRAP
0
1/14
NOP
1/7
Second byte of two-byte instructions (F4xx): F4 8 MOVW
*n[Rn]
4/15
DIV
Rn.A
3/14-63
F4 9 JMPL
*n[Rn]
4/16
Legend:
* = Indirect addressing operand prefix
& = Direct addressing operand prefix F4 A MOV
*n[Rn],A
4/17
# = immediate operand
#16 = immediate 16-bit number
lab = 16-label
i di t 8 bit b
F4 B MOV
A,*n[Rn]
4/16
n = immediate 8-bit number
Pd = Peripheral register containing destination type
Pn = Peripheral register
Ps = Peri
p
heral register containing source byte
F4 C BR
*n[Rn]
4/16
Ps
=
Peri heral
register
containing
source
byte
ra = Relative address
Rd = Register containing destination type
Rn = Re
g
ister file
F4 D CMP
*n[Rn],A
4/18
Rn Register
file
Rp = Register pair
Rpd= Destination register pair
Rps = Source Register pair F4 E CALL
*n[Rn]
4/20
Rs = Register containing source byte F4 F CALLR
*n[Rn]
4/22
†All conditional jumps (opcodes 01–0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ
instructions have a relative address as the last operand.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
development system support
The TMS370 family development support tools include an assembler, a C compiler, a linker, an in-circuit
emulator (XDS/22), CDT, and an EEPROM/UVEPROM programmer.
D
Assembler/linker (Part No. TMDS3740850–02 for PC)
– Includes extensive macro capability
– Features high-speed operation
– Includes format conversion utilities for popular formats
D
ANSI C-Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700, Sun-3
or Sun-4)
– Generates assembly code for the TMS370 that can be inspected easily
– Improves code execution speed and reduces code size with optional optimizer pass
– Enables direct reference of the TMS370’s port registers by using a naming convention
– Provides flexibility in specifying the storage for data objects
– Interfaces C functions and assembly functions easily
– Includes assembler and linker
D
CDT370 (compact development tool) real-time in-circuit emulation
– Base (Part Number EDSCDT370 – for PC, requires cable)
– Cable for 68-pin PLCC (Part No. EDSTRG68PLCC)
– Cable for 64-pin SDIP (Part No. EDSTRG64SDIL)
– Provides EEPROM and EPROM programming support
– Allows inspection and modification of memory locations
– Allows uploading/downloading of program and data memory
– Provides capability to execute programs and software routines
– Includes 1024 samples trace buffer
– Includes single-step executable instructions
– Allows use of software breakpoints to halt program execution at selected address
D
XDS/22 (extended development support) in-circuit emulator
– Base (Part Number TMDS3762210 for PC, requires cable)
– Cable for 68-pin PLCC/64-Pin SDIP (Part No. TMDS3788868)
– Contains all of the features of the CDT370 described above but does not have the capability to program
the data EEPROM and program EPROM
– Contains sophisticated breakpoint trace and timing hardware that provides up to 2047 qualified trace
samples with symbolic disassembly
– Allows breakpoints to be qualified by address and/or data on any type of memory acquisition. Up to four
levels of events can be combined to cause a breakpoint
– Provides timers for analyzing total and average time in routines
HP700 is a trademark of Hewlett-Packard Company.
Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
development system support (continued)
– Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and
for tracing display
D
Microcontroller programmer
– Base (Part No. TMDS3760500A – for PC, requires programmer head)
– Single unit head for 68-pin PLCC (Part No. TMDS3780510A)
– Single unit head for 64-pin SDIP (Part No. TMDS3780511A)
– Personal computer-based, window/ function-key oriented user interface for ease of use and rapid
learning environment
D
Design kit (Part No. TMDS3770110 – for PC)
– Includes TMS370 Application Board and TMS370 Assembler diskette and documentation.
– Supports quick evaluation of TMS370 functionality
– Provides capability to upload and download code
– Provides capability to execute programs and software routines, and to single-step executable
instructions
– Allows software breakpoints to halt program execution at selected addresses
– Includes wire-wrap prototype area
– Includes reverse assembler
D
Starter Kit (Part No. TMDS37000 – For PC)
– Includes TMS370 Assembler diskette and documentation
– Includes TMS370 Simulator
– Includes programming adapter board and programming software
– Does not include – (to be supplied by the user):
– + 5 V power supply
– ZIF sockets
– 9-pin RS232 cable
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device numbering conventions
Figure 17 illustrates the numbering and symbol nomenclature for the TMS370Cx5x family.
7370 5 2C
Prefix: TMS = Standard prefix for fully qualified devices
SE = System evaluator (window EPROM) that is used for
prototyping purpose.
Family: 370 = TMS370 8-Bit Microcontroller Family
Technology: C = CMOS
Program Memory Types: 0 = Mask ROM
1 = ROM-less, No Data EEPROM
2 = ROM-less
3 = Mask ROM, No Data EEPROM
4 = ROM memory with security
7 = EPROM
Device Type: 5 = ’x5x device containing the following modules:
– Timer 1
– Timer 2A
– Serial Peripheral Interface
– Serial Communications Interface 1
– Analog-to-Digital Converter 1
Memory Size: 0 = 4K bytes
2 = 8K bytes
3 = 12K bytes
6 = 16K bytes
8 = 32K Bytes
9 = 48K Bytes
Temperature Ranges: A = –40°Cto 85°C
L= 0°Cto 70°C
T=–40°Cto 105°C
Packages: FN = Plastic Leaded Chip Carrier
FZ = Ceramic Leaded Chip Carrier
NM = Plastic Shrink Dual-In-Line
JN = Ceramic Shrink Dual-in-Line
ROM and EPROM Option: A = For ROM device, the watchdog timer can be configured
as one of the three different mask options:
– A standard watchdog
– A hard watchdog
– A simple watchdog
The clock can be either:
– Divide-by-4 clock
– Divide-by-1 (PLL) clock
The low-power modes can be either:
– Enabled
– Disabled
A = For ROM-less device, a standard watchdog, a divide-by-4
clock, and low-power modes are enabled.
A = For EPROM device, a standard watchdog, a divide-by-4
clock, and low-power modes are enabled.
B = For EPROM device, a hard watchdog, a divide-by-1
(PLL) clock, and low-power modes are enabled.
TMS AFNT
Figure 17. TMS370Cx5x Family Nomenclature
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device part numbers
Table 24 provides a list of all the ‘x5x devices available. The device part number nomenclature is designed to
assist ordering. Upon ordering, the customer must specify not only the device part number but also the clock
and watchdog timer options desired. Remember that each device can have only one of the three possible
watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders
involving ROM devices.
Table 24. Device Part Numbers
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
DEVICE PART NUMBERS
FOR 68 PINS
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
DEVICE PART NUMBERS
FOR 64 PINS
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
DEVICE PART NUMBERS
FOR 68 PINS
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
DEVICE PART NUMBERS
FOR 64 PINS
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C050AFNA
TMS370C050AFNL
TMS370C050AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C050ANMA
TMS370C050ANML
TMS370C050ANMT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C356AFNA
TMS370C356AFNL
TMS370C356AFNT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C356ANMA
TMS370C356ANML
TMS370C356ANMT
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C150AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C456AFNA
TMS370C456AFNL
TMS370C456AFNT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁÁ
TMS370C250AFNT
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁ
TMS370C756AFNT
ÁÁÁÁÁÁÁÁÁ
TMS370C756ANMT
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C350AFNA
TMS370C350AFNL
TMS370C350AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C350ANMA
TMS370C350ANML
TMS370C350ANMT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C058AFNA
TMS370C058AFNL
TMS370C058AFNT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C058ANMA
TMS370C058ANML
TMS370C058ANMT
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C052AFNA
TMS370C052AFNL
TMS370C052AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C052ANMA
TMS370C052ANML
TMS370C052ANMT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C358AFNA
TMS370C358AFNL
TMS370C358AFNT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C358ANMA
TMS370C358ANML
TMS370C358ANMT
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C352AFNA
TMS370C352AFNL
TMS370C352AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C352ANMA
TMS370C352ANML
TMS370C352ANMT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C758AFNT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C758ANMT
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C452AFNA
TMS370C452AFNL
TMS370C452AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C758BFNT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C758BNMT
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C353AFNA
TMS370C353AFNL
TMS370C353AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C059AFNA†
TMS370C059AFNL†
TMS370C059AFNT†
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C056AFNA
TMS370C056AFNL
TMS370C056AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C056ANMA
TMS370C056ANML
TMS370C056ANMT
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
TMS370C759AFNT†
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
TMS370C156AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
SE370C756AFZT‡
SE370C758AFZT‡
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
SE370C756AJNT‡
SE370C758AJNT‡
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
TMS370C256AFNT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
SE370C758BFZT‡
SE370C759AFZT†‡
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
SE370C758AJNT‡
SE370C758BJNT‡
†Only operate up to 3 MHz SYSCLK
‡System evaluators are for use only in prototype environment, and their reliability has not been characterized.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
new code release form
Figure 18 shows a sample of the new code release form.
NEW CODE RELEASE FORM
TEXAS INSTRUMENTS
TMS370 MICROCONTROLLER PRODUCTS DA TE:
To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:
1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)
2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.
Company Name:
Street Address:
Street Address:
City: State Zip
Contact Mr ./Ms.:
Phone: ( ) Ext.:
Customer Purchase Order Number:
Customer Part Number:
Customer Application: Customer Print Number *Yes: #
No: (Std. spec to be followed)
*If Y es: Customer must provide ”print” to TI w/NCRF for approval before ROM
code processing starts.
TMS370 Device:
TI Customer ROM Number:
(provided by Texas Instruments) CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS
OSCILLATOR FREQUENCY MIN TYP MAX
[] External Drive (CLKIN)
[] Crystal
[] Ceramic Resonator
Low Power Modes
[] Enabled
[] Disabled
W atchdog counter
[] Standard
[] Hard Enabled
[] Simple Counter
Clock Type
[] Standard (/4)
[] PLL (/1)
[] Supply Voltage MIN: MAX:
(std range: 4.5V to 5.5V)
NOTE:
Non ’A’ version ROM devices of the TMS370 microcontrollers will have the
“Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog
options. See the
TMS370 Family User’s Guide
(literature number SPNU127)
or the
TMS370 Family Data Manual
(literature number SPNS014B).
TEMPERATURE RANGE
[] ’L’: 0° to 70°C (standard)
[] ’A’: –40° to 85°C
[] ’T’: –40° to 105°C
PACKAGE TYPE
[] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC
[] “FN” 28-pin PLCC [] “FN” 68-pin PLCC
[] “N” 40-pin PDIP [] “NM” 64-pin PSDIP
[] “NJ” 40-pin PSDIP (formerly known as N2)
SYMBOLIZATION BUS EXPANSION
[] TI standard symbolization
[] TI standard w/customer part number
[] Customer symbolization
(per attached spec, subject to approval)
[] YES [] NO
NON-STANDARD SPECIFICA TIONS:
ALL NON-ST ANDARDS SPECIFICA TIONS MUST BE APPROVED BY THE TI ENGINEERING ST AFF: If the customer requires expedited production material
(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the
satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard
TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the
TI part number.
RELEASE AUTHORIZA TION:
This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must
be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification
code is approved by the customer.
1. Customer: Date: 2. TI: Field Sales:
Marketing:
Prod. Eng.:
Proto. Release:
Figure 18. Sample New Code Release Form
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table 25 is a listing of all the peripheral file frames using the ’Cx5x (provided for a quick reference).
Table 25. Peripheral File Frame Compilation
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
PF
ÁÁÁÁÁ
BIT 7
ÁÁÁÁ
BIT 6
ÁÁÁÁÁ
BIT 5
ÁÁÁÁ
BIT 4
ÁÁÁÁ
BIT 3
ÁÁÁÁÁ
BIT 2
ÁÁÁÁ
BIT 1
ÁÁÁÁÁ
BIT 0
ÁÁÁÁ
REG
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SYSTEM CONFIGURATION REGISTERS
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P010
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
COLD
START OSC
POWER PF AUTO
WAIT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
OSC FLT
FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
MC PIN
WPO
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
MC PIN
DATA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
µP/µC
MODE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCCR0
ÁÁÁ
ÁÁÁ
P011
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—AUTOWAIT
DISABLE
ÁÁÁÁ
ÁÁÁÁ
—MEMORY
DISABLE
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
SCCR1
ÁÁÁ
Á
Á
Á
ÁÁÁ
P012 HALT/
STANDBY PWRDWN/
IDLE
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—BUS
STEST CPU
STEST
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—INT1
NMI PRIVILEGE
DISABLE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCCR2
ÁÁÁ
ÁÁÁ
P013 Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P014
ÁÁÁÁÁ
ÁÁÁÁÁ
BUSY
ÁÁÁÁ
ÁÁÁÁ
VPPS
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
W0
ÁÁÁÁÁ
ÁÁÁÁÁ
EXE
ÁÁÁÁ
ÁÁÁÁ
EPCTLH
ÁÁÁ
Á
Á
Á
ÁÁÁ
P015
to
P016 Reserved
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P017
ÁÁÁÁÁ
ÁÁÁÁÁ
INT1
FLAG
ÁÁÁÁ
ÁÁÁÁ
INT1
PIN DATA
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
INT1
POLARITY
ÁÁÁÁ
ÁÁÁÁ
INT1
PRIORITY
ÁÁÁÁÁ
ÁÁÁÁÁ
INT1
ENABLE
ÁÁÁÁ
ÁÁÁÁ
INT1
ÁÁÁ
Á
Á
Á
ÁÁÁ
P018
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT2
FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
PIN DATA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
DATA DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
DATA OUT
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT2
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
PRIORITY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
INT2
ENABLE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
INT2
ÁÁÁ
ÁÁÁ
P019
ÁÁÁÁÁ
ÁÁÁÁÁ
INT3
FLAG
ÁÁÁÁ
ÁÁÁÁ
INT3
PIN DATA
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
INT3
DATA DIR
ÁÁÁÁ
ÁÁÁÁ
INT3
DATA OUT
ÁÁÁÁÁ
ÁÁÁÁÁ
INT3
POLARITY
ÁÁÁÁ
ÁÁÁÁ
INT3
PRIORITY
ÁÁÁÁÁ
ÁÁÁÁÁ
INT3
ENABLE
ÁÁÁÁ
ÁÁÁÁ
INT3
ÁÁÁ
ÁÁÁ
P01A
ÁÁÁÁÁ
ÁÁÁÁÁ
BUSY
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
AP
ÁÁÁÁ
ÁÁÁÁ
W1W0
ÁÁÁÁÁ
ÁÁÁÁÁ
EXE
ÁÁÁÁ
ÁÁÁÁ
DEECTL
ÁÁÁ
ÁÁÁ
P01B Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P01C
ÁÁÁÁÁ
ÁÁÁÁÁ
BUSY
ÁÁÁÁ
ÁÁÁÁ
VPPS
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
W0
ÁÁÁÁÁ
ÁÁÁÁÁ
EXE
ÁÁÁÁ
ÁÁÁÁ
EPCTLM
ÁÁÁ
ÁÁÁ
P01D Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P01E
ÁÁÁÁÁ
ÁÁÁÁÁ
BUSY
ÁÁÁÁ
ÁÁÁÁ
VPPS
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
W0
ÁÁÁÁÁ
ÁÁÁÁÁ
EXE
ÁÁÁÁ
ÁÁÁÁ
EPCTLL
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DIGITAL PORT CONTROL REGISTERS
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
P01F Reserved
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P020
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
APORT1
ÁÁÁ
ÁÁÁ
P021
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port A Control Register 2
ÁÁÁÁ
ÁÁÁÁ
APORT2
ÁÁÁ
ÁÁÁ
P022
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port A Data
ÁÁÁÁ
ÁÁÁÁ
ADATA
ÁÁÁ
ÁÁÁ
P023
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port A Direction
ÁÁÁÁ
ÁÁÁÁ
ADIR
ÁÁÁ
ÁÁÁ
P024
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
BPORT1
ÁÁÁ
ÁÁÁ
P025
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port B Control Register 2
ÁÁÁÁ
ÁÁÁÁ
BPORT2
ÁÁÁ
ÁÁÁ
P026
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port B Data
ÁÁÁÁ
ÁÁÁÁ
BDATA
ÁÁÁ
ÁÁÁ
P027
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port B Direction
ÁÁÁÁ
ÁÁÁÁ
BDIR
ÁÁÁ
P028
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
CPORT1
ÁÁÁ
ÁÁÁ
P029
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port C Control Register 2
ÁÁÁÁ
ÁÁÁÁ
CPORT2
ÁÁÁ
ÁÁÁ
P02A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port C Data
ÁÁÁÁ
ÁÁÁÁ
CDATA
ÁÁÁ
ÁÁÁ
P02B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port C Direction
ÁÁÁÁ
ÁÁÁÁ
CDIR
ÁÁÁ
ÁÁÁ
P02C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port D Control Register 1
ÁÁÁÁ
ÁÁÁÁ
DPORT1
ÁÁÁ
ÁÁÁ
P02D
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port D Control Register 2†
ÁÁÁÁ
ÁÁÁÁ
DPORT2
ÁÁÁ
ÁÁÁ
P02E
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port D Data
ÁÁÁÁ
ÁÁÁÁ
DDATA
ÁÁÁ
ÁÁÁ
P02F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port D Direction
ÁÁÁÁ
ÁÁÁÁ
DDIR
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
†To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table 25. Peripheral File Frame Compilation (Continued)
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
PF
ÁÁÁÁ
ÁÁÁÁ
BIT 7
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 6
ÁÁÁÁ
ÁÁÁÁ
BIT 5
ÁÁÁÁ
ÁÁÁÁ
BIT 4
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 3
ÁÁÁÁ
ÁÁÁÁ
BIT 2
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 1
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 0
ÁÁÁ
ÁÁÁ
REG
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SPI MODULE CONTROL REGISTER
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P030
ÁÁÁÁ
ÁÁÁÁ
SPI SW
RESET
ÁÁÁÁÁ
ÁÁÁÁÁ
CLOCK
POLARITY
ÁÁÁÁ
ÁÁÁÁ
SPI BIT
RATE2
ÁÁÁÁ
ÁÁÁÁ
SPI BIT
RATE1
ÁÁÁÁÁ
ÁÁÁÁÁ
SPI BIT
RATE0
ÁÁÁÁ
ÁÁÁÁ
SPI
CHAR2
ÁÁÁÁÁ
ÁÁÁÁÁ
SPI
CHAR1
ÁÁÁÁÁ
ÁÁÁÁÁ
SPI
CHAR0
ÁÁÁ
ÁÁÁ
SPICCR
ÁÁÁ
Á
Á
Á
ÁÁÁ
P031
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RECEIVER
OVERRUN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPI INT
FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
MASTER/
SLAVE
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
TALK
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPI INT
ENA
ÁÁÁ
Á
Á
Á
ÁÁÁ
SPICTL
ÁÁÁ
Á
Á
Á
ÁÁÁ
P032
to
P036 Reserved
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁÁ
ÁÁÁ
P037
ÁÁÁÁ
ÁÁÁÁ
RCVD7
ÁÁÁÁÁ
ÁÁÁÁÁ
RCVD6
ÁÁÁÁ
ÁÁÁÁ
RCVD5
ÁÁÁÁ
ÁÁÁÁ
RCVD4
ÁÁÁÁÁ
ÁÁÁÁÁ
RCVD3
ÁÁÁÁ
ÁÁÁÁ
RCVD2
ÁÁÁÁÁ
ÁÁÁÁÁ
RCVD1
ÁÁÁÁÁ
ÁÁÁÁÁ
RCVD0
ÁÁÁ
ÁÁÁ
SPIBUF
ÁÁÁ
ÁÁÁ
P038 Reserved
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P039
ÁÁÁÁ
ÁÁÁÁ
SDAT7
ÁÁÁÁÁ
ÁÁÁÁÁ
SDAT6
ÁÁÁÁ
ÁÁÁÁ
SDAT5
ÁÁÁÁ
ÁÁÁÁ
SDAT4
ÁÁÁÁÁ
ÁÁÁÁÁ
SDAT3
ÁÁÁÁ
ÁÁÁÁ
SDAT2
ÁÁÁÁÁ
ÁÁÁÁÁ
SDAT1
ÁÁÁÁÁ
ÁÁÁÁÁ
SDAT0
ÁÁÁ
ÁÁÁ
SPIDAT
ÁÁÁ
Á
Á
Á
ÁÁÁ
P03A
to
P03C Reserved
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁÁ
ÁÁÁ
P03D
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
SPICLK
DATA IN
ÁÁÁÁ
ÁÁÁÁ
SPICLK
DATA OUT
ÁÁÁÁÁ
ÁÁÁÁÁ
SPICLK
FUNCTION
ÁÁÁÁÁ
ÁÁÁÁÁ
SPICLK
DATA DIR
ÁÁÁ
ÁÁÁ
SPIPC1
ÁÁÁ
Á
Á
Á
ÁÁÁ
P03E
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SPISIMO
DATA IN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPISIMO
DATA OUT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SPISIMO
FUNCTION
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SPISIMO
DATA DIR
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPISOMI
DATA IN
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SPISOMI
DATA OUT
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPISOMI
FUNCTION
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SPISOMI DATA
DIR
ÁÁÁ
Á
Á
Á
ÁÁÁ
SPIPC2
ÁÁÁ
ÁÁÁ
P03F SPI
STEST SPI
PRIORITY SPI
ESPEN
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
SPIPRI
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
TIMER 1 MODULE REGISTER
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Capture/Compare
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P040
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T1 Counter MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁ
ÁÁÁ
T1CNTR
ÁÁÁ
ÁÁÁ
P041
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T1 Counter LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P042
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compare Register MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁ
ÁÁÁ
T1C
ÁÁÁ
ÁÁÁ
P043
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compare Register LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
ÁÁÁ
P044
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture/Compare Register MSbyte
ÁÁÁÁÁ
Bit 8
ÁÁÁ
T1CC
ÁÁÁ
ÁÁÁ
P045
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture/Compare Register LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P046
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
W atchdog Counter MSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 8
ÁÁÁ
ÁÁÁ
WDCNTR
ÁÁÁ
ÁÁÁ
P047
ÁÁÁÁ
ÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
W atchdog Counter LSbyte
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P048
ÁÁÁÁ
ÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
W atchdog Reset Key
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 0
ÁÁÁ
ÁÁÁ
WDRST
ÁÁÁ
Á
Á
Á
ÁÁÁ
P049
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
WD OVRFL
TAP SEL†
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
WD
INPUT
SELECT2†
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
WD
INPUT
SELECT1†
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
WD
INPUT
SELECT0†
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1
INPUT
SELECT2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1
INPUT
SELECT1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1 INPUT
SELECT0
ÁÁÁ
Á
Á
Á
ÁÁÁ
T1CTL1
ÁÁÁ
Á
Á
Á
ÁÁÁ
P04A
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
WD OVRFL
RST ENA†
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
WD OVRFL
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
WD OVRFL
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1 OVRFL
INT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1 OVRFL
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1 SW
RESET
ÁÁÁ
Á
Á
Á
ÁÁÁ
T1CTL2
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Dual-Compare
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P04B
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EDGE
INT FLAG
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1C2
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1C1
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EDGE
INT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1C2
INT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1C1
INT ENA
ÁÁÁ
Á
Á
Á
ÁÁÁ
T1CTL3
ÁÁÁ
Á
Á
Á
P04C
ÁÁÁÁ
Á
ÁÁ
Á
T1
MODE = 0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
T1C1
OUT ENA
ÁÁÁÁ
Á
ÁÁ
Á
T1C2
OUT ENA
ÁÁÁÁ
Á
ÁÁ
Á
T1C1
RST ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
T1CR
OUT ENA
ÁÁÁÁ
Á
ÁÁ
Á
T1EDGE
POLARITY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
T1CR
RST ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
T1EDGE
DET ENA
ÁÁÁ
Á
Á
Á
T1CTL4
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Capture/Compare
ÁÁÁ
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P04B
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EDGE
INT FLAG
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1C1
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EDGE
INT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1C1
INT ENA
ÁÁÁ
Á
Á
Á
ÁÁÁ
T1CTL3
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
†Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table 25. Peripheral File Frame Compilation (Continued)
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
PF
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 7
ÁÁÁÁ
ÁÁÁÁ
BIT 6
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 5
ÁÁÁÁ
ÁÁÁÁ
BIT 4
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 3
ÁÁÁÁ
ÁÁÁÁ
BIT 2
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 1
ÁÁÁÁ
ÁÁÁÁ
BIT 0
ÁÁÁÁ
ÁÁÁÁ
REG
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Capture/Compare (Continued)
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P04C
ÁÁÁÁÁ
ÁÁÁÁÁ
T1
MODE = 1
ÁÁÁÁ
ÁÁÁÁ
T1C1
OUT ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
T1C1
RST ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
T1EDGE
POLARITY
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
T1EDGE
DET ENA
ÁÁÁÁ
ÁÁÁÁ
T1CTL4
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Capture/Compare
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P04D
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1EVT DATA
IN
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EVT DATA
OUT
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T1EVT
FUNCTION
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1EVT DATA
DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1PC1
ÁÁÁ
ÁÁÁ
P04E
ÁÁÁÁÁ
ÁÁÁÁÁ
T1PWM
DATA IN
ÁÁÁÁ
ÁÁÁÁ
T1PWM
DATA OUT
ÁÁÁÁÁ
ÁÁÁÁÁ
T1PWM
FUNCTION
ÁÁÁÁ
ÁÁÁÁ
T1PWM
DATA DIR
ÁÁÁÁÁ
ÁÁÁÁÁ
T1IC/CR
DATA IN
ÁÁÁÁ
ÁÁÁÁ
T1IC/CR
DATA OUT
ÁÁÁÁÁ
ÁÁÁÁÁ
T1IC/CR
FUNCTION
ÁÁÁÁ
ÁÁÁÁ
T1IC/CR
DATA DIR
ÁÁÁÁ
ÁÁÁÁ
T1PC2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P04F T1 STEST T1
PRIORITY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T1PRI
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SCI1 MODULE CONTROL REGISTER
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P050
ÁÁÁÁÁ
ÁÁÁÁÁ
STOP BITS
ÁÁÁÁ
ÁÁÁÁ
EVEN/ODD
PARITY
ÁÁÁÁÁ
ÁÁÁÁÁ
PARITY
ENABLE
ÁÁÁÁ
ÁÁÁÁ
ASYNC/
ISOSYNC
ÁÁÁÁÁ
ÁÁÁÁÁ
ADDRESS/
IDLE WUP
ÁÁÁÁ
ÁÁÁÁ
SCI CHAR2
ÁÁÁÁÁ
ÁÁÁÁÁ
SCI CHAR1
ÁÁÁÁ
ÁÁÁÁ
SCI CHAR0
ÁÁÁÁ
ÁÁÁÁ
SCICCR
ÁÁÁ
Á
Á
Á
ÁÁÁ
P051
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCI SW
RESET
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
CLOCK
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
TXWAKE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SLEEP
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
TXENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RXENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCICTL
ÁÁÁ
ÁÁÁ
P052
ÁÁÁÁÁ
ÁÁÁÁÁ
BAUDF
(MSB)
ÁÁÁÁ
ÁÁÁÁ
BAUDE
ÁÁÁÁÁ
ÁÁÁÁÁ
BAUDD
ÁÁÁÁ
ÁÁÁÁ
BAUDC
ÁÁÁÁÁ
ÁÁÁÁÁ
BAUDB
ÁÁÁÁ
ÁÁÁÁ
BAUDA
ÁÁÁÁÁ
ÁÁÁÁÁ
BAUD9
ÁÁÁÁ
ÁÁÁÁ
BAUD8
ÁÁÁÁ
ÁÁÁÁ
BAUD
MSB
ÁÁÁ
Á
Á
Á
ÁÁÁ
P053
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BAUD7
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD6
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BAUD5
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD4
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BAUD3
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BAUD1
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD0
(LSB)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
BAUD
LSB
ÁÁÁ
ÁÁÁ
P054
ÁÁÁÁÁ
ÁÁÁÁÁ
TXRDY
ÁÁÁÁ
ÁÁÁÁ
TX EMPTY
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
SCI TX
INT ENA
ÁÁÁÁ
ÁÁÁÁ
TXCTL
ÁÁÁ
Á
Á
Á
ÁÁÁ
P055
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RX
ERROR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RXRDY
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BRKDT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
FE
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
OE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
PE
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RXWAKE
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCI RX
INT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
RXCTL
ÁÁÁ
ÁÁÁ
P056
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
P057
ÁÁÁÁÁ
RXDT7
ÁÁÁÁ
RXDT6
ÁÁÁÁÁ
RXDT5
ÁÁÁÁ
RXDT4
ÁÁÁÁÁ
RXDT3
ÁÁÁÁ
RXDT2
ÁÁÁÁÁ
RXDT1
ÁÁÁÁ
RXDT0
ÁÁÁÁ
RXBUF
ÁÁÁ
ÁÁÁ
P058
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
P059
ÁÁÁÁÁ
ÁÁÁÁÁ
TXDT7
ÁÁÁÁ
ÁÁÁÁ
TXDT6
ÁÁÁÁÁ
ÁÁÁÁÁ
TXDT5
ÁÁÁÁ
ÁÁÁÁ
TXDT4
ÁÁÁÁÁ
ÁÁÁÁÁ
TXDT3
ÁÁÁÁ
ÁÁÁÁ
TXDT2
ÁÁÁÁÁ
ÁÁÁÁÁ
TXDT1
ÁÁÁÁ
ÁÁÁÁ
TXDT0
ÁÁÁÁ
ÁÁÁÁ
TXBUF
ÁÁÁ
Á
Á
Á
ÁÁÁ
P05A
P05B
P05C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P05D
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCICLK
DATA IN
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCICLK
DATA OUT
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCICLK
FUNCTION
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCICLK
DATA DIR
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCIPC1
ÁÁÁ
ÁÁÁ
P05E
ÁÁÁÁÁ
ÁÁÁÁÁ
SCITXD
DATA IN
ÁÁÁÁ
ÁÁÁÁ
SCITXD
DATA OUT
ÁÁÁÁÁ
ÁÁÁÁÁ
SCITXD
FUNCTION
ÁÁÁÁ
ÁÁÁÁ
SCITXD
DATA DIR
ÁÁÁÁÁ
ÁÁÁÁÁ
SCIRXD
DATA IN
ÁÁÁÁ
ÁÁÁÁ
SCIRXD
DATA OUT
ÁÁÁÁÁ
ÁÁÁÁÁ
SCIRXD
FUNCTION
ÁÁÁÁ
ÁÁÁÁ
SCIRXD
DATA DIR
ÁÁÁÁ
ÁÁÁÁ
SCIPC2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P05F SCI STEST SCITX
PRIORITY SCIRX
PRIORITY SCI
ESPEN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
SCIPRI
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T2A MODULE REGISTER
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Dual-Capture
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
P060
ÁÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T2A Counter MSbyte
ÁÁÁÁ
Bit 8
ÁÁÁÁ
T2ACNTR
ÁÁÁ
ÁÁÁ
P061
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T2A Counter LSbyte
ÁÁÁÁ
ÁÁÁÁ
Bit 0
ÁÁÁÁ
ÁÁÁÁ
T2ACNTR
ÁÁÁ
ÁÁÁ
P062
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compare Register MSbyte
ÁÁÁÁ
ÁÁÁÁ
Bit 8
ÁÁÁÁ
ÁÁÁÁ
T2AC
ÁÁÁ
ÁÁÁ
P063
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compare Register LSbyte
ÁÁÁÁ
ÁÁÁÁ
Bit 0
ÁÁÁÁ
ÁÁÁÁ
T2AC
ÁÁÁ
ÁÁÁ
P064
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture/Compare Register MSbyte
ÁÁÁÁ
ÁÁÁÁ
Bit 8
ÁÁÁÁ
ÁÁÁÁ
T2ACC
ÁÁÁ
ÁÁÁ
P065
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture/Compare Register LSbyte
ÁÁÁÁ
ÁÁÁÁ
Bit 0
ÁÁÁÁ
ÁÁÁÁ
T2ACC
ÁÁÁ
ÁÁÁ
P066
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 15
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture Register 2 MSbyte
ÁÁÁÁ
ÁÁÁÁ
Bit 8
ÁÁÁÁ
ÁÁÁÁ
T2AIC
ÁÁÁ
ÁÁÁ
P067
ÁÁÁÁÁ
ÁÁÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capture Register 2 LSbyte
ÁÁÁÁ
ÁÁÁÁ
Bit 0
ÁÁÁÁ
ÁÁÁÁ
T2AIC
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table 25. Peripheral File Frame Compilation (Continued)
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
PF
ÁÁÁÁ
ÁÁÁÁ
BIT 7
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 6
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 5
ÁÁÁÁ
ÁÁÁÁ
BIT 4
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 3
ÁÁÁÁ
ÁÁÁÁ
BIT 2
ÁÁÁÁ
ÁÁÁÁ
BIT 1
ÁÁÁÁÁ
ÁÁÁÁÁ
BIT 0
ÁÁÁ
ÁÁÁ
REG
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Dual-Capture (Continued)
ÁÁÁ
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06A
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A OVRFL-
INT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2A OVRFL
INT FLAG
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A
INPUT
SELECT1
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A INPUT
SELECT0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2A SW
RESET
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2ACTL1
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Dual-Compare
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P06B
ÁÁÁÁ
ÁÁÁÁ
T2AEDGE1
INT FLAG
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AC2
INT FLAG
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AC1
INT FLAG
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
T2AEDGE1
INT ENA
ÁÁÁÁ
ÁÁÁÁ
T2AC2
INT ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AC1
INT ENA
ÁÁÁ
ÁÁÁ
T2ACTL2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06C
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A
MODE = 0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AC1
OUT ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AC2
OUT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AC1
RST ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AEDGE1
OUT ENA
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
RST ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AEDGE1
DET ENA
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2ACTL3
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Dual-Capture
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P06B
ÁÁÁÁ
ÁÁÁÁ
T2AEDGE1
INT FLAG
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AEDGE2
INT FLAG
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AC1
INT FLAG
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
T2AEDGE1
INT ENA
ÁÁÁÁ
ÁÁÁÁ
T2AEDGE2
INT ENA
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AC1
INT ENA
ÁÁÁ
ÁÁÁ
T2ACTL2
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06C
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2A
MODE = 1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
—
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AC1
RST ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AEDGE2
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE1
POLARITY
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AEDGE2
DET ENA
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AEDGE1
DET ENA
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2ACTL3
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Modes: Dual-Compare and Dual-Capture
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
P06D
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AEVT
DATA IN
ÁÁÁÁ
ÁÁÁÁ
T2AEVT
DATA OUT
ÁÁÁÁ
ÁÁÁÁ
T2AEVT
FUNCTION
ÁÁÁÁÁ
ÁÁÁÁÁ
T2AEVT
DATA DIR
ÁÁÁ
ÁÁÁ
T2APC1
ÁÁÁ
Á
Á
Á
ÁÁÁ
P06E
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AIC2/PWM
DATA IN
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AIC2/PWM
DATA OUT
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AIC2/PWM
FUNCTION
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AIC2/PWM
DATA DIR
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AIC1/CR
DATA IN
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AIC1/CR
DATA OUT
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
T2AIC1/CR
FUNCTION
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
T2AIC1/CR
DATA DIR
ÁÁÁ
Á
Á
Á
ÁÁÁ
T2APC2
ÁÁÁ
ÁÁÁ
P06F T2A STEST T2A
PRIORITY
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
T2APRI
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ADC1 MODULE CONTROL REGISTER
ÁÁÁ
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
P070
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
CONVERT
START
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SAMPLE
START
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
REF VOLT
SELECT2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
REF VOLT
SELECT1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
REF VOLT
SELECT0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
AD INPUT
SELECT2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
AD INPUT
SELECT1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
AD INPUT
SELECT0
ÁÁÁ
Á
Á
Á
ÁÁÁ
ADCTL
ÁÁÁ
ÁÁÁ
P071
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
AD READY
ÁÁÁÁ
ÁÁÁÁ
AD INT
FLAG
ÁÁÁÁÁ
ÁÁÁÁÁ
AD INT ENA
ÁÁÁ
ÁÁÁ
ADSTAT
ÁÁÁ
ÁÁÁ
P072
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
A-to-D Conversion Data Register
ÁÁÁ
ÁÁÁ
ADDATA
ÁÁÁ
Á
Á
Á
ÁÁÁ
P073
to
P07C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁÁ
ÁÁÁ
P07D
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port E Data Input Register
ÁÁÁ
ÁÁÁ
ADIN
ÁÁÁ
ÁÁÁ
P07E
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Port E Input Enable Register
ÁÁÁ
ÁÁÁ
ADENA
ÁÁÁ
ÁÁÁ
P07F AD STEST AD
PRIORITY AD ESPEN
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁ
ÁÁÁ
ADPRI
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range,VCC1‡, VCC2, VCC3 (see Note 2) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, All pins except MC –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current per buffer, IO (VO = 0 to VCC1)§ ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum ICC current 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum ISS current – 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A version – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T version – 40°C to 105°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
‡VCC1 = VCC
§Electrical characteristics are specified with all output buffers loaded with specified I O current. Exceeding the specified IO current in any buf fer
can affect the levels on other buffers.
NOTE 2: Unless otherwise noted, all voltage values are with respect to VSS1.
recommended operating conditions
MIN NOM MAX UNIT
VCC1
Supply voltage (see Note 2) 4.5 5 5.5
V
V
CC1 RAM data-retention supply voltage (see Note 3) 3 5.5
V
VCC2 Digital I/O supply voltage (see Note 2) 4.5 5 5.5
V
VCC3 Analog supply voltage (see Note 2) 4.5 5 5.5
V
VSS2 Digital I/O supply ground – 0.3 0 0.3 V
VSS3 Analog supply ground – 0.3 0 0.3 V
VIL
Low level in
p
ut voltage
All pins except MC VSS1 0.8 V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
MC, normal operation VSS1 0.3 V
All pins except MC, XTAL2/CLKIN, and
RESET 2 VCC1
V
IH
High-level input voltage MC (non-WPO mode) VCC1–0.3 VCC1+0.3 V
IH
gg
XTAL2/CLKIN 0.8 VCC1 VCC1
RESET 0.7 VCC1 VCC1
EEPROM write protect override (WPO) 11.7 12 13
VMC
MC (mode control) voltage EPROM programming voltage (VPP)13 13.2 13.5
V
V
MC
()g
(see Note 4) Microprocessor VCC1–0.3 VCC1+0.3
V
Microcomputer VSS1 0.3
L version 0 70
TAOperating free-air temperature A version – 40 85 °C
T version – 40 105
NOTES: 2. Unless otherwise noted, all voltage values are with respect to VSS1.
3. RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range.
4. The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin
two system-clock cycles (tc) before RESET goes inactive (high). The WPO mode can be selected anytime a sufficient voltage is
present on MC.
electrical characteristics over recommended operating free-air temperature range (unless
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage (see Note 5) IOL = 1.4 mA 0.4 V
VOH
High level out
p
ut voltage
IOH = –50 µA0.9 VCC1
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
IOH = –2 mA 2.4
V
0 V < VI ≤ 0.3 V 10
0.3 V < VI < VCC1–0.3 V 50
µA
II
In
p
ut current
MC VCC1–0.3 V ≤ VI ≤ VCC1+0.3 V 10 µ
A
I
I
Inp
u
t
c
u
rrent
VCC1 + 0.3 V < VI ≤ 13 V 650
12 V ≤ VI ≤ 13 V See Note 6 50 mA
I/O pins 0 V ≤ VI ≤ VCC1 ± 10 µA
IOL Low-level output current (see Note 5) VOL = 0.4 V 1.4 mA
IOH
High level out
p
ut current
VOH = 0.9 VCC1 – 50 µA
I
OH
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
VOH = 2.4 V – 2 mA
TMS370Cx50A
TMS370Cx52A 30 45
Supply current
(id)
TMS370Cx53A
TMS370Cx56A
TMS370Cx58A
TMS370Cx58B
SYSCLK = 5 MHz See Notes 7 and 8 35 56
(operating mode)
OSC POWER bit = 0
(see Note 9)
TMS370Cx50A
TMS370Cx52A 20 30 mA
(see
Note
9)
TMS370Cx53A
TMS370Cx56A
TMS370Cx58A
TMS370Cx58B
SYSCLK = 3 MHz See Notes 7 and 8 25 36
TMS370Cx59A†46 55
ICC
Sl t
TMS370Cx50A
TMS370Cx52A 511
Supply current
(operating mode)
OSC POWER bit = 0
(see Note 9)
TMS370Cx53A
TMS370Cx56A
TMS370Cx58A
TMS370Cx58B
SYSCLK = 0.5 MHz See Notes 7 and 8 13 18 mA
TMS370Cx59A†22 28
S l t (STANDBY d )
SYSCLK = 5 MHz, See Notes 7 and 8 12 17
Supply current (STANDBY mode)
OSC POWER bit = 0 (see Note 10)
SYSCLK = 3 MHz, See Notes 7 and 8 811 mA
OSC
POWER
bit
=
0
(see
Note
10)
SYSCLK = 0.5 MHz, See Notes 7 and 8 2.5 3.5
Supply current (STANDBY mode) SYSCLK = 3 MHz, See Notes 7 and 8 6 8.6
mA
y( )
OSC POWER bit = 1 (see Note 11) SYSCLK = 0.5 MHz, See Notes 7 and 8 2 3
mA
Supply current (HALT mode) XTAL2/CLKIN < 0.2 V, See Note 7 2 30 µA
†TMS370Cx59 only operate up to 3 MHz SYSCLK
NOTES: 5. In prior versions of the TMS370 family, the IOL current was equal to 2 mA for ports A, B, C, and D and the RESET pin.
6. Input current IPP is a maximum of 50 mA only when the EPROM is being programmed.
7. Single chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ VCC – 0.2V.
8. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current
can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance
in pF).
9. Maximum operating current for TMS370Cx50A and TMS370Cx52A = 7.6 (SYSCLK) + 7 mA. Maximum operating current for
TMS370Cx53A, TMS370Cx56A, TMS370Cx58A, and TMS370Cx58B = 10 (SYSCLK) + 5.8 mA.
10. Maximum standby current for TMS370Cx5xA = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).
1 1. Maximum standby current for TMS370Cx5xA and TMS370Cx5xB = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, valid only up
to 3 MHz of SYSCLK.)
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
External
Clock Signal
XTAL1XTAL2/CLKIN
C2
(see Note B)
C1
(see Note B) Crystal/Ceramic
Resonator
(see Note A)
XTAL1XTAL2/CLKIN
C3
(see Note B)
NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.
B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic
resonators.
Figure 19. Recommended Crystal/Clock Connections
1.2 kΩ
20 pF
VO
Load Voltage
Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V
Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V
NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN
driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.
Figure 20. Typical Output Load Circuit (see Note A)
VCC
GND
300 Ω
20 Ω
I/O
Pin Data
Output
Enable
VCC
GND
INT1
6 kΩ
20 Ω
30 Ω
Figure 21. Typlcal Buffer Circuitry
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
A Address RXD SCIRXD
AR Array S Slave mode
B Byte SC SYSCLK
CI XTAL2/CLKIN SCC SCICLK
D Data SIMO SPISIMO
E EDS SOMI SPISOMI
FE Final SPC SPICLK
IE Initial TXD SCITXD
M Master mode W Write
PGM Program WT WAIT
R Read
Lowercase subscripts and their meanings are:
c cycle time (period) r rise time
d delay time su setup time
f fall time v valid time
h hold time w pulse duration (width)
The following additional letters are defined as follows:
H High
L Low
V Valid
Z High impedance
All timings are measured between high and low measurement points as indicated in Figure 22 and Figure 23.
0.8 V (Low)
2 V (High)
0.8 V (Low)
0.8 VCC V (High)
Figure 22. XTAL2/CLKIN Measurement Points Figure 23. General Measurement Points
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
external clocking requirements for clock divided by 4†
NO. PARAMETER MIN MAX UNIT
1 tw(Cl) Pulse duration, XTAL2/CLKIN (see Note 12) 20 ns
2 tr(Cl) Rise time, XTAL2/CLKIN 30 ns
3 tf(CI) Fall time, XTAL2/CLKIN 30 ns
4 td(CIH-SCL) Delay time, XTAL2/CLKIN rise to SYSCLK fall 100 ns
CLKIN‡Crystal operating frequency 2 20 MHz
SYSCLK§System clock¶0.5 5 MHz
†For VIL and VIH, refer to recommended operating conditions.
‡’x59A operates up to 12 MHz CLKIN
§’x59A operates up to 3 MHz SYSCLK
¶SYSCLK = CLKIN/4
NOTE 12: This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a
low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
XTAL2/CLKIN
3
2
1
4
SYSCLK
Figure 24. External Clock Timing for Divide-by-4
external clocking requirements for clock divided by 1 (PLL)†
NO. PARAMETER MIN MAX UNIT
1 tw(Cl) Pulse duration, XTAL2/CLKIN (see Note 12) 20 ns
2 tr(Cl) Rise time, XTAL2/CLKIN 30 ns
3 tf(CI) Fall time, XTAL2/CLKIN 30 ns
4 td(CIH-SCH) Delay time, XTAL2/CLKIN rise to SYSCLK rise 100 ns
CLKIN#Crystal operating frequency 2 5 MHz
SYSCLK§System clock|| 2 5 MHz
†For VIL and VIH, refer to recommended operating conditions.
§’x59A operates up to 3 MHz SYSCLK
#’x59A operates up to 3 MHz CLKIN (for divide-by-1 clock option)
|| SYSCLK = CLKIN/1
NOTE 12: This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a
low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
XTAL2/CLKIN
3
2
1
4
SYSCLK
Figure 25. External Clock Timing for Divide-by-1
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
general purpose output signal-switching time requirements
MIN NOM MAX UNIT
trRise time 30 ns
tfFall time 30 ns
tf
tr
Figure 26. Signal-Switching Timing
recommended EEPROM timing requirements for programming
MIN MAX UNIT
tw(PGM)B Pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms
tw(PGM)AR Pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms
recommended EPROM operating conditions for programming
MIN NOM MAX UNIT
VCC1 Supply voltage 4.75 5.5 6 V
VPP Supply voltage at MC pin 13 13.2 13.5 V
IPP Supply current at MC pin during programming (VPP = 13 V) 30 50 mA
SYSCLK
System clock
Divide-by-4 0.5 5
MHz
SYSCLK
S
y
stem
clock
Divide-by-1 2 5
MH
z
recommended EPROM timing requirements for programming
MIN NOM MAX UNIT
tw(EPGM) Pulse duration, programming signal (see Note 13) 0.40 0.50 3 ms
NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
switching characteristics and timing requirements for external read and write (see Figure 27 and
Figure 28)†
NO. PARAMETER MIN MAX UNIT
5
t
Cycle time SYSCLK (system clock)
Divide-by-4 clock 200 2000
ns
5
t
c
C
y
cle
time
,
SYSCLK
(s
y
stem
clock)
Divide-by-1 PLL 200 500
ns
6 tw(SCL) Pulse duration, SYSCLK low 0.5tc–25 0.5tcns
7 tw(SCH) Pulse duration, SYSCLK high 0.5tc0.5tc+20 ns
8 td(SCL-A) Delay time, SYSCLK low to address R/W and OCF
valid 0.25tc+75 ns
9 tv(A) Valid time, address to EDS, CSE1, CSE2, CSH1,
CSH2, CSH3, and CSPF low 0.5tc–90 ns
10 tsu(D) Setup time, write data time to EDS high 0.75t c–80‡ns
11 th(EH-A) Hold time, address, R/W and OCF from EDS, CSE1,
CSE2, CSH1, CSH2, CSH3, and CSPF high 0.5tc–60 ns
12 th(EH-D)W Hold time, write data time from EDS high 0.75tc+15 ns
13 td(DZ-EL) Delay time, data bus high impedance to EDS low (read
cycle) 0.25tc–35 ns
14 td(EH-D) Delay time, EDS high to data bus enable (read cycle) 1.25tc–40 ns
15 td(EL-DV)R Delay time, EDS low to read data valid tc–95‡ns
16 th(EH-D)R Hold time, read time from EDS high 0 ns
17 tsu(WT-SCH) Setup time, WAIT time to SYSCLK high 0.25tc+70§ns
18 th(SCH-WT) Hold time, W AIT time from SYSCLK high 0 ns
19 td(EL-WTV) Delay time, EDS low to WAIT valid 0.5tc–60 ns
20 twPulse duration, EDS, CSE1, CSE2, CSH1, CSH2,
CSH3, and CSPF low tc–80‡tc+40‡ns
21 td(AV-DV)R Delay time, address valid to read data valid 1.5tc–115‡ns
22 td(AV-WTV) Delay time, address valid to W AIT valid tc–115 ns
23 td(AV-EH) Delay time, address valid to EDS high (end of write) 1.5tc–85‡ns
†tc = system-clock cycle time = 1/SYSCLK
‡If wait states, PFW ait, or the autowait feature is used, add tc to this value for each wait state invoked.
§If the autowait feature is enabled, the W AIT input can assume a “don’t care” condition until the third cycle of the access. The W AIT signal must
be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time.
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
18
17
16
13
8
OCF
R/W
WAIT
DATA
EDS, CSE1, CSE2, CSH1,
CSH2, CSH3, CSPF
ADDRESS
SYSCLK
22
19
14
15
21
9
11
20
7
6
5
370 Drives Data Read Data Drive Read Data
Valid Read Data
Disable 370 Drives
Data
Figure 27. Switching Characteristics and Timing Requirements for External-Read
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
18
17
8
R/W
WAIT
DATA
EDS, CSE1, CSE2, CSH1,
CSH2, CSH3, CSPF
ADDRESS
SYSCLK
12
23 10
22
19
9
11
20
7
6
5
Figure 28. Switching Characteristics and Timing Requirements for External-Write
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SCI1 isosynchronous† mode timing characteristics and requirements for internal clock
(see Note 14 and Figure 29)
NO. MIN MAX UNIT
24 tc(SCC) Cycle time, SCICLK 2tc131072tcns
25 tw(SCCL) Pulse duration, SCICLK low tc– 45 0.5tc(SCC)+45 ns
26 tw(SCCH) Pulse duration, SCICLK high tc– 45 0.5tc(SCC)+45 ns
27 td(SCCL-TXDV) Delay time, SCITXD valid after SCICLK low – 50 60 ns
28 tv(SCCH-TXD) Valid time, SCITXD data valid after SCICLK high tw(SCCH) – 50 ns
29 tsu(RXD-SCCH) Setup time, SCIRXD to SCICLK high 0.25 tc + 145 ns
30 tv(SCCH-RXD) Valid time, SCIRXD data valid after SCICLK high 0 ns
NOTE 14: tc = system-clock cycle time = 1/SYSCLK
SCIRXD
SCITXD
SCICLK
29
28
24
26
25
Data Valid
Data Valid
27
30
Figure 29. SCI1 Isosynchronous† Mode Timing for Internal Clock
†Isosynchronous = Isochronous
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SCI1 isosynchronous† mode timing characteristics and requirements for external clock
(see Note 14 and Figure 30)
NO. MIN MAX UNIT
31 tc(SCC) Cycle time, SCICLK 10tcns
32 tw(SCCL) Pulse duration, SCICLK low 4.25tc+ 120 ns
33 tw(SCCH) Pulse duration, SCICLK high tc + 120 ns
34 td(SCCL-TXDV) Delay time, SCITXD valid after SCICLK low 4.25tc + 145 ns
35 tv(SCCH-TXD) Valid time, SCITXD data valid after SCICLK high tw(SCCH) ns
36 tsu(RXD-SCCH) Setup time, SCIRXD to SCICLK high 40 ns
37 tv(SCCH-RXD) Valid time, SCIRXD data after SCICLK high 2tcns
NOTE 14: tc = system-clock cycle time = 1/SYSCLK
SCIRXD
SCITXD
SCICLK
36
35
31
33
32
Data Valid
Data Valid
34
37
Figure 30. SCI1 Isosynchronous† Timing for External Clock
†Isosynchronous = Isochronous
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SPI master mode external timing characteristics and requirements (see Note 14 and Figure 31)
NO. MIN MAX UNIT
38 tc(SPC)M Cycle time, SPICLK 2tc256tcns
39 tw(SPCL)M Pulse duration, SPICLK low tc– 45 0.5tc(SPC)+45 ns
40 tw(SPCH)M Pulse duration, SPICLK high tc– 55 0.5tc(SPC)+45 ns
41 td(SPCL-SIMOV)M Delay time, SPISIMO valid after SPICLK low (polarity = 1) – 65 50 ns
42 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (polarity =1) tw(SPCH) – 50 ns
43 tsu(SOMI-SPCH)M Setup time, SPISOMI to SPICLK high (polarity = 1) 0.25 tc + 150 ns
44 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high
(polarity = 1) 0 ns
NOTE 14: tc = system-clock cycle time = 1/SYSCLK
Data Valid
Data Valid
SPISOMI
SPISIMO
SPICLK
44
43
4241
38
40
39
NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.
Figure 31. SPI Master External Timing
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SPI slave mode external timing characteristics and requirements (see Note 14 and Figure 32)
NO. MIN MAX UNIT
45 tc(SPC)S Cycle time, SPICLK 8tcns
46 tw(SPCL)S Pulse duration, SPICLK low 4tc– 45 0.5tc(SPC)S+45 ns
47 tw(SPCH)S Pulse duration, SPICLK high 4tc– 45 0.5tc(SPC)S+45 ns
48 td(SPCL-SOMIV)S Delay time, SPISOMI valid after SPICLK low (polarity = 1) 3.25tc + 130 ns
49 tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (polarity =1) tw(SPCH)S ns
50 tsu(SIMO-SPCH)S Setup time, SPISIMO to SPICLK high (polarity = 1) 0 ns
51 tv(SPCH-SIMO)S Valid time, SPISIMO data after SPICLK high (polarity = 1) 3tc + 100 ns
NOTE 14: tc = system-clock cycle time = 1/SYSCLK
Data Valid
Data Valid
SPISOMI
SPISIMO
SPICLK
51
50
4948
45
47
46
NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.
Figure 32. SPI-Slave External Timing
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
The ADC1 has a separate power bus for its analog circuitry . These pins are referred to as VCC3 and VSS3. The
purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry that can
be present on VSS1 and VCC1 from coupling into the ADC1 analog stage. All ADC1 specifications are given with
respect to VSS3 unless otherwise noted.
Resolution 8-bits (256 values). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monotonic Yes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output conversion mode 00h to FFh (00 for VI ≤ VSS3 ≤; FF for VI ≤ Vref). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion time (excluding sample time) 164 tc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
MIN NOM MAX UNIT
VCC3
Analog su
pp
ly voltage
4.5 5 5.5
V
V
CC3
Analog
s
u
ppl
y v
oltage
VCC1–0.3 VCC1+0.3
V
VSS3 Analog ground VSS1–0.3 VSS1+0.3 V
Vref Non-VCC3 reference†2.5 VCC3 VCC3 + 0.1 V
Analog input for conversion VSS3 Vref V
†Vref must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time.
operating characteristics over recommended ranges operating conditions
PARAMETER MIN MAX UNIT
Absolute accuracy‡VCC3 = 5.5 V Vref = 5.1 V ±1.5 LSB
Differential/integral linearity error‡§ VCC3 = 5.5 V Vref = 5.1 V ±0.9 LSB
ICC3
Analog su
pp
ly current
Converting 2 mA
I
CC3
Analog
s
u
ppl
y
c
u
rrent
Nonconverting 5 µA
II
Input current, AN0–AN7 0 V ≤ VI ≤ 5.5 V 2µA
I
IIref input charge current 1 mA
Zf
Source im
p
edance of V f
SYSCLK ≤ 3 MHz 24 kΩ
Z
ref
So
u
rce
impedance
of
V
ref 3 MHz < SYSCLK ≤ 5 MHz 10 kΩ
‡Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and
differential/integral linearity errors in terms of LSBs increase.
§Excluding quantization error of 1/2 LSB
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the
sample time is user-defined so that the high-impedance can be accommodated without penalty to the
low-impedance sources. The sample period begins when the SAMPLE ST AR T bit of the ADC1 control register
(ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START,
ADCTL.7) is set to 1. After a hold time, the converter will reset the SAMPLE ST ART and CONVERT START bits,
signaling that a conversion has started and that the analog signal can be removed.
analog timing requirements
MIN MAX UNIT
tsu(S) Setup time, analog to sample command 0 ns
th(AN) Hold time, analog input from start of conversion 18tcns
tw(S) Pulse duration, sample time per kilohm of source impedance†1µs/kΩ
†The value given is valid for a signal with a source impedance > 1 kΩ. If the source impedance is < 1 kΩ, use a minimum sampling time of 1µs.
Analog In
Sample Start
Convert Start
Analog Stable
th(AN)
tw(S)
tsu(S)
Figure 33. Analog Timing
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table 26 is designed to aid the user in referencing a device part number to a mechanical drawing. The table
shows a cross-reference of the device part number to the TMS370 generic package name and the associated
mechanical drawing by drawing number and name.
Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PKG TYPE
(mil pin spacing)
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
TMS370 GENERIC NAME
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
PKG TYPE NO. AND
MECHANICAL NAME
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
DEVICE PART NUMBERS
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
FN – 68 pin
(50-mil pin spacing)
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
PLASTIC LEADED CHIP CARRIER
(PLCC)
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
FN(S-PQCC-J**) PLASTIC J-LEADED
CHIP CARRIER
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
TMS370C050AFNA
TMS370C050AFNL
TMS370C050AFNT
TMS370C150AFNT
TMS370C250AFNT
TMS370C350AFNA
TMS370C350AFNL
TMS370C350AFNT
TMS370C052AFNA
TMS370C052AFNL
TMS370C052AFNT
TMS370C352AFNA
TMS370C352AFNL
TMS370C352AFNT
TMS370C452AFNA
TMS370C452AFNL
TMS370C452AFNT
TMS370C353AFNA
TMS370C353AFNL
TMS370C353AFNT
TMS370C056AFNA
TMS370C056AFNL
TMS370C056AFNT
TMS370C156AFNT
TMS370C256AFNT
TMS370C356AFNA
TMS370C356AFNL
TMS370C356AFNT
TMS370C456AFNA
TMS370C456AFNL
TMS370C456AFNT
TMS370C756AFNT
TMS370C058AFNA
TMS370C058AFNL
TMS370C058AFNT
TMS370C358AFNA
TMS370C358AFNL
TMS370C358AFNT
TMS370C758AFNT
TMS370C758BFNT
TMS370C059AFNA
TMS370C059AFNL
TMS370C059AFNT
TMS370C759AFNT
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
FZ – 68 pin
(50-mil pin spacing)
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
CERAMIC LEADED CHIP CARRIER
(CLCC)
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
FZ(S-CQCC-J**) J-LEADED CERAMIC
CHIP CARRIER
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
SE370C756AFZT
SE370C758AFZT
SE370C758BFZT
SE370C759AFZT
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
JN – 64 pin
(70-mil pin spacing)
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
CERAMIC SHRINK DUAL-IN-LINE
PACKAGE (CSDIP)
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
JN(R-CDIP-T64) CERAMIC DUAL-IN-LINE
PACKAGE
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
SE370C756AJNT
SE370C758AJNT
SE370C758BJNT
TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUAR Y 1997
72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference (Continued)
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
PKG TYPE
(mil pin spacing)
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
TMS370 GENERIC NAME
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
PKG TYPE NO. AND
MECHANICAL NAME
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
DEVICE PART NUMBERS
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
NM – 64 pin
(70-mil pin spacing)
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
PLASTIC SHRINK DUAL-IN-LINE
PACKAGE (PSDIP)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
NM(R-PDIP-T64) PLASTIC SHRINK
DUAL-IN-LINE PACKAGE
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
TMS370C050ANMA
TMS370C050ANML
TMS370C050ANMT
TMS370C350ANMA
TMS370C350ANML
TMS370C350ANMT
TMS370C052ANMA
TMS370C052ANML
TMS370C052ANMT
TMS370C352ANMA
TMS370C352ANML
TMS370C352ANMT
TMS370C056ANMA
TMS370C056ANML
TMS370C056ANMT
TMS370C356ANMA
TMS370C356ANML
TMS370C356ANMT
TMS370C756ANMT
TMS370C058ANMA
TMS370C058ANML
TMS370C058ANMT
TMS370C358ANMA
TMS370C358ANML
TMS370C358ANMT
TMS370C758ANMT
TMS370C758BNMT
PACKAGE OPTION ADDENDUM
www.ti.com 5-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SE370C756AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI
SE370C756AJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI
SE370C758AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI
SE370C758AJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI
SE370C758BFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI
SE370C758BJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI
SE370C759AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI
TMS370C256AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI
TMS370C356AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI
TMS370C356ANMT OBSOLETE SDIP NM 64 TBD Call TI Call TI
TMS370C756AFNT ACTIVE PLCC FN 68 TBD Call TI Call TI
TMS370C758AFNTG4 NRND PLCC FN 68 18 Green (RoHS
& no Sb/Br) NIPDAU Level-3-260C-168 HR
TMS370C758ANMT OBSOLETE SDIP NM 64 TBD Call TI Call TI
TMS370C758BFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI
TMS370C758BNMT OBSOLETE SDIP NM 64 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 5-Apr-2012
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP®Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright ©2012, Texas Instruments Incorporated
