X9118 (R) Dual Supply/Low Power/1024-Tap/2-Wire Bus Data Sheet December 4, 2009 Single Digitally-Controlled (XDCPTM) Potentiometer FN8161.4 Features * 1024 Resistor Taps - 10-Bit Resolution The X9118 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. * 2-Wire Serial Interface for Write, Read and Transfer Operations of the Potentiometer * Wiper Resistance, 40 Typical @ 5V The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. * Four Non-Volatile Data Registers for Each Potentiometer * Non-Volatile Storage of Multiple Wiper Positions * Power On Recall: Loads Saved Wiper Position on Power-Up * Standby Current < 15A Max * System VCC: 2.7V to 5.5V Operation * Analog V+/V-: -5V to +5V * 100k End to End Resistance The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. * Endurance: 100,000 Data Changes Per Bit Per Register * 100 yr. Data Retention * 14 Ld TSSOP * Low Power CMOS * Pb-Free Available (RoHS Compliant) Ordering Information PART NUMBER PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (C) 5 10% 100 0 to +70 14 Ld TSSOP M14.173 14 Ld TSSOP (Pb-free) M14.173 PACKAGE PKG. DWG. # X9118TV14 X9118 TV X9118TV14Z (Note 1) X9118 TVZ 0 to +70 X9118TV14I (Note 2) X9118 TVI -40 to +85 14 Ld TSSOP M14.173 X9118TV14IZ (Note 1) X9118 TVZI -40 to +85 14 Ld TSSOP (Pb-free) M14.173 X9118TV14-2.7 (Note 2) X9118 TVF 0 to +70 14 Ld TSSOP M14.173 0 to +70 14 Ld TSSOP (Pb-free) M14.173 -40 to +85 14 Ld TSSOP M14.173 -40 to +85 14 Ld TSSOP (Pb-free) M14.173 X9118TV14Z-2.7 (Note 1) X9118 TVZF X9118TV14I-2.7 (Note 2) X9118 TVG X9118TV14IZ-2.7 (Note 1) X9118 TVZG 2.7 to 5.5 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 2. Not recommended for new designs. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9118 Functional Diagram VCC 2-WIRE BUS INTERFACE ADDRESS DATA STATUS RH WRITE READ TRANSFER BUS INTERFACE AND CONTROL POWER ON RECALL CONTROL VSS 100k 1024-TAPS POT WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3) NC NC V+ WIPER RL RW V- Detailed Functional Diagram VCC V+ POWER ON RECALL DR0 SCL INTERFACE AND CONTROL CIRCUITRY SDA A1 A0 DR1 DATA DR2 DR3 RH WIPER COUNTER REGISTER (WCR) 100K 1024-TAPS RL CONTROL RW WP VSS V- Circuit Level Applications System Level Applications * Vary the gain of a voltage amplifier * Adjust the contrast in LCD displays * Provide programmable DC reference voltages for comparators and detectors * Control the power level of LED transmitters in communication systems * Control the volume in audio circuits * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems * Vary the frequency and duty cycle of timer ICs * Vary the DC biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits 2 FN8161.4 December 4, 2009 X9118 Pin Configuration DEVICE ADDRESS (A1-A0) X9118 (14 LD TSSOP) TOP VIEW The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9118. A maximum of 4 XDCP devices may occupy the 2-wire serial bus. V+ NC 1 14 VCC 2 13 RL A0 3 12 RH SCL 4 11 RW HARDWARE WRITE PROTECT INPUT (WP) WP 5 10 SDA 6 NC A1 VSS 7 9 8 The WP pin when LOW prevents nonvolatile writes to the Data Registers. V- Potentiometer Pins RH, RL Pin Assignments The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. PIN (TSSOP) SYMBOL 1 V+ Analog Supply Voltage RW 2 NC No Connect 3 A0 Device Address for 2-wire bus The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. 4 SCL Serial Clock for 2-wire bus 5 WP Hardware Write Protect 6 SDA Serial Data Input/Output for 2-wire bus 7 VSS System Ground 8 V- Analog Supply Voltage 9 A1 Device Address for 2-wire bus 10 NC No Connect 11 RW Wiper terminal of the Potentiometer 12 RH High terminal of the Potentiometer 13 RL Low terminal of the Potentiometer 14 VCC FUNCTION Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system or digital supply voltage. The VSS pin is the system ground. ANALOG SUPPLY VOLTAGES (V+ AND V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Other Pins System Supply Voltage NO CONNECT Pin Descriptions No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) Principles of Operation The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. The X9118 is an integrated microcircuit incorporating a resistor array and its registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides a detailed description of the following: It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by 2-wire master to supply 2-wire serial clock to the X9118. 3 * Resistor Array Description * Serial Interface Description * Instruction and Register Description Resistor Array Description The X9118 is comprised of a resistor array. The array contains 1023, in effect, discrete resistive segments that are connected in series (see Figure 1). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). FN8161.4 December 4, 2009 X9118 SERIAL DATA PATH RH SERIAL BUS INPUT FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) REGISTER 1 (DR1) 10 REGISTER 2 (DR2) 10 REGISTER 3 (DR3) PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) C O U N T E R D E C O D E If WCR = 000[HEX] then RW = RL If WCR = 3FF[HEX] then RW = RH RL R W FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM At both ends of each array and between each resistor segment is a CMOS switch (transmission gate) connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. START CONDITION All commands to the X9118 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9118 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. See Figure 3. STOP CONDITION The WCR may be written directly. The Data Registers and the WCR can be read and written by the host system. Serial Interface Description All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 3. SERIAL INTERFACE - 2-WIRE ACKNOWLEDGE The X9118 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9118 will be considered a slave device in all applications. Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. CLOCK AND DATA CONVENTIONS The X9118 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte, the X9118 will respond with a final acknowledge. See Figure 2. Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 3. 4 FN8161.4 December 4, 2009 X9118 SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER ACKNOWLEDGE POLLING INSTRUCTION AND REGISTER DESCRIPTION The disabling of the inputs during the internal nonvolatile write operation can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9118 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9118 is still busy with the write operation no ACK will be returned. If the X9118 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Device Addressing: Identification Byte (ID and A) Flow 1. ACK Polling Sequence NONVOLATILE WRITE COMMAND COMPLETED ENTERACK POLLING ISSUE START Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier. The ID[3:0] bits is the device ID for the X9118; this is fixed as 0101[B] (refer to Table 1). The A[1:0] bits in the ID byte are the internal slave address. The physical device address is defined by the state of the A1-A0 input pins. The slave address is externally specified by the user. The X9118 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9118 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1-A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is the LSB and is used to set the device for read or write operations. INSTRUCTION BYTE AND REGISTER SELECTION ISSUE SLAVE ADDRESS ACK RETURNED? ISSUE STOP NO Table 3 provides a complete summary of the instruction set opcodes. YES FURTHER OPERATION? The next byte sent to the X9118 contains the instruction and register pointer information. The three most significant bits are used to provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 2. NO YES ISSUE INSTRUCTION ISSUE STOP PROCEED PROCEED 5 FN8161.4 December 4, 2009 X9118 TABLE 1. IDENTIFICATION BYTE FORMAT DEVICE TYPE IDENTIFIES INTERNAL SLAVE ADDRESS SET TO 0 FOR PROPER OPERATION READ OR WRITE BIT ID3 ID2 ID1 ID0 0 A1 A0 R/W 0 1 0 1 0 A1 A0 R/W (MSB) (LSB) TABLE 2. INSTRUCTION BYTE FORMAT INSTRUCTION OPCODE I2 REGISTER SELECTION SET TO 0 FOR PROPER OPERATION I1 I0 0 RB SET TO 0 FOR PROPER OPERATION RA 0 (MSB) 0 (LSB) REGISTER SELECTED RB RA DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 TABLE 3. INSTRUCTION SET INSTRUCTION SET INSTRUCTION R/W I2 I1 I0 0 RB RA 0 0 Read Wiper Counter Register 1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter Register Write Wiper Counter Register 0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register pointed to RB-RA. Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to RB-RA. XFR Data Register to Wiper Counter Register 1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to by RB-RA to the Wiper Counter Register XFR Wiper Counter Register to Data Register 0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register to the Data Register pointed to by RB-RA. OPERATION NOTE: 3. 1/ = data is one or zero. 6 FN8161.4 December 4, 2009 X9118 Instruction and Register Description Four of the six instructions are four bytes in length. These instructions are: DEVICE ADDRESSING * Read Wiper Counter Register - read the current wiper position of the potentiometer, Wiper Counter Register (WCR) The X9118 contains a Wiper Counter Register (see Table 4) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The contents of the WCR can be altered in one of three ways: 1. It may be written directly by the host via the write Wiper Counter Register instruction (serial load) 2. It may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data register 3. It is loaded with the contents of its Data Register zero (R0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9118 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. Data Registers (DR) The potentiometer has four 10-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit 9-Bit 0 are used to store one of the 1024 wiper position (0 ~1023). * Write Wiper Counter Register - change current wiper position of the potentiometer, * Read Data Register - read the contents of the selected Data Register; * Write Data Register - write a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. Two instructions (see Figure 4) require a two-byte sequence to complete. These instructions transfer data between the host and the X9118; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are: * XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to the Wiper Counter Register. * XFR Wiper Counter Register to Data Register -This transfers the contents of the specified Wiper Counter Register to the specified Data Register. See "Instruction Format" on page 8 for more details. Other POWER-UP AND DOWN REQUIREMENTS At all times, the V+ voltage must be greater than or equal to the voltage at RH or RL, and the voltage at RH or RL must be greater than or equal to the voltage at V-. During power-up and power down, VCC, V+, and V- must reach their final values within 1ms of each other. TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9-WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V V V V V V V V V V (MSB) (LSB) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9-BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV) BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NV NV NV NV NV NV NV NV NV NV MSB LSB 7 FN8161.4 December 4, 2009 X9118 SCL SDA 0 1 0 1 S ID3 ID2 ID1 ID0 T A DEVICE ID R T 0 A1 A0 R/W INTERNAL ADDRESS 0 0 A I2 I1 I0 0 C K INSTRUCTION OPCODE RB RA 0 0 A C K REGISTER ADDRESS S T O P FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE SCL 0 SDA 1 0 1 0 0 0 X X 0 0 X S ID3 ID2 ID1 ID0 0 A1 A0 R/W A I2 I1 I0 0 RB RA 0 T C A DEVICE ID INTERNAL K INSTRUCTION REGISTER R OPCODE ADDRESS ADDRESS T A C K X X X X X W C R 9 W A W W C C C C R K R R 8 7 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W A C C R K 0 S T O P WIPER OR DATA POSITION FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS) Instruction Format Read Wiper Counter Register (WCR) Instruction R/W = 1 Device Type Device S Identifier Addresses T A R 0 1 0 1 0 A1 A0 T 0 0 Wiper Position M (Sent by Slave on SDA) A W W W W W W W W C C C C C C C C C K R R R R R R R R 7 6 5 4 3 2 1 0 8 Wiper Position S (Sent by Slave on SDA) A W W C C C 0 K X X X X X X R R Register Addresses Opcode S A C K 1 0 0 0 0 9 M A C K S T O P Wiper Position S (Sent by Master on SDA) A W W W W W W W W C C C C C C C C C K R R R R R R R R 7 6 5 4 3 2 1 0 S A C K Write Wiper Counter Register (WCR) Device Type Identifier 0 1 0 1 Device Addresses 0 A1 A0 R/W = 0 S T A R T S A C K Instruction Opcode Register Addresses 1 0 0 1 0 0 0 0 Wiper Position S (Sent by Master on SDA) A W W C C C K X X X X X X R R 9 8 S T O P Read Data Register (DR) Instruction Opcode R/W = 1 Device Type Device S Identifier Addresses T A R 0 1 0 1 0 A1 A0 T 8 S A C K 1 0 1 0 Register Addresses RB RA 0 Wiper Position (Sent by Slave on SDA) S A W C C 0 K X X X X X X R 9 Wiper Position or Data (Sent by Slave on SDA) M W A W W W W C C C C C C K R R R R R 7 6 5 4 8 W C R 3 W C R 2 W C R 1 M S W A T C C O R K P 0 FN8161.4 December 4, 2009 X9118 Instruction Register S Opcode Addresses A C K 1 1 0 0 RB RA 0 0 Wiper Position or Data S (Sent by Master on SDA) A W W C K X X X X X X C C R R 9 8 Wiper Position or Data S (Sent by Master on SDA) A C W W W W W W W W K C C C C C C C C R R R R R R R R 7 6 5 4 3 2 1 0 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Device Type Device S Identifier Addresses T A R T 0 1 0 1 0 A1 A0 R/W = 0 Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) R/W = 0 Device S Device Type Identifier Addresses T A R 0 1 0 1 0 A1 A0 T Instruction Register S S S Opcode Addresses A T A C O C K 1 1 1 0 RB RA 0 0 K P HIGH-VOLTAGE WRITE CYCLE Device S Device Type Identifier Addresses T A R 0 1 0 1 0 A1 A0 T R/W = 1 Transfer Data Register (DR) to Wiper Counter Register (WCR) Instruction Register S S S Opcode Addresses A T A C O C K 1 1 0 0 RB RA 0 0 K P NOTES: 1. "A1 ~ A0": stands for the device addresses sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register. 9 FN8161.4 December 4, 2009 X9118 Absolute Maximum Ratings Thermal Information Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Voltage on SCL, SDA, or Any Address Input with Respect to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage on V+ (referenced to VSS) (Note 7) . . . . . . . . . . . . . . . .10V Voltage on V- (referenced to VSS) (Note 7) . . . . . . . . . . . . . . . . -10V (V+) - (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Any Voltage on RH/RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ Any Voltage on RL/RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Supply Voltage (VCC) Limits (Note 7) X9118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% X9118-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Thermal Resistance (Typical, Note 3) JA (C/W) 14 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Power Rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW Wiper current (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Specifications SYMBOL RTOTAL Over the recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN End to End Resistance TYP MAX UNITS 100 End to End Resistance Tolerance RW Wiper Resistance IW = (VRH - VRL)/RTOTAL, VCC = 3V, VRL = -3V 150 k 20 % 500 RW Wiper Resistance IW = (VRH - VRL)/RTOTAL, VCC = 5V, VRL = 0V 100 Vv+ Voltage on V+ Pin X9118 (Note 7) +4.5 +5.5 V X9118-2.7 (Note 7) +2.7 +5.5 V Vv- Voltage on V- Pin X9118 -5.5 -4.5 V X9118-2.7 -5.5 -2.7 V Voltage on any RH or RL Pin VSS = 0V V- Noise Ref: 1kHz VTERM Resolution V+ V -120 dBV 0.1 % Absolute Linearity (Note 4) Rw(n)(actual) - Rw(n)(expected), where n = 1 to 1023 1.5 MI (Note 6) Relative Linearity (Note 5) Rw(m + 1) - [Rw(m) + MI], where m = 1 to 1023 1.5 MI (Note 6) Temperature Coefficient of RTOTAL CH/CL/CW 40 Ratiometric Temperature Coefficient Wiper at middle point Potentiometer Capacitances See Macro model 300 ppm/C 20 ppm/C 10/10/25 pF NOTES: 4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 6. MI = RTOT/1023 or (RH - RL)/1023, single pot 7. VCC, V+, V- must reach their final values within 1ms of each other. 8. n = 0, 1, 2, ...,1023; m = 0, 1, 2, ..., 1022. 10 FN8161.4 December 4, 2009 X9118 DC Operating SpecificationsOver the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 3 mA ICC1 VCC Supply Current (Active) ICC2 VCC Supply Current (Nonvolatile Write) fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Non-volatile Write State only) 7 mA ISB VCC Current (Standby) VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-wire, Standby State only) 15 A ILI Input Leakage Current VIN = VSS to VCC 10 A ILO Output Leakage Current VOUT = VSS to VCC 10 A VIH Input HIGH Voltage VCC x 0.7 VCC + 1 V VIL Input LOW Voltage -1 VCC x 0.3 V VOL Output LOW Voltage 0.4 V fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Read and Volatile Write States only) IOL = 3mA Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Capacitance SYMBOL TEST CIN/OUT (Note 9) Input/Output Capacitance (SI) CIN (Note 9) Input Capacitance (SCL, WP, A1 and A0) TYP UNITS TEST CONDITIONS 8 pF VOUT = 0V 6 pF VIN = 0V Power-Up Timing SYMBOL PARAMETER MIN MAX UNITS 0.2 50 V/ms tr VCC (Note 9) VCC Power-up Rate tPUR (Note 10) Power-up to Initiation of Read Operation 1 ms tPUW (Note 10) Power-up to Initiation of Write Operation 50 ms NOTES: 9. This parameter is not 100% tested 10. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level VCC x 0.5 11 FN8161.4 December 4, 2009 X9118 Equivalent A.C. Load Circuit 5V 3V 1533 SPICE MACROMODEL 867 RTOTAL RL RH SDAOUTPUT SDA OUTPUT 100pF CW CL 10pF CL 10pF 25pF 100pF RW AC Timing High-Voltage Write Cycle Timing SYMBOL PARAMETER MIN MAX UNITS 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time tDH 250 ns SDA Data Output Hold Time 0 ns tI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1300 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns High-Voltage Write Cycle Timing SYMBOL tWR PARAMETER High-Voltage Write Cycle Time (store instructions) TYP MAX UNITS 5 10 ms XDCP Timing SYMBOL PARAMETER TYP UNITS tWRPO Wiper Response Time After the Third (last) Power Supply is Stable 8 s tWRL Wiper Response Time After Instruction Issued (all load instructions) 8 s 12 FN8161.4 December 4, 2009 X9118 Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Timing Diagrams Start and Stop Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA 13 tDH FN8161.4 December 4, 2009 X9118 XDCP Timing (For All Load Instructions) (STOP) SCL LSB SDA tWRL RW Write Protect and Device Address Pins Timing (START) SCL (STOP) ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 Applications Information Basic Configurations of Electronic Potentiometers +VR VR RW I Three terminal Potentiometer; Variable voltage divider 14 Two terminal Variable Resistor; Variable current FN8161.4 December 4, 2009 X9118 Application Circuits NONINVERTING AMPLIFIER VS VOLTAGE REGULATOR + VO - VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 COMPARATOR WITH HYSTERISIS OFFSET VOLTAGE ADJUSTMENT R1 R2 VS VS - + 100k VO - VO + +12V 10 } 10k } TL072 10k R1 R2 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) -12V 15 FN8161.4 December 4, 2009 X9118 Application Circuits (Continued) ATTENUATOR FILTER C VS + R2 R1 R VO + VS VO - - R3 R4 R2 R1 = R2 = R3 = R4 = 10k R1 GO = 1 + R2/R1 fc = 1/(2RC) VO = G V S -1/2 G +1/2 R2 } VS R1 } INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT R2 C1 + VS - - VO + R1 ZIN R3 VO = G VS G = - R2/R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FUNCTION GENERATOR R2 - + C R1 - } RA + } RB frequency R1, R2, C amplitude RA, RB 16 FN8161.4 December 4, 2009 X9118 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E 0.25(0.010) M E1 2 INCHES SYMBOL 3 0.05(0.002) -A- 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE GAUGE PLANE -B1 M14.173 B M 0.25 0.010 SEATING PLANE L A D -C- e A1 b A2 c 0.10(0.004) 0.10(0.004) M C A M B S NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MIN MAX MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N 14 0o 14 7 8o 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. Rev. 2 4/06 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN8161.4 December 4, 2009