AK4393VFP - AKM Semiconductor - Datasheet.Directory

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 1 -

GENERA L DESCRIPTION

T he AK43 93 is a high performan ce stereo DAC for t he 96 kHz sampling mod e of DAT , DVD including a

24bit digital filter. The AK4 393 introdu ce s the advanced multi-bit sy stem for ∆Σ modulato r. T his ne w

architecture achieves the wider dynamic range, while keeping much the sa me superior distortion

characteristics as conve ntional Single-Bit way. In th e AK4393, the analog outputs are filtered in the analog

domain by switche d-capacitor filte r (SCF) with high tolerance to clock jitter. The analog outputs are full

differe ntia l output, so the device is suitable for h i-end applications. The operating voltages support analog

5V and digital 3.3V, so it is easy to I/F with 3.3V logic IC.

FEATURES

• 128x Oversampling

• Sampling Rat e up to 108kHz

• 24Bit 8x Digital F ilter

Ripple: ±0.005dB, Attenuation: 75dB

• High Tolerance to Clock Jitter

• Low D ist ort io n Dif f erenti al Outp ut

• Digital de-emphasis for 32, 44. 1, 48 & 96kHz sampling

• Soft Mute

• THD+N: -100dB

• DR, S/N: 120dB

• I/F forma t : MSB justified, 16/20/24bit LSB justified, I2S

• Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs

Double Speed: 128fs, 192fs, 256fs or 384fs

• Power Sup ply : 4. 75 to 5.25V (A nalog), 3 to 5.25V (Digital)

• Smal l Packag e: 28 pin VSOP

DEM1

LRCK

BICK

SDAT

A

Audio Data

Interface

DEM0DVDD

CSN

AVDD

AOUTR+

8x

Interpolator SCF

∆Σ

Modulator

AOUTR-

SCF

De-emphasis

Soft Mute

Control Register Clock Di vider

De-emphasis

Control

PDN

CCLK CDTI P/S MCLK CKS0 CKS1 CKS2

V

REFH

V

REFL

AOUTL+

AOUTL-

V

COM

BVSS

A

VSSDVSS

DIF2DIF1DIF0

SMUTE De-emphasis

Soft Mute 8x

Interpolator ∆Σ

Modulator

DFS

Advanced Multi-Bit 96kHz 24-Bit ∆Σ DAC

AK4393

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 2 -

 Ordering Guide

AK4393VF -40 ~ +85 °C 28pin VSOP (0.65mm pitch)

AKD4393 Evaluation Board

 P i n Layout

6

5

4

3

2

1

DVSS

DVDD

PDN

MCLK

BICK

SDATA

LRCK 7

SMUTE/CSN 8

CKS2

CKS1

CKS0

P/S

VCOM

AOUTL+

AOUTL-

AOUTR+

Top

View

10

9

DFS

DEM0/CCLK

DEM1/CDTI 11

DIF0 12

AOUTR-

AVSS

AVDD

VREFH

23

24

25

26

27

28

22

21

19

20

18

17

13

14

16

15

DIF1

DIF2

VREFL

BVSS

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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PIN/FUNCTION

No. Pin Name I/O Function

1 DVSS - Digital Ground Pin

2 DVDD - Digital Power Sup ply Pin, 3.3V or 5.0V

3 MCLK I Master Clock Input Pin

4

PDN

I

Power - D own M ode Pin

When at “L”, the AK4393 is in power-down mode a nd is held in reset.

The AK4393 should always be reset upon power-up.

5 BICK

I

Audi o Seri al Data Clock Pin

The clock of 64 fs or m ore than is recom mended to be input on this pin.

6 SDATA

I

Audi o Ser i al Data Input Pin

2’s complement MSB-fir st da ta is input on this pin.

7 LRCK I L/R Clock Pin

SMUTE

I

Soft Mute Pin in p arallel mode

When th is pin goes "H", soft mute cycle is initiated.

When returning “L”, the output mu te releases.

8

CSN I Chip Select Pin in serial mode

9 DFS

I

Double Spe ed Sampling Mode Pin (Inter nal pull-d own pin)

“L”: Nor mal Speed , “H”: Dou ble Speed

DEM0 I De-emp hasis Enable Pin in para llel mode

10 CCLK I Control Data Clock Pin in serial mode

DEM1 I De-emp hasis Enable Pin in para llel mode

11 CDTI I Cont r ol Dat a In put Pin in ser ial mode

12 DIF0 I Digital Input Format Pin

1 3 D I F1 I Digi t a l Inpu t Form a t Pin

1 4 D I F2 I Digi t a l Inpu t Form a t Pin

15 BVSS - Substrate Ground Pin, 0V

16 VREFL I Low Level Volta ge Reference Input Pin

17 VREFH I High Level Voltage Reference Input Pin

18 AVDD - Analog Power Supply Pin, 5.0V

19 AVSS - Anal og Ground Pin, 0V

20 AOUTR- O Rch Neg ative a na log output Pin

21 AOUTR+ O Rch Positi ve analog output Pin

22 AOUTL- O Lch Negative analog output Pin

23 AOUTL+ O Lch Positive analog out put Pin

24 VCOM O Common Voltage Output Pin, 2.6V

25 P/S I Parallel/Serial Select Pin (Internal pul l-up pin)

“L”: Serial control mode, “H”: Parallel contr ol mode

26 CKS0 I Master Clock Select Pin

27 CKS1 I Master Clock Select Pin

28 CKS2 I Master Clock Select Pin

Note: All input pin s except in ternal pull-up/down pins sh ould not be left floati ng.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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A B SOLUTE MAXIMUM R ATIN GS

(AVSS , BVSS, DVS S = 0V; Not e 1)

Parameter Symbol min max Units

Power Su p p l i e s:

Analog

Digital

| BVSS-DVSS | (Note 2)

AVDD

DVDD

∆ GND

-0.3

-

6.0

0.3

V

Input Cur rent , An y pin Except Suppli es IIN - ±10 mA

Input Voltage VIND -0.3 DVDD+0.3 V

Ambi ent Operat ing Temperature Ta - 40 85 °C

Storage Temperature Tstg -65 150 °C

Notes: 1. All voltages with respect to g round.

2. AVSS, BVSS and DVSS must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at th ese extremes.

RECOMMENDED OPERAT I NG CONDITIONS

(AVSS, BVSS, DVSS=0V; Note 1)

Parameter Symbol min typ max Units

Power Su p p l i e s:

(Note 3) Analog

Digital AVDD

DVDD 4.75

3.0 5.0

3.3 5.25

5.25 V

V

Vol ta g e Reference

(Note 4) “H” voltage reference

“L” voltage reference

VREFH-VREFL

VREFH

VREFL

∆ VRE F

AVDD-0.5

AVSS

3.0

-

AVDD

-

AVDD

V

Notes: 3. The power up sequence bet ween AVDD and DVDD is not critical.

4. Analog output voltage scales with the volta ge of (VREFH-VREFL).

AOUT (typ.@0dB) = (AO UT+) - (AOUT-) = ±2.4Vpp×(VREFH- VREFL)/5.

* AKM assumes no responsibility for the usage beyond the conditions in this da ta sheet.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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ANAL O G CHARACTERIST ICS

(Ta = 25°C; AVD D = 5V, DVDD = 3.3V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREF L = AVS S;

fs = 44.1kHz ; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data ; Measurement Bandwidth = 20Hz~20kHz;

RL ≥ 600Ω; Extern al circuit: Figure 11; un less ot herwise specifi ed)

Parameter min typ max Units

Resolution 24 Bit s

Dynamic Characteristics (Note 5)

fs=44.1kHz

BW=20kHz 0dBFS

-60dBFS

-100

-53 -90

- dB

dB

THD+N

fs=96kHz

BW=40kHz 0dBFS

-60dBFS -97

-51 -86

- dB

dB

fs=44.1kHz (Note 6)

(Note 7) 112

- 117

120

dB

Dyn am i c Ran ge

(-60dBFS with A-weighted)

fs=96kHz

(Note 7) 111

- 116

118

dB

fs= 44 . 1k Hz (Note 8)

(Note 7) 112

- 117

120

dB

S/N (A-weighted

fs=96kHz

(Note 7) 111

- 116

118

dB

Interchannel Isolation (1kHz) 100 120 dB

DC Accuracy

Interchannel Gain Mismat ch 0.15 0.3 dB

Gain Drift (Note 9) 20 - ppm/°C

Output Voltage (Note 10) ±2.25 ±2.4 ±2.55 Vpp

Load Resistance (Note 11) 600 Ω

Output Current 3.5 mA

Power Supplie s

Power Supply Curren t

Normal Operati on (PDN = “H”)

AVDD

DVDD(f s=44.1kHz)

DVDD(fs=96kHz)

AVDD + DVDD

60

3

5

-

90

mA

Power-Down Mode (PDN = “L”)

AVDD + DVDD (Note 12)

10

50

µA

Power Supply Rejection ( Note 13) 50 dB

Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode.

At 96kHz, measured by ROHDE & SCHWARZ, UPD. Averag ing mode.

Refer to the eva board m anual.

6. 101dB at 16bit data and 116dB at 20bit data.

7. By Figure12. Externa l LPF Circuit Example 2.

8. S/N does not depend on input bit length.

9. The voltage on (VREFH-VREFL) is held +5V externally.

10. Full-scale voltage (0dB). Output voltage scales with the voltage of (VREFH-VREFL).

AOUT (typ.@0 dB) = (AOUT+ ) - (AOUT-) = ±2.4Vpp× (VREFH-VREFL)/5.

11. For AC-load. 1kΩ for DC - l o a d .

12. In the power-down mode. P/S = DVDD, an d all other digital input pins including clock pins (MCLK, BICK

and LRCK) are held DVSS.

13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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FIL TER CHARACTERISTICS (fs = 44.1kHz)

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5 .25 V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.01dB (Note 14)

-6.0dB PB

0

-

22.05 20.0

- kHz

kHz

Stopband (Note 14) SB 24.1 kHz

Passba nd Ripple PR ± 0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 15) GD - 28 - 1/fs

Di g i t a l Fi lt e r + SC F

Frequency Response 0 ∼ 20.0kHz - ± 0.2 - dB

Note: 14. The passband and stopband frequencies scale with fs.

For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs.

15. The calculatin g d elay time which occurred by digital filtering. Th is time is from set ting the 16/20/24bit data of

both channel s to input register to the output of analog signal.

FILTER CHARA CTERIST I CS (fs = 96kHz)

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5 .25 V; fs = 96kHz; Double Speed Mode; DEM = OFF)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.01dB (Note 14)

-6.0dB PB

0

-

48.0 43.5

- kHz

kHz

Stopband (Note 14) SB 52.5 kHz

Passba nd Ripple PR ± 0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 15) GD - 28 - 1/fs

Di g i t a l Fi lt e r + SC F

Frequency Response 0 ∼ 40.0kHz - ± 0.3 - dB

DC CHARACTE RIS T I CS

(Ta = 25°C; AVD D = 4.75 ~ 5.2 5V; DVDD = 3.0~5.25V)

Parameter Symbol min typ max Units

High-Level Input Voltage

Low-Level Input Voltage VIH

VIL 70%DVDD

- -

30%DVDD V

V

Input Leakage Current (Note 16) Iin - - ± 10 µA

Note: 16. DFS and P/S pin s have inter nal pull-down or pull-up devices, nominally 100kΩ.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 7 -

SWI TCHING CHARACTERISTICS

(Ta = 25°C; AVD D = 4.75 ~ 5.2 5V; DVDD = 3.0~5.25V; CL = 20pF)

Parameter Symbol min typ max Units

Master Cloc k Timing (Note 17)

Normal Speed: 256fs, Double Speed: 128fs

Pu l se Wi d t h Low

Pulse Wi dt h High

fCLK

tCLKL

tCLKH

7.7

28

28 13.824 MHz

ns

Normal Speed: 384fs, Double Speed: 192fs

Pu l se Wi d t h Low

Pulse Wi dt h High

fCLK

tCLKL

tCLKH

11.5

20

20 20.736 MHz

ns

Normal Speed: 512fs, Double Speed: 256fs

Normal Speed: 768fs, Double Speed: 384fs

Pu l se Wi d t h Low

Pulse Wi dt h High

fCLK

tCLKL

tCLKH

15.4

23.0

7

27.648

41.472 MHz

MHz

ns

LRCK Fr eq ue nc y (Note 18)

Normal Speed Mode (DFS = “L”)

Double Speed Mode (DFS = “H”)

Duty Cycle

fsn

fsd

Duty

30

60

45

44.1

88.2

54

108

55

kHz

%

Serial Interface Timing

BICK Period

BICK Pulse Width Low

Pulse Width High

BICK “↑” to LRCK Edge (Note 19)

LRCK Edge to BICK “↑” (Note 19)

SDATA Hold Time

SDATA Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

140

60

20

ns

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN High Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

80

50

150

50

ns

Reset Timing

PDN Pulse Width (Note 20)

tPW

150

ns

Notes: 17. For Double Speed mode ple ase see Appendix A for relationship of MCLK and BC LK/LRCK.

18. When the normal and double speed modes are switched, AK4393 should be reset by PDN pin or RSTN bit.

19. BICK rising edge must not occu r at the same time as LRCK edge.

20. The AK4393 can be r eset by bringing PDN “L” to “H”.

When the states of CKS2-0 or DFS change , the AK4393 shoul d be reset by PDN pin or RSTN bit.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 8 -

 Timing Diagram

1/fCLK

tCLKL

50%DVDD

tCLKH

MCLK

1/fns,1/fds

50%DVDD

LRCK

tBCK

tBCKL

50%DVDD

tBCKH

BICK

Clock Timing

For Double Speed mode timing please see Appendix A for relationship of MCLK and BCLK/LRCK.

tLRB

LRCK

BICK

tSDS

SDATA

tSDH

50%DVDD

tBLR

50%DVDD

Au di o Inte r f ace Timi ng

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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tCSS

CSN

CCLK

CDTI

50%DVDD

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

50%DVDD

WRITE Command Input Timing

CSN

CCLK

CDTI

50%DVDD

D3 D2 D1 D0

tCSW

tCSH

50%DVDD

WRITE Data Input Timing

tPW

30%DVDD

PDN

Power-down Timing

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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OPER A T ION OVERVIEW

 System Clock

The external clo ck s, whic h a re required to o pe rat e the A K4393, are MCL K, L RCK and B ICK. The master clo ck (M CL K)

should be synchronized with LRCK but the phase is not critical. However, in Double Speed Mode, the phase

rela tionship between MCLK and LRCK/BICK is limited. (Refe r to Appendix A). The MCLK is used to o perate the

digital interpolation filter and the de lta-sig ma modulator. The samp ling spee d is s et b y DFS (Table 1). The sampling rate

(LRCK), CKS0/1/2 and DFS deter mine the frequency of MCLK (Table 2).

All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4393 is in normal operation

mode (PDN = “H”). If these clocks ar e not provided, the AK4393 may draw excess current because the device utilizes

dy namic refreshed logic internally . If the external clocks are not present, the AK4393 should be in the power-do wn mode

(PDN = “L”) or in the re set mode (RS TN = “0”). After exiting reset at power-up etc., the AK4393 is in power-down mode

until MCLK and LRCK ar e in put.

DFS Sampli ng Rate (fs)

0 Normal Speed Mode 30kHz~54kHz Default

1 Double Speed Mode 60kHz~108kHz

Table 1. Sampling Speed

Mode CKS2 CKS1 CKS0 Normal Double

0 0 0 0 256fs 128fs

Default

1 0 0 1 256fs

256fs

2 0 1 0 384fs 192fs

3 0 1 1 384fs

384fs

4 1 0 0 512fs 256fs

5 1 0 1 512fs N/A

6 1 1 0 768fs 384fs

7 1 1 1 768fs N/A

Ta ble 2. System Clock s

LRCK MCLK BICK

fs 256fs 384fs 512fs 768fs 64fs

32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 2.0480MHz

44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 2.8224MHz

48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 3.0720MHz

Table 3. System clock exa mpl e (Normal Speed M ode)

LRCK MCLK BICK

fs 128fs 192fs 256fs 384fs 64fs

88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz

96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz

Table 4. System clock exampl e (Doubl e Speed Mode)

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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 A udio Serial Interfa ce Forma t

Data is shifted in v ia the SDA TA pin using BI CK and LR CK inputs. F iv e data formats are sup po rted and sele cte d b y the

DIF0-2 as show n in Table 5 . In all fo rmats the s erial data is MSB-f irst, 2's compliment f ormat and is latched o n the rising

edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs.

Mode DIF2 DIF1 DIF0 Mode BICK Figure

0 0 0 0 0: 16bit LSB Justified ≥32fs Figu re 1

1 0 0 1 1: 20bit LSB Justified ≥40fs Figu re 2

2 0 1 0 2: 24bit MSB Justi fied ≥48fs Figure 3

3 0 1 1 3: I2S Compatible ≥48fs Fi gu r e 4

4 1 0 0 4: 24bit LSB Justified ≥48fs Figu re 2

Table 5. Audio Data Formats

SDATA

BICK

LRCK

SDAT

A

1514 654

BICK

0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1

3210 1514

(

32fs

)

(

64fs

)

0141 151617 31 0 1 14151617 31 0 1

15 14 0 15 14 0

M ode 0 Don’t care Don’t care

15 :M S B, 0:L SB

M ode 0 1514 6543210

Lch D ata Rch Data

Figure 1. Mode 0 Timing

SDATA

LRCK

BICK

(

64fs

)

091 10 11 12 31 0 1 9 10 11 12 31 0 1

19 0 19 0

M ode 1 Don’t care Don’t care

19:MSB, 0:L SB

SDAT

A

Mode 4 23:MSB, 0:LSB

20 19 0 20 19 0

Don’ t car e Don’t care

22 21 22 21

Lch Data Rch Data

8

23 23

8

Figure 2. Mode 1,4 Timing

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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LRCK

BICK

(

64fs

)

SDAT

A

0221 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 1 0 Don’t care

23

Lch Data Rch Data

23 30 2222423 30

22 1 0 Don’t care

23 22

23

Figure 3. Mode 2 Timing

LRCK

BICK

(

64fs

)

SDATA

031 2 24 31 0 1 31 0 1

23:MSB, 0:L SB

22 10Don’t care

23

Lch Data Rch Data

23 25 322423 25

22 1 0 Don’t care

23 23

Figure 4. Mode 3 Timing

 De-emphasis filter

A digital de-emphasis filter is available fo r 32, 44.1, 48 or 96kHz sampling rates (tc = 50/15µs) and is enabled or disabled

wit h t h e DE M0, DE M1 an d DFS in pu t pi n s.

DEM1 DEM0 DFS Mode

0 0 0 44.1kHz Default

0 1 0 OFF

1 0 0 48kHz

1 1 0 32kHz

0 0 1 OFF

0 1 1 OFF

1 0 1 96kHz

1 1 1 OFF

Table 6. De-emphasis filter control

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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 Soft mute operation

Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -∞

during 1024 LRCK cycles. When SMUTE is returned to “L”, the mut e is cancelled and the output attenuation gradually

changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRC K cycles after starting th e

operation, the attenuation is discontin ued and returned to 0dB. The soft mut e is effecti ve for changing the signal source

with out stopping the signal transmission.

SMUTE

Attenuation

1024/fs

0dB

-∞

AOUT

1024/fs

GD GD

(1)

(2)

(3)

Notes:

(1) The output signal is at tenuated by -∞ during 1024 LRCK cycles (1024/fs).

(2) Analog output corresponding to digit al input has th e group delay (GD).

(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.

Figure 5. Soft mute operation

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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 System Reset

The AK4 393 s hou ld be res e t o nce b y bringing PD N = “L ” upo n po w er-up . The AK43 93 is powe red u p and the inte rnal

timing starts clockin g by LRCK “↑” after exiting reset and power down state by MCLK. The AK4393 is in the

power-down mode until MCLK and LRCK are input.

 Power-Down

The AK4393 is placed in t h e power-d own m ode by br i n g ing PDN pin “L” and t h e anlog out put s a r e floatin g ( Hi-Z).

Fi gure 6 shows an exa mple of the system timing at the power-down and power-up.

N or ma l Op er ati o n

Internal

State

PDN

Power-do wn No rmal O peration

GD GD

“0” data

D/A Out

(Analog)

D/A In

(Digital)

Clock In

M CL K, LR CK, BI CK

(1) (3)

External

MUTE (5)

(3) (1)

Mute ON

(2)

(4)

Don’t care

Notes:

(1) The analog output corresponding to digital input has th e group delay (GD).

(2) Analog outp uts are floating (Hi -Z) at th e power-down mode.

(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.

(4) The externa l clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).

(5) Please mute the analog output externally if th e click noise (3) influences system application.

The timing example is shown in this figure.

Fi gure 6. Power -d own/ up sequ en ce exam pl e

 C lic k Noi se f r om analog ou t put

Cl i ck n oi s e occu r s f r om a n a log ou tp u t i n t h e foll owi n g c a ses.

1) When switching de-emphasis mode by DEM0, DEM1 and DFS pins,

2) When switching serial da ta mode by DIF0, DIF1 and DIF2 pins,

3) When goi ng a nd exiting power down mode by PDN pi n,

4) When switching normal speed an d double speed by DFS pin,

However in case of 1) & 2), If th e input data is “0” or the soft mute is enabl ed (after 1024 LRCK cycles from SMUTE

= “ H” ), n o cli ck n oi s e occur ex ce p t f or s wi t ch i n g D FS p in.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

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 Mode Control Int erf ace

Pi ns (parallel con trol mode) or registers (serial control mode) can con tr ol each functions of the AK4393. For DIF2-0,

CK S2-0 and D FS , the se tting o f pin and registe r are “O R ed” internally . So , eve n s erial c ontrol mo de, pin s etting c an also

control these function s .

The seri al control interface is enabled by the P/S pin = “L”. In this mode, p in setting must be all “L”. Internal registers

may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. T he data on this interface consists of Chip address

(2bits, C1/0; fixed to “01”), Read/Wr ite (1bit; fixed to “1”), Register address (MSB fi rst, 5bits) and Con trol data (MSB

first, 8bits). The AK4393 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge.

The writing o f data b e comes v alid b y CSN “↑”. The clock speed of CCLK is 5MHz(ma x). The CSN and CCLK must be

fixed to “H” wh en the register does not be accessed.

PDN = “L” resets the registers to the ir de f ault values . When the state of P/S pin is c hanged, the AK 4393 sho uld be re se t

by PDN = “L”. In seri al mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.

CDTI

CCLK

C1

012345678 9 10 11 12 13 14 15

D4D5D6D7

A

1

A

2

A

3

A

4R/WC0

A

0D0D1D2D3

CSN

C1-C0: C hi p Address (Fixed to “01”)

R/W: READ/WRIT E (Fixed to “1”, Write only)

A4-A0: Register Address

D7-D0: Control Data

Figure 7. Control I/F Timing

*The AK4393 does not support t he read comman d and chip address. C1/0 and R/W ar e fixed to “011”

*Wh en the AK4393 is in the power down mode (PDN = “L”) or the MCLK is n ot provided, writing into the con trol

register is inhibited.

*For set ting the regist ers, the following sequence i s recommended.

y Control 1 register

(1) Writing RSTN = “0” and other bits (D6-D1) to the register at the same time.

(2 ) Writing RSTN = “1” to the regi ster. The other bits are no change.

y Control 2 register

Th is wr it in g sequence h as no limit a tion like contr ol 1 register.

*When RSTN = “0”, the click noise is ou tput from AOUT pins.

*I f the mode setting is done without setting RSTN = “0” , la rg e nois e may be output from AOUT pins. (Especially when

CKS0/1/2 are changed.)

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 16 -

 Regi ster Ma p

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN

01H Control 2 0 0 0 0 DFS DEM1 DEM0 SMUTE

02H Test TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0

Notes:

For addresses from 03H to 1FH, dat a must not be written.

When PDN pin goes to “L”, the registe rs are initialized to their default values. When RSTN bit goes to “0”, the only

inte rnal timing is reset and the registers are not initialized to their default v alues. DI F2-0, CKS 2-0 and DFS b its are

ORed with pins respectively.

 Register Definitions

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN

default 0 0 0 0 0 0 0 1

RST N: Internal timing r eset

0: Reset. All registers are not initialized.

1: Normal Opera tion

When the s tates of CKS2-0 or DFS change, the AK4393 should be reset by PDN pi n or RSTN bit.

DIF2-0: Audio data interface modes (see Table 5)

Initial: “000”, Mode 0

Register bits are ORed with DIF2-0 pins if P/S = “L”.

CKS2 -0: Master Clock Frequency Select (see Table 2)

Initial: “000”, Mode 0

Register bi ts are ORed with CKS2-0 p ins if P/S = “L”.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Control 2 0 0 0 0 DFS DEM1 DEM0 SMUTE

default 0 0 0 0 0 0 0 0

SMUTE: Soft Mute Ena bl e

0: Normal operation

1: DAC outputs soft-muted

DE M1-0 : De-em p ha si s r espon se (see Table 6)

Initi al: “00”, 44.1kHz

DFS: Sampl ing speed control (see Tabl e 1)

0: Normal speed

1: Double speed

Register bit is ORed wit h DFS pin if P/S = “L”.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Test TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0

default 0 0 0 0 0 0 0 0

TEST7-0: Test mode. Do not write any data to 02H.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 17 -

SYST EM DESIGN

Fi gure 8 and 9 show the system connection diagram. An evaluation board (AKD4393) is available which demon strat es

the optimum l ayout, power supply arrangements and measurement results.

DVSS

1

DVDD2

MCLK3

PDN

4

BICK5

SDATA6

LRCK

7

CSN

8

DFS9

CCLK10

CDTI

11

DIF0

12

CKS2 28

CKS1 27

CKS0 26

P/S 25

VCOM 24

AOUTL+ 23

AOUTL- 22

AOUTR+ 21

AOUTR- 20

AVSS 19

AVDD 18

VREFH 17

Master Clock

Micro-

controller

0.1u10u

+

10u

0.1u +

10u

+Supply 5 V

AK4393

0.1u

Digital

Supply

13

14

16

15

DIF1

DIF2

VREFL

BVSS

fs

24bit Audio Data

Reset & Power down

64fs 10u

0.1u +

Lch

LPF

Rch

LPF

Lch Out

Analog GroundDigital Ground

Analog

Rch Out

Figure 8. Typical Connection Diagram (Seri a l mode)

Notes:

- LRCK = fs, BICK = 64fs.

- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of

regulator etc.

- AVSS, BVSS and DVSS mu st be connected to the same ana log ground plane.

- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive

load.

- All input pins except pull-down/pull-up pins should not be left floating.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 18 -

DVSS

1

DVDD

2

MCLK

3

PDN

4

BICK5

SDATA6

LRCK7

SMUTE

8

DFS9

DEM010

DEM111

DIF0

12

CKS2 28

CKS1 27

CKS0 26

P/S 25

VCOM 24

AOUTL+ 23

AOUTL- 22

AOUTR+ 21

AOUTR- 20

AVSS 19

AVDD 18

VREFH 17

Master Clock

Mode

setting

0.1u10u

+

10u

0.1u +

10u

+Supply 5V

AK4393

0.1u

Digital

Supply

13

14

16

15

DIF1

DIF2

VREFL

BVSS

fs

24bit Audio Data

Reset & Power down

64fs 10u

0.1u +

Lch

LPF

Rch

LPF Rc h O ut

Lch Out

Master

Clock

Select

Analog

Analog Gro undDigital Ground

Figure 9. Typical Connection Diagram (Parallel mode)

Notes:

- LRCK = fs, BICK = 64fs.

- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of

regulat or etc.

- AVSS, BV SS and DVSS must be con nected to the same analog ground plan e.

- W hen AOU T drive s so me capac itiv e load, some re sisto r should b e adde d in series be twe en A OUT and c apacitiv e

load.

- All input pins except pull-down/ pull-u p pi ns should n ot be left floatin g .

Analog GroundD igital Ground

System

Controller

DVSS

1

DVDD

2

MCLK3

PDN

4

BICK5

SDATA6

LRCK

7

SMUTE

8

DFS9

DEM010

DEM1

11

DIF012

CKS2 28

CKS1 27

CKS0 26

P/S 25

VCOM 24

AOUTL+ 23

AOUTL- 22

A

OUTR+ 21

AOUTR- 20

AVSS 19

AVDD 18

VREFH

AK4393

17

13

14

16

15

DIF1

DIF2

VREFR

BVSS

Figure 10. Ground Layout

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 19 -

1. Grounding and Power Supply Decoupling

To minimiz e couplin g by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.

AVDD is supplied from analog supply in system and DVDD is sup plied from digital supply in system. If AVDD and

DVDD are supplied se parate ly, the po wer up seq uence is no t critical. AVSS, BVSS and D VSS must be connec ted

to analog ground plane. S ystem ana log gr oun d and d ig it al gr ound sh ould be con n ect ed toget h er n ear to wh er e the

sup plies are bro ught onto the printed c ircui t board. De c o u pling c apacitors f or high frequenc y s ho uld be place d as near as

possible.

2. Voltage Reference

The differential Voltage between VREFH and VREFL set the analog output range. VR EF H pin is normally co nnected to

AVDD and VREF L pin is normally connected to AVSS. VREFH and VREFL should be co nne cted w ith a 0.1µF ceramic

capacitor. VCOM is a signal ground of this chip. An electrolytic capacit or 10µF p arallel with a 0.1µF ceramic capacitor

attached to VCOM p in eliminates the effec ts o f high frequency noise. No load current may be drawn from VCOM pin. All

signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pin s in order to avoid unwanted

coupling into the AK4393.

3. Anal og Outp ut s

The a na log outputs a re full differential outputs a nd 2.4Vpp (typ@ VREF=5V) centered around V COM. The differe ntial

outputs are summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT- . If the sum ming gai n is 1,

the output r ange is 4.8Vpp (typ@VREF= 5V). The bias voltage of the external summing circuit is supplied externally.

The input da ta format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFH (@2 4bit) and

a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit).

The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modul ator beyond the audio

passband.

Fi gu r e 11 sh ows an exam p le of ext ern a l LP F circu i t s umm in g t he di ffer enti a l out pu ts by a n op- a m p .

Figure 12 shows an example of differential outputs and LPF circuit example by thre e op-am ps.

1k 1k

1k

1k 1k

1k 1n

+Vop

1n

-Vop

AOUT-

AOUT+

3.3n Analog

Out

AK4393

Fi gure 11. External LPF Circuit Example 1

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 20 -

300

47u 300

AOUTL-

620

10n

300

220

10n

6

4

3

2710u

0.1u

0.1u 10u

10u

NJM5534D

300

47u

300

AOUTL+

620

10n

300

220

10n

6

4

3

2710u

0.1u

0.1u 10u

NJM5534D

32

1

100

0.1u +

NJM5534D

0.1u 10u

100

4

3

2

4.7n

620

430

7

+

++

-

+

-

+

-

+

4.7n

Lch

-15

+15

6

430

Fi gure 12. External LPF Circuit Example 2

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 21 -

PACKAGE

0.1±0.1

0-10°

D e ta il A

Seating Plane

NOT E : Dimension "*" does n ot include mold flash.

0.10

0.15-0.05

0.22±0.1 0.65

*9.8±0.2 1.25±0.2

A

114

15

28

p

in VS OP

(

Unit: m m

)

*5.6±0.2

7.6±0.2

0.5±0.2

+0.1

0.675

 Material & Lead finish

Package molding compound: Ep oxy

Lead fr ame material: Cu

Lead fr ame surfa ce treatment: Solder pl ate

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 22 -

MARKING

AKM

A

K4393VF

XXXBYYYYC

XXXXBYY YYC dat a code iden t i fier

XXXB: Lot n umber (X : Di gi t num ber , B : Alpha character )

YYYYC: Assembly date (Y : Digit num ber C : Alpha character)

IMPO RTANT NOTICE

• Th ese pr o duc t s a nd t h eir spe ci fi ca t i o ns a r e subj e c t t o c h an ge wi tho ut noti ce. Befo r e c o nsi d eri n g

any use or a ppl ic at ion , c onsul t the Asahi Ka sei Mi cro syst ems C o., Lt d. (AK M) sal es of f ic e or

authorized distributor concerni ng their current status.

• AKM assum es no l iab i l it y for i nf r ing em en t o f a ny p at e nt, i n t ell ec t u al pr o per t y, or oth er r i ght in t h e

appl i c ati on or use o f any i nf or ma tion c ontai ne d her ei n.

• A ny expor t o f these products, or dev ice s or s y ste ms c on ta ining them , may req uir e a n export licen s e

or oth er o ff i ci al app rova l un der the l aw a nd re gul at ion s of t he co unt ry of expo rt p ert ai ni ng to

c ustom s and tari f f s, cur rency exchan ge, or strat egi c m at eri al s.

• AKM products are neither intended nor authorized for use as critic al components in any safety, life

support, or ot her hazard rel ated devi ce or system, and AKM assumes no responsibil ity relating to

any such use, except w ith the express writ ten consent of the Representative Director of AKM. As

used here:

(a) A h azar d r e l at e d de vi ce o r system is one d es i g ned or int e nd ed fo r l i fe s upp or t o r m aint e na nc e

of safety or for applications in medicine, aerospace, nuclear energy, or other fields , in which its

failure to f unction or perf orm may reasonabl y be expected to resul t in loss of life or in

si gni f ic ant i nju ry or d ama ge t o pe rson or pr oper ty.

(b) A critical component is one whose failure to function or perform may reasonably be expected to

resul t, whether direct ly or i ndirectly, in the loss of the saf ety or eff ectiveness of t he devi ce or

system con ta ini ng it , an d w hi ch m ust the ref or e me et ve ry hi gh sta ndar ds of perfor ma nce a nd

reli abili ty.

• It is the responsibility of the buyer or distributor of an AKM product who di stributes, disposes of, or

otherwise places the produc t with a third part y to notify that party in advance of the above content

and conditions, and the buyer or distributor agrees to assume any and all res ponsibility and liability

for and hold AKM harmless from any and all c lai ms arising from the use of said product in the

absence of such noti fication.

ASAHI KASEI [AK4393]

M0039-E-02 2003/09

- 23 -

Appendi x A

In Double Speed Mode, the phase relat ionship between MCLK and LRCK/BICK is limited (Tabl e 7). If the phase

relationship happens du ring this prohibited period, it is possible t o occur the inverse of output channel. The phase

relationship must be se t to avo id the p rohib ited pe riod whe n the A K 4393 ope rate s at Double S peed Mode. The prohibited

period is specified by the co mbination o f digital power supply voltage (DVDD), MCLK frequency and audio data format

(Tab le 5) . W he n the audio data fo rmats are 16 /20/24b it L SB Jus tif ied ( Mod e 0, 1,4) and 24b it M SB Jus tif ie d ( Mod e 2) , the

phase relationship (tLRM: Figure 11) between the rising edge of LRCK and the rising edge of MCLK has the prohibited

period of min to max in Table 7. In case of I2S Compatible (Mode 3), the relationship between the falli n g edge of BICK

and the rising edge of MCLK has t he prohibited period (tBCM: Figure 12)

Mode Settin g Pr oh ibited Per iod

Sampling

Mod e Digital Power

Supply, DVDD MCLK

Frequency CKS2 CKS1 CKS0 DFS min max

Units

Double Speed 3.0 to 5.25V 128fs 0 0 0 1 0.4 1.7 ns

Double Speed 3.0 to 5.25V 192fs 0 1 0 1 -0.5 0.8 ns

Double Speed 3.0 to 5.25V 256fs 0 0 1 1 -0.7 0.7 ns

Double Speed 3.0 to 5.25V 256fs 1 0 0 1 -0.7 0.7 ns

Double Speed 3.0 to 5.25V 384fs 0 1 1 1 -1.7 -0.3 ns

Double Speed 3.0 to 5.25V 384fs 1 1 0 1 -1.7 -0.3 ns

Double Speed 4.75 to 5.25V 128fs 0 0 0 1 0.8 1.5 ns

Double Speed 4.75 to 5.25V 192fs 0 1 0 1 -0.2 0.5 ns

Double Speed 4.75 to 5.25V 256fs 0 0 1 1 -0.3 0.4 ns

Double Speed 4.75 to 5.25V 256fs 1 0 0 1 -0.3 0.4 ns

Double Speed 4.75 to 5.25V 384fs 0 1 1 1 -1.0 -0.3 ns

Double Speed 4.75 to 5.25V 384fs 1 1 0 1 -1.0 -0.3 ns

Table 7. Prohibited Period

Figure 11. 16/20/24bit LSB Justified, 24bit MSB Justifi ed

Figure 12. I2S Compatible

tLRM

LRCK

MCLK

50%DVDD

tBCM

BICK

MCLK

50%DVDD