DM74ALS574AWM - Fairchild Semiconductor

September 1986

Revised February 2000

DM74ALS574A Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs

DM74ALS574A

Octal D-Type Edge-Triggered Flip-Flop

with 3-STATE Outputs

General Descript ion

These 8-bit registers feature totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low- impedance loads. The hi gh -im ped ance state and

increased high-logic-level drive provide these registers with

the capability of being connecte d directly to and driving the

bus line s in a bu s-or ga ni zed sy stem wi th ou t n eed fo r inte r-

face or pull-up compone nts. They are par ticularly attractive

for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

The eight flip-flops of the DM74ALS574A are edge-trig-

gered D-type flip-flops. On the positive transition of the

clock, the Q outputs will be set to the logic states that were

set up at the D inputs.

A buffered output control input can be used to place the

eight o utputs in either a normal log ic state (HIGH or LOW

logic levels) or a high-impedance state. In the high-imped-

ance state th e outputs neit her load nor dr ive the bu s lines

significantly.

The output co ntrol does not affect th e internal operation of

the flip-flops. That is, the old data can be retained or new

data can be entered even while the outputs are OFF.

Features

■Switching specifications at 50 pF

■Switching specifications guaranteed over full tempera-

ture and VCC range

■Advanced oxide-isolated, ion-implanted Schottky TTL

process

■Functionally equivalent with DM74LS374

■Improv ed AC pe rfo rma nce over D M7 4LS37 4 at app roxi -

mately half the power

■3-STATE b uffer-type outputs drive bus lines directl y

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the orderin g c ode.

Connection Diagram

Order Number Package Number Package Description

DM74ALS574AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74ALS574ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74ALS574AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2

DM74ALS574A

Function Table

L = LOW Sta t e

H = HIGH State

X = Don’t Care

↑ = Positive Edge Transition

Z = High Impedance State

Q0 = Previo us C onditio n of Q

Logic Diagram

Output Clock D Output

Control Q

L↑HH

L↑LL

LLXQ

HXXZ

3 www.fairchildsemi.com

DM74ALS574A

Absolute Maximum Ratings(Note 1)

Note 1: The “Abso lute Maximum Ratings” ar e those value s beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Re comm ended Operat ing Co ndition s” table will de fine the cond itions

for actu al device operation.

Recommended Operating Conditions

Note 2: Th e (↑) arrow indicates t he positiv e edge of th e C lock is used for ref erence.

Electri cal Characteristics

over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.

Supply Voltage 7V

Input Voltage 7V

Voltage Applied to Disabled Output 5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Typical θJA

N Package 56.0°C/W

M Package 75.0°C/W

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.5 5 5.5 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −2.6 mA

IOL LOW Level Output Current 24 mA

fCLOCK Clock Frequency 0 35 MHz

tWWidth of Clock Pulse HIGH 14 ns

LOW 14 ns

tSU Data Setup Time (Note 2) 15 ↑ ns

tHData Hold Time (Note 2) 0 ↑ ns

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.2 V

VOH HIGH Level VCC = 4.5V IOH = Max 2.4 3.2 V

Output Voltage VIL = VIL Max

VCC = 4.5V to 5.5V IOH = −400 µAV

CC − 2V

VOL LOW Level VCC = 4.5V IOL = 12 mA 0.25 0.4 V

Output Voltage VIH = 2V

IOL = 24 mA 0.35 0. 5 V

IIInput Current at Max Input Voltage VCC = 5.5V, VIH = 7V 0.1 mA

IIH HIGH Level Input Current VCC = 5.5V, VIH = 2.7V 20 µA

IIL LOW Level Input Current VCC = 5.5V, VIL = 0.4V −0.2 mA

IOOutput Drive Current VCC = 5.5V, VO = 2.25V −30 −112 mA

IOZH OFF-State Output Current VCC = 5.5V, VIH = 2V 20 µA

HIGH Level Voltage Applied VO = 2.7V

IOZL OFF-State Output Current d VCC = 5.5V, VIH = 2V −20 µA

LOW Level Voltage Applied VO = 0.4V

ICC Supply Current VCC = 5.5V Outputs HIGH 11 18 mA

Outputs Open Outputs LOW 17 27 mA

Outputs Disabled 17 28 mA

www.fairchildsemi.com 4

DM74ALS574A

Switching Characteri stics

over recommended operating free air temperature range

Symbol Parameter Conditions From To Min Max Units

fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V 35 MHz

tPLH Propagation Delay Time RL = 500ΩClock Any Q 4 14 ns

LOW-to-HIGH Level Output CL = 50 pF

tPHL Propagation Delay Time Clock Any Q 4 14 ns

HIGH-to-LOW Level Output

tPZH Output Enable Time Output Control Any Q 4 18 ns

to HIGH Level Output

tPZL Output Enable Time Output Control Any Q 4 18 ns

to LOW Level Output

tPHZ Output Disable Time Output Control Any Q 2 10 ns

from HIGH Level Output

tPLZ Output Disable Time Output Control Any Q 2 12 ns

from LOW Level Output

5 www.fairchildsemi.com

DM74ALS574A

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

www.fairchildsemi.com 6

DM74ALS574A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

7 www.fairchildsemi.com

DM74ALS574A Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Packag e Num be r N20A

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.