WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 1 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
16Mx72 SYNCHRONOUS DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 25mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive edge
of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature Ranges
Organized as 16M x 72
Weight: WEDPN16M72V-XB2X - 2.5 grams typical
BENEFITS
60% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 19% I/O Reduction
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 72 density (contact factory for
information)
* This product is subject to change without notice.
GENERAL DESCRIPTION
The 128MByte (1Gb) SDRAM is a high-speed CMOS, dynamic
random-access, memory using 5 chips containing 268,435,456
bits. Each chip is internally confi gured as a quad-bank DRAM with
a synchronous interface. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-12 select the row). The address bits registered
coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option. An AUTO PRECHARGE function may be enabled
to provide a self-timed row precharge that is initiated at the end
of the burst sequence.
The 1Gb SDRAM uses an internal pipelined architecture to achieve
high-speed operation. This architecture is compatible with the 2n rule
of prefetch architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with
CSP Approach (mm) WEDPN16M72V-XB2X S
A
V
I
N
G
S
Area 5 x 265mm2 = 1,328mm2525mm260%
I/O Count 5 x 54 pins = 270 pins 219 Balls 19%
21
25
WEDPN16M72V-XB2X
22.3
11.9
54
TSOP
11.9
54
TSOP
11.9
54
TSOP
11.9
54
TSOP
11.9
54
TSOP
DENSITY COMPARISONS
Continued on page 4
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 2 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ1
DQ3
DQ6
DQ7
CAS0#
CS0#
V
SS
V
SS
NC
NC
DQ56
DQ57
DQ60
DQ62
V
SS
V
SS
DQ30
DQ28
DQ25
DQ24
CLK1
CKE1
V
CC
V
CC
CS2#
CAS2#
DQ39
DQ38
DQ35
DQ33
V
CC
DQ0
DQ2
DQ4
DQ5
DQML0
WE0#
RAS0#
V
SS
V
SS
CKE3
CLK3
DQMH3
DQ58
DQ59
DQ61
DQ63
DQ31
DQ29
DQ27
DQ26
NC
DQMH1
NC
V
CC
V
CC
RAS2#
WE2#
DQML2
DQ37
DQ36
DQ34
DQ32
DQ14
DQ12
DQ10
DQ8
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
DQ55
DQ53
DQ51
DQ49
DQ17
DQ19
DQ21
DQ23
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
DQ40
DQ42
DQ44
DQ46
DQ15
DQ13
DQ11
DQ9
DQMH0
CLK0
CKE0
V
CC
V
CC
CS3#
CAS3#
WE3#
DQ54
DQ52
DQ50
DQ48
DQ16
DQ18
DQ20
DQ22
DQML1
WE1#
CS1#
V
SS
V
SS
CKE2
CLK2
DQMH2
DQ41
DQ43
DQ45
DQ47
V
SS
V
SS
V
CC
V
CC
NC
NC
NC
V
SS
V
SS
NC
RAS3#
DQML3
NC
V
SS
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
NC
RAS1#
CAS1#
V
CC
V
CC
NC
NC
CS4#
NC
V
CC
V
SS
V
SS
A9
A0
A2
A12
NC
DQMH4
DQ73
DQ75
DQ77
DQ79
A8
A1
A3
DNU
NC
WE4#
DQ70
DQ68
DQ66
DQ64
A10
A7
A5
DNU
BA0
CLK4
DQ72
DQ74
DQ76
DQ78
A11
A6
A4
DNU
BA1
CAS4#
DQ71
DQ69
DQ67
DQ65
V
SS
V
SS
V
CC
V
CC
NC
CKE4
NC
V
SS
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
NC
RAS4#
DQML4
V
CC
V
SS
V
SS
FIGURE 1 – PIN CONFIGURATION
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
TOP VIEW
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 3 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
A
0-12
A
0-12
BA
0-1
BA
0-1
CLK
0
CLK
CAS#
CKE
0
CKE
CS
0
# CS#
DQML
0
DQML
DQMH
0
DQMH
RAS
1
#
WE
1
#
CAS
1
#
WE#
U1
RAS#
A
0-12
BA
0-1
CLK
1
CLK
CAS#
RAS
0
#
WE
0
#
CAS
0
#
WE#
U0
RAS#
CKE
1
CKE
CS
1
# CS#
DQML
1
DQML
DQMH
1
DQMH
RAS
2
#
WE
2
#
CAS
2
#
WE#
U2
RAS#
A
0-12
BA
0-1
CLK
2
CLK
CAS#
CKE
2
CKE
CS
2
# CS#
DQML
2
DQML
DQMH
2
DQMH
RAS
3
#
WE
3
#
CAS
3
#
WE#
U3
RAS#
A
0-12
BA
0-1
CLK
3
CLK
CAS#
CKE
3
CKE
CS
3
# CS#
DQML
3
DQML
DQMH
3
DQMH
RAS
4
#
WE
4
#
CAS
4
#
WE#
U4
RAS#
A
0-12
BA
0-1
CLK
4
CLK
CAS#
CKE
4
CKE
CS
4
# CS#
DQML
4
DQML
DQMH
4
DQMH
DQ16
•
•
•
•
•
•
DQ31
DQ0
•
•
•
•
•
•
DQ15
DQ32
•
•
•
•
•
•
DQ47
DQ0
•
•
•
•
•
•
DQ15
DQ48
•
•
•
•
•
•
DQ63
DQ0
•
•
•
•
•
•
DQ15
DQ64
•
•
•
•
•
•
DQ79
DQ0
•
•
•
•
•
•
DQ15
DQ0
•
•
•
•
•
•
DQ15
DQ0
•
•
•
•
•
•
DQ15
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 4 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
automatic column-address generation, the ability to interleave
between internal banks in order to hide precharge time and the
capability to randomly change column addresses on each clock
cycle during a burst access.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command which
is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0 and BA1 select the
bank, A0-12 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register defi nition, command descriptions and device
operation.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefi ned
manner. Operational procedures other than those specifi ed may
result in undefi ned operation. Once power is applied to VCC and
VCCQ (simultaneously) and the clock is stable (stable clock is
defi ned as a signal cycling within timing constraints specifi ed for the
clock pin), the SDRAM requires a 100μs delay prior to issuing any
command other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100μs period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP commands
should be applied.
Once the 100μs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied, a
PRECHARGE command should be applied. All banks must be
precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for Mode Register programming. Because the Mode
Register will power up in an unknown state, it should be loaded prior
to applying any operational command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to defi ne the specifi c mode of operation
of the SDRAM. This defi nition includes the selec-tion of a burst
length, a burst type, a CAS latency, an operating mode and a
write burst mode, as shown in Figure 3. The Mode Register is
programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the
device loses power.
Mode register bits M0-M2 specify the burst length, M3 specifi es
the type of burst (sequential or interleaved), M4-M6 specify the
CAS latency, M7 and M8 specify the operating mode, M9 specifi es
the WRITE burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefi ned but should be driven LOW
during loading of the mode register.
The Mode Register must be loaded when all banks are idle, and
the controller must wait the specifi ed time before initiating the
subsequent operation. Violating either of these requirements will
result in unspecifi ed operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented, with
the burst length being programmable, as shown in Figure 3. The
burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst
is available for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
FIGURE 3 – MODE REGISTER DEFINITION
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length CAS Latency BT
A
9
A
7
A
6
A
5
A
4
A
3
A
8
A
2
A
1
A
0
Mode Register (Mx)
Address Bus
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8 M7
Op Mode
A
10
A
11
Reserved*
WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = 0, 0
to ensure compatibility
with future devices.
Unused
A
12
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 5 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst will
wrap within the block if a boundary is reached. The block is uniquely
selected by A1-8 when the burst length is set to two; by A2-8 when
the burst length is set to four; and by A3-8 when the burst length
is set to eight. The remaining (least signifi cant) address bit(s) is
(are) used to select the starting location within the block. Full-page
bursts wrap within the page if the boundary is reached.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type and
is selected via bit M3.
The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown
in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the fi rst
piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency
is m clocks, the data will be available by clock edge n+m. The I/Os
will start driving as a result of the clock edge one cycle earlier (n +
m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the
clock cycle time is such that all relevant access times are met, if a
READ command is registered at T0 and the latency is programmed
to two clocks, the I/Os will start driving after T1 and the data will be
valid by T2. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by setting M7and M8 to
zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length
applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because
unknown operation or incompatibility with future versions may
result.
TABLE 2 – CAS LATENCY
SPEED
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS LATENCY = 2 CAS LATENCY = 3
-100 ≤75 ≤100
-125 ≤100 ≤125
-133 ≤100 ≤133
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2 applies
to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
COMMANDS
The Truth Table provides a quick reference of available commands.
This is followed by a written description of each command. Three
additional Truth Tables appear following the Operation section;
these tables provide current state/next state information.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from
being executed by the SDRAM, regardless of whether the CLK signal
is enabled. The SDRAM is effectively deselected. Operations already
in progress are not affected.
TABLE 1 – BURST DEFINITION
Burst
Length Starting Column
Address Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
2
A0
0 0-1 0-1
1 1-0 1-0
4
A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full
Page (y)
n = A0-9/8/7
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Not Supported
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the starting column
within the block.
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the starting column
within the block.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-8 select the unique column to be accessed, and Mode Register bit
M3 is ignored.
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 6 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 4 – CAS LATENCY
CLK
I/O
T2T1 T3T0
CAS Latency = 3
LZ
DOUT
t
OH
t
COMMAND NOPREAD
t
AC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
I/O
T2T1 T3T0
CAS Latency = 2
LZ
DOUT
t
OH
t
COMMAND NOPREAD
t
AC
NOP
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP
to an SDRAM which is selected (CS# is LOW). This prevents
unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11. See Mode Register
heading in the Register Defi nition section. The LOAD MODE
REGISTER command can only be issued when all banks are
idle, and a subsequent executable command cannot be issued
until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a
particular bank for a subsequent access. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs
A0-11 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a different
row in the same bank.
READ
The READ command is used to initiate a burst read access to an
active row. The value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-8 selects the starting column
location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row
being accessed will be precharged at the end of the READ burst; if
AUTO PRECHARGE is not selected, the row will remain open for
subsequent accesses. Read data appears on the I/Os subject to
the logic level on the DQM inputs two clocks earlier. If a given DQM
signal was registered HIGH, the corresponding I/Os will be High-Z
two clocks later; if the DQM signal was registered LOW, the I/Os will
provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an
active row. The value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-8 selects the starting column
location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row
being accessed will be precharged at the end of the WRITE burst;
if AUTO PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os is written
to the memory array subject to the DQM input logic level appearing
coincident with the data. If a given DQM signal is registered LOW,
the corresponding data will be written to memory; if the DQM signal
is registered HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will
be available for a subsequent row access a specifi ed time (tRP)
after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select
the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once
a bank has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being issued
to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above, without
requiring an explicit command. This is accomplished by using
A10 to enable AUTO PRECHARGE in conjunction with a specifi c
READ or WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE burst, except
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 7 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
in the full-page burst mode, where AUTO PRECHARGE does
not apply. AUTO PRECHARGE is nonpersistent in that it is either
enabled or disabled for each individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated at
the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time (tRP)
is completed. This is determined as if an explicit PRECHARGE
command was issued at the earliest possible time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either
fi xed-length or full-page bursts. The most recently registered READ
or WRITE command prior to the BURST TERMINATE command
will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM
and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in
conventional DRAMs. This command is nonpersistent, so it must
be issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This
makes the address bits “Don’t Care” during an AUTO REFRESH
command. Each 256Mb SDRAM requires 8,192 AUTO REFRESH
cycles every refresh period (tREF). Providing a distributed AUTO
REFRESH command will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate
(tRC), once every refresh period (tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data in the
SDRAM, even if the rest of the system is powered down. When in
the self refresh mode, the SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). Once the
SELF REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own
internal clocking, causing it to perform its own AUTO REFRESH
cycles. The SDRAM must remain in self refresh mode for a
minimum period equal to tRAS and may remain in self refresh
mode for an indefi nite period beyond that.
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable (stable clock is defi ned as a
signal cycling within timing constraints specifi ed for the clock pin)
prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two clocks) for
tXSR, because time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands
must be issued as both SELF REFRESH and AUTO REFRESH
utilize the row refresh counter.
* Self refresh available in commercial and industrial temperatures only.
TRUTH TABLE – COMMANDS AND DQM OPERATION
(NOTE 1)
NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR I/Os
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (Select bank and activate row) ( 3) L L H H X Bank/Row X
READ (Select bank and column, and start READ burst) (4) L H L H L/H 8 Bank/Col X
WRITE (Select bank and column, and start WRITE burst) (4) L H L L L/H 8 Bank/Col Valid
BURST TERMINATE L H H L X X Active
PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L X Code X
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X X X
LOAD MODE REGISTER (2) L L L L X Op-Code X
Write Enable/Output Enable (8) ––––L – Active
Write Inhibit/Output High-Z (8) –––– H – High-Z
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 defi ne the op-code written to the Mode Register.
3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being
read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for
CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock
delay).
WEDPN16M72V-XB2X
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Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(NOTES 1, 6)
VCC = +3.3V ±0.3V; -55°C TA +125°C
Parameter/Condition Symbol Min Max Units
Supply Voltage VCC 3 3.6 V
Input High Voltage: Logic 1; All inputs (21) VIH 2V
CC + 0.3 V
Input Low Voltage: Logic 0; All inputs (21) VIL -0.3 0.8 V
Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V) II-5 5 μA
Input Leakage Address Current: Any input 0V VIN VCC (All other pins not under test = 0V) II-25 25 μA
Output Leakage Current: I/Os are disabled; 0V VOUT VCC I
OZ -5 5 μA
Output Levels:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
VOH 2.4 – V
VOL – 0.4 V
IDD SPECIFICATIONS AND CONDITIONS
(NOTES 1,6,11,13)
VCC = +3.3V ±0.3V; -55°C TA +125°C
Parameter/Condition Symbol Max Units
Operating Current: Active Mode;
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19) ICC1 625 mA
Standby Current: Active Mode; CKE = HIGH; CS = HIGH;
All banks active after tRCD met; No accesses in progress (3, 12, 19) ICC3 200 mA
Operating Current: Burst Mode; Continuous burst;
Read or Write; All banks active; CAS latency = 3 (3, 18, 19) ICC4 675 mA
Self Refresh Current: CKE 0.2V (Commercial and Industrial Temperatures)(27) ICC7 12.5 mA
ABSOLUTE MAXIMUM RATINGS
Parameter Unit
Voltage on VCC, VCCQ Supply relative to VSS -1 to 4.6 V
Voltage on NC or I/O pins relative to VSS -1 to 4.6 V
Operating Temperature TA (Mil) -55 to +125 °C
Operating Temperature TA (Ind) -40 to +85 °C
Storage Temperature, Plastic -55 to +125 °C
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage
to the device. This is a stress rating only and func tion al op er a tion of the device at these or any other
conditions greater than those in di cat ed in the operational sections of this specifi cation is not implied.
Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability.
CAPACITANCE
(NOTE 2)
Parameter Symbol Max Unit
Input Capacitance: CLK CI1 7 pF
Addresses, BA0-1 Input Capacitance CA22 pF
Input Capacitance: All other input-only pins CI2 6 pF
Input/Output Capacitance: I/Os CIO 8 pF
BGA THERMAL RESISTANCE
Description Symbol Max Unit Notes
Junction to Ambient (No Airfl ow) JA 15.6 °C/W 1
Junction to Ball JB 10.6 °C/W 1
Junction to Case (Top) JC 6.9 °C/W 1
NOTE: 1. Refer to BGA Thermal Resistance Correlation application note at www.whiteedc.com in
the application notes section for modeling conditions.
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 9 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter Symbol
-100 -125 -133
UnitMin Max Min Max Min Max
Access time from CLK (pos. edge) CL = 3 tAC 7 6 5.5 ns
CL = 2 tAC 766ns
Address hold time tAH 1 1 0.8 ns
Address setup time tAS 2 2 1.5 ns
CLK high-level width tCH 3 3 2.5 ns
CLK low-level width tCL 3 3 2.5 ns
Clock cycle time (22) CL = 3 tCK 10 8 7.5 ns
CL = 2 tCK 13 10 10 ns
CKE hold time tCKH 1 1 0.8 ns
CKE setup time tCKS 2 2 1.5 ns
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 0.8 ns
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2 2 1.5 ns
Data-in hold time tDH 1 1 0.8 ns
Data-in setup time tDS 2 2 1.5 ns
Data-out high-impedance time CL = 3 (10) tHZ 7 6 5.5 ns
CL = 2 (10) tHZ 7 6 6 ns
Data-out low-impedance time tLZ 1 1 1 ns
Data-out hold time (load) tOH 3 3 3 ns
Data-out hold time (no load) (26) tOHN 1.8 1.8 1.8 ns
ACTIVE to PRECHARGE command tRAS 50 120,000 50 120,000 50 120,000 ns
ACTIVE to ACTIVE command period tRC 70 68 68 ns
ACTIVE to READ or WRITE delay tRCD 20 20 20 ns
Refresh period (8,192 rows) – Commercial, Industrial tREF 64 64 64 ms
Refresh period (8,192 rows) – Military tREF 16 16 16 ms
AUTO REFRESH period tRFC 70 70 70 ns
PRECHARGE command period tRP 20 20 20 ns
ACTIVE bank A to ACTIVE bank B command tRRD 20 20 20 ns
Transition time (7) tT 0.3 1.2 0.3 1.2 0.3 1.2 ns
WRITE recovery time (23) tWR
1 CLK + 7ns 1 CLK + 7ns 1 CLK +
7.5ns —
(24) 15 15 15 ns
Exit SELF REFRESH to ACTIVE command tXSR 80 80 75 ns
WEDPN16M72V-XB2X
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Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
AC FUNCTIONAL CHARACTERISTICS
(NOTES 5,6,7,8,9,11)
Parameter/Condition Symbol -100 -125 -133 Units
READ/WRITE command to READ/WRITE command (17) tCCD 111t
CK
CKE to clock disable or power-down entry mode (14) tCKED 1 1 1 tCK
CKE to clock enable or power-down exit setup mode (14) tPED 111t
CK
DQM to input data delay (17) tDQD 0 0 0 tCK
DQM to data mask during WRITEs tDQM 0 0 0 tCK
DQM to data high-impedance during READs tDQZ 2 2 2 tCK
WRITE command to input data delay (17) tDWD 0 0 0 tCK
Data-in to ACTIVE command (15) tDAL 455t
CK
Data-in to PRECHARGE command (16) tDPL 2 2 2 tCK
Last data-in to burst STOP command (17) tBDL 111t
CK
Last data-in to new READ/WRITE command (17) tCDL 1 1 1 tCK
Last data-in to PRECHARGE command (16) tRDL 2 2 2 tCK
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25) tMRD 222t
CK
Data-out to high-impedance from PRECHARGE command (17) CL = 3 tROH 333t
CK
CL = 2 tROH 2——t
CK
NOTES:
1. All voltages referenced to VSS.
2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
3. IDD is dependent on output loading and cycle rates. Specifi ed values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifi cations are used only to indicate cycle time at which proper operation over
the full temperature range is ensured.
6. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VCC must be powered up
simultaneously.) The two AUTO REFRESH command wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifi cation, the clock and CKE must transit between
VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q 1.5V
50Ω
10. tHZ defi nes the time at which the output achieves the open circuit condition; it is not a reference
to VOH or VOL. The last valid data element will meet tOH before going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover
point.
12. Other input signals are allowed to transition no more than once every two clocks and are
otherwise at valid VIH or VIL levels.
13. ICC specifi cations are tested after the device is properly initialized.
14. Timing actually specifi ed by tCKS; clock(s) specifi ed as a reference only at minimum cycle rate.
15. Timing actually specifi ed by tWR plus tRP; clock(s) specifi ed as a reference only at minimum cycle
rate.
16. Timing actually specifi ed by tWR.
17. Required clocks are specifi ed by JEDEC functionality and are not dependent on any timing
parameter.
18. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the
maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns.
22. The clock frequency must remain constant (stable clock is defi ned as a signal cycling within
timing constraints specifi ed for the clock pin) during access or precharge states (READ, WRITE,
including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the fi rst
clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 11 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
219 x Ø0.762 (0.030) NOM
1.27
(0.050)
NOM
25.1 (0.988) MAX
19.05 (0.750) NOM
21.1 (0.831)
MAX
19.05
(0.750)
NOM
2.03 (0.080)
MAX
0.61
(0.024)
NOM
PACKAGE DIMENSION – 219 PLASTIC BALL GRID ARRAY (PBGA)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
BOTTOM VIEW
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 12 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
WED P N 16M 72 V - XXX B2 X
WHITE ELECTRONIC DESIGNS CORP.
PLASTIC
SDRAM
CONFIGURATION, 16M x 72
3.3V POWER SUPPLY
FREQUENCY (MHz)
100 = 100MHz
125 = 125MHz
133 = 133MHz
PACKAGE:
B2 = 219 Plastic Ball Grid Array (PBGA), 21mm x 25mm
DEVICE GRADE:
M = Military -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
WEDPN16M72V-XB2X
December 2014 © 2014 Microsemi Corporation. All rights reserved. 13 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
Rev. 5
Microsemi Corporation reserves the right to change products or specifi cations without notice.
Document Title
16M x 72 SDRAM Multi-Chip Package, 21mm x 25mm
Revision History
Rev # History Release Date Status
Rev 0 Initial Release April 2004 Preliminary
Rev 1 Changes (Pg. 1, 14)
1.1 Change status to Final
June 2004 Final
Rev 2 Changes (Pg. 1, 14)
2.1 Change typical weight to 2.5g
2.2 Change packae size to 525mm2 in table
November 2004 Final
Rev 3 Changes (Pg. 1, 6, 9, 10, 11, 13, 14)
3.1 Update Capacitance table values
3.2 Add Thermal Resistance table values
3.3 Change Max Storage Temperature to 125°C
3.4 Change ICC7 to 12.5 mA for commerical and industrial temperatures only
3.5 Add 133MHz option
3.6 Update ICC1, ICC3 and ICC4
July 2005 Final
Rev 4 Changes (Pg. 1-13)
4.1 Change document layout from White Electronic Designs to Microsemi
July 2011 Final
Rev 5 Changes (Pg. 11)
5.1 Correct MO drawing to 21 x 25 mm
December 2014 Final
