Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specication and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specication before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
®Long-term Support
World Class Quality
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
• Power supply:
NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
• JTAG Boundary Scan for BGA packages
• Industrial temperature available
• Lead-free available
DESCRIPTION
The 9 Meg product family features high-speed, low-power
synchronous static RAMs designed to provide a burstable,
high-performance, 'no wait' state, device for networking and
communications applications. They are organized as 256K
words by 36 bits and 512K words by 18 bits, fabricated
with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW. Separate byte enables allow individual bytes to be
written.
A burst mode pin (MODE) denes the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
256K x 36 and 512K x 18
9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM JUNE 2017
FAST ACCESS TIME
Symbol Parameter -250 -200 -166 Units
tkq Clock Access Time 2.6 3.1 3.5 ns
tkc Cycle Time 4 5 6 ns
Frequency 250 200 166 MHz
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
BLOCK DIAGRAM
Address
Registers
Control register
CLK
/CKE
/CE
CE2
/CE2
ADV
/WE
/BWx
(X=a,b,c,d or a,b)
Control Logic
K
/OE
ZZ
K
Address
Registers
Address
Registers
Burst Logic
K
MODE
ADV
A0-A1 A'0-A'1
A2-17(A2-A18)
A0-17 ( A0-18) A0-17 ( A0-18)
256Kx36;
512Kx18
Memory Array
Data-In
Register
Data-In
Register
K
K
Output
Register
K
Output
Buffers
A0-17(A0-18)
36(18)
DQx/DQPx
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
Bottom View
165-Ball, 13 mm x 15mm BGA
Bottom View
119-Ball, 14 mm x 22 mm BGA
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
1 2345678910 11
ANC ACE BWcBWbCE2CKE ADV A A NC
B NC A CE2 BWdBWaCLK WE OE NC ANC
CDQPc NC Vddq VSS VSS VSS VSS VSS Vddq NC DQPb
DDQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb
EDQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb
F DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb
G DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb
HNC NC NC Vdd VSS VSS VSS Vdd NC NC ZZ
J DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa
K DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa
L DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa
MDQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa
N DQPd NC Vddq VSS NC NC NC VSS Vddq NC DQPa
P NC NC AATdI A1* TDO AAANC
RMODE NC AATMS A0* TCK A A A A
Note: A0 and A1 are the two least signicant bits (LSB) of the address eld and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CLK Synchronous Clock
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a-d) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDI JTAG Pins
TDO, TMS
VDD Power Supply
NC No Connect
DQx Data Inputs/Outputs
DQPx Parity Data I/O
VDDQ I/O Power Supply
VSS Ground
PIN CONFIGURATION — 256K x 36, 165-Ball BGA (TOP VIEW)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
119-PIN BGA PACKAGE CONFIGURATION 256K x 36 (TOP VIEW)
1234567
AA
BWb
BNC
CNC
DDQc DQPc Vss
EDQc DQc Vss
F
VDDQ DQc
GDQc DQc
HDQc DQc
J
VDDQ VDD
KDQd DQd
L
DQd DQd
MVDDQ DQd
NDQd DQd
Vss
P
NC
DQPd
RA
CE2
MODE
A0*
A
A
A
VSS
VSS
VSS
VSS
BWd
V
SS
VSS
VSS
NC
NC
VDD
VDD VDD
VDD
NC
Vss
Vss
Vss
Vss
Vss
NC
CE2
NCA
NC
T
UVDDQ
NC
VDDQ
DQd
A
NC
TMS TDI
A
A
BWc
TCK
A1*
CKE
NC
CLK
NC
WE
A
OE
CE
NC
ADV
TDO
A
NC
BWa
A
A
A
DQPa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQPb
A
A
VDDQ
ZZ
DQa
DQa
VDDQ
DQa
DQa
VDDQ
DQb
DQb
VDDQ
DQb
DQb
NC
VDDQ
VSS
Note: A0 and A1 are the two least signicant bits(LSB) of the address eld and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CLK Synchronous Clock
CKE Clock Enable
CE Synchronous Chip Select
CE2 Synchronous Chip Select
CE2 Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDO JTAG Pins
TMS, TDI
Vdd Power Supply
VSS Ground
NC No Connect
DQa-DQd Data Inputs/Outputs
DQPa-Pd Parity Data I/O
Vddq I/O Power Supply
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
165-PIN BGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW)
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CLK Synchronous Clock
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
12345678910 11
AABWbCKE
BNC A WE OE
CNCNC Vss Vss
DNCDQb Vss Vss NC
ENCDQb Vss Vss Vss
F
NC DQb NC
GNCDQb
NC
NC
HNCNC
VDDQ
J
DQb NC DQa
KDQb NC
L
DQb NC Vss
M DQb NC Vss
N DQPb NC Vss Vss NC
PNCNC A1* TDO
R MODE ATCK
CE2
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
AA
A
A
A
A
A
A
AA
A
A
NC A
A
CE
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDI
TMS
CE2
CLK
Vss
NC
A0*
NC
Vss
Vss
Vss
Vss
Vss
Vss
ADV
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
NC
ZZ
DQa
DQa
DQa
DQa
DQPa
Note: A0 and A1 are the two least signicant bits (LSB) of the address eld and set the internal burst counter if burst is desired.
MODE Burst Sequence Selection
TCK, TDI JTAG Pins
TDO, TMS
VDD Power Supply
NC No Connect
DQx Data Inputs/Outputs
DQPx Parity Data I/O
VDDQ I/O Power Supply
VSS Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
119-PIN BGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW)
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CLK Synchronous Clock
CKE Clock Enable
CE Synchronous Chip Select
CE2 Synchronous Chip Select
CE2 Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDO JTAG Pins
TMS, TDI
Vdd Power Supply
VSS Ground
NC No Connect
DQa-DQb Data Inputs/Outputs
DQPa-Pb Parity Data I/O
Vddq I/O Power Supply
1234567
AA
BNC
CNC
DDQb Vss
EDQb Vss
F
VDDQ
GDQb
HDQb
J
VDDQ VDD
KDQb
L
DQb
MVDDQ DQb
NDQb NC
Vss
P
NC
DQPb
RA
CE2
MODE
A
A0*
A
A
V
SS
V
SS
V
SS
V
SS
NC
V
SS
V
SS
NC
NC
VDD
VDD VDD
VDD
NC
Vss
Vss
Vss
Vss
Vss
NC
CE2
NCA
NC
T
UVDDQ
NC
VDDQ
A
NC
TMS TDI
A
A
BWb
TCK
A1*
CKE
NC
CLK
NC
WE
A
OE
CE
NC
ADV
TDO
A
NC
BWa
A
A
A
DQPa
DQa
DQa
DQa
DQa
A
A
VDDQ
ZZ
DQa
DQa
VDDQ
DQa
DQa
VDDQ
VDDQ
NC
VDDQ
NC
NC
NC
NC
NC
NC
NC
NC
A
V
SS
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
Note: A0 and A1 are the two least signicant bits(LSB) of the address eld and set the internal burst counter if burst is desired.
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
PIN CONFIGURATION
100-Pin QFP
512K x 18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
V
DDQ
Vss
NC
DQPa
DQa
DQa
Vss
V
DDQ
DQa
DQa
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
NC
NC
Vss
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
Vss
NC
NC
DQb
DQb
Vss
V
DDQ
DQb
DQb
NC
V
DD
NC
Vss
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQPb
NC
Vss
V
DDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
V
DD
Vss
CLK
WE
CKE
OE
ADV
NC
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
V
DD
NC
NC
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQb
DQb
Vss
V
DDQ
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
DQa
DQa
Vss
V
DDQ
DQa
DQa
DQPa
DQPc
DQc
DQc
V
DDQ
Vss
DQc
DQc
DQc
DQc
Vss
V
DDQ
DQc
DQc
NC
V
DD
NC
Vss
DQd
DQd
V
DDQ
Vss
DQd
DQd
DQd
DQd
Vss
V
DDQ
DQd
DQd
DQPd
A
A
CE
CE2
BW
d
BWc
BW
b
BW
a
CE2
V
DD
Vss
CLK
WE
CKE
OE
ADV
NC
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
V
DD
NC
NC
A
A
A
A
A
A
A
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CLK Synchronous Clock
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
WE Write Enable
CKE Clock Enable
Vss Ground for Core
NC Not Connected
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
DQPa-DQPd Parity Data I/O
MODE Burst Sequence Selection
Vdd Power Supply
VSS Ground for output Buffer
Vddq I/O Power Supply
ZZ Snooze Enable
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
SYNCHRONOUS TRUTH TABLE(1)
Address
Operation Used CE CE2 CE2 ADV WE BWx OE CKE CLK
Not Selected N/A H X X L X X X L ↑
Not Selected N/A X L X L X X X L ↑
Not Selected N/A X X H L X X X L ↑
Not Selected Continue N/A X X X H X X X L ↑
Begin Burst Read External Address L H L L H X L L ↑
Continue Burst Read Next Address X X X H X X L L ↑
NOP/Dummy Read External Address L H L L H X H L ↑
Dummy Read Next Address X X X H X X H L ↑
Begin Burst Write External Address L H L L L L X L ↑
Continue Burst Write Next Address X X X H X L X L ↑
NOP/Write Abort N/A L H L L L H X L ↑
Write Abort Next Address X X X H X H X L ↑
Ignore Clock Current Address X X X X X X X H ↑
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed rst.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation nally depends on status of asynchronous pins (ZZ and OE).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ WRITE
BURST
BURST
BURST
DS
DS
DS
READ
DSDS
READ WRITE
WRITE
BURST BURST
WRITE
READ
STATE DIAGRAM
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
ASYNCHRONOUS TRUTH TABLE(1)
Operation ZZ OE I/O STATUS
Sleep Mode H X High-Z
Read L L DQ
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data
bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation WE BWa BWb
READ H X X
WRITE BYTE a L L H
WRITE BYTE b L H L
WRITE ALL BYTEs L L L
WRITE ABORT/NOP L H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
WRITE TRUTH TABLE (x36)
Operation WE BWa BWb BWc BWd
READ H X X X X
WRITE BYTE a L L H H H
WRITE BYTE b L H L H H
WRITE BYTE c L H H L H
WRITE BYTE d L H H H L
WRITE ALL BYTEs L L L L L
WRITE ABORT/NOP L H H H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
LINEAR BURST ADDRESS TABLE (MODE = VSS)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter NLP Value NVP/NVVP Value Unit
TSTG Storage Temperature –65 to +150 –65 to +150 °C
Pd Power Dissipation 1.6 1.6 W
IouT Output Current (per I/O) 100 100 mA
VIn, VouT Voltage Relative to VSS for I/O Pins –0.5 to Vddq + 0.3 –0.5 to Vddq + 0.3 V
VIn Voltage Relative to VSS for –0.3 to Vdd+0.5 –0.3 to Vdd+0.3 V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric elds; however, precau-
tions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3.
This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1A1', A0' = 1,1
OPERATING RANGE (IS61NLPx)
Range Ambient Temperature VDD VDDq
Commercial 0°C to +70°C 3.3V ± 5% 3.3V / 2.5V ± 5%
Industrial -40°C to +85°C 3.3V ± 5% 3.3V / 2.5V ± 5%
OPERATING RANGE (IS61NVPx)
Range Ambient Temperature VDD VDDq
Commercial 0°C to +70°C 2.5V ± 5% 2.5V ± 5%
Industrial -40°C to +85°C 2.5V ± 5% 2.5V ± 5%
OPERATING RANGE (IS61NVVPx)
Range Ambient Temperature VDD VDDq
Commercial 0°C to +70°C 1.8V ± 5% 1.8V ± 5%
Industrial -40°C to +85°C 1.8V ± 5% 1.8V ± 5%
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 1, 2, 3
3.3V 2.5V 1.8V
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
Voh Output HIGH Voltage Ioh = –4.0 mA (3.3V) 2.4 — 2.0 — Vddq - 0.4 — V
Ioh = –1.0 mA (2.5V, 1.8V)
Vol Output LOW Voltage Iol = 8.0 mA (3.3V) — 0.4 — 0.4 — 0.4 V
Iol = 1.0 mA (2.5V, 1.8V)
VIh Input HIGH Voltage 2.0 Vdd + 0.3 1.7 Vdd + 0.3 0.6Vdd Vdd + 0.3 V
VIl Input LOW Voltage –0.3 0.8 –0.3 0.7 –0.3 0.3Vdd V
IlI Input Leakage Current VSS ≤ VIn ≤ Vdd(1) –5 5 –5 5 –5 5 µA
Ilo Output Leakage Current VSS ≤ VouT ≤ Vddq, OE = VIh –5 5 –5 5 –5 5 µA
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: VIh (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2)
1.8V: VIh (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: VIl (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: VIl (AC) ≥ -0.5V (Pulse width less than tkc /2)
-250
MAX
-200
MAX
-166
MAX
Symbol Parameter Test Conditions Temp. range x18 x36 x18 x36 x18 x36 Unit
Icc
AC Operating
Supply Current
Device Selected, OE = VIh,
ZZ ≤ VIl, All Inputs ≤ 0.2V or
≥ Vdd – 0.2V, Cycle Time ≥
tkc min.
Com.
Ind.
215
220
215
220
175
180
175
180
165
170
165
170
mA
ISb
Standby Current
TTL Input
Device Deselected, Vdd =
Max., All Inputs ≤ VIl or ≥ VIh,
ZZ ≤ VIl, f = Max.
Com.
Ind.
65
70
65
70
65
70
65
70
65
70
65
70
mA
ISbI
Standby Current
CMOS Input
Device Deselected,Vdd =
Max.,VIn ≤ VSS + 0.2V or
≥Vdd – 0.2V
f = 0
Com.
Ind.
50
55
50
55
50
55
50
55
50
55
50
55
mA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or VSS. It exhibits ±100µA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ Vdd – 0.2V.
14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
3.3V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
+3.3V
Figure 1 Figure 2
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cIn Input Capacitance VIn = 0V 6 pF
couT Input/Output Capacitance VouT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°c, f = 1 MHz, Vdd = 3.3V.
3.3V I/O OUTPUT LOAD EQUIVALENT
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
2.5V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 2.5V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.25V
and Reference Level
Output Load See Figures 3 and 4
Z
O
= 50Ω
1.25V
50Ω
OUTPUT
1,667 Ω
5 pF
Including
jig and
scope
1,538 Ω
OUTPUT
+2.5V
Figure 3 Figure 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1.8V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 1.8V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 0.9V
and Reference Level
Output Load See Figures 5 and 6
Z
O
= 50Ω
0.9V
50Ω
OUTPUT
1K Ω
5 pF
Including
jig and
scope
1K Ω
OUTPUT
+1.8V
Figure 5 Figure 6
1.8V I/O OUTPUT LOAD EQUIVALENT
16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-250 -200 -166
Symbol Parameter Min. Max. Min. Max. Min. Max Unit
fmax Clock Frequency — 250 — 200 — 166 MHz
tkc Cycle Time 4.0 — 5 — 6 — ns
tkh Clock High Time 1.7 — 2 — 2.4 — ns
tkl Clock Low Time 1.7 — 2 — 2.4 — ns
tkq Clock Access Time — 2.6 — 3.1 — 3.5 ns
tkqx(2) Clock High to Output Invalid 0.8 — 1.5 — 1.5 — ns
tkqlz(2,3) Clock High to Output Low-Z 0.8 — 1 — 1.2 — ns
tkqhz(2,3) Clock High to Output High-Z — 2.6 — 3.1 — 3.5 ns
toeq Output Enable to Output Valid — 2.6 — 3.1 — 3.5 ns
toelz(2,3) Output Enable to Output Low-Z 0 — 0 — 0 — ns
toehz(2,3) Output Disable to Output High-Z — 2.6 — 3.0 — 3.5 ns
taS Address Setup Time 1.2 — 1.4 — 0 1.5 ns
twS Read/Write Setup Time 1.2 — 1.4 — 0 1.5 ns
tceS Chip Enable Setup Time 1.2 — 1.4 — 0 1.5 ns
tSe Clock Enable Setup Time 1.2 — 1.4 — 0 1.5 ns
tadVS Address Advance Setup Time 1.2 — 1.4 — 0 1.5 ns
tdS Data Setup Time 1.2 — 1.4 — 0 1.5 ns
tah Address Hold Time 0.3 — 0.4 — 0.5 — ns
the Clock Enable Hold Time 0.3 — 0.4 — 0.5 — ns
twh Write Hold Time 0.3 — 0.4 — 0.5 — ns
tceh Chip Enable Hold Time 0.3 — 0.4 — 0.5 — ns
tadVh Address Advance Hold Time 0.3 — 0.4 — 0.5 — ns
tdh Data Hold Time 0.3 — 0.4 — 0.5 — ns
tPower(4) Vdd (typical) to First Access 1 — 1 — 1 — ms
Notes:
1. Conguration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. tPower is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be
initiated.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 17
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
SLEEP MODE TIMING
Don't Care
Deselect or Read Only Deselect or Read Only
tRZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
ISB2
ZZ setup cycle ZZ recovery cycle
Normal
operation
cycle
tPDS tPUS
tZZI
High-Z
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Temperature Min. Max. Unit
Range
Isb2 Current during SNOOZE MODE ZZ ≥ Vih Com. — 20 mA
Ind. — 25
tpds ZZ active to input ignored — 2 cycle
tpus ZZ inactive to input sampled 2 — cycle
tzzi ZZ active to SNOOZE current — 2 cycle
trzzi ZZ inactive to exit SNOOZE current 0 — ns
18 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
READ CYCLE TIMING
t
DS
CLK
ADV
Address
WRITE
CKE
CE
OE
Data Out
A1 A2 A3
t
KH
t
KL
t
KC
Q3-3 Q3-4Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
t
OEHZ
t
SE
t
HE
t
AS
t
AH
t
WS
t
WH
t
CES
t
CEH
t
ADVS
t
ADVH
t
KQHZ
t
KQ
t
OEQ
t
OEHZ
Q1-1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 19
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
WRITE CYCLE TIMING
t
DS
t
DH
CLK
ADV
Address
WRITE
CKE
CE
OE
Data In
Data Out
A1 A2 A3
t
KH
t
KL
t
KC
t
SE
t
HE
D3-3 D3-4D3-2D3-1D2-4D2-3D2-2D2-1D1-1
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
t
OEHZ
Q0-3 Q0-4
20 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
SINGLE READ/WRITE CYCLE TIMING
CLK
C
KE
Address
W
RITE
C
E
ADV
O
E
Data Out
Data In D5
t
SE
t
HE
t
KH
t
KL
t
KC
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D2
t
OELZ
t
OEQ
A1 A2 A3 A4 A5 A6 A7 A8 A9
Q1 Q3 Q4 Q6 Q7
t
DS
t
DH
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 21
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
CKE OPERATION TIMING
A1 A2 A3 A4 A5 A6
Q1 Q3 Q4
CLK
CKE
Address
WRITE
CE
ADV
OE
Data Out
Data In D2
t
SE
t
HE
t
KH
t
KL
t
KC
t
KQLZ
t
KQHZ
t
KQ
t
DH
t
DS
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
22 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
CE OPERATION TIMING
Don't Care
Undefined
CLK
CKE
Address
WRITE
CE
ADV
OE
Data Out
Data In
t
SE
t
HE
t
KH
t
KL
t
KC
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D5
D3
t
DH
t
DS
t
OELZ
t
OEQ
Q1 Q2 Q4
t
KQHZ
t
KQLZ
t
KQ
A1 A2 A3 A4 A5
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 23
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The serial boundary scan Test Access Port (TAP) is only
available in the BGA package. (Not available in QFP
package.) This port operates in accordance with
IEEE
Standard 1149.1-1900, but does not include all functions
required for full 1149.1 compliance. These functions from
the
IEEE specication
are excluded because they place
added delay in the critical speed path of the SRAM. The
TAP controller operates in a manner that does not conict
with the performance of other devices using 1149.1 fully
compliant TAPs.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to Vdd through a pull-up resistor.
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All inputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any regis-
ter. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an applica-
tion. TDI is connected to the Most Signicant Bit (MSB)
on any register.
31 30 29
. . .
2 1 0
2 1 0
0
x
. . . . .
2 1 0
Bypass Register
Instruction Register
Identification Register
Boundary Scan
Register*
TAP CONTROLLER
Selection Circuitry Selection Circuitry TDOTDI
TCK
TMS
TAP CONTROLLER BLOCK DIAGRAM
24 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the cur-
rent state of the
TAP
state machine (see
TAP
Controller
State Diagram). The output changes on the falling edge
of TCK and TDO is connected to the Least Signicant Bit
(LSB) of any register.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (Vdd) for ve
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on
the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the in-
struction register. This register is loaded when it is placed
between the
TDI
and
TDO
pins. (See
TAP
Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the CaptureIR state, the two
least signicant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the
SRAM
with minimal delay. The bypass reg-
ister is set LOW (VSS) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the
SRAM
. Several no connect
(NC)
pins are
also included in the scan register to reserve pins for higher
density devices. The x36 conguration has a 75-bit-long
register and the x18 conguration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed be-
tween the
TDI
and
TDO
pins when the controller is moved
to the
Shift-DR
state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Identication (ID) Register
The ID register is loaded with a vendor-specic, 32-bit
code during the Capture-DR state when the IDCODE com-
mand is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identication Register Denitions table.
Scan Register Sizes
Register Bit Size Bit Size
Name (x18) (x36)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan 90 90
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field Description 256K x 36 512K x 18
Revision Number (31:28) Reserved for version number. xxxx xxxx
Device Depth (27:23) Denes depth of SRAM. 256K or 512K 00111 01000
Device Width (22:18) Denes width of the SRAM. x36 or x18 00100 00011
ISSI Device ID (17:12) Reserved for future use. xxxxx xxxxx
ISSI JEDEC ID (11:1) Allows unique identication of SRAM vendor. 00001010101 00001010101
ID Register Presence (0) Indicate the presence of an ID register. 1 1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 25
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
TAP INSTRUCTION SET
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as
RESERVED
and should not be used and the other ve instructions are
described below. The TAP controller used in this SRAM
is not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the
Input
or
Output
buf-
fers. The
SRAM
does not implement the
1149.1
commands
EXTEST
or
INTEST
or the
PRELOAD
portion of
SAMPLE/
PRELOAD
; instead it performs a capture of the
Inputs and
Output
ring when these instructions are executed. Instruc-
tions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted from
the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, the TAP control-
ler must be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When an
EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is a difference between the instruc-
tions, unlike the
SAMPLE/PRELOAD
instruction, EXTEST
places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specic, 32-
bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also places
all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant. When the
SAMPLE/PRELOAD instruction is loaded to the instruc-
tion register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
It is important to realize that the TAP controller clock oper-
ates at a frequency up to 10 MHz, while the SRAM clock
runs more than an order of magnitude faster. Because of
the clock frequency differences, it is possible that during
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition (metastable state). The device will not be harmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up
plus hold times (tcS and tch). To insure that the SRAM
clock input is captured correctly, designs need a way to
stop (or slow) the clock during a SAMPLE/PRELOAD
instruction. If this is not an issue, it is possible to capture
all other signals and simply ignore the value of the CLK
captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the
PRELOAD
part of the command is not
implemented, putting the
TAP
into the
Update
to the
Update-
DR
state while performing a
SAMPLE/PRELOAD
instruction
will have the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruc-
tion register and the TAP is placed in a Shift-DR state,
the bypass register is placed between the TDI and TDO
pins. The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
26 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
INSTRUCTION CODES
Code Instruction Description
000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register be-
tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
011 RESERVED Do Not Use: This instruction is reserved for future use.
100
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between
TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
101 RESERVED Do Not Use: This instruction is reserved for future use.
110 RESERVED Do Not Use: This instruction is reserved for future use.
111 BYPASS Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test/Idle 11 1
11
11
1
1
11
11
1
0
0
0
0
1
00
0
0
0
0
0
0
0
0
0
10
TAP CONTROLLER STATE DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 27
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
TAP Electrical Characteristics (2.5V and 3.3V operating range)
Symbol Parameter Test Conditions Min. Max. Units
Voh1 Output HIGH Voltage Ioh = –2.0 mA 1.7 — V
Voh2 Output HIGH Voltage Ioh = –100
µ
A 2.1 — V
Vol1 Output LOW Voltage Iol = 2.0 mA — 0.7 V
Vol2 Output LOW Voltage Iol = 100
µ
A — 0.2 V
VIh Input HIGH Voltage 1.7 Vdd +0.3 V
VIl Input LOW Voltage –0.3 0.7 V
Ix Input Leakage Current VSS ≤ V I ≤ Vddq –10 10
µ
A
TAP Electrical Characteristics (1.8V operating range)
Symbol Parameter Test Conditions Min. Max. Units
Voh1 Output HIGH Voltage Ioh = –2.0 mA Vdd-0.4 — V
Vol1 Output LOW Voltage Iol = 2.0 mA -0.3 0.5 V
VIh Input HIGH Voltage 1.3 Vdd +0.3 V
VIl Input LOW Voltage –0.3 0.7 V
Ix Input Leakage Current VSS ≤ V I ≤ Vddq –10 10
µ
A
Parameter Symbol Min Max Units
TCK cycle time tTHTH 100 –ns
TCK high pulse width tTHTL 40 – ns
TCK low pulse width tTLTH 40 – ns
TMS Setup tMVTH 10 –ns
TMS Hold tTHMX 10 –ns
TDI Setup tDVTH 10 –ns
TDI Hold tTHDX 10 –ns
TCK Low to Valid Data tTLOV –20 ns
TAP AC ELECTRICAL CHARACTERISTICS (OVER OPERATING RANGE)
28 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
DON'T CARE
UNDEFINED
TCK
TMS
TDI
TDO
tTHTL
tTLTH
tTHTH
tMVTH tTHMX
tDVTH tTHDX
1 2 3 4 5 6
tTLOX
tTLOV
TAP TIMING
20 pF
TDO
GND
50Ω
Vtrig
Z0 = 50Ω
TAP Output Load Equivalent
(1.8V/2.5V/3.3V) Input pulse levels 0 to 1.8V/0 to 2.5V/0 to 3.0V
Input rise and fall times 1.5ns
Input timing reference levels 0.9V/1.25V/1.5V
Output reference levels 0.9V/1.25V/1.5V
Test load termination supply voltage 0.9V/1.25V/1.5V
Vtrig 0.9V/1.25V/1.5V
TAP TEST CONDITIONS
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 29
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
119 BGA BOUNDARY SCAN ORDER
TBD
30 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
165 BGA BOUNDARY SCAN ORDER
Continued on next page
165 BGA
X36 X18
Bit # Bump ID Signal Bump ID Signal
1 N6 NC N6 NC
2 N7 NC N7 NC
3 N10 NC N10 NC
4 P11 NC P11 NC
5 P8 A17 P8 A17
6 R8 A16 R8 A16
7 R9 A15 R9 A15
8 P9 A14 P9 A14
9 P10 A13 P10 A13
10 R10 A12 R10 A12
11 R11 A11 R11 A11
12 H11 ZZ H11 ZZ
13 N11 DQa0 N11 NC
14 M11 DQa1 M11 NC
15 L11 DQa2 L11 NC
16 M10 DQa3 M10 NC
17 L10 DQa4 L10 NC
18 K11 DQa5 K11 DQa8
19 J11 DQa6 J11 DQa7
20 K10 DQa7 K10 DQa6
21 J10 DQa8 J10 DQa5
22 H9 NC H9 NC
23 H10 NC H10 NC
24 G11 DQb8 G11 DQa4
25 F11 DQb7 F11 DQa3
26 G10 DQb6 G10 DQa2
27 E11 DQb5 E11 DQa1
28 D11 DQb4 D11 DQa0
29 F10 DQb3 C11 NC
30 E10 DQb2 E10 NC
31 D10 DQb1 D10 NC
32 C11 DQb0 F10 NC
33 A11 NC A11 A18
34 B11 NC B11 NC
35 A10 A10 A10 A10
36 B10 A9 B10 A9
37 A9 A8 A9 A8
38 B9 NC B9 NC
39 C10 NC C10 NC
40 A8 ADV A8 ADV
165 BGA
X36 X18
Bit # Bump ID Signal Bump ID Signal
41 B8 /OE B8 /OE
42 A7 /CKE A7 /CKE
43 B7 /WE B7 /WE
44 B6 CLK B6 CLK
45 A6 /CE2 A6 /CE2
46 B5 /Bwa B5 /Bwa
47 A5 /Bwb A5 NC
48 A4 /Bwc A4 /Bwb
49 B4 /Bwd B4 NC
50 B3 CE2 B3 CE2
51 A3 /CE1 A3 /CE1
52 A2 A7 A2 A7
53 B2 A6 B2 A6
54 C2 NC C2 NC
55 B1 NC B1 NC
56 A1 NC A1 NC
57 C1 DQc0 C1 NC
58 D1 DQc1 D1 NC
59 E1 DQc2 E1 NC
60 D2 DQc3 D2 NC
61 E2 DQc4 E2 NC
62 F1 DQc5 F1 DQb8
63 G1 DQc6 G1 DQb7
64 F2 DQc7 F2 DQb6
65 G2 DQc8 G2 DQb5
66 H1 NC H1 NC
67 H2 NC H2 NC
68 H3 NC H3 NC
69 J1 DQd8 J1 DQb4
70 K1 DQd7 K1 DQb3
71 J2 DQd6 J2 DQb2
72 L1 DQd5 L1 DQb1
73 M1 DQd4 M1 DQb0
74 K2 DQd3 M1 NC
75 L2 DQd2 L2 NC
76 M2 DQd1 M2 NC
77 N1 DQd0 K2 NC
78 N2 NC N2 NC
79 P1 NC P1 NC
80 R1 MODE R1 MODE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 31
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
165 BGA
X36 X18
Bit # Bump ID Signal Bump ID Signal
81 R2 NC R2 NC
82 P3 A5 P3 A5
83 R3 A4 R3 A4
84 P2 NC P2 NC
85 P4 A2 P4 A2
86 R4 A3 R4 A3
87 N5 NC N5 NC
88 P6 A1 P6 A1
89 R6 AD R6 AD
90 * Int * Int
32 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
ORDERING INFORMATION (VDD = 3.3V/VDDq = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Access Time Order Part Number Package
256Kx36
250 IS61NLP25636B-250TQL 100 QFP, Lead-free
IS61NLP25636BHD-250TQL(1) 100 QFP, Lead-free
IS61NLP25636B-250B3 165 BGA
IS61NLP25636B-250B2 119 BGA
200 IS61NLP25636B-200TQL 100 QFP, Lead-free
IS61NLP25636B-200B3 165 BGA
IS61NLP25636B-200B3L 165 BGA, Lead-free
IS61NLP25636B-200B2 119 BGA
IS61NLP25636B-200B2L 119 BGA, Lead-free
512Kx18
250 IS61NLP51218B-250TQL 100 QFP, Lead-free
IS61NLP51218B-250B3 165 BGA
IS61NLP51218B-250B2 119 BGA
200 IS61NLP51218B-200TQL 100 QFP, Lead-free
IS61NLP51218B-200B3 165 BGA
IS61NLP51218B-200B2 119 BGA
Note:
1. High driver strength
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 33
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
ORDERING INFORMATION (VDD = 3.3V/VDDq = 2.5V/3.3V)
Industrial Range: -40°C to +85°C
Access Time Order Part Number Package
256Kx36
250 IS61NLP25636B-250TQLI 100 QFP, Lead-free
IS61NLP25636B-250B3I 165 BGA
IS61NLP25636B-250B2I 119 BGA
200 IS61NLP25636B-200TQLI 100 QFP, Lead-free
IS61NLP25636B-200B3I 165 BGA
IS61NLP25636B-200B3LI 165 BGA, Lead-free
IS61NLP25636B-200B2I 119 BGA
IS61NLP25636B-200B2LI 119 BGA, Lead-free
512Kx18
250 IS61NLP51218B-250TQLI 100 QFP, Lead-free
IS61NLP51218B-250B3I 165 BGA
IS61NLP51218B-250B2I 119 BGA
200 IS61NLP51218B-200TQLI 100 QFP, Lead-free
IS61NLP51218B-200B3I 165 BGA
IS61NLP51218B-200B2I 119 BGA
34 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
ORDERING INFORMATION (VDD = 2.5V/VDDq = 2.5V)
Industrial Range: -40°C to +85°C
Access Time Order Part Number Package
256Kx36
250 IS61NVP25636B-250TQLI 100 QFP, Lead-free
IS61NVP25636B-250B3I 165 BGA
IS61NVP25636B-250B2I 119 BGA
200 IS61NVP25636B-200TQLI 100 QFP, Lead-free
IS61NVP25636B-200B3I 165 BGA
IS61NVP25636B-200B2I 119 BGA
512Kx18
250 IS61NVP51218B-250TQLI 100 QFP, Lead-free
IS61NVP51218B-250B3I 165 BGA
IS61NVP51218B-250B2I 119 BGA
200 IS61NVP51218B-200TQLI 100 QFP, Lead-free
IS61NVP51218B-200B3I 165 BGA
IS61NVP51218B-200B2I 119 BGA
ORDERING INFORMATION (VDD = 1.8V/VDDq = 1.8V)
Please contact SRAM Marketing at sram@issi.com
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 35
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
36 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 37
Rev. A3
06/21/2017
IS61NLP25636B/IS61NVP/NVVP25636B
IS61NLP51218B/IS61NVP/NVVP51218B
®Long-term Support
World Class Quality