BQ2201SNTR - Texas Instruments - Datasheet.Directory

Features

➤Power monitoring and switching

for 3-volt battery-backup applica-

tions

➤Write-protect control

➤3-volt primary cell inputs

➤Less than 10ns chip-enable

propagation delay

➤5% or 10% supply operation

General Description

The CMOS bq2201 SRAM Nonvolatile

Controller Unit provides all necessary

functions for converting a standard

CMOS SRAM into nonvolatile

read/write memory.

A precision comparator monitors the

5V VCC input for an out-of-tolerance

condition. When out of tolerance is

detected, a conditioned chip-enable

output is forced inactive to write-

protect any standard CMOS SRAM.

During a power failure, the external

SRAM is switched from the VCC

supply to one of two 3V backup sup-

plies. On a subsequent power-up, the

SRAM is write-protected until a

power-valid condition exists.

The bq2201 is footprint- and timing-

compatible with industry stan-

dards with the added benefit of a

chip-enable propagation delay of

less than 10ns.

SRAM Nonvolatile Controller Unit

bq2201

Oct. 1998 D

Pin Names

VOUT Supply output

BC1—BC23-volt primary backup cell inputs

THS Threshold select input

CE chip-enable active low input

CECON Conditioned chip-enable output

VCC +5-volt supply input

VSS Ground

NC No Connect

Functional Description

Pin Connections

An external CMOS static RAM can be battery-backed

using the VOUT and the conditioned chip-enable output

pin from the bq2201. As VCC slews down during a power

failure, the conditioned chip-enable output CECON is

forced inactive independent of the chip-enable input CE.

This activity unconditionally write-protects external

SRAM as VCC falls to an out-of-tolerance threshold VPFD.

VPFD is selected by the threshold select input pin, THS.

If THS is tied to VSS, power-fail detection occurs at 4.62V

typical for 5% supply operation. If THS is tied to VCC,

power-fail detection occurs at 4.37V typical for 10% sup-

ply operation. The THS pin must be tied to VSS or VCC for

proper operation.

If a memory access is in process during power-fail detec-

tion, that memory cycle continues to completion before the

memory is write-protected. If the memory cycle is not ter-

minated within time tWPT, the CECON output is uncondi-

tionally driven high, write-protecting the memory.

PN220101.eps

8-Pin Narrow DIP or SOIC

VCC

BC1

CECON

VOUT

BC2

THS

VSS

PN2201E.eps

16-Pin SOIC

CON

OUT

THS

VSS

As the supply continues to fall past VPFD, an internal

switching device forces VOUT to one of the two external

backup energy sources. CECON is held high by the VOUT

energy source.

During power-up, VOUT is switched back to the VCC sup-

ply as VCC rises above the backup cell input voltage

sourcing VOUT. The CECON output is held inactive for

time tCER (120 ms maximum) after the supply has

reached VPFD, independent of the CE input, to allow for

processor stabilization.

During power-valid operation, the CE input is fed

through to the CECON output with a propagation delay

of less than 10ns. Nonvolatility is achieved by hardware

hookup, as shown in Figure 1.

Energy Cell Inputs—BC1,BC2

Two primary backup energy source inputs are provided

on the bq2201. The BC1and BC2inputs accept a 3V pri-

mary battery, typically some type of lithium chemistry.

If no primary cell is to be used on either BC1or BC2, the

unused input should be tied to VSS.

If both inputs are used, during power failure the VOUT

output is fed only by BC1as long as it is greater than

2.5V. If the voltage at BC1falls below 2.5V, an internal

isolation switch automatically switches VOUT from BC1

to BC2.

To prevent battery drain when there is no valid data to

retain, VOUT and CECON are internally isolated from

BC1and BC2by either of the following:

■Initial connection of a battery to BC1or BC2,or

■Presentation of an isolation signal on CE.

A valid isolation signal requires CE low as VCC crosses

both VPFD and VSO during a power-down. See Figure 2.

Between these two points in time, CE must be brought

to the point of (0.48 to 0.52)*VCC and held for at least

700ns. The isolation signal is invalid if CE exceeds

0.54*VCC at any point between VCC crossing VPFD and

VSO.

The appropriate battery is connected to VOUT and CECON

immediately on subsequent application and removal of VCC.

FG220101.eps

VCC

BC1

THS

VSS

VOUT

CECON

BC2

bq2201

VCC

CMOS

SRAM

From Address Decoder

Primary

Cell

Primary

Cell

Figure 1. Hardware Hookup (5% Supply Operation)

Oct. 1998 D

TD220101.eps

VCC

VPFD

VSO

0.5 VCC

700ns

Figure 2. Battery Isolation Signal

bq2201

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V

VTDC voltage applied on any pin excluding VCC

relative to VSS -0.3 to 7.0 V VT≤VCC + 0.3

TOPR Operating temperature

0 to +70 °C Commercial

-40 to +85 °C Industrial “N”

TSTG Storage temperature -55 to +125 °C

TBIAS Temperature under bias -40 to +85 °C

TSOLDER Soldering temperature 260 °C For 10 seconds

IOUT VOUT current 200 mA

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

Recommended DC Operating Conditions (TA=T

OPR)

Symbol Parameter Minimum Typical Maximum Unit Notes

VCC Supply voltage

4.75 5.0 5.5 V THS = VSS

4.50 5.0 5.5 V THS = VCC

VSS Supply voltage 0 0 0 V

VIL Input low voltage -0.3 - 0.8 V

VIH Input high voltage 2.2 - VCC + 0.3 V

VBC1,

VBC2 Backup cell voltage 2.0 - 4.0 V

THS Threshold select -0.3 - VCC + 0.3 V

Note: Typical values indicate operation at TA= 25°C, VCC = 5V or VBC.

Oct. 1998 D

bq2201

DC Electrical Characteristics (TA=T

OPR,V

CC = 5V ±10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILI Input leakage current - - ±1µAV

IN =V

SS to VCC

VOH Output high voltage 2.4 - - V IOH = -2.0mA

VOHB VOH, BC supply VBC - 0.3 - - V VBC >V

CC,I

OH = -10µA

VOL Output low voltage - - 0.4 V IOL = 4.0mA

ICC Operating supply current - 3 5 mA No load on VOUT and CECON.

VPFD Power-fail detect voltage

4.55 4.62 4.75 V THS = VSS

4.30 4.37 4.50 V THS = VCC

VSO Supply switch-over voltage - VBC -V

CCDR Data-retention mode

current - - 100 nA

VOUT data-retention current

to additional memory not in-

cluded.

VOUT1 VOUT voltage VCC - 0.2 - - V VCC >V

BC,I

OUT = 100mA

VCC - 0.3 - - V VCC >V

BC,I

OUT = 160mA

VOUT2 VOUT voltage VBC - 0.3 - - V VCC <V

BC,I

OUT = 100µA

VBC Active backup cell

voltage

-V

BC2 -VV

BC1 < 2.5V

-V

BC1 -VV

BC1 > 2.5V

IOUT1 VOUT current - - 160 mA VOUT >V

CC - 0.3V

IOUT2 VOUT current - 100 - µAV

OUT >V

BC - 0.2V

Note: Typical values indicate operation at TA= 25°C, VCC = 5V or VBC.

Oct. 1998 D

bq2201

AC Test Conditions

Parameter Test Conditions

Input pulse levels 0V to 3.0V

Input rise and fall times 5ns

Input and output timing reference levels 1.5V (unless otherwise specified)

Output load (including scope and jig) See Figure 3

FG220102.eps

960

100pF

CECON

510

Figure 3. Output Load

Capacitance (TA= 25°C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CIN Input capacitance - - 8 pF Input voltage = 0V

COUT Output capacitance - - 10 pF Output voltage = 0V

Note: This parameter is sampled and not 100% tested.

Oct. 1998 D

bq2201

TD220102.eps

VCC

CECON

tPF

tFS

4.75

VPFD

4.25 VSO

tWPT VOHB

Power-Down Timing

Power-Fail Control (TA = TOPR)

Symbol Parameter Minimum Typical Maximum Unit Notes

tPF VCC slew, 4.75V to 4.25V 300 - - µs

tFS VCC slew, 4.25V to VSO 10 - - µs

tPU VCC slew, 4.25V to 4.75V 0 - - µs

tCED Chip-enable propagation

delay - 7 10 ns

tCER Chip-enable recovery 40 80 120 ms

Time during which SRAM is

write-protected after VCC

passes VPFD on power-up.

tWPT Write-protect time 40 100 150 µs

Delay after VCC slews down

past VPFD before SRAM is

write-protected.

Note: Typical values indicate operation at TA= 25°C.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Oct. 1998 D

bq2201

Oct. 1998 D

TD220103.eps

VCC

tPU

CECON VOHB

VSO4.25 VPFD

4.75

tCER

tCED tCED

Power-Up Timing

bq2201

Oct. 1998 D

8-Pin SOIC Narrow (SN)

Dimension Minimum Maximum

A 0.060 0.070

A1 0.004 0.010

B 0.013 0.020

C 0.007 0.010

D 0.185 0.200

E 0.150 0.160

e 0.045 0.055

H 0.225 0.245

L 0.015 0.035

All dimensions are in inches.

8-Pin SOIC Narrow (SN)

8-Pin DIP Narrow (PN)

Dimension Minimum Maximum

A 0.160 0.180

A1 0.015 0.040

B 0.015 0.022

B1 0.055 0.065

C 0.008 0.013

D 0.350 0.380

E 0.300 0.325

E1 0.230 0.280

e 0.300 0.370

G 0.090 0.110

L 0.115 0.150

S 0.020 0.040

All dimensions are in inches.

8-Pin DIP Narrow (PN)

bq2201

Oct. 1998 D

S: 16-Pin SOIC

.004

16-Pin S (SOIC)

Dimension Minimum Maximum

A 0.095 0.105

A1 0.004 0.012

B 0.013 0.020

C 0.008 0.013

D 0.400 0.415

E 0.290 0.305

e 0.045 0.055

H 0.395 0.415

L 0.020 0.040

All dimensions are in inches.

bq2201

Oct. 1998 D

Data Sheet Revision History

Change No. Page No. Description Nature of Change

1 Added industrial temperature range

2 1, 3, 4 10% supply operation Was: THS tied to VOUT

Is: THS tied to VCC

3 1, 9, 11 Added 16-pin package option

Note: Change 1 = Sept. 1991 B changes from Sept. 1990 A.

Change 2 = Aug. 1997 C changes from Sept. 1991 B.

Change 3 = Oct. 1998 D changes from Aug. 1997 C.

Ordering Information

bq2201

Package Option:

PN = 8-pin narrow plastic DIP

SN = 8-pin narrow SOIC

S = 16-pin SOIC

Device:

bq2201 Nonvolatile SRAM Controller

Temperature Range:

blank = Commercial (0 to +70°C)

N = Industrial (-40 to +85°C)

bq2201

Oct. 1998 D

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

BQ2201PN ACTIVE PDIP P 8 50 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

BQ2201PNE4 ACTIVE PDIP P 8 50 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

BQ2201SN ACTIVE SOIC D 8 75 Green (RoHS &