TPD2S017DBVR - Texas Instruments - Datasheet.Directory

FEATURES APPLICATIONS

16Ch2_Out

25VCC

Ch1_Out

GND

Ch1_In 4Ch2_In

DESCRIPTION/ORDERING INFORMATION

TPD2S017

www.ti.com

.......................................................................................................................................................................................... SLLS949 – SEPTEMBER 2009

2-CHANNEL ULTRA-LOW CLAMP VOLTAGE ESD SOLUTIONWITH SERIES-RESISTOR ISOLATION

•Hi-Speed USB•Ultra-Low Clamp Voltage Ensures theProtection of Ultra-Low Voltage Core Chipset

•IEEE 1394 InterfaceDuring ESD Events

•Low-Voltage Differential Signaling (LVDS)•Exceeds ESD Protection to IEC61000-4-2

•Mobile Display Digital Interface (MDDI)/MobileIndustry Processor Interface (MIPI)(Level 4)

•HS Signal•Matching of Series Resistor (R =1 Ω) of ± 8 m Ω

(Typical)

DBV PACKAGE•Differential Channel Input Capacitance

(TOP VIEW)Matching of 0.02 pF (Typical)•High-Speed Data Rate and EMI Filter Action atHigh Frequencies ( – 3 dB Bandwidth, ≈3 GHz)•Available in 6-Pin Small-Outline Transistor[SOT (DBV)] Package•Flow-Through Single-In-Line Pin Mapping forthe High-Speed Lines Ensures no AdditionalBoard Layout Burden While Placing the ESDProtection Chip Near the Connector

The TPD2S017 provides a robust system-level ESD solution for the high-speed lines interfacing low-voltage,ESD-sensitive core chipset. This device offers two stage ESD clamps in each line with ≈1- Ωseries resistorisolation. This architecture allows the device to generate very low clamp voltage during system level ESD strikes.Due to the series resistor component, the TPD2S017 provides a controlled filter roll-off for even greater spuriousEMI suppression and signal integrity. This device offers a flow-through pin mapping for ease of board layout. Themonolithic silicon technology allows matching component values, including clamp capacitance, series resistormatching, etc., between the differential signal pairs. Tight matching of the line capacitance and series resistorsensure that the differential signal distortion due to added ESD clamp remains minimal, and also allow the part tooperate at high-speed differential data rate (in excess of 1.5 Gbps).

The TPD2S017 confirms the IEC61000-4-2 (Level 4) ESD protection and ± 15 kV HBM ESD protection. Thisdevice is offered in space saving DBV packages.

The TPD2S017 is characterized for operation over ambient air temperature of – 40 ° C to 85 ° C.

ORDERING INFORMATION

PACKAGE

(1) (2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

– 40 ° C to 85 ° C SOT (SOT-23) – DBV Reel of 3000 TPD2S017DBVR NFTF

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

Ch2_Out

VCC (optional)

Ch1_Out

GND

Ch1_In

Ch2_In

ABSOLUTE MAXIMUM RATINGS

(1)

ESD RATINGS

TPD2S017

SLLS949 – SEPTEMBER 2009 ..........................................................................................................................................................................................

www.ti.com

CIRCUIT DIAGRAM

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTIONNAME NO.

Ch1_In 3

I High-speed ESD clamp inputCh2_In 4Ch1_Out 1

O High-speed ESD clamp outputCh2_Out 6GND 2 – GroundV

5 – Optional power

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

IO voltage range 0 5 VT

stg

Storage temperature range – 85 125 ° CTA Operating temperature – 40 85 ° C

(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PARAMETER MIN MAX UNIT

Out pin ± 11IEC 61000-4-2 Contact Discharge kVIn pin ± 11Human Body Model In and out pins ± 15 kV

Product Folder Link(s): TPD2S017

DISSIPATION RATINGS

ELECTRICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS

-9

-8

-7

-6

-5

-4

-3

-2

-1

1.000E+06 1.000E+07 1.000E+08 1.000E+09 1.000E+10

Frequency (Hz)

Insertion Loss (dB)

I/O to I/O

TPD2S017

www.ti.com

≤25 ° C DERATING FACTOR

(1)

= 70 ° CPACKAGE

POWER RATING ABOVE T

≤25 ° C POWER RATING

DBV 463.18 mW -4.63 mW/C 254.75 mW

(1) Derating factor is defined as the inverse of the traditional junction-to-ambient thermal resistance (R

θJA

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R Series resistor 1 Ω

Current from I/O pins V

= 3 V 0.01 0.1 µAChannel-to-channel resistanceΔRS V

= 3 V ± 8 ± 15 m Ωmatch

Diode forward voltage for lowerV

= 8 mA – 0.6 – 0.8 – 0.95 VclampR

DYN

Dynamic resistance (for I/O clamp) I = 9A 0.8 Ω

IO capacitance V

= 2.5 V 1 pFV

Break-down voltage I

= 1 mA 11 12 V

Figure 1. Insertion Loss Data (S21)

Product Folder Link(s): TPD2S017

0.0

0.8

1.6

2.4

3.2

4.0

4.8

5.6

6.4

7.2

8.0

0 5 10 15 20 25 30 35 40 45 50

Time (us)

IPP (A)

104

117

130

PPP (W)

Current (A)

Power (W)

0.0

0.8

1.6

2.4

3.2

4.0

4.8

5.6

6.4

7.2

8.0

0 5 10 15 20 25 30 35 40 45 50

Time (us)

IPP (A)

104

117

130

PPP (W)

Current (A)

Power (W)

TPD2S017

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Figure 2. Peak Pulse WaveformsCh1_Out, PUT wrt GND, V

= 5.0 V

Figure 3. Peak Pulse WaveformsCh2_In, PUT wrt GND, V

= 5.0 V

Product Folder Link(s): TPD2S017

-5

0 20 40 60 80 100 120 140 160 180 200

Time (ns)

Amplitude (V)

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0 20 40 60 80 100 120 140 160 180 200

Time (nS)

Amplitude (V)

TPD2S017

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Figure 4. IEC Clamping Waveforms8 kV Contact, 1 GHz Bandwidth

Figure 5. IEC Clamping Waveforms– 8 kV Contact, 1 GHz Bandwidth

Product Folder Link(s): TPD2S017

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TPD2S017DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 5-Oct-2009

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPD2S017DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Sep-2009

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPD2S017DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Sep-2009

Pack Materials-Page 2

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