TSC2007IPWRQ1 - Texas Instruments

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire

Micro TOUCH SCREEN CONTROLLER with I

C™Interface

Check for Samples: TSC2007-Q1

1FEATURES

23•Qualified for Automotive Applications •Low Power:

•4-Wire Touch Screen Interface –32.24 μA at 1.2 V, Fast Mode, 8.2 kHz Eq

Rate

•Single 1.2 V to 3.6 V Supply/Reference

–39.31 μA at 1.8 V, Fast Mode, 8.2 kHz Eq

•Ratiometric Conversion Rate

•Effective Throughput Rate: –53.32 μA at 2.7 V, Fast Mode, 8.2 kHz Eq

–Up to 20 kHz (8-Bit) or 10 kHz (12-Bit) Rate

•Preprocessing to Reduce Bus Activity •Enhanced ESD Protection:

•I2C Interface Supports: – ±8 kV HBM

–Standard, Fast, and High-Speed Modes – ±1 kV CDM

•Simple, Command-Based User Interface: – ±25 kV Air Gap Discharge

–TSC2003-Q1 Compatible – ±15 kV Contact Discharge

–8- or 12-Bit Resolution •5 x 6.4 TSSOP-16 Package

•On-Chip Temperature Measurement

•Touch Pressure Measurement U.S. Patent NO. 6246394; other patents pending.

•Digital Buffered PENIRQ APPLICATIONS

•On-Chip, Programmable PENIRQ Pull-Up •Media Players

•Auto Power-Down Control •Multiscreen Touch Control Systems

DESCRIPTION

The TSC2007-Q1 is a very low-power touch screen controller designed to work with power-sensitive, handheld

applications that are based on an advanced low-voltage processor. It works with a supply voltage as low as 1.2V,

which can be supplied by a single-cell battery. It contains a complete, ultra-low power, 12-bit, analog-to-digital

(A/D) resistive touch screen converter, including drivers and the control logic to measure touch pressure.

In addition to these standard features, the TSC2007-Q1 offers preprocessing of the touch screen measurements

to reduce bus loading, thus reducing the consumption of host processor resources that can then be redirected to

more critical functions.

The TSC2007-Q1 supports an I2C serial bus and data transmission protocol in all three defined modes: standard,

fast, and high-speed. It offers programmable resolution of 8 or 12 bits to accommodate different screen sizes and

performance needs.

The TSC2007-Q1 is available in a 16-pin TSSOP package. The TSC2007-Q1 is characterized for the –40°C to

+85°C industrial temperature range.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2I2C is a trademark of NXP Semiconductors.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PENIRQ

I C

Serial

Interface

and

Control

2SCL

SDA

A[0:1]

X+

X-

Y+

Y-

AUX

TEMP

Mux

VDD/REF

GND

SAR

ADC

Internal

Clock

Touch

Screen

Drivers

Interface

Preprocessing

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

TAPACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING

–40°C to +85°C TSSOP –PW Reel of 2000 TSC2007IPWRQ1 TS2007I

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see

the TI website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER VALUE UNIT

Analog input X+, Y+, AUX to GND –0.4 to VDD + 0.1 V

Voltage Analog input X–, Y–to GND –0.4 to VDD + 0.1 V

Voltage range VDD/REF pin to GND –0.3 to +5 V

Digital input voltage to GND –0.3 to VDD + 0.3 V

Digital output voltage to GND –0.3 to VDD + 0.3 V

Power dissipation (TJMax - TA)/θJA

Thermal impedance, θJA TSSOP package 86 °C/W

Operating free-air temperature range, TA–40 to +85 °C

Storage temperature range, TSTG –65 to +150 °C

Junction temperature, TJMax +150 °C

Vapor phase (60 sec) +215 °C

Lead temperature Infrared (15 sec) +220 °C

IEC contact discharge(2) X+, X–, Y+, Y– ±15 kV

IEC air discharge(2) X+, X–, Y+, Y– ±25 kV

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to

absolute-maximum rated conditions for extended periods may affect device reliability.

(2) Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS

At TA=–40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AUXILIARY ANALOG INPUT

Input voltage range 0 VDD V

Input capacitance 12 pF

Input leakage current –1 +1 μA

A/D CONVERTER

Resolution Programmable: 8 or 12 bits 12 Bits

No missing codes 12-bit resolution 11 Bits

Integral linearity ±1.5 LSB(1)

VDD = 1.8V –1.2 LSB

Offset error VDD = 3.0V –3.1 LSB

VDD = 1.8V 0.7 LSB

Gain error VDD = 3.0V 0.1 LSB

TOUCH SENSORS

TA= +25°C, VDD = 1.8V, command '1011'set '0000'51 kΩ

PENIRQ pull-up resistor, RIRQ TA= +25°C, VDD = 1.8V, command '1011'set '0001'90 kΩ

Y+, X+ 6 Ω

Switch

on-resistance Y–, X–5Ω

Switch drivers drive current(2) 100ms duration 50 mA

INTERNAL TEMPERATURE SENSOR

Temperature range –40 +85 °C

VDD = 3V 1.94 °C/LSB

Differential

method(3) VDD = 1.6V 1.04 °C/LSB

Resolution VDD = 3V 0.35 °C/LSB

TEMP1(4) VDD = 1.6V 0.19 °C/LSB

VDD = 3V ±2°C/LSB

Differential

method(3) VDD = 1.6V ±2°C/LSB

Accuracy VDD = 3V ±3°C/LSB

TEMP1(4) VDD = 1.6V ±3°C/LSB

INTERNAL OSCILLATOR

VDD = 1.2V 3.19 MHz

VDD = 1.8V 3.66 MHz

8-Bit VDD = 2.7V 3.78 MHz

VDD = 3.6V 3.82 MHz

Internal clock frequency, fCCLK VDD = 1.2V 1.6 MHz

VDD = 1.8V 1.83 MHz

12-Bit VDD = 2.7V 1.88 MHz

VDD = 3.6V 1.91 MHz

VDD = 1.6V 0.0056 %/°C

Frequency drift VDD = 3.0V 0.012 %/°C

(1) LSB means Least Significant Bit. With VDD/REF pin = +1.6V, one LSB is 391 μV.

(2) Specified by design, but not tested. Exceeding 50 mA source current may result in device degradation.

(3) Difference between TEMP1 and TEMP2 measurement; no calibration necessary.

(4) Temperature drift is –2.1 mV/°C.

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

At TA=–40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUT/OUTPUT

Logic family CMOS

1.2V ≤VDD <1.6V 0.7 ×VDD VDD + 0.3 V

VIH 1.6V ≤VDD ≤3.6V 0.7 ×VDD VDD + 0.3 V

1.2V ≤VDD <1.6V –0.3 0.2 ×VDD V

VIL 1.6V ≤VDD ≤3.6V –0.3 0.3 ×VDD V

IIL SCL and SDA pins –1 1 μA

Logic level CIN (5) SCL and SDA pins 10 pF

VOH IOH = 2 TTL loads VDD –0.2 VDD V

VOL IOL = 2 TTL loads 0 0.2 V

ILEAK Floating output –1 1 μA

COUT (5) Floating output 10 pF

Data format Straight binary

POWER-SUPPLY REQUIREMENTS

Power-supply voltage, VDD Specified performance 1.2 3.6 V

32.56k eq rate 128 190 μA

VDD = 1.2V 8.2k eq rate 32.24 μA

12-bit Fast mode 34.42k eq rate 165 240 μA

Quiescent supply current (clock = 400kHz) VDD = 1.8V

(VDD with sensor off) 8.2k eq rate 39.31 μA

PD[1:0] = 0,0 34.79k eq rate 226.2 335 μA

VDD = 2.7V 8.2k eq rate 53.32 μA

Power down supply current Not addressed, SCL = SDA = 1 0 0.8 μA

POWER ON/OFF SLOPE REQUIREMENTS(5)

VDD off ramp TA=–40°C to +85°C 2 kV/s

TA=–40°C to +85°C, VDD = 0V 1.2 s

VDD off time TA=–20°C to +85°C, VDD = 0V 0.3 s

VDD on ramp TA=–40°C to +85°C 12 kV/s

(5) Not production tested. Specified by design.

Product Folder Link(s): TSC2007-Q1

AUX

SCL

SDA

PENIRQ

VDD/REF

X+

Y+

X-

Y-

GND

TSC2007

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

PIN CONFIGURATION

PW PACKAGE

TSSOP-16

(TOP VIEW)

PIN ASSIGNMENTS

PIN NO. PIN NAME I/O A/D DESCRIPTION

1 VDD/REF Supply voltage and external reference input

2 X+ I A X+ channel input

3 Y+ I A Y+ channel input

4 X–I A X–channel input

5 Y–I A Y–channel input

6 GND Ground

7 NC No connection

8 NC No connection

9 NC No connection

10 PENIRQ O D Data available interrupt output. A delayed (process delay) pen touch detect. Pin polarity with active low.

11 SDA I/O D Serial data I/O

Serial clock. This pin is normally an input, but acts as an output when the device stretches the clock to delay a bus

12 SCL I/O D transfer.

13 A1 I D Address input bit 1

14 A0 I D Address input bit 0

15 NC No connection

16 AUX I A Auxiliary channel input

Product Folder Link(s): TSC2007-Q1

tHD, STA

tSU, DAT

tHD, DAT

tSU, STA

tSU, STO

tHD, STA

tLOW

tHIGH

tRtF

tBUF

SDA

START

CONDITION

START

CONDITION

STOP

CONDITION

REPEATED

START

CONDITION

SCL

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

TIMING INFORMATION

Figure 1. Detailed I/O Timing

TIMING REQUIREMENTS: I2C Standard Mode (SCL = 100kHz)

All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.

2-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SCL clock frequency fSCL 0 100 kHz

Bus free time between a STOP and START condition tBUF 4.7 μs

Hold time (repeated) START condition tHD, STA 4.0 μs

Low period of SCL clock tLOW 4.7 μs

High period of the SCL clock tHIGH 4.0 μs

Setup time for a repeated START condition tSU, STA 4.7 μs

Data hold time tHD, DAT 0 3.45 μs

Data setup time tSU, DAT 250 ns

Rise time for both SDA and SCL signals (receiving) tRCb= total bus capacitance 1000 ns

Fall time for both SDA and SCL signals (receiving) tFCb= total bus capacitance 300 ns

Fall time for both SDA and SCL signals (transmitting) tFCb= total bus capacitance 250 ns

Setup time for STOP condition tSU, STO 4.0 μs

Capacitive load for each bus line CbCb= total capacitance of one bus line in pF 400 pF

8 bits 40 SCL + 127 CCLK, VDD = 1.8V 434.7 μs

Cycle time 12 bits 49 SCL + 148 CCLK, VDD = 1.8V 570.9 μs

8 bits VDD = 1.8V 2.3 kSPS

Effective throughput 12 bits VDD = 1.8V 1.75 kSPS

8 bits VDD = 1.8V 16.1 kHz

Equivalent rate = effective throughput ×712 bits VDD = 1.8V 12.26 kHz

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

TIMING REQUIREMENTS: I2C Fast Mode (SCL = 400kHz)

All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.

2-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SCL clock frequency fSCL 0 400 kHz

Bus free time between a STOP and START condition tBUF 1.3 μs

Hold time (repeated) START condition tHD, STA 0.6 μs

Low period of SCL clock tLOW 1.3 μs

High period of the SCL clock tHIGH 0.6 μs

Setup time for a repeated START condition tSU, STA 0.6 μs

Data hold time tHD, DAT 0 0.9 μs

Data setup time tSU, DAT 100 ns

Rise time for both SDA and SCL signals (receiving) tRCb= total bus capacitance 20+0.1×Cb300 ns

Fall time for both SDA and SCL signals (receiving) tFCb= total bus capacitance 20+0.1×Cb300 ns

Fall time for both SDA and SCL signals (transmitting) tFCb= total bus capacitance 20+0.1×Cb250 ns

Setup time for STOP condition tSU, STO 0.6 μs

Capacitive load for each bus line CbCb= total capacitance of one bus line in pF 400 pF

8 bits 40 SCL + 127 CCLK, VDD = 1.8V 134.7 μs

Cycle time 12 bits 49 SCL + 148 CCLK, VDD = 1.8V 203.4 μs

8 bits VDD = 1.8V 7.42 kSPS

Effective throughput 12 bits VDD = 1.8V 4.92 kSPS

8 bits VDD = 1.8V 51.97 kHz

Equivalent rate = effective throughput ×712 bits VDD = 1.8V 34.42 kHz

TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 1.7MHz)

All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.

2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SCL clock frequency fSCL 0 1.7 MHz

Hold time (repeated) START condition tHD, STA 160 ns

Low period of SCL clock tLOW 320 ns

High period of the SCL clock tHIGH 120 ns

Setup time for a repeated START condition tSU, STA 160 ns

Data hold time tHD, DAT 0 150 ns

Data setup time tSU, DAT 10 ns

Rise time for SCL signal (receiving) tRCb= total bus capacitance 20 80 ns

Rise time for SDA signal (receiving) tRCb= total bus capacitance 20 160 ns

Fall time for SCL signal (receiving) tFCb= total bus capacitance 20 80 ns

Fall time for SDA signal (receiving) tFCb= total bus capacitance 20 160 ns

Fall time for both SDA and SCL signals (transmitting) tFCb= total bus capacitance 20 160 ns

Setup time for STOP condition tSU, STO 160 ns

Capacitive load for each bus line CbCb= total capacitance of one bus line in pF 400 pF

8 bits 40 SCL + 127 CCLK, VDD = 1.8V 58.2 μs

Cycle time 12 bits 49 SCL + 148 CCLK, VDD = 1.8V 109.7 μs

8 bits VDD = 1.8V 17.17 kSPS

Effective throughput 12 bits VDD = 1.8V 9.12 kSPS

8 bits VDD = 1.8V 120.22 kHz

Equivalent rate = effective throughput ×712 bits VDD = 1.8V 63.81 kHz

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 3.4MHz)

All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.

2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SCL clock frequency fSCL 0 3.4 MHz

Hold time (repeated) START condition tHD, STA 160 ns

Low period of SCL clock tLOW 160 ns

High period of the SCL clock tHIGH 60 ns

Setup time for a repeated START condition tSU, STA 160 ns

Data hold time tHD, DAT 0 70 ns

Data setup time tSU, DAT 10 ns

Rise time for SCL signal (receiving) tRCb= total bus capacitance 10 40 ns

Rise time for SDA signal (receiving) tRCb= total bus capacitance 10 80 ns

Fall time for SCL signal (receiving) tFCb= total bus capacitance 10 40 ns

Fall time for SDA signal (receiving) tFCb= total bus capacitance 10 80 ns

Fall time for both SDA and SCL signals (transmitting) tFCb= total bus capacitance 10 80 ns

Setup time for STOP condition tSU, STO 160 ns

Capacitive load for each bus line CbCb= total capacitance of one bus line in pF 100 pF

8 bits 40 SCL + 127 CCLK, VDD = 1.8V 46.5 μs

Cycle time 12 bits 49 SCL + 148 CCLK, VDD = 1.8V 95.3 μs

8 bits VDD = 1.8V 21.52 kSPS

Effective throughput 12 bits VDD = 1.8V 10.49 kSPS

8 bits VDD = 1.8V 150.65 kHz

Equivalent rate = effective throughput ×712 bits VDD = 1.8V 73.46 kHz

Product Folder Link(s): TSC2007-Q1

-40 -20 0 20 40 60 80 100

Temperature(°C)

Power-DownSupplyCurrent(nA)

100

V =1.6V

V =3.6V

DD V =3.0V

-40 -20 0 20 40 60 80 100

Temperature(°C)

SupplyCurrent( A)m

350

300

250

200

150

100

High-SpeedMode=3.4MHz

FastMode=400kHz

StandardMode=100kHz

600

500

400

300

200

100

SupplyCurrent( A)m

1.2 1.6 2.0 2.4 2.8 3.2

3.6

V (V)

High-SpeedMode=3.4MHz

FastMode=400kHz

StandardMode=100kHz

300

250

200

150

100

SupplyCurrent( A)m

1.2 1.6 2.0 2.4 2.8 3.2

3.6

V (V)

T =+25 C°

I CSpeed=400kHz

PD1=PD0=0

X,Y,ZConversionat200SSPS

withMAV

TouchSensorModeledBy:

2k forX-PlaneW

2k forY-PlaneW

1k forZ(TouchResistance)W

MAVBypassed

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

TYPICAL CHARACTERISTICS

At TA=–40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,

and MAV filter enabled (see MAV Filter section), unless otherwise noted.

POWER-DOWN SUPPLY CURRENT SUPPLY CURRENT

vs vs

TEMPERATURE TEMPERATURE

Figure 2. Figure 3.

SUPPLY CURRENT SUPPLY CURRENT

SUPPLY VOLTAGE vs

(AUX Conversion) SUPPLY VOLTAGE

Figure 4. Figure 5.

Product Folder Link(s): TSC2007-Q1

Temperature( C)°

SupplyCurrent( A)m

-40 -20

0 20 40 60 80 100

High-SpeedMode=3.4MHz

FastMode=400kHz

StandardMode=100kHz

V (V)

1.2 1.6 2.0 2.4 2.8 3.2

250

200

150

100

3.6

SupplyCurrent( A)m

High-SpeedMode=3.4MHz

FastMode=400kHz

StandardMode=100kHz

Temperature( C)°

Deltafrom+25 C(LSB)°

-40 -20

-2

-4

-6

200 40 60 80 100

V =1.8V

Temperature( C)°

Deltafrom+25 C(LSB)°

-40 -20

-2

-4

-6

200 40 60 80 100

V =1.8V

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

At TA=–40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,

and MAV filter enabled (see MAV Filter section), unless otherwise noted.

SUPPLY CURRENT (Part Not Addressed) SUPPLY CURRENT (Part Not Addressed)

vs vs

TEMPERATURE SUPPLY VOLTAGE

Figure 6. Figure 7.

CHANGE IN GAIN CHANGE IN OFFSET

vs vs

TEMPERATURE TEMPERATURE

Figure 8. Figure 9.

Product Folder Link(s): TSC2007-Q1

R ( )W

1.2 1.6 2.0 2.4 2.8 3.2

3.6

V (V)

Y+

X+

Y-

X-

-40 -20 0 20 40 60 80 100

Temperature(°C)

R (W)

Y+

X+,Y+:V =3.0VtoPin

X-,Y-:PintoGND

Y-

X-

X+

-40 -20 0 20 40 60 80 100

Temperature(°C)

R ( )W

Y+

X+,Y+:V =1.8VtoPin

X ,Y :PintoGND- -

Y-

X-

X+

-40 -20 0 20 40 60 80 100

Temperature(°C)

TEMPDiodeVoltage(mV)

850

800

750

700

650

600

550

500

450

400

V =1.8V

TEMP2

94.2mV

TEMP1

MeasurementIncludes

A/DConverterOffset

andGainErrors

137.5mV

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

TYPICAL CHARACTERISTICS (continued)

At TA=–40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,

and MAV filter enabled (see MAV Filter section), unless otherwise noted.

SWITCH ON-RESISTANCE SWITCH ON-RESISTANCE

vs vs

SUPPLY VOLTAGE TEMPERATURE

Figure 10. Figure 11.

SWITCH ON-RESISTANCE TEMP DIODE VOLTAGE

vs vs

TEMPERATURE TEMPERATURE

Figure 12. Figure 13.

Product Folder Link(s): TSC2007-Q1

V (V)

1.2 1.6 2.0 2.4 2.8 3.2

588

586

584

582

580

578

576

574

3.6

TEMP1DiodeVoltage(mV)

V =VREFDD

MeasurementIncludes

A/DConverterOffset

andGainErrors

V (V)

1.2 1.6 2.0 2.4 2.8 3.2

704

702

700

698

696

694

692

690

3.6

TEMP2DiodeVoltage(mV)

V =VREFDD

MeasurementIncludes

A/DConverterOffset

andGainErrors

Temperature( C)°

InternalOscillatorClockFrequency(MHz)

-40 -20

3.40

3.30

3.20

3.10

3.00

2.90

2.80

2.70

0 20 40 60 80 100

V =1.2V

Temperature( C)°

InternalOscillatorClockFrequency(MHz)

-40 -20

3.70

3.65

3.60

0 20 40 60 80 100

V =1.8V

Temperature( C)°

InternalOscillatorClockFrequency(MHz)

-40 -20

3.90

3.85

3.80

3.75

3.70

0 20 40 60 80 100

V =3.0V

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

At TA=–40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,

and MAV filter enabled (see MAV Filter section), unless otherwise noted.

TEMP1 DIODE VOLTAGE TEMP2 DIODE VOLTAGE

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 14. Figure 15.

INTERNAL OSCILLATOR CLOCK FREQUENCY INTERNAL OSCILLATOR CLOCK FREQUENCY

vs vs

TEMPERATURE TEMPERATURE

Figure 16. Figure 17.

INTERNAL OSCILLATOR CLOCK FREQUENCY

TEMPERATURE

Figure 18.

Product Folder Link(s): TSC2007-Q1

X+

Y+

X-

Y-

AuxiliaryInput GND

TSC2007

GND

1 Fm0.1 Fm

Touch

Screen

GPIO

SDA

SCL

Host

Processor

PENIRQ

SDA

SCL

VDD/REF

AUX

GND

1.2kW1.2kW

1.8VDC

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

OVERVIEW

The TSC2007-Q1 is an analog interface circuit for a human interface touch screen device. All peripheral

functions are controlled through the command byte and onboard state machines. The TSC2007-Q1 features

include:

•Very low-power touch screen controller

•Very small onboard footprint

•Relieves host from tedious routine tasks by preprocessing, thus saving resources for more critical tasks

•Ability to work on very low supply voltage

•Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required

•Miniature, yet complete; requires no external supporting component

•Enhanced electrostatic discharge (ESD) protection

The TSC2007-Q1 consists of the following blocks (refer to the block diagram on the front page):

•Touch Screen Sensor Interface

•Auxiliary Input (AUX)

•Temperature Sensor

•Acquisition Activity Preprocessing

•Internal Conversion Clock

•I2C Interface

Communication with the TSC2007-Q1 is done via an I2C serial interface. The TSC2007-Q1 is an I2C slave

device; therefore, data are shifted into or out of the TSC2007-Q1 under control of the host microprocessor, which

also provides the serial data clock.

Control of the TSC2007-Q1 and its functions is accomplished by writing to the command register of an internal

state machine. A simple command protocol compatible with I2C is used to address this register.

A typical application of the TSC2007-Q1 is shown in Figure 19.

Figure 19. Typical Circuit Configuration

Product Folder Link(s): TSC2007-Q1

ConductiveBar

InsulatingMaterial(Glass)

Silver

Ink

TransparentConductor(ITO)

BottomSide

Transparent

Conductor(ITO)

TopSide

X+

X-

Y+

Y-

ITO=IndiumTinOxide

RTOUCH +RX−plate @XPosition

4096 ǒZ2

Z1*1Ǔ

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

TOUCH SCREEN OPERATION

A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in

resistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). The

change in the resistance ratio marks the location on the touch screen.

The TSC2007-Q1 supports resistive 4-wire configurations, as shown in Figure 20. The circuit determines location

in two coordinate pair dimensions, although a third dimension can be added for measuring pressure.

4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT

A 4-wire touch screen is typically constructed as shown in Figure 20. It consists of two transparent resistive

layers separated by insulating spacers.

Figure 20. 4-Wire Touch Screen Construction

The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.

The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of the

Y position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+

and Y–drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the

voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+

lead does not affect the conversion because of the high input impedance of the A/D converter.

Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X position

on the screen. This process provides the X and Y coordinates to the associated processor.

Measuring touch pressure (Z) can also be done with the TSC2007-Q1. To determine pen or finger touch, the

pressure of the touch must be determined. Generally, it is not necessary to have very high performance for this

test; therefore, 8-bit resolution mode may be sufficient (however, data sheet calculations are shown using the

12-bit resolution mode). There are several different ways of performing this measurement. The TSC2007-Q1

supports two methods. The first method requires knowing the X-plate resistance, the measurement of the

X-position, and two additional cross panel measurements (Z2and Z1) of the touch screen (see Figure 21).

Equation 1 calculates the touch resistance:

(1)

Product Folder Link(s): TSC2007-Q1

RTOUCH +RX−plate @XPosition

4096 ǒ4096

Z1*1Ǔ*RY−plate @ǒ1*YPosition

4096 Ǔ

X-Position

MeasureX-Position

MeasureZ -Position

Touch

X+ Y+

X-Y-

Z -Position

Touch

X+ Y+

Y-X-

MeasureZ -Position

Z -Position

Touch

X+ Y+

Y-X-

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-position and

Y-position, and Z1.Equation 2 also calculates the touch resistance:

(2)

Figure 21. Pressure Measurement

When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across the

touch panel often overshoots and then slowly settles down (decays) to a stable dc value. This effect is a result of

mechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed.

This settling time must be accounted for, or else the converted value is incorrect. Therefore, a delay must be

introduced between the time the driver for a particular measurement is turned on, and the time a measurement is

made.

In some applications, external capacitors may be required across the touch screen for filtering noise picked up by

the touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of these

capacitors provides a low-pass filter to reduce the noise, but creates an additional settling time requirement when

the panel is touched. The settling time typically shows up as gain error.

To solve this problem, the TSC2007-Q1 can be commanded to turn on the drivers only, without performing a

conversion. Time can then be allowed to perform a conversion before the command is issued.

The TSC2007-Q1 touch screen interface can measure position (X,Y) and pressure (Z).

Product Folder Link(s): TSC2007-Q1

Converter

GND

VDD

TEMP1

TEMP2

+IN

-IN

DV+kT

q@ln(N)

T+q@DV

k@ln(N)

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

INTERNAL TEMPERATURE SENSOR

In some applications, such as battery recharging, an ambient temperature measurement is required. The

temperature measurement technique used in the TSC2007-Q1 relies on the characteristics of a semiconductor

junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic

versus temperature. The ambient temperature can be predicted in applications by knowing the +25°C value of

the VBE voltage and then monitoring the delta of that voltage as the temperature changes.

The TSC2007-Q1 offers two modes of temperature measurement. The first mode requires calibration at a known

temperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown in

Figure 22, is used during this measurement cycle. This voltage is typically 580mV at +25°C with a 10μA current.

The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (TC) of this

voltage is very consistent at –2.1mV/°C. During the final test of the end product, the diode voltage would be

stored at a known room temperature, in system memory, for calibration purposes by the user. The result is an

equivalent temperature measurement resolution of 0.35°C/LSB (1LSB = 732μV with VREF = 3.0V).

Figure 22. Functional Block Diagram of Temperature Measurement Mode

The second mode does not require a test temperature calibration, but uses a two-measurement (differential)

method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This

mode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times larger

than the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion is

represented by:

(3)

Where:

N = the resistance ratio = 91.

k = Boltzmann's constant = 1.3807 ×10–23 J/K (joules/kelvins).

q = the electron charge = 1.6022 ×10–19 C (coulombs).

T = the temperature in kelvins (K).

This method can provide a much improved absolute temperature measurement, but a lower resolution of

1.6°C/LSB. The resulting equation to solve for T is:

(4)

Where:

ΔV=VBE (TEMP2) –VBE(TEMP1) (in mV)

∴T = 2.573 ⋅ΔV (in K)

or T = 2.573 ⋅ΔV–273 (in °C)

Temperature 1 and temperature 2 measurements have the same timing as the other data acquisition cycles

shown in Figure 33 and Figure 34.

Product Folder Link(s): TSC2007-Q1

Converter

-REF

+REF

+IN

-IN

PenTouch

Control

Logic

C3-C0

MAV

VDD

GND

TEMP1

TEMP2

RIRQ 90kW50kW

AUX

GND

X+

X-

Y+

Y-

VDD/REF PENIRQ

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

ANALOG-TO-DIGITAL CONVERTER

Figure 23 shows the analog inputs of the TSC2007-Q1. The analog inputs (X, Y, and Z touch panel coordinates,

chip temperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register

(SAR) A/D converter. The A/D architecture is based on capacitive redistribution architecture, which inherently

includes a sample-and-hold function.

Figure 23. Analog Input Section (Simplified Diagram)

A unique configuration of low on-resistance switches allows an unselected A/D converter input channel to

provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a

differential input to the converter and a differential reference input architecture, it is possible to negate errors

caused by the driver switch on-resistance.

Product Folder Link(s): TSC2007-Q1

Converter

+IN +REF

Y+

VDD/REF

X+

Y-

GND

-REF

-IN

Converter

+IN +REF

Y+

VDD/REF

X+

Y-

GND

-REF

-IN

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

Reference

The TSC2007-Q1 uses an external voltage reference that is applied to the VDD/REF pin. The upper reference

voltage range is the same as the supply voltage range, which allows for simple, 1.2V to 3.6V, single-supply

operation of the chip.

Reference Mode

There is a critical item regarding the reference when making measurements while the switch drivers are on. For

this discussion, it is useful to consider the basic operation of the TSC2007-Q1 (see Figure 19). The application

used in the following example shows the device being used to digitize a resistive touch screen. If the touch

screen controller uses a single-ended reference mode, as shown in Figure 24, a measurement of the current Y

position of the pointing device is made by connecting the X+ input to the A/D converter, turning on the Y+ and Y–

drivers, and digitizing the voltage on X+. For this measurement, the resistance in the X+ lead does not affect the

conversion; it does affect the settling time, but the resistance is usually small enough that this timing is not a

concern. However, because the resistance between Y+ and Y–is fairly low, the on-resistance of the Y drivers

does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0V input

or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost

across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the

touch screen, providing an additional source of error. Therefore, the TSC2007-Q1 does not support single-ended

reference mode.

Figure 24. Simplified Diagram of Single-Ended Reference

This situation is resolved, as shown in Figure 25, by using the differential mode; the +REF and –REF inputs are

connected directly to Y+ and Y–, respectively. This mode makes the A/D converter ratiometric. The result of the

conversion is always a percentage of the external reference, regardless of how it changes in relation to the

on-resistance of the internal switches.

Figure 25. Simplified Diagram of Differential Reference

(Both Y Switches Enabled, X+ is Analog Input)

Product Folder Link(s): TSC2007-Q1

OutputCode

FS=Full-ScaleVoltage=VREF

(1)

1LSB=V /4096

REF

(1)

FS 1LSB-

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

InputVoltage (V)

(2)

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

Touch Screen Settling

In some applications, external capacitors may be required across the touch screen to filter noise picked up by the

touch screen (that is, noise generated by the LCD panel or backlight circuitry). These capacitors provide a

low-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched.

The settling time typically shows up as a gain error. The problem is that the input and/or reference has not

settled to its final steady-state value before the A/D converter samples the input(s) and provides the digital

output. Additionally, the reference voltage may continue to change during the measurement cycle.

To resolve these settling-time problems, the TSC2007-Q1 can be commanded to turn on the drivers only without

performing a conversion (see Table 3). Time can then be allowed, before the command is issued, to perform a

conversion. Generally, the time it takes to communicate the conversion command over the I2C bus is adequate

for the touch screen to settle.

Variable Resolution

The TSC2007-Q1 provides either 8-bit or 12-bit resolution for the A/D converter. Lower resolution is often

practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower

resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which

also lowers power consumption.

8-Bit Conversion

The TSC2007-Q1 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is needed,

and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, a

conversion result can be read by transferring only one data byte. The internal clock runs twice as fast at 4MHz.

The faster clock shortens each conversion by four bits and reduces data transfer time, which results in fewer

clock cycles and provides lower power consumption.

Conversion Clock and Conversion Time

The TSC2007-Q1 contains an internal clock, which drives the state machines inside the device that perform the

many functions of the part. This clock is divided down to provide a clock that runs the A/D converter. The

frequency of this clock is 4MHz clock for 8-bit mode, and 2MHz for the 12-bit mode.

Data Format

The TSC2007-Q1 output data are in straight binary format as shown in Figure 26. This figure shows the ideal

output code for the given input voltage and does not include the effects of offset, gain, or noise.

(1) Reference voltage at converter: +REF –(–REF). See Figure 23.

(2) Input voltage at converter, after multiplexer: +IN –(–IN). See Figure 23.

Figure 26. Ideal Input Voltages and Output Codes

Product Folder Link(s): TSC2007-Q1

GND

TEMP1

TEMP2

VDD

PenTouch

X+

Y+

Y-

HighwhentheX+orY+

driverison,orwhenany

sensorconnection/short-

circuittestsareactivated.

GND

Sense

Viasgotosystemanaloggroundplane.

GND

Highwhen

theX+orY+

driverison.

Control

Logic

RIRQ

VDD/REF

PENIRQ

Connectto

AnalogSupply

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

Touch Detect

The PENIRQ can be used as an interrupt to the host. RIRQ is an internal pull-up resistor with a programmable

value of either 50kΩ(default) or 90kΩ. Write command '1011' (setup command) followed by data '0001' sets the

pull-up to 90kΩ.NOTE: The first three bits must be '0's and the select bit is the last bit. To change the pull-up

back to 50kΩ, issue write command '1011' followed by data '0000'.

An example for the Y-position measurement is detailed in Figure 27. The PENIRQ output is pulled high by an

internal pull-up. While in power-down mode with PD0 = 0, the Y–driver is on and connected to GND, and the

PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to ground

through the touch screen, and the PENIRQ output goes low because of the current path through the panel to

GND, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-position, the X+

input is disconnected from the PENIRQ pull-down transistor to eliminate any pull-up resistor leakage current from

flowing through the touch screen, thus causing no errors.

In addition to the measurement cycles for X-, Y-, and Z-position, commands that activate the X-drivers, Y-drivers,

and Y+ and X-drivers without performing a measurement also disconnect the X+ input from the PENIRQ

pull-down transistor, and disable the pen-interrupt output function, regardless of the value of the PD0 bit. Under

these conditions, the PENIRQ output is forced low. Furthermore, if the last command byte written to the

TSC2007-Q1 contains PD0 = 1, the pen-interrupt output function is disabled and cannot detect when the panel is

touched. In order to re-enable the pen-interrupt output function under these circumstances, a command byte

must be written to the TSC2007-Q1 with PD0 = 0.

When the bus master sends the address byte with the R/W bit = 0, and the TSC2007-Q1 sends an acknowledge,

the pen-interrupt function is disabled. If the command that follows the address byte contains PD0 = 0, then the

pen-interrupt function is enabled at the end of a conversion. This action is approximately 100μs (12-bit mode) or

50μs (8-bit mode) after the TSC2007-Q1 receives a STOP/START condition, following the receipt of a command

byte (see Figure 31 and Figure 30 for further details about when the conversion cycle begins).

In both cases previously listed, it is recommended that whenever the host writes to the TSC2007-Q1, the master

processor masks the interrupt associated to PENIRQ. This masking prevents false triggering of interrupts when

the PENIRQ line is disabled in the cases previously listed.

Figure 27. Example of a Pen-Touch Induced Interrupt via the PENIRQ Pin

Product Folder Link(s): TSC2007-Q1

7Acquired

Data

7m asue rementsinput

intotemporaryarray

Sortby

descendingorder

Averagingoutp tu

fromwindowof3

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

Preprocessing

The TSC2007-Q1 has a combined MAV filter (median value filter and averaging filter).

MAV Filter

If the acquired signal source is noisy because of the digital switching circuit, it may necessary to evaluate the

data without noise. In this case, the median value filter operation helps remove the noise. The array of seven

converted results is sorted first. The middle three values are then averaged to produce the output value of the

MAV filter.

The MAV filter is applied to all measurements for all analog inputs including the touch screen inputs, temperature

measurements TEMP1 and TEMP2, and auxiliary input AUX. To shorten the conversion time, the MAV filter may

be bypassed through the setup command; see Table 3 and Table 4.

Figure 28. MAV Filter Operation (Patent Pending)

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

I2C INTERFACE

The TSC2007-Q1 supports the I2C serial bus and data transmission protocol in all three defined modes:

standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device

receiving data as a receiver. The device that controls the message is called a master. The devices that are

controlled by the master are slaves. The bus must be controlled by a master device that generates the serial

clock (SCL), controls the bus access, and generates the START and STOP conditions. The TSC2007-Q1

operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL.

The following bus protocol has been defined (see Figure 29):

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy Both data and clock lines remain HIGH.

Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines

a START condition.

Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,

defines the STOP condition.

Data Valid The state of the data line represents valid data, when, after a START condition, the data line is stable

for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition.

The number of data bytes transferred between START and STOP conditions is not limited

and is determined by the master device. The information is transferred byte-wise and each

receiver acknowledges with a ninth-bit.

Within the I2C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHz

clock rate), and a high-speed mode (1.7MHz or 3.4MHz clock rate) are each defined. The

TSC2007-Q1 works in all three modes.

Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse that is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is stable LOW during the HIGH period of the

acknowledge clock pulse. Of course, setup and hold times must be taken into account. A

master must signal an end of data to the slave by not generating an acknowledge bit on the

last byte that has been clocked out of the slave. In this case, the slave must leave the data

line HIGH to enable the master to generate the STOP condition.

Product Folder Link(s): TSC2007-Q1

SDA

SCL

1 2 76 8 9 1 2 3-8 8 9

SlaveAddress

MSB

RepeatedIfMoreBytesAreTransferred

R/W

DirectionBit

Acknowledgement

SignalfromReceiver

Acknowledgement

SignalfromReceiver

START

Condition

ACK ACK

STOPCondition

orRepeated

STARTCondition

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

Figure 29 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two

types of data transfer are possible:

1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the

slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave

address and each received byte.

2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is

transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are

transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other

than the last byte. At the end of the last received byte, a not-acknowledge is returned.

The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends

with a STOP condition or a repeated START condition. Because a repeated START condition is also the

beginning of the next serial transfer, the bus is not released.

The TSC2007-Q1 may operate in the following two modes:

1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is

received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning

and end of a serial transfer. Address recognition is performed by hardware after reception of the slave

address and direction bit.

2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver

mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data are

transmitted on SDA by the TSC2007-Q1 while the serial clock is input on SCL. START and STOP conditions

are recognized as the beginning and end of a serial transfer.

I2C Fast or Standard Mode (F/S Mode)

In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Information

section.

In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a

START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has

finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition

on SDA while SCL is high, as shown in Figure 29. The bus is free for another transmission after a STOP

condition has occurred. Figure 29 shows the complete F/S mode transfer on the I2C, 2-wire serial interface. The

address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA

state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are

transmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word

plus acknowledge bit).

Figure 29. Complete Fast- or Standard-Mode Transfer

Product Folder Link(s): TSC2007-Q1

8-BitMasterCode00001xxx

IfPthen

FastorStandardMode

IfSr(dottedlines)

thenHigh-SpeedMode

1 6 7 8 92to5

2to51 6 7 8 9 1 6 7 8 9

2to5

SDA

SCL

SDA

SCL

=CurrentSourcePull-Up

=ResistorPull-Up

A=Acknowledge(SD LOWA )

N=NotAckno ledgew (SDAHIGH)

S START= Condition

P=STOP Con iiond t

Sr=RepeatedSTAR CondT iti no

NtH

High-SpeedMode

FastorStandardMode

tFS

Sr P

7-BitSlaveAddress R/WA nx(8-BitDATA + A/N)

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

I2C High-Speed Mode (Hs Mode)

The TSC2007-Q1 can operate with high-speed I2C masters. To do so, the pull-up resistor on SCL must be

changed to an active pull-up, as recommended in the I2C specification.

Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I2C bus

specification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist:

1. START condition (S)

2. 8-bit master code (00001xxx)

3. Not-acknowledge bit (N)

Figure 30 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for

triggering Hs mode, and are not to be used for slave addressing or any other purpose. The master code

indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the

Hs mode specification. Because no device is allowed to acknowledge the master code, the master code is

followed by a not-acknowledge bit (N).

After the not-acknowledge bit (N) and SCL have been pulled-up to a HIGH level, the master switches to

Hs-mode and enables the current-source pull-up circuit for SCL (at time tHshown in Figure 30). Because other

devices can delay the serial transfer before tHby stretching the LOW period of SCL, the master enables the

current-source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thus

speeding up the last part of the rise time of the SCL.

The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit

address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition

and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-up

circuit. This disabling enables other devices, such as the TSC2007-Q1, to delay the serial transfer (until the

converted data are stored in the TSC internal shift register) by stretching the LOW period of SCL. The master

re-enables its current-source pull-up circuit again when all devices have released SCL, and SCL reaches a HIGH

level, which speeds up the last part of the SCL signal rise time.

Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S mode

after a STOP condition (P). To reduce the overhead of the master code, it is possible for the master to link a

number of Hs mode transfers, separated by repeated START conditions (Sr).

Figure 30. Complete High-Speed Mode Transfer

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

DIGITAL INTERFACE

ADDRESS BYTE

The TSC2007-Q1 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are

factory-preset to comply with the I2C standard for A/D converters and are always set at '10010'. The logic state of

the address input pins (A1-A0) determines the two LSBs of the device address to activate communication.

Therefore, a maximum of four devices with the same preset code can be connected on the same bus at one

time.

The A1-A0 address inputs are read whenever an address byte is received, and should be connected to the

supply pin (VDD/REF) or the ground pin (GND). The slave address is latched into the TSC2007-Q1 on the falling

edge of SCL after the read/write bit has been received by the slave.

The last bit of the address byte (R/W) defines the operation to be performed. When set to a '1', a read operation

is selected; when set to a ‘0’, a write operation is selected. Following the START condition, the TSC2007-Q1

monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, the

appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.

Table 1. I2C Slave Address Byte

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 A1 A0 R/W

Bit D0: R/W

1: I2C master read from TSC (I2C read addressing).

0: I2C master write to TSC (I2C write addressing).

COMMAND BYTE

Table 2. Command Byte Definition (Excluding the Setup Command)(1)

BIT NAME DESCRIPTION

D7-D4 C3-C0 All Converter Function Select bits as detailed in Table 3, except for the setup command ('1011').

00: Power down between cycles. PENIRQ enabled.

01: A/D converter on. PENIRQ disabled.

D3-D2 PD1-PD0 10: A/D converter off. PENIRQ enabled.

11: A/D converter on. PENIRQ disabled.

0: 12-bit (Lower speed referred to as the 2MHz clock).

D1 M 1: 8-bit (Higher speed referred to as the 4MHz clock).

D0 X Don't care.

(1) The command byte definition for the setup command is shown in Table 4.

Bits D7-D4: C3-C0—Converter function select bits. These bits select the input to be converted and the converter

function to be executed, activate the drivers, and configure the PENIRQ pull-up resistor (RIRQ). Table 3 lists the

possible converter functions.

Bits D3-D2: PD1-PD0—Power-down bits. These two bits select the power-down mode that the TSC2007-Q1 will

be in after the current command completes, as shown in Table 2.

It is recommended to set PD0 = 0 in each command byte to get the lowest power consumption possible. If

multiple X-, Y-, and Z-position measurements will be done one right after another (such as when averaging), PD0

=1 will leave the touch screen drivers on at the end of each conversion cycle.

Bit D1: M—Mode bit. If M = 0, the TSC2007-Q1 is in 12-bit mode. If M = 1, 8-bit mode is selected.

Bit D0: X—Don’t care.

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

When the TSC2007-Q1 powers up, the power-down bits must be written to ensure that the device is placed into

the mode that achieves the lowest power. Therefore, immediately after power-up, send a command byte that

sets PD1 = PD0 = 0, so that the device will be in the lowest power mode, powering down between conversions.

Table 3. Converter Function Select

INPUT TO

A/D REFERENCE

C3 C2 C1 C0 FUNCTION CONVERTER X-DRIVERS Y-DRIVERS ACK MODE

0 0 0 0 Measure TEMP0 TEMP0 OFF OFF Y Single-Ended

0 0 0 1 Reserved N/A OFF OFF N Single-Ended

0 0 1 0 Measure AUX AUX OFF OFF Y Single-Ended

0 0 1 1 Reserved N/A OFF OFF N Single-Ended

0 1 0 0 Measure TEMP1 TEMP1 OFF OFF Y Single-Ended

0 1 0 1 Reserved N/A OFF OFF N Single-Ended

0 1 1 0 Reserved N/A OFF OFF N Single-Ended

0 1 1 1 Reserved N/A OFF OFF N Single-Ended

1 0 0 0 Activate X-drivers N/A ON OFF Y Differential

1 0 0 1 Activate Y-drivers N/A OFF ON Y Differential

1 0 1 0 Activate Y+, X-drivers N/A X–ON Y+ ON Y Differential

1 0 1 1 Setup command(1) N/A OFF OFF N N/A

1 1 0 0 Measure X position Y+ ON OFF Y Differential

1 1 0 1 Measure Y position X+ OFF ON Y Differential

1 1 1 0 Measure Z1 position X+ X–ON Y+ ON Y Differential

1 1 1 1 Measure Z2 position Y–X–ON Y+ ON Y Differential

(1) The setup command has an additional four bits of data. These data are static; that is, they are not changed by other commands, except

for the power-on reset. The default value for these bits after power-on reset is 0000. Table 4 shows the definition of these data bits.

Table 4. Command Byte Definition for the Setup Command

BIT NAME DESCRIPTION

D7-D4 C3-C0 = '1011' Setup command; must write '1011'.

D3-D2 PD1-PD0 = '00' Reserved; must write '00'.

0: Use the onboard MAV filter (default).

D1 Filter control 1: Bypass the onboard MAV filter.

0: RIRQ = 50kΩ(default).

D0 PENIRQ pull-up resistor (RIRQ) select 1: RIRQ = 90kΩ.

Product Folder Link(s): TSC2007-Q1

SDA

SCL

10 0 1 0

A1 A0

R/W

0C3 C2 C1 C0 PD1 PD0 M X 0

START

TSC2007

ACK

TSC2007

ACK

AddressByte CommandByte

Acquisition Conversion

STOPor

RepeatedSTART

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

START A CONVERTER FUNCTION/WRITE CYCLE

A conversion/write cycle begins when the master issues the address byte containing the slave address of the

TSC2007-Q1, with the eighth bit equal to a 0 (R/W = 0), as shown in Table 1. Once the eighth bit has been

received, and the address matches the A1-A0 address input pin setting, the TSC2007-Q1 issues an

acknowledge.

When the master receives the acknowledge bit from the TSC2007-Q1, the master writes the command byte to

the slave (see Table 2). After the command byte is received by the slave, the slave issues another acknowledge

bit. The master then ends the write cycle by issuing a repeated START or a STOP condition, as shown in

Figure 31.

Figure 31. Complete I2C Serial Write Transmission

If the master sends additional command bytes after the initial byte, but before sending a STOP or repeated

START condition, the TSC2007-Q1 does not acknowledge those bytes.

The input multiplexer channel for the A/D converter is selected when bits C3 through C0 are clocked in. If the

selected channel is an X-,Y-, or Z-position measurement, the appropriate drivers turn on once the acquisition

period begins.

When R/W = 0, the input sample acquisition period starts on the falling edge of SCL when the C0 bit of the

command byte has been latched, and ends when a STOP or repeated START condition has been issued. A/D

conversion starts immediately after the acquisition period. The multiplexer inputs to the A/D converter are

disabled once the conversion period starts. However, if an X-, Y-, or Z-position is being measured, the respective

touch screen drivers remain on during the conversion period. A complete write cycle is shown in Figure 31.

Product Folder Link(s): TSC2007-Q1

SDA

SCL

10 0 1 0 A1 A0

R/W

D11 D10 D9 D8 D7 D6 D5 D4 0

D3 D2 D1 D0 0 00 0 1

START TSC2007

ACK

MASTER

ACK

MASTER

NACK

STOPor

Repeated

START

AddressByte DataByte1 DataByte2

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

READ A CONVERSION/READ CYCLE

For best performance, the I2C bus should remain in an idle state while an A/D conversion is taking place. This

idling prevents digital clock noise from affecting the bit decisions being made by the TSC2007-Q1. The master

should wait for at least 10μs before attempting to read data from the TSC2007-Q1 to realize this best

performance. However, the master does not need to wait for a completed conversion before beginning a read

from the slave, if full 12-bit performance is not necessary.

Data access begins with the master issuing a START condition followed by the address byte (see Table 1) with

R/W = 1.

When the eighth bit has been received and the address matches, the slave issues an acknowledge. The first

byte of serial data then follows (D11-D4, MSB first).

After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge.

The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0,

followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to

indicate that the last data byte has been received. If the master somehow acknowledges the second data byte,

invalid data are returned (FFh). This condition applies to both 12-and 8-bit modes. See Figure 32 for a complete

I2C read transmission.

Figure 32. Complete I2C Serial Read Transmission

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

THROUGHPUT RATE AND I2C BUS TRAFFIC

Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is

much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The

throughput is further limited by the I2C bus bandwidth. The effective throughput is approximately 20kSPS at 8-bit

resolution, or 10kSPS at 12-bit resolution. This preprocessing saves a large portion of the I2C bandwidth for the

system to use on other devices.

Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal

4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For VDD = 1.2V, the frequency

reduces to 3.19MHz, which gives a 3.19MHz/16 = 199kSPS raw A/D converter sample rate.

12-Bit Operation

For 12-bit operation, sending the conversion result across the I2C bus takes 49 bus clocks (SCL clock). Each

write cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle

takes 29 I2C cycles (START, STOP, address byte, 3 ACKs, and data bytes 1 and 2). Seven

sample-and-conversions take 19 x 7 internal clocks to complete. The MAV filter loop requires 19 internal clocks.

For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 5. Because the first

acquisition cycle overlaps with the I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For

12-bit mode, (19 ×7 + 19) –4 = 148 CCLKs plus I/O are required.

8-Bit Operation

For 8-bit operation, sending the conversion result across the I2C bus takes 40 bus clocks (SCL clock). Each write

cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle takes 20

I2C cycles (START, STOP, address byte, 2 ACKs, and data byte 1). Seven sample-and-conversions takes 16 x 7

internal clocks to complete. The MAV filter loop requires 19 internal clocks. For VDD = 1.2V, the complete

processed data cycle time calculations are shown in Table 5. Because the first acquisition cycle overlaps with the

I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For 8-bit mode, (16 ×7 + 19) –4 = 127

CCLKs plus I/O are required.

Table 5. Measurement Cycle Time Calculations

STANDARD MODE: 100kHz (Period = 10μs)

8-Bit 40 ×10μs + 127 ×313ns = 439.8μs (2.27kSPS through the I2C bus)

12-Bit 49 ×10μs + 148 ×625ns = 582.5μs (1.72kSPS through the I2C bus)

FAST MODE: 400kHz (Period = 2.5μs)

8-Bit 40 ×2.5μs + 127 ×313ns = 139.8μs (7.15kSPS through the I2C bus)

12-Bit 49 ×2.5μs + 148 ×625ns = 215μs (4.65kSPS through the I2C bus)

HIGH-SPEED MODE: 1.7MHz (Period = 588ns)

8-Bit 40 ×588ns + 127 ×313ns = 63.3μs (15.79kSPS through the I2C bus)

12-Bit 49 ×588ns + 148 ×625ns = 121.3μs (8.24kSPS through the I2C bus)

HIGH-SPEED MODE: 3.4MHz (Period = 294ns)

8-Bit 40 ×294ns + 127 ×313ns = 51.6μs (19.39kSPS through the I2C bus)

12-Bit 49 ×294ns + 148 ×625ns = 106.9μs (9.35kSPS through the I2C bus)

As an example, use VDD = 1.2V and 12-bit mode with the Fast-mode I2C clock (fSCL = 400kHz). The equivalent

TSC throughput is at least seven times faster than the effective throughput across the bus (4.65k x 7 =

32.55kSPS). The supply current to the TSC for this rate and configuration is 128μA. To achieve an equivalent

sample throughput of 8.2kSPS using the device without preprocessing, the TSC2007-Q1 consumes only

(8.2/32.55) ×128μA = 32.24μA.

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

Table 6. Effective and Equivalent Throughput Rates

TSC

CONVERSION EFFECTIVE EQUIVALENT NO. NO. CCLK

SUPPLY I2C BUS SPEED CYCLE TIME THROUGHPUT THROUGHPUT OF OF fCCLK PERIODS

VOLTAGE (fSCL) RESOLUTION (μs) (kSPS) (kSPS) SCL CCLK (kHz) (ns)

8-bit 433.6 2.31 16.14 40 127 3780 264.6

100kHz

Standard 12-bit 568.7 1.76 12.31 49 148 1880 531.9

8-bit 133.6 7.49 52.40 40 127 3780 264.6

400kHz

Fast 12-bit 201.2 4.97 34.79 49 148 1880 531.9

2.7V 8-bit 57.1 17.50 122.53 40 127 3780 264.6

1.7MHz

High-Speed 12-bit 107.5 9.30 65.09 49 148 1880 531.9

8-bit 45.4 22.04 154.31 40 127 3780 264.6

3.4MHz

High-Speed 12-bit 93.1 10.74 75.16 49 148 1880 531.9

8-bit 434.7 2.30 16.10 40 127 3660 273.2

100kHz

Standard 12-bit 570.9 1.75 12.26 49 148 1830 546.4

8-bit 134.7 7.42 51.97 40 127 3660 273.2

400kHz

Fast 12-bit 203.4 4.92 34.42 49 148 1830 546.4

1.8V 8-bit 58.2 17.17 120.22 40 127 3660 273.2

1.7MHz

High-Speed 12-bit 109.7 9.12 63.81 49 148 1830 546.4

8-bit 46.5 21.52 150.65 40 127 3660 273.2

3.4MHz

High-Speed 12-bit 95.3 10.49 73.46 49 148 1830 546.4

8-bit 439.8 2.27 15.92 40 127 3190 313.5

100kHz

Standard 12-bit 582.5 1.72 12.02 49 148 1600 625.0

8-bit 139.8 7.15 50.07 40 127 3190 313.5

400kHz

Fast 12-bit 215.0 4.65 32.56 49 148 1600 625.0

1.2V 8-bit 63.3 15.79 110.51 40 127 3190 313.5

1.7MHz

High-Speed 12-bit 121.3 8.24 57.70 49 148 1600 625.0

8-bit 51.6 19.39 135.72 40 127 3190 313.5

3.4MHz

High-Speed 12-bit 106.9 9.35 65.47 49 148 1600 625.0

Product Folder Link(s): TSC2007-Q1

Acquisition1

6SCLs

Conversion1

15CCLKs

STOPor

REPEATEDSTART()

Conversion2

15CCLKs

Conversion7

15CCLKs

MAVFilter

19CCLKs

Acquisition2

4CCLKs

148CCLKs(FilterisEnabled,12-BitMode)

SDA

SCL

10 0 10

A1 A0

R/W

0C3 C2 C1 C0 PD1 PD0 M X 0

START

TSC2007

ACK

TSC2007

ACK

TSC2007

ACK

CCLK

AddressByte CommandByte

10 0 1 0

A1 A0 0

R/W

AddressByte

I CWrite

2I C

2Read

D11 D10 D9 D8 D7 D6 D5 D4 0

D3 D2 D1 D0 000 0 1

DataByte1

MASTER

ACK

MASTER

NACK

STOPor

REPEATEDSTART

DataByte2

ClockStretched

Acquisition1

6SCLs

Conversion1

15CCLKs

STOPor

REPEATEDSTART()

15CCLKs(FilterisDisabled,12-BitMode)

SDA

SCL

10 0 1 0

A1 A0

R/W

0C3 C2 C1 C0 PD1 PD0 M X 0

START

TSC2007

ACK

TSC2007

ACK

TSC2007

ACK

ClockStretched

CCLK

AddressByte CommandByte

10 0 1 0

A1 A0 0

R/W

AddressByte

D11 D10 D9 D8 D7 D6 D5 D4 0

D3 D2 D1 D0 000 0 1

DataByte1

MASTER

ACK

MASTER

NACK

STOPor

REPEATEDSTART

DataByte2

I C

2Write I C

2Read

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

Figure 33. Data Acquisition Cycle (Filter Enabled)

Figure 34. Data Acquisition Cycle (Filter Disabled)

Product Folder Link(s): TSC2007-Q1

1.2Vto3.6V

0.9V

0.3V

VDD

tVDD_OFF_RAMP

tVDD_OFF

tVDD_ON_RAMP

Temperature( C)°

V OffTimeforValidPOR(s)

-40 -20

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0 20 40 60 80 100

RecommendedV OffTime

forT = 40 Cto+85 C- ° °

TypicalV OffTimeforVariousTemperatures

TSC2007-Q1

SBAS545 –SEPTEMBER 2011

www.ti.com

POWER-ON RESET (POR)

During TSC2007-Q1 power-up, an internal power-on reset (POR) is automatically implemented. The POR brings

the TSC to the default working condition, and checks the A0 and A1 pins for the two LSBs of the I2C address.

The TSC2007-Q1 senses the power-up curve to decide whether or not to implement a POR.

It is required to follow the power-on/off slope and interval requirements, as provided in the Electrical

Characteristics , in order to ensure a proper POR of the TSC2007-Q1.

Figure 35. Power-On Reset Timing

Table 7. Timing Requirements for Figure 35

PARAMETER TEST CONDITIONS MIN MAX UNIT

VDD off ramp TA=–40°C to +85°C 2 kV/s

TA=–40°C to +85°C, VDD = 0V 1.2 s

VDD off time TA=–20°C to +85°C, VDD = 0V 0.3 s

VDD on ramp TA=–40°C to +85°C 12 kV/s

Figure 36. VDD Off Time vs Temperature

Product Folder Link(s): TSC2007-Q1

TSC2007-Q1

www.ti.com

SBAS545 –SEPTEMBER 2011

LAYOUT

The following layout suggestions should obtain optimum performance from the TSC2007-Q1. Keep in mind that

many portable applications have conflicting requirements for power, cost, size, and weight. In general, most

portable devices have fairly clean power and grounds because most of the internal components are very low

power. This situation would mean less bypassing for the converter power and less concern regarding grounding.

However, each situation is unique and the following suggestions should be reviewed carefully.

For optimum performance, care should be taken with the physical layout of the TSC2007-Q1 circuitry. The basic

SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections,

and digital inputs that occur immediately before latching the output of the analog comparator. Therefore, during

any single conversion for an n-bit SAR converter, there are nwindows in which large external transient voltages

can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby

digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage,

layout, and the exact timing of the external event. The error can change if the external event changes in time

with respect to the SCL input.

With this consideration in mind, power to the TSC2007-Q1 should be clean and well-bypassed. A 0.1μF ceramic

bypass capacitor should be placed as close to the device as possible. In addition, a 1μF to 10μF capacitor may

also be needed if the impedance of the connection between VDD/REF and the power supply is high.

A bypass capacitor is generally not needed on the VDD/REF pin because the internal reference is buffered by an

internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any

bypass capacitor that is used without oscillation.

The TSC2007-Q1 architecture offers no inherent rejection of noise or voltage variation with regard to using an

external reference input, which is of particular concern when the reference input is tied to the power supply. Any

noise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filtered

out, voltage variation because of line frequency (50Hz or 60Hz) can be difficult to remove. Some package

options have pins labeled as VOID. Avoid any active trace going under any pin marked as VOID unless it is

shielded by a ground or power plane.

The GND pin should be connected to a clean ground point. In many cases, this point is the analog ground. Avoid

connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a

ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout

includes an analog ground plane dedicated to the converter and associated analog circuitry.

In the specific case of use with a resistive touch screen, care should be taken with the connection between the

converter and the touch screen. Resistive touch screens have fairly low resistance; therefore, the interconnection

should be as short and robust as possible. Loose connections can be a source of error when the contact

resistance changes with flexing or vibrations.

As indicated previously, noise can be a major source of error in touch-screen applications (for example,

applications that require a back-lit LCD panel). This electromagnetic interference (EMI) noise can be coupled

through the LCD panel to the touch screen and cause flickering of the converted A/D converter data. Several

things can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connected

to ground, which couples the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y–, X+, and

X–to ground, can also help. Note, however, that the use of these capacitors increases screen settling time and

requires a longer time for panel voltages to stabilize. The resistor value varies depending on the touch screen

sensor used. The PENIRQ pull-up resistor (RIRQ) may be adequate for most of sensors.

Product Folder Link(s): TSC2007-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 24-May-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TSC2007IPWRQ1 ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TSC2007-Q1 :

•Catalog: TSC2007

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TSC2007IPWRQ1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TSC2007IPWRQ1 TSSOP PW 16 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265