MS29C2G24MAKLA1-6I - White Electronic Designs

MS29C2G24MAKLA1-XX

*PRELIMINARY

Rev. 2 www.microsemi.com

Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

2Gb NAND FLASH (x16) / 1Gb LPDDR (x32)

FEATURES

 Package:

• 152 Plastic Ball Grid Array (PBGA), 14 x 14 mm

• 0.65 mm pitch

 Micron® NAND Flash and LPDDR components

 RoHS-compliant, “green” package

 Separate NAND Flash and LPDDR interfaces

 Space-saving multichip package/package-on-package

combination

 Low-voltage operation (1.8V)

 Commercial and industrial temperature ranges

 Same footprint as Micron MT29C2G24MAKLA-XIT

NAND Flash-Speciﬁ c Features

Organization

 Page size

• x16: 1056 words (1024 + 32 words)

 Block size: 64 pages (128K + 4K bytes)

Mobile LPDDR-Speciﬁ c Features

 No external voltage reference required

 No minimum clock rate requirement

 1.8V LVCMOS-compatible inputs

 Programmable burst lengths

 Partial-array self refresh (PASR)

 Deep power-down (DPD) mode

 Selectable output drive strength

* This product is under development, is not qualiﬁ ed or characterized and is subject to change

without notice.

Micron® is a registered trademark of Micron Technology, Inc.

GENERAL DESCRIPTION

Microsemi package-on-package (PoP) MCP products combine

NAND Flash and Mobile LPDRAM devices in a single MCP.

These products target mobile applications with low-power, high-

performance, and minimal package-footprint design requirements.

The NAND Flash and Mobile LPDRAM devices are packaged with

separate interfaces (no shared address, control, data, or power

balls). This bus architecture supports an optimized interface to

processors with separate NAND Flash and Mobile LPDRAM buses.

The NAND Flash and Mobile LPDRAM devices have separate core

power connections and share a common ground (that is, VSS is

tied together on the two devices).

The bus architecture of this device also supports separate NAND

Flash and Mobile LPDRAM functionality without concern for device

interaction.

Microsemi NAND Flash devices include an asynchronous data

interface for high-performance I/O operations. These devices

use a highly multiplexed 8-bit bus (I/Ox) to transfer commands,

address, and data. There are ﬁ ve control signals used to implement

the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#.

Additional signals control hardware write protection and monitor

device status (R/B#).

This hardware interface creates a low pin-count device with

a standard pinout that remains the same from one density to

another, enabling future upgrades to higher densities with no

board redesign.

A target is the unit of memory accessed by a chip enable signal. A

target contains one or more NAND Flash die. A NAND Flash die

is the minimum unit that can independently execute commands

and report status. A NAND Flash die, in the ONFI speciﬁ cation,

is referred to as a logical unit (LUN). There is at least one NAND

Flash die per chip enable signal.

This device has an internal 4-bit ECC that can be enabled using

the GET/SET features. See Internal ECC and Spare Area Mapping

for ECC for more information.

The 1Gb Mobile low-power DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing 1,073,741,824. It is

internally conﬁ gured as a quad-bank DRAM. Each of the x32’s

268M-bit banks is organized as 8,192 rows by 1024 columns by

32 bits. In the reduced page-size (LG) option, each of the x32's

268M-bit banks is organized as 16,384 rows by 512 columns by

32 bits.

For a more detailed data

sheet on operations and

speciﬁ cations; contact factory.

NOTES:

1. Throughout this data sheet, various ﬁ gures and text refer to DQs as “DQ.” DQ should be

interpreted as any and all DQ collectively, unless speciﬁ cally stated otherwise. Additionally, the

x16 is divided into 2 bytes: the lower byte and the upper byte. For the lower byte (DQ[7:0]), DM

refers to LDM and DQS refers to LDQS. For the upper byte (DQ[15:8]), DM refers to UDM and

DQS refers to UDQS. The x32 is divided into 4 bytes. For DQ[7:0], DM refers to DM0 and DQS

refers to DQS0. For DQ[15:8], DM refers to DM1 and DQS refers to DQS1. For DQ[23:16], DM

refers to DM2 and DQS refers to DQS2. For DQ[31:24], DM refers to DM3 and DQS refers to

DQS3.

2. Complete functionality is described throughout the document; any page or diagram may have

been simpliﬁ ed to convey a topic and may not be inclusive of all requirements.

3. Any speciﬁ c requirement takes precedence over a general statement.

MS29C2G24MAKLA1-XX

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1 2 3 4 5 6 7 8 9 101112131415161718192021

VSSQ

DQ3

DQ0

VSSQ

DQ4

DM0

VDD

FWE#

I/O13

I/O10

I/O12

I/O8

I/O9

I/O1

I/O3

DNU

DQ21

VDD

DQ20

DQ23

DM3

DQ22

DQS3

DQ28

DQS0

DQ5

DQ1

VDDQ

DQ2

VSS

I/O14

I/O15

RE#

VSS

VCC

I/O11

VSS

VCC

I/O0

I/O2

LOCK

VDDQ

DQS2

DQ26

DQ29

DQ31

VDDQ

DQ30

VDD

VSSQ

A11

VDD

A12

CS0#

RAS#

VDDQ

DQ24

DQ25

DQ27

VSSQ

VSS

VDDQ

VSS

DNU

CAS#

BA1

VSSQ

VDDQ

DQ6

DM2

VSSQ

DM1

DQ7

VSS

CK#

DQ13

VDDQ

DQ18

VSSQ

DQ14

DQ16

DQ8

DQ10

DQS1

DQ12

DQ11

DQ15

DQ9

DQ19

DQ17

A10

VSSQ

VSS

VDD

DWE#

BA0

VSSQ

VDDQ

CKE0

DNU

I/O6

I/O4

VDD

VDDQ

I/O7

I/O5

DNU

VSS

WP#

RFU

VCC

VSS

R/B#

CLE

CE0#

ALE

VSS

VCC

VSS

VDD

FIGURE 1 – PIN CONFIGURATION

TOP VIEW

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CE0#

CLE

ALE

RE#

FWE#

WP#

LOCK

CS0#

CK#

CKE0

RAS#

CAS#

DWE#

ddress 0-12,

BA0, BA1

VCC

I/O 0-15

R/B#

VSS

VDD

VDDQ

DQ 0-31

DQS

VSS

VSSQ

2G NAND Flash

(x16)

1G LPDDR

(x32)

FIGURE 2 – 152-BALL (SINGLE LPDDR) FUNCTIONAL BLOCK DIAGRAM

ELECTRICAL SPECIFICATIONS

TABLE 1 – ABSOLUTE MAXIMUM RATINGS

Parameters/Conditions Symbol Min Max Unit

VCC, VDD, VDDQ supply voltage relative to VSS VCC, VDD, VDDQ –1.0 2.4 V

Voltage on any pin relative to VSS VIN –0.5 2.4 or (supply voltage1 + 0.3V),

whichever is less V

Storage temperature range – –55 +150 °C

Note: 1. Supply voltage references VCC, VDD, or VDDQ.

Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this speciﬁ cation is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

TABLE 2 – RECOMMENDED OPERATING CONDITIONS

Parameters Symbol Min Typ Max Unit

Supply voltage VCC, VDD 1.70 1.80 1.95 V

I/O supply voltage VDDQ 1.70 1.80 1.95 V

Operating temperature range — –40 — +85 °C

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TABLE 3 – x16 NAND BALL DESCRIPTIONS

Symbol Type Description

ALE Input Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address register.

CE0# Input Chip enable: Gates transfers between the host system and the NAND device.

CLE Input Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip command register.

LOCK Input When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK LOCK, connect LOCK to VSS during

power-up, or leave it unconnected (internal pull-down).

RE# Input Read enable: Gates information from the NAND device to the host system.

FWE# Input Write enable: Gates information from the host system to the NAND device.

WP# Input Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations.

I/O[15:0] Input/output Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information. Data is output only during READ

operations; at other times the I/Os are inputs.

R/B# Output Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in progress.

VCC Supply VCC: NAND power supply.

TABLE 4 – x32 LPDDR BALL DESCRIPTIONS

Symbol Type Description

A[12:0] Input Address inputs: Speciﬁ es the row or column address. Also used to load the mode registers. The maximum LPDDR address is

determined by density and conﬁ guration.

BA0, BA1 Input Bank address inputs: Speciﬁ es one of the 4 banks.

CAS# Input Column select: Speciﬁ es which command to execute.

CK, CK# Input CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are sampled and referenced on the

crossing of the rising edge of CK with the falling edge of CK#.

CKE0 Input Clock enable: CKE0 is used for a single LPDDR product.

CS0# Input Chip select: CS0# is used for a single LPDDR product.

DM[3:0] Input Data mask: Determines which bytes are written during WRITE operations.

RAS# Input Row select: Speciﬁ es the command to execute.

DWE# Input Write enable: Speciﬁ es the command to execute.

DQ[31:0] Input/output Data bus: Data inputs/outputs.

DQS[3:0] Input/output Data strobe: Coordinates READ/WRITE transfers of data; one DQS per DQ byte.

TQ Output Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C.

VDD Supply VDD: LPDDR power supply.

VDDQ Supply VDDQ: LPDDR I/O power supply.

VSSQ Supply VSSQ: LPDDR I/O ground.

TABLE 3 – NON-DEVICE-SPECIFIC DESCRIPTIONS

Symbol Type Description

VSS Supply VSS: Shared ground.

DNU — Do not use

NC — No connect: Not internally connected.

RFU1— Reserved for future use.

Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details.

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2Gb: x16 NAND FLASH MEMORY – 1.8V

FEATURES

 Open NAND Flash Interface (ONFI) 1.0-compliant1

 Single-level cell (SLC) technology

 Organization

• Page size x16: 1056 words (1024 + 32 words)

• Block size: 64 pages (128K + 4K bytes)

• Device size: 2Gb: 2048 blocks

 Asynchronous I/O performance

• tRC/tWC: 35ns

 Array performance

• Read page: 25μs

• Program page: 300μs (TYP)

• Erase block: 500μs (TYP)

 Command set: ONFI NAND Flash Protocol

 Advanced command set

• Program cache

• Read cache sequential

• Read cache random

• One-time programmable (OTP) mode

• Programmable drive strength

• Interleaved die (LUN) operations

• Read unique ID

• Block lock

• Internal data move

 Operation status byte provides software method for

detecting

• Operation completion

• Pass/fail condition

• Write-protect status

 Internal data move operations supported within the device

from which data is read

 Ready/Busy# (R/B#) signal provides a hardware method of

detecting operation completion

 WP# signal: Write protect entire device

 First blocks (block address 00h) is valid when shipped from

factory with ECC; for minimum required ECC, see Error

Management

 RESET (FFh) required as ﬁ rst command after power-on

 Quality and reliability

• Data retention: 10 years

 Endurance: 100,000 program/erase cycles

 Operating voltage range

• VCC: 1.7–1.95V

 Operating temperature

• Commercial: 0°C to +70°C

• Industrial (IT): –40ºC to +85ºC

NOTES:

1. The ONFI 1.0 speciﬁ cation is available at www.onﬁ .org.

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NAND FLASH ELECTRICAL SPECIFICATIONS

Stresses greater than those listed can cause permanent damage to

the device. This is a stress rating only, and functional operation of

the device at these or any other conditions above those indicated

in the operational sections of this speciﬁ cation is not guaranteed.

Exposure to absolute maximum rating conditions for extended

periods can affect reliability.

TABLE 6 – ABSOLUTE MAXIMUM RATINGS

Voltage on any pin relative to VSS

Parameter/Condition Symbol Min Max Unit

Voltage Input VIN –0.6 +2.4 V

VCC supply voltage VCC –0.6 +2.4 V

Storage temperature TSTG –65 +150 °C

Short circuit output current, I/Os – – 5 mA

TABLE 7 – RECOMMENDED OPERATING CONDITIONS

Parameter/Condition Symbol Min Typ Max Unit

Operating temperature Commercial TA

0 – +70 °C

Industrial –40 – +85 °C

VCC supply voltage VCC 1.65 1.8 1.95 V

Ground supply voltage VSS 000V

TABLE 8 – VALID BLOCKS

Parameter Symbol Device Min Max Unit Notes

Valid block number NVB 2G 2008 2048 blocks 1, 2

NOTES:

1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad blocks

upon shipment. Additional bad blocks may develop over time; however, the total number of

available blocks will not drop below NVB during the endurance life of the device. Do not erase or

program blocks marked invalid by the factory.

2. Block 00h (the ﬁ rst block) is guaranteed to be valid with ECC when shipped from the factory.

TABLE 9 – CAPACITANCE

Description Symbol Max Unit Notes

Input capacitance CIN 10 pF 1, 2

Input/output capacitance (I/O) CIO 10 pF 1, 2

NOTES:

1. These parameters are veriﬁ ed in device characterization and are not tested.

2. Test conditions: TC = 25°C; f = 1 MHz; Vin = 0V. TABLE 10 – TEST CONDITIONS

Parameter Device Value Notes

Input pulse levels 2G 0.0V to VCC

Input rise and fall times 5ns

Input and output timing levels VCC/2

Output load 1 TTL GATE and CL = 30pF 1

NOTE:

1. Veriﬁ ed in device characterization, not tested.

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NAND FLASH ELECTRICAL SPECIFICATIONS – AC CHARACTERISTICS AND OPERATING

CONDITIONS TABLE 11 – AC CHARACTERISTICS: COMMAND, DATA, AND ADDRESS INPUT

Parameter Symbol Min Max Unit Notes

ALE to data start tADL 100 – ns 1

ALE hold time tALH 4–ns

ALE setup time tALS 15 – ns

CE# hold time tCH 4–ns

CLE hold time tCLH 5–ns

CLE setup time tCLS 15 – ns

CE# setup time tCS 24 – ns

Data hold time tDH 4–ns

Data setup time tDS 15 – ns

WRITE cycle time tWC 35 – ns

WE# pulse width HIGH tWH 15 – ns

WE# pulse width tWP 17 – ns

WP# setup time tWW 100 – ns

NOTE:

1. Timing for tADL begins in the address cycle on the ﬁ nal rising edge of WE# and ends with the ﬁ rst rising edge of WE# for data input.

TABLE 12 – AC CHARACTERISTICS: NORMAL OPERATION

Note 1 applies to all

Parameter Symbol Min Max Unit Notes

ALE to RE# delay tAR 10 – ns

CE# access time tCEA –30ns

CE# HIGH to output High-Z tCHZ –45ns2

CLE to RE# delay tCLR 10 – ns

CE# HIGH to output hold tCOH 15 – ns

Output High-Z to RE# LOW tIR 0–ns

READ cycle time tRC 35 – ns

RE# access time tREA –24ns

RE# HIGH hold time tREH 15 – ns

RE# HIGH to output hold tRHOH 15 – ns

RE# HIGH to WE# LOW tRHW 100 – ns

RE# HIGH to output High-Z tRHZ – 100 ns 2

RE# LOW to output hold tRLOH 0–ns

RE# pulse width tRP 17 – ns

Ready to RE# LOW tRR 20 – ns

Reset time (READ/PROGRAM/ERASE) tRST – 5/10/500 s3

WE# HIGH to busy tWB – 100 ns 4

WE# HIGH to RE# LOW tWHR 80 – ns

NOTES:

1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.

2. Transition is measured ±200mV from steady-state voltage with load. This parameter is not tested.

3. The ﬁ rst time the RESET (FFh) command is issued while the device is idle, the device will be busy for a maximum of 1ms. Thereafter, the device will be busy for maximum 5s.

4. Do not issue a new command during tWB, even if R/B# is ready.

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NAND FLASH ELECTRICAL SPECIFICATIONS – DC CHARACTERISTICS AND OPERATING

CONDITIONS (cont'd)

TABLE 12 – DC CHARACTERISTICS AND OPERATING CONDITIONS

Parameter Conditions Symbol Min Typ Max Unit Notes

Sequential READ current tRC = tRC (MIN); CE# = VIL; IOUT = 0mA ICC1 –1020mA

PROGRAM current – ICC2 –1020mA

ERASE current – ICC3 –1020mA

Standby current (TTL) CE# = VIH; LOCK = WP# = 0V/VCC ISB1 ––1mA

Standby current (CMOS) CE# = VCC - 0.2V; LOCK = WP# = 0V/VCC ISB2 –1050A

Staggered power-up current Rise time = 1ms

Line capacitance = 0.1FIST – – 10 per die mA 1

Input leakage current VIN = 0V to VCC ILI – – ±10 A

Output leakage current VOUT = 0V to VCC ILO – – ±10 A

Input high voltage I/O[15:0], CE#, CLE, ALE, WE#, RE#,WP#, R/B# VIH 0.8 x VCC –V

CC + 0.3 V

Input low voltage, all inputs – VIL –0.3 – 0.2 x VCC V

Output high voltage IOH = –100AV

OH VCC – 0.1 – – V 2

Output low voltage IOL = –100AV

OL – – 0.1 V 2

Output low current VOL = 0.4V IOL (R/B#) 34–mA3

NOTES:

1. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC (MIN).

2. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.

3. IOL (RB#) may need to be relaxed if R/B pull-down strength is not set to full.

TABLE 13 – PROGRAM/ERASE CHARACTERISTICS

Parameter Symbol Typ Max Unit Notes

Number of partial page programs NOP – 4 Cycles 1

BLOCK ERASE operation time tBERS 0.5 3 ms

Busy time for PROGRAM CACHE operation (1.8V) tCBSY 3 600 s2

Busy time for SET FEATURES and GET FEATURES operations (1.8V) tFEAT –3s

Busy time for PROGRAM/ERASE on locked block tLBSY –3s

LAST PAGE PROGRAM operation time tLPROG –––3

Busy time for OTP DATA PROGRAM operation if OTP is protected tOBSY –30s

PAGE PROGRAM operation time (1.8V) tPROG 300 600 s

Data transfer from Flash array to data register tR–25s

Busy time for READ CACHE operation tRCBSY 325s

NOTES:

1. Four total partial-page programs to the same page.

2. tCBSY MAX time depends on timing between internal program completion and data-in.

3. tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) - address load time (last page) - data load time (last page).

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64 pages = 1 block

(64K + 2K) words

1 page = (1K + 32 words)

1 block = (1K + 32) words x 64 pages

= (64K + 2K) words

1 device = (1K + 32) words x 64 pages x 2048 blocks

= 2112Mb

Cache Register

Data Register

2048 blocks

per device

1 block

321024

1056 words

I/O15

I/O0

FIGURE 3 – ARRAY ORGANIZATION

TABLE 14 – ARRAY ADDRESSING

Cycle I/O[15:8] I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second LOW LOW LOW LOW LOW LOW CA101CA9 CA8

Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

Fifth LOW LOW LOW LOW LOW LOW LOW LOW BA16

NOTES:

1. If CA10 is 1, then CA[9:5] must be 0.

2. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address.

3. I/O[15:8] are not used during the addressing sequence and should be driven LOW.

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1Gb: x32 MOBILE LPDDR SDRAM

Features

 VDD/VDDQ = 1.8V

 Bidirectional data strobe per byte of data (DQS)

 Internal, pipelined double data rate (DDR) architecture; two

data accesses per clock cycle

 Differential clock inputs (CK and CK#)

 Commands entered on each positive CK edge

 DQS edge-aligned with data for READs; center-aligned with

data for WRITEs

 4 internal banks for concurrent operation

 Data masks (DM) for masking write data—one mask per

byte

 Programmable burst lengths (BL): 2, 4, 8, or 16

 Concurrent auto precharge option is supported

 Auto refresh and self refresh modes

 1.8V LVCMOS-compatible inputs

 Partial-array self refresh (PASR)

 Deep power-down (DPD)

 Status read register (SRR)

 Selectable output drive strength (DS)

 Clock stop capability

 64ms refresh

TABLE 15 – CONFIGURATION ADDRESING – 1Gb

Architecture 32 Meg x 32

Conﬁ guration 8 Meg x 32 x 4 banks

Refresh count 8K

Row addressing 8K A[13:0]

Column addressing 1K A[9:0]

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LPDDR ELECTRICAL SPECIFICATIONS

Stresses greater than those listed may cause permanent damage

to the device. This is a stress rating only, and functional operation

of the device at these or any other conditions above those indicated

in the operational sections of this speciﬁ cation is not implied.

Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

TABLE 16 – ABSOLUTE MAXIMUM RATINGS

Note 1 applies to all parameters in this table

Parameter Symbol Min Max Unit

VDD/VDDQ supply voltage relative to VSS VDD/VDDQ –1.0 2.4 V

Voltage on any pin relative to VSS VIN –0.5 2.4 or (VDDQ + 0.3V),

whichever is less V

Storage temperature (plastic) TSTG –55 150 ˚C

NOTE: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed VDD.

TABLE 17 – AC/DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

Notes 1–5 apply to all parameters/conditions in this table; VCC/VCCQ = 1.70–1.95V

Parameter/Condition Symbol Min Max Unit Notes

Supply voltage VDD 1.70 1.95 V 6, 7

I/O supply voltage VDDQ 1.70 1.95 V 6, 7

Address and command inputs

Input voltage high VIH 0.8 × VDDQ VDDQ + 0.3 V 8, 9

Input voltage low VIL –0.3 0.2 × VDDQ V 8, 9

Clock inputs (CK, CK#)

DC input voltage VIN –0.3 VDDQ + 0.3 V 10

DC input differential voltage VID(DC) 0.4 × VDDQ VDDQ + 0.6 V 10, 11

AC input differential voltage VID(AC) 0.6 × VDDQ VDDQ + 0.6 V 10, 11

AC differential crossing voltage VIX 0.4 × VDDQ 0.6 × VDDQ V 10, 12

Data inputs

DC input high voltage VIH(DC) 0.7 × VDDQ VDDQ + 0.3 V 8, 9, 13

DC input low voltage VIL(DC) –0.3 0.3 × VDDQ V 8, 9, 13

AC input high voltage VIH(AC) 0.8 × VDDQ VDDQ + 0.3 V 8, 9, 13

AC input low voltage VIL(AC) –0.3 0.2 × VDDQ V 8, 9, 13

Data outputs

DC output high voltage: Logic 1 (IOH = –0.1mA) VOH 0.9 × VDDQ –V

DC output low voltage: Logic 0 (IOL = 0.1mA) VOL – 0.1 × VDDQ V

Leakage current

Input leakage current

Any input 0V  VIN  VDD

(All other pins not under test = 0V)

II–1 1 A

Output leakage current

(DQ are disabled; 0V  VOUT  VDDQ)IOZ –5 5 A

Operating temperature

Commercial TA 0 70 ˚C

Industrial TA –40 85 ˚C

Notes on next page

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LPDDR ELECTRICAL SPECIFICATIONS (cont'd)

NOTES:

1. All voltages referenced to VSS.

2. All parameters assume proper device initialization.

3. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal

supply voltage levels, but the related speciﬁ cations and device operation are guaranteed for the

full voltage range speciﬁ ed.

4. Outputs measured with equivalent load; transmission line delay is assumed to be very small:

I/O

20pF

I/O

10pF

Full drive strength Half drive strength

50 50

5. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input

timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The output timing

reference voltage level is VDDQ/2.

6. Any positive glitch must be less than one-third of the clock cycle and not more than +200mV or

2.0V, whichever is less. Any negative glitch must be less than one-third of the clock cycle and

not exceed either –150mV or +1.6V, whichever is more positive.

7. VDD and VDDQ must track each other and VDDQ must be less than or equal to VDD.

8. To maintain a valid level, the transitioning edge of the input must:

8a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC)

or VIH(AC).

8b. Reach at least the target AC level.

8c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC)

or VIH(DC).

9. VIH overshoot: VIHmax = VDDQ + 1.0V for a pulse width 3ns and the pulse width cannot be

greater than one-third of the cycle rate. VIL undershoot: VILmin = –1.0V for a pulse width 3ns

and the pulse width cannot be greater than one-third of the cycle rate.

10. CK and CK# input slew rate must be 1 V/ns (2 V/ns if measured differentially).

11. VID is the magnitude of the difference between the input level on CK and the input level on CK#.

12. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations

in the DC level of the same.

13. DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must be

added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns,

functionality is uncertain.

TABLE 18 – CAPACITANCE (X32)

Note 1 applies to all the parameters in this table

Parameter Symbol Min Max Unit Notes

Input capacitance: CK, CK# CCK 1.5 3.0 pF

Delta input capacitance: CK, CK# CDCK – 0.25 pF 2

Input capacitance: command and address CI1.5 3.0 pF

Delta input capacitance: command and address CDI – 0.5 pF 2

Input/output capacitance: DQ, DQS, DM CIO 1.5 4.5 pF

Delta input/output capacitance: DQ, DQS, DM CDIO – 0.5 pF 3

NOTES:

1. This parameter is guaranteed by design, not tested.

2. The input capacitance per pin group will not differ by more than this maximum amount for any given device.

3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device.

MS29C2G24MAKLA1-XX

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LPDDR ELECTRICAL SPECIFICATIONS – IDD PARAMETERS

TABLE 19 – IDD SPECIFICATIONS AND CONDITIONS

Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V

Parameter/Condition Symbol

Max

Unit Notes-5 -54 -6 -75

Operating 1 bank active precharge current: tRC = tRC (MIN); tCK = tCK (MIN); CKE is HIGH; CS is

HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus

inputs are stable

IDD0 110 105 100 70 mA 6

Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH; tCK = tCK (MIN);

Address and control inputs are switching; Data bus inputs are stable

IDD2P 600 600 600 600 A 7, 8

Precharge power-down standby current: Clock stopped; All banks idle; CKE is LOW; CS is

HIGH, CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are

stable

IDD2PS 600 600 600 600 A7

Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS = HIGH;

tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable

IDD2N 18 17 15 12 mA 9

Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE = HIGH;

CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs

are stable

IDD2NS 14 13 8 8 mA 9

Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK = tCK (MIN);

Address and control inputs are switching; Data bus inputs are stable

IDD3P 3.6 3.6 3.6 3.6 mA 8

Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW; CS = HIGH;

CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable

IDD3PS 3.6 3.6 3.6 3.6 mA

Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK = tCK (MIN);

Address and control inputs are switching; Data bus inputs are stable

IDD3N 20 19 18 16 mA 6

Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS = HIGH;

CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable

IDD3NS 16 15 14 12 mA 6

Operating burst read: 1 bank active; BL = 4; CL = 3; tCK = tCK (MIN); Continuous READ bursts;

Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data changing each burst

IDD4R 150 145 140 120 mA 6

Operating burst write: One bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE bursts;

Address inputs are switching; 50% data changing each burst

IDD4W 150 145 140 120 mA 6

Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are

switching; Data bus inputs are stable

tRFC = 138ns IDD5 140 140 140 140 mA 10

tRFC = tREFI IDD5A 15 15 15 14 mA 10, 11

Typical deep power-down current at 25°C: Address and control pins are stable; Data bus inputs

are stable

IDD8 10 10 10 10 A 7, 13

Notes on next page

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LPDDR ELECTRICAL SPECIFICATIONS – IDD PARAMETERS (cont'd)

TABLE 20 – IDD6 SPECIFICATIONS AND CONDITIONS

Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V

Parameter/Condition Symbol Low Power Standard Units

Self refresh:

CKE = LOW; tCK = tCK (MIN); Address and control inputs are stable;

Data bus inputs are stable

Full array, 85˚CI

DD6 1000 1200 A

Full array, 45˚C 500 750 A

1/2 array, 85˚C 750 900 A

1/2 array, 45˚C 440 730 A

1/4 array, 85˚C 600 750 A

1/4 array, 45˚C 380 680 A

1/8 array, 85˚C 550 750 A

1/8 array, 45˚C 350 620 A

1/16 array, 85˚C 500 700 A

1/16 array, 45˚C 330 540 A

NOTES:

1. All voltages referenced to VSS.

2. Tests for IDD characteristics may be conducted at nominal supply voltage levels, but the related

speciﬁ cations and device operation are guaranteed for the full voltage range speciﬁ ed.

3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input

timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The output timing

reference voltage level is VDDQ/2.

4. IDD is dependent on output loading and cycle rates. Speciﬁ ed values are obtained with minimum

cycle time with the outputs open.

5. IDD speciﬁ cations are tested after the device is properly initialized and values are averaged at

the deﬁ ned cycle rate.

6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum

absolute value for the respective parameter. tRASmax for IDD measurements is the largest multiple

of tCK that meets the maximum absolute value for tRAS.

7. Measurement is taken 500ms after entering into this operating mode to provide settling time for

the tester.

8. VDD must not vary more than 4% if CKE is not active while any bank is active.

9. IDD2N speciﬁ es DQ, DQS, and DM to be driven to a valid high or low logic level.

10. CKE must be active (HIGH) during the entire time a REFRESH command is executed. From the

time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge

until tRFC later.

11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH

command period (tRFC (MIN)) else CKE is LOW (for example, during standby).

12. Values for IDD6 85˚C are guaranteed for the entire temperature range. All other IDD6 values are

estimated.

13. Typical values at 25˚C, not a maximum value.

MS29C2G24MAKLA1-XX

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LPDDR ELECTRICAL SPECIFICATIONS – AC OPERATING CONDITIONS

TABLE 21 – ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V

Parameter Symbol

-5 -54 -6 -75

Unit NotesMin Max Min Max Min Max Min Max

Access window of DQ from CK/CK# CL = 3 tAC

2.0 5.0 2.0 5.0 2.0 5.5 2.0 6.0 ns

CL = 2 2.0 6.5 2.0 6.5 2.0 6.5 2.0 6.5

Clock cycle time CL = 3 tCK

5.0 – 5.4 – 6 – 7.5 – ns 10

CL = 2 12–12–12–12–

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CKE minimum pulse width (high and low) tCKE 1–1–1–1–t

CK 11

Auto precharge write recovery + precharge time tDAL –––––––––12

DQ and DM input hold time relative to DQS (fast slew rate) tDHf 0.6 – 0.6 – 0.6 – 0.8 – ns 13, 14,

DQ and DM input hold time relative to DQS (slow slew rate) tDHs 0.7 – 0.7 – 0.7 – 0.9 – ns

DQ and DM input setup time relative to DQS (fast slew rate) tDSf 0.6 – 0.6 – 0.6 – 0.8 – ns 13, 14,

DQ and DM input setup time relative to DQS (slow slew rate) tDSs 0.7 – 0.7 – 0.7 – 0.9 – ns

DQ and DM input pulse width (for each input) tDIPW 1.8 – 1.9 – 2.1 – 1.8 – ns 16

Access window of DQS from CK/CK# CL = 3 tDQSCK

2.0 5.0 2.0 5.0 2.0 5.5 2.0 6.0 ns

CL = 2 2.0 6.5 2.0 6.5 2.0 6.5 2.0 6.5 ns

DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ – 0.4 – 0.45 – 0.45 – 0.6 ns 13, 17

WRITE command to ﬁ rst DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge from CK rising – hold time tDSH 0.2 – 0.2 – 0.2 – 0.2 – tCK

DQS falling edge to CK rising – setup time tDSS 0.2 – 0.2 – 0.2 – 0.2 – tCK

Data valid output window (DVW) n/a tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns 17

Half-clock period tHP tCH, tCL –t

CH, tCL –t

CH, tCL –ns18

Data-out High-Z window from CK/ CK# CL = 3 tHZ

– 5.0 – 5.0 – 5.5 – 6.0 ns 19, 20

CL = 2 – 6.5 – 6.5 – 6.5 – 6.5 ns

Data-out Low-Z window from CK/CK# tLZ 1.0 – 1.0 – 1.0 – 1.0 – ns 19

Address and control input hold time (fast slew rate) tIHF0.9 – 1.0 – 1.1 – 1.3 – ns 15, 21

Address and control input hold time (slow slew rate) tIHS1.1 – 1.2 – 1.2 – 1.5 – ns

Address and control input setup time (fast slew rate) tISF0.9 – 1.0 – 1.1 – 1.3 – ns 15, 21

Address and control input setup time (slow slew rate) tISS1.1 – 1.2 – 1.2 – 1.5 – ns

Address and control input pulse width tIPW 2.3 – 2.5 – 2.6 – tIS + tIH –ns16

LOAD MODE REGISTER command cycle time tMRD 2–2–2–2–t

DQ–DQS hold, DQS to ﬁ rst DQ to go nonvalid, per access tQH tHP -

tQHS –tHP -

tQHS – ns 13, 17

Data hold skew factor tQHS – 0.5 – 0.5 – 0.65 – 0.75 ns

ACTIVE-to-PRECHARGE command tRAS 40 70,000 42 70,000 42 70,000 45 70,000 ns 22

ACTIVE to ACTIVE/ACTIVE to AUTO REFRESH command period tRC 55 – 58.2 – 60 – 67.5 – ns

Active to read or write delay tRCD 15 – 16.2 – 18 – 22.5 – ns

Refresh period tREF –64–64–64–64ms28

Notes on next page

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LPDDR ELECTRICAL SPECIFICATIONS – AC OPERATING CONDITIONS (cont'd)

TABLE 22 – ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (cont'd)

Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V

Parameter Symbol

-5 -54 -6 -75

Unit NotesMin Max Min Max Min Max Min Max

Average periodic refresh interval tREFI – 7.8 – 7.8 – 7.8 – 7.8 s23

AUTO REFRESH command period tRFC 110–110–110–110– ns

PRECHARGE command period tRP 15 – 16.2 – 18 – 22.5 – ns

DQS read preamble CL = 3 tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK

CL = 2 tRPRE 0.5 1.1 0.5 1.1 0.5 1.1 0.5 1.1 tCK

DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Active bank a to active bank b command tRRD 10 – 10.8 – 12 – 15 – ns

Read of SRR to next valid command tSRC CL + 1 – CL + 1 – CL + 1 – CL + 1 – tCK

SRR to read tSRR 2–2–2–2–t

DQS write preamble tWPRE 0.25 – 0.25 – 0.25 – 0.25 – tCK

DQS write preamble setup time tWPRES 0–0–0–0– ns24, 25

DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 26

Write recovery time tWR 15–15–15–15– ns 27

Internal WRITE-to-READ command delay tWTR 2–2–1–1–t

Exit power-down mode to ﬁ rst valid command tXP 2–2–1–1–t

Exit self refresh to ﬁ rst valid command tXSR 112.5 – 112.5 – 112.5 – 112.5 – ns 28

NOTES:

1. All voltages referenced to VSS.

2. All parameters assume proper device initialization.

3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nominal supply

voltage levels, but the related speciﬁ cations and device operation are guaranteed for the full

voltage ranges speciﬁ ed.

4. The circuit shown below represents the timing reference load used in deﬁ ning the relevant

timing parameters of the device. It is not intended to be either a precise representation of the

typical system environment or a depiction of the actual load presented by a production tester.

System designers will use IBIS or other simulation tools to correlate the timing reference load

to system environment. Speciﬁ cations are correlated to production test conditions (generally a

coaxial transmission line terminated at the tester electronics). For the half-strength driver with a

nominal 10pF load, parameters tAC and tQH are expected to be in the same range. However, these

parameters are not subject to production test but are estimated by design/characterization. Use of

IBIS or other simulation tools for system design validation is suggested.

I/O

20pF

I/O

10pF

Full drive strength Half drive strength

50 50

5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point at which

CK and CK# cross; the input reference voltage level for signals other than CK/ CK# is VDDQ/2.

6. A CK and CK# input slew rate 1 V/ns (2 V/ns if measured differentially) is assumed for all

parameters.

7. All AC timings assume an input slew rate of 1 V/ns.

8. CAS latency deﬁ nition: with CL = 2, the ﬁ rst data element is valid at (tCK + tAC) after the clock at

which the READ command was registered; for CL = 3, the ﬁ rst data element is valid at (2 × tCK +

tAC) after the ﬁ rst clock at which the READ command was registered.

9. Timing tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still

referenced to VDDQ/2 or to the crossing point for CK/CK#. The output timing reference voltage level

is VDDQ/2.

10. Clock frequency change is only permitted during clock stop, power-down, or self refresh mode.

11. In cases where the device is in self refresh mode for tCKE, tCKE starts at the rising edge of the clock

and ends when CKE transitions HIGH.

12. tDAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round up to the next highest integer.

13. Referenced to each output group: For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with

DQ[23:16]; and DQS3 with DQ[31:24].

14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/ DQS

slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each

100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, functionality is uncertain.

15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and

addresses) are measured between VIL(DC) to VIH(AC) for rising input signals and VIH(DC) to VIL(AC) for

falling input signals.

16. These parameters guarantee device timing but are not tested on each device.

17. The valid data window is derived by achieving other speciﬁ cations: tHP (tCK/2), tDQSQ, and tQH (tHP -

tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical

data valid window can be derived. The clock is provided a maximum duty cycle variation of 45/55.

Functionality is uncertain when operating beyond a 45/55 ratio.

18. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK and CK# inputs,

collectively.

19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These

parameters are not referenced to a speciﬁ c voltage level, but specify when the device output is no

longer driving (tHZ) or begins driving (tLZ).

20. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.

21. Fast command/address input slew rate 1 V/ns. Slow command/address input slew rate 0.5 V/

ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per

each 100 mV/ns reduction in slew rate from the 0.5 V/ns. tIH has 0ps added, therefore, it remains

constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain.

22. READs and WRITEs with auto precharge must not be issued until tRAS (MIN) can be satisﬁ ed prior to

the internal PRECHARGE command being issued.

23. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125s

24. This is not a device limit. The device will operate with a negative value, but system performance

could be degraded due to bus turnaround.

25. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case

shown (DQS going from High-Z to logic low) applies when no WRITEs were previously in progress

on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending

on tDQSS.

26. The maximum limit for this parameter is not a device limit. The device will operate with a greater

value for this parameter, but system performance (bus turnaround) will degrade accordingly.

27. At least 1 clock cycle is required during tWR time when in auto precharge mode.

28. Clock must be toggled a minimum of two times during the tXSR period.

MS29C2G24MAKLA1-XX

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Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

13 (0.512) BSC

1.28

MAX

Ball A1 ID

0.65 (0.026) TYP

13 (0.512) BSC

14 ±0.1 (0.551±0.004)

152x Ø0.46 (0.018)

0.34

(0.014)

MIN

14 ±0.1 (0.551±0.004)

0.65

(0.026)

TYP

21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

FIGURE 23 – 152-BALL BGA PACKAGE

BOTTOM VIEW

NOTE: (1) Dimension applies to solder ball post reﬂ ow on Ø0.35 ball pad.

All linear dimensions are millimeters and parenthetically in inches

MS29C2G24MAKLA1-XX

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ORDERING INFORMATION

MICROSEMI CORPORATION

PRODUCT FAMILY

29C-2Gb/1Gb

NAND FLASH DENSITY

2G = 2Gb NAND FLASH

LPDRAM DENSITY

24M = 1G LPDDR

OPERATING VOLTAGE RANGE

A = 1.8V

NAND FLASH CONFIGURATION

K = x16

LPDRAM CONFIGURATION

L = x32

CHIP COUNT

A = 2; 1 NAND FLASH / 1 LPDDR SDRAM

PACKAGE CODES

1 = 152 Ball BGA

LPDRAM ACCESS TIME

X = CLOCK CYCLE TIME

Speed Grade Clock Rate CAS Latency

-5 200 MHz CL3

-54 185 MHz CL3

-6 166 MHz CL3

-75 133 MHz CL3

OPERATING TEMPERATURE

I = INDUSTRIAL TEMPERATURE (-40°C to +85°C)

C = COMMERCIAL TEMPERATURE (0°C to +70°C)

MS 29C 2G 24M A K L A 1 - X X

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Document Title

2GB NAND / 1GB LPDDR

Revision History

Rev # History Release Date Status

Rev 0 Changes (Pg. 1-19)

0.1 Create new data sheet

April 2011 Advanced

Rev 1 Changes (Pg. 2-4)

1.1 Figure 1 – pin AA15 from A13 to DNU

1.2 Figure 2 – changed Address 0-14 to 0-12

1.3 Table 4 – changed A[14:0] to A[12:0]

July 2011 Advanced

Rev 2 Changes (Pg. 1)

2.1 Change status to Preliminary and add bullet to Features section "Same

footprint as Micron MT29C2G24MAKLA-XIT"

October 2011 Preliminary