HD6433434TF - Renesas Technology / Hitachi Semiconductor

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Renesas Technology Corp.

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April 1, 2003

To all our customers

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Hitachi Single-Chip Microcomputer

H8/3437 Series

H8/3437

HD6473437, HD6433437

H8/3436

HD6433436

H8/3434

HD6473434, HD6433434

H8/3437W

HD6433437W

H8/3436W

HD6433436W

H8/3434W

HD6433434W

H8/3437F-ZTAT™

HD64F3437

H8/3437SF-ZTAT™

HD64F3437S

H8/3434F-ZTAT™

HD64F3434

Hardware Manual

ADE-602-077F

Rev. 7.0

3/14/03

Hitachi, Ltd.

The revision list can be viewed directly by 

clicking the title page.

The revision list summarizes the locations of 

revisions and additions. Details should always 

be checked by referring to the relevant text.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demands especially high quality and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

they are used as test pins or to reduce noise. If something is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the

chip and a low level is input on the reset pin. During the period where the states are

undefined, the register settings and the output state of each pin are also undefined. Design

your system so that it does not malfunction because of processing while it is in this

undefined state. For those products which have a reset function, reset the LSI immediately

after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these addresses. Do not access these registers; the system’s

operation is not guaranteed if they are accessed.

Preface

The H8/3437 Series is a high-performance single-chip microcomputer that integrates peripheral

functions necessary for system configuration with an H8/300 CPU featuring a 32-bit internal

architecture as its core.

On-chip peripheral functions include ROM, RAM, four kinds of timers, a serial communication

interface (SCI), host interface (HIF), keyboard controller, D/A converter, A/D converter, and I/O

ports, enabling the H8/3437 Series to be used as a microcontroller for embedding in high-speed

control systems. Flash memory (F-ZTAT™*), PROM (ZTAT®*), and mask ROM are available

as on-chip ROM, enabling users to respond quickly and flexibly to changing application

specifications and the demands of the transition from initial to full-fledged volume production.

Note: * F-ZTAT is a trademark of Hitachi, Ltd.

ZTAT is a registered trademark of Hitachi, Ltd.

Intended Readership: This manual is intended for users undertaking the design of an application

system using a H8/3437 Series microcomputer. Readers using this manual

require a basic knowledge of electrical circuits, logic circuits, and

microcomputers.

Purpose: The purpose of this manual is to give users an understanding of the

hardware functions and electrical characteristics of the H8/3437 Series.

Details of execution instructions can be found in the H8/300 Series

Programming Manual, which should be read in conjunction with the present

manual.

Using this Manual:

• For an overall understanding of the H8/3437 Series’ functions

Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system

control functions, peripheral functions, and electrical characteristics.

• For a detailed understanding of CPU functions

Refer to the separate publication H8/300 Series Programming Manual.

• For a detailed description of a register’s function when the register name is known.

Information on addresses, bit contents, and initialization is summarized in Appendix B,

Internal I/O Register.

Note on bit notation: Bits are shown in high-to-low order from left to right.

Related Material: The latest information is available at our Web Site. Please make sure that you

have the most up-to-date information available.

http://www.hitachisemiconductor.com/

User's Manuals on the H8/3437 Series:

Manual Title ADE No.

H8/3437 Series Hardware Manual This manual

H8/300 Series Programming Manual ADE-602-025

Users manuals for development tools:

Manual Title ADE No.

C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual ADE-702-247

Simulator Debugger Users Manual ADE-702-282

Hitachi Debugging Interface Users Manual ADE-702-161

Hitachi Embedded Workshop Users Manual ADE-702-201

H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging

Interface Users Manual ADE-702-231

Notes on S-Mask Model

(Single-Power-Supply Specification)

There are two versions of the H8/3437F with on-chip flash memory: a dual-power-supply version

and a single-power-supply (S-mask) version. Points to be noted when using the H8/3437F single-

power-supply S-mask model are given below.

1. Notes on Voltage Application

12 V must not be applied to the S-mask model (single-power-supply specification), as this may

permanently damage the device.

The flash memory programming power supply for the S-mask model (single-power-supply

specification) is VCC. The programming power supply for the dual-power-supply model is the FVPP

pin (12 V), but the single-power-supply model (S-mask model) does not have an FVPP pin.

Also, in boot mode, 12 V has to be applied to the MD1 pin in the dual-power-supply model, but 12

V application is not necessary in the single-power-supply model (S-mask model).

The maximum rating of the MD1 pin is VCC +0.3 V. Applying a voltage in excess of the

maximum rating will permanently damage the device.

Do not select the HN28F101 programmer setting for the S-mask model (single-power-supply

specification). If this setting is made by mistake, 12 V will be applied to the STBY pin, possibly

causing permanent damage to the device.

When using a PROM programmer to program the on-chip flash memory in the S-mask model

(single-power-supply specification), use a PROM programmer that supports Hitachi

microcomputer devices with 64-kbyte on-chip flash memory. Also, only use the specified socket

adapter. Using the wrong PROM programmer or socket adapter may damage the device.

The following PROM programmers support the S-mask model (single-power-supply

specification).

DATA I/O: UNISITE, 2900, 3900, etc.

Minato: 1892, 1891, 1890, etc.

2. Product Type Names and Markings

Table 1 shows examples of product type names and markings for the H8/3437F (dual-power-

supply specification) and H8/3437SF (single-power-supply specification), and the differences in

flash memory programming power supply.

Table 1 Differences in H8/3437F and H8/3437F S-Mask Model Markings

Dual-Power-Supply Model:

H8/3437F Single-Power-Supply Model:

H8/3437F S-Mask Model

Product type name HD64F3437F16/TF16 HD64F3437SF16/TF16

Sample markings

H8/3437

64F3437F16

8M3

JAPAN

H8/3437

HD S

64F3437F16

8M3

JAPAN

“S” is printed above the type name

Flash memory

programming power

supply

VPP power supply

(12.0 V ±0.6 V) VCC power supply

(5.0 V ±10%)

3. Differences in S-Mask Model

Table 2 shows the differences between the H8/3437F (dual-power-supply specification) and

H8/3437SF (single-power-supply specification).

Table 2 Differences between H8/3437F and H8/3437F S-Mask Model

Item Dual-Power-Supply Model:

H8/3437F Single-Power-Supply Model:

H8/3437F S-Mask Model

Program/

erase voltage 12 V must be applied from off-chip

VPP (12.0 V ±0.6 V) 12 V application not required

VCC single-power-supply programming

VCC (5.0 V ±10%)

FVPP (FWE)

pin function Dual function as FVPP power supply

and STBY function No programming control pin

Programming

modes • Writer mode

• On-board

 Boot mode

 User programming mode

(See section 21 for the use of these

modes)

Operating

modes allowing

on-board

programming

• Writer mode

• Boot mode

• User programming mode

(See section 21 for the use of these

modes)

On-board

programming

unit

1-byte-unit programming 32-byte-unit programming

Programming

with PROM

programmer

Select Hitachi stand-alone flash

memory HN28F101 setting Special programming mode setting

required. Use of PROM programmer

that supports Hitachi microcomputer

device types with 64-kbyte on-chip flash

memory. (128-byte-unit fast page

programming)

Boot mode

setting

method

Reset release after MD1 = FVPP/STBY =

12 V application MD1

0MD0

0P92

1P91

1P90

Setting level

Reset release after above pin settings

User program

mode setting

method

FVPP = 12 V application Control bits set by software

Item Dual-Power-Supply Model:

H8/3437F Single-Power-Supply Model:

H8/3437F S-Mask Model

Programming

mode timing RES

MD0

MD112 V

12 V

Min 0 µs

tMDS

tMDS: 4tcyc (min.)

VPP

RES

MD1,

MD1

P92,

P91,

P90

tMDS

tMDS: 4tcyc (min.)

Prewrite

processing Required before erasing Not required

Programming

processing Block corresponding to programming

address must be set in EBR1/EBR2

registers before programming

Settings at left not required

EBR register

configuration EBR1, EBR2 EBR2

Memory map

(block

configuration)

LB0 (4 kbytes)

LB1(8 kbytes)

LB2 (8 kbytes)

LB3 (8 kbytes)

LB4 (8 kbytes)

LB5 (8 kbytes)

LB6 (12 kbytes)

LB7 (2 kbytes)

SB0 (128 bytes)

SB1 (128 bytes)

SB2 (128 bytes)

SB3 (128 bytes)

SB4 (512 bytes)

SB5 (1 kbyte)

SB6 (1 kbyte)

SB7 (1 kbyte)

60 kbytes EB4 (24 kbytes)

EB5 (16 kbytes)

EB6 (12 kbytes)

EB7 (2 kbytes)

EB0 (1 kbyte)

EB1 (1 kbyte)

EB2 (1 kbyte)

EB3 (1 kbyte)

60 kbytes

Reset during

operation Drive RES pin low for at least 10

system clock cycles (10ø). (RES pulse

width tRESW = min. 10tcyc)

Drive RES pin low for at least 20

system clock cycles (20ø). (RES pulse

width tRESW = min. 20tcyc)

Item Dual-Power-Supply Model:

H8/3437F Single-Power-Supply Model:

H8/3437F S-Mask Model

MDCR 76 321

MDS1 0

MDS0

——

—4

—— — 76 321

MDS1 0

MDS0

——

EXPE 4

—— —

Bit 7: Expanded mode enable (EXPE)

WSCR 76 321

WC1 0

WC0

RAMS RAM0

CKDBL

—WMS1WMS0 76 321

WC1 0

WC0

CKDBL

FLSHE

—— WMS1WMS0

Bit 4: Flash memory control register

enable (FLSHE)

FLMCR1 7

VPP

EV 2

PV 1

—— 4

—7

FWE SWE

EV 2

PV 1

—4

—

Bit 7: Flash write enable (FWE)

Bit 6: Software write enable (SWE)

FLMCR2 —7

FLER 6321

ESU 0

PSU

—— 4

—— —

Bit 7: Flash memory error (FLER)

Bit 1: Erase setup (ESU)

Bit 0: Program setup (PSU)

EBR1 76 321054

LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 —

This address is not used.

EBR2 76 321054

SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 76 321054

EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

Erase block register (EBR2)

EB0 (1 kbyte): H'0000 to H'03FF

EB1 (1 kbyte): H'0400 to H'07FF

EB2 (1 kbyte): H'0800 to H'0BFF

EB3 (1 kbyte): H'0C00 to H'0FFF

EB4 (28 kbytes): H'1000 to H'7FFF

EB5 (16 kbytes): H'8000 to H'BFFF

EB6 (12 kbytes): H'C000 to H'EF7F

EB7 (2 kbytes): H'EF00 to H'F77F

Details

concerning

flash memory

See section 20, ROM (Dual-Power-

Supply 60-Kbyte Flash Memory

Version)

See section 21, ROM (Single-Power-

Supply 60-Kbyte Flash Memory

Version)

Electrical

characteristics See section 23, Electrical

Characteristics See section 23, Electrical

Characteristics

Registers See Appendix B, Registers See Appendix B, Registers

Table 3 shows differences in the development environments of the H8/3437F (dual-power-supply

specification) and H8/3437SF (single-power-supply specification).

Table 3 H8/3437F and H8/3437F S-Mask Model Development Environments

Item Dual-Power-Supply Model:

H8/3437F Single-Power-Supply Model:

H8/3437F S-Mask Model

E6000

emulator Emulator

unit Hitachi

HS3008EPI60H Hitachi

HS3008EPI60H

User

cable Hitachi

HS3437ECH61H Hitachi

HS3437ECH61H

Programming

socket adapter Hitachi

HS3434ESHF1H Minato

DATA I/O

Adapter board Hitachi

HS0008EASF1H/2H Hitachi

HS0008EASF3H

Windows interface

software Hitachi

HS6400FWIW2SF Hitachi

HS6400FWIW2SF

Table 4 shows differences in the pin settings of the H8/3437F (dual-power-supply specification)

and H8/3437SF (single-power-supply specification).

Table 4 H8/3437F and H8/3437F S-Mask Model Pin Settings

Item Dual-Power-Supply Model:

H8/3437F Single-Power-Supply Model:

H8/3437F S-Mask Model

Boot mode

12 V

H8/3437F

FVPP/STBY

MD1

VCC (5 V)

VSS

(GND)

H8/3437SF

P92

P91

P90

MD1

MD0

User programming

mode 12 V

H8/3437F

FVPP/STBY

There are no state transitions due to pin

states. Transitions should be implemented

by means of register settings by software.

List of Items Revised or Added for This Version

Section Page Item Description

(see Manual for details)

Notes on S-Mask Model

(Single-Power-Supply

Specification)

Table 1 Differences in

H8/3437F and H8/3437F S-

Mask Model Markings

Single-Power-Supply

Model: H8/3437F S-

mask model sample

marking amended

1.1 Overview 3 Table 1.1 Features “Other features”

specifications amended.

4 H8/3434F-ZTAT ROM

amended in “Series

Lineup” specifications.

Notes 1 and 3 deleted

1.3.1 Pin Arrangement 6 Figure 1.2 Pin Arrangement

(FP-100B, TFP-100B, Top

View)

Rotated 90 degrees to

the left, so that pin 1 is at

the bottom left.

6.2.2 Oscillator Circuit

(H8/3437SF) 95 to 99 Added

12.3.2 Asynchronous

Mode 264 Figure 12.5 Sample Flowchart

for Transmitting Serial Data Flowchart amended.

Procedure 1 description

added.

Section 13 I2C Bus

Interface [Option] 283 Descriptions 1 and 3

deleted

13.4 Application Notes 311 to 315 • Note on Issuance of

Retransmission Start

Condition

• Note on Issuance of Stop

Condition

• Countermeasure

• Additional Note

• Precautions when Clearing

the IRIC Flag when Using

the Wait Function

Added

15.6 Application Notes 354 Figure 15.10 Example of

Analog Input Circuit Figure amended

18.3.2 Notes on

Programming 373 (1) description added.

19.6.1 Writer Mode

Setting 418 Description amended

Section Page Item Description

(see Manual for details)

21.1.7 Flash Memory

Operating Modes 504 Figure 21.2 Flash Memory

Related State Transitions “SWE” amended to

“FLSHE”.

505 Figure 21.3 Boot Mode Procedure 2 amended.

506 Figure 21.4 User

Programming Mode (Example) Procedure 2 amended.

21.2.3 Erase Block

description added.

21.3.1 Boot Mode 516 RAM Area Allocation in Boot

Mode Description amended.

517 Figure 21.9 RAM Areas in

Boot Mode Amended

Notes on Use of Boot Mode 5 description amended.

21.4 to 21.4.4 520 to 524 Entire description

amended.

21.5.1 Writer Mode

Setting 528 * and Note description

added.

21.5.3 Operation in

Writer Mode 538 Figure 21.22 Status Read

Mode Timing Waveforms

Table 21.19 Status Read

Mode Return Codes

Note amended

21.6 Flash Memory

Programming and Erasing 540 (1) Program with the specified

voltage and timing Description amended.

Precautions 541 Table 21.22 Area Accessed in

Each Mode with FLSHE = 0

and FLSHE = 1

FLSHE = 1 mode 2

amended

22.3.5 Application Note 2 description deleted.

23 Electrical

Characteristics 553 to 604 Heading number

amended

23.3 Electrical

Characteristics

(H8/3437SF Low-Voltage

Version)

579 Entire description newly

added.

B.2 Function 665 I2C Bus Control Register

Bit 2 to 0: I2C Transfer Rate

Select

Table amended and note

added

Contents

Section 1 Overview........................................................................................................... 1

1.1 Overview............................................................................................................................ 1

1.2 Block Diagram................................................................................................................... 5

1.3 Pin Assignments and Functions ........................................................................................ 6

1.3.1 Pin Arrangement .................................................................................................. 6

1.3.2 Pin Functions........................................................................................................ 7

Section 2 CPU..................................................................................................................... 19

2.1 Overview............................................................................................................................ 19

2.1.1 Features ................................................................................................................ 19

2.1.2 Address Space ...................................................................................................... 20

2.1.3 Register Configuration ......................................................................................... 20

2.2 Register Descriptions......................................................................................................... 21

2.2.1 General Registers.................................................................................................. 21

2.2.2 Control Registers.................................................................................................. 21

2.2.3 Initial Register Values.......................................................................................... 22

2.3 Data Formats...................................................................................................................... 23

2.3.1 Data Formats in General Registers....................................................................... 24

2.3.2 Memory Data Formats.......................................................................................... 25

2.4 Addressing Modes............................................................................................................. 26

2.4.1 Addressing Mode.................................................................................................. 26

2.4.2 Calculation of Effective Address.......................................................................... 28

2.5 Instruction Set.................................................................................................................... 32

2.5.1 Data Transfer Instructions.................................................................................... 34

2.5.2 Arithmetic Operations.......................................................................................... 36

2.5.3 Logic Operations.................................................................................................. 37

2.5.4 Shift Operations.................................................................................................... 37

2.5.5 Bit Manipulations................................................................................................. 39

2.5.6 Branching Instructions.......................................................................................... 44

2.5.7 System Control Instructions................................................................................. 46

2.5.8 Block Data Transfer Instruction........................................................................... 47

2.6 CPU States......................................................................................................................... 49

2.6.1 Overview.............................................................................................................. 49

2.6.2 Program Execution State...................................................................................... 50

2.6.3 Exception-Handling State .................................................................................... 50

2.6.4 Power-Down State................................................................................................ 51

2.7 Access Timing and Bus Cycle........................................................................................... 51

2.7.1 Access to On-Chip Memory (RAM and ROM)................................................... 51

2.7.2 Access to On-Chip Register Field and External Devices..................................... 53

Section 3 MCU Operating Modes and Address Space........................................... 57

3.1 Overview............................................................................................................................ 57

3.1.1 Mode Selection..................................................................................................... 57

3.1.2 Mode and System Control Registers.................................................................... 57

3.2 System Control Register (SYSCR).................................................................................... 58

3.3 Mode Control Register (MDCR)....................................................................................... 60

3.4 Address Space Map in Each Operating Mode................................................................... 61

Section 4 Exception Handling........................................................................................ 65

4.1 Overview............................................................................................................................ 65

4.2 Reset.................................................................................................................................. 65

4.2.1 Overview.............................................................................................................. 65

4.2.2 Reset Sequence..................................................................................................... 65

4.2.3 Disabling of Interrupts after Reset ....................................................................... 68

4.3 Interrupts............................................................................................................................ 68

4.3.1 Overview.............................................................................................................. 68

4.3.2 Interrupt-Related Registers .................................................................................. 70

4.3.3 External Interrupts................................................................................................ 74

4.3.4 Internal Interrupts................................................................................................. 74

4.3.5 Interrupt Handling................................................................................................ 75

4.3.6 Interrupt Response Time...................................................................................... 80

4.3.7 Precaution............................................................................................................. 81

4.4 Note on Stack Handling..................................................................................................... 82

Section 5 Wait-State Controller .................................................................................... 83

5.1 Overview............................................................................................................................ 83

5.1.1 Features ................................................................................................................ 83

5.1.2 Block Diagram...................................................................................................... 83

5.1.3 Input/Output Pins.................................................................................................. 84

5.1.4 Register Configuration ......................................................................................... 84

5.2 Register Description.......................................................................................................... 84

5.2.1 Wait-State Control Register (WSCR) .................................................................. 84

5.3 Wait Modes........................................................................................................................ 86

Section 6 Clock Pulse Generator .................................................................................. 89

6.1 Overview............................................................................................................................ 89

6.1.1 Block Diagram...................................................................................................... 89

6.1.2 Wait-State Control Register (WSCR) .................................................................. 90

6.2 Oscillator Circuit ............................................................................................................... 91

6.2.1 Oscillator (Generic Device).................................................................................. 91

6.2.2 Oscillator Circuit (H8/3437S).............................................................................. 95

6.3 Duty Adjustment Circuit.................................................................................................... 99

6.4 Prescaler ............................................................................................................................ 99

iii

Section 7 I/O Ports ............................................................................................................ 101

7.1 Overview............................................................................................................................ 101

7.2 Port 1.................................................................................................................................. 104

7.2.1 Overview.............................................................................................................. 104

7.2.2 Register Configuration and Descriptions ............................................................. 105

7.2.3 Pin Functions in Each Mode ................................................................................ 107

7.2.4 Input Pull-Up Transistors..................................................................................... 109

7.3 Port 2.................................................................................................................................. 110

7.3.1 Overview.............................................................................................................. 110

7.3.2 Register Configuration and Descriptions ............................................................. 111

7.3.3 Pin Functions in Each Mode ................................................................................ 113

7.3.4 Input Pull-Up Transistors..................................................................................... 115

7.4 Port 3.................................................................................................................................. 116

7.4.1 Overview.............................................................................................................. 116

7.4.2 Register Configuration and Descriptions ............................................................. 117

7.4.3 Pin Functions in Each Mode ................................................................................ 119

7.4.4 Input Pull-Up Transistors..................................................................................... 120

7.5 Port 4.................................................................................................................................. 121

7.5.1 Overview.............................................................................................................. 121

7.5.2 Register Configuration and Descriptions ............................................................. 122

7.5.3 Pin Functions........................................................................................................ 124

7.6 Port 5.................................................................................................................................. 126

7.6.1 Overview.............................................................................................................. 126

7.6.2 Register Configuration and Descriptions ............................................................. 126

7.6.3 Pin Functions........................................................................................................ 128

7.7 Port 6.................................................................................................................................. 129

7.7.1 Overview.............................................................................................................. 129

7.7.2 Register Configuration and Descriptions ............................................................. 129

7.7.3 Pin Functions........................................................................................................ 132

7.7.4 Input Pull-Up Transistors..................................................................................... 134

7.8 Port 7.................................................................................................................................. 135

7.8.1 Overview.............................................................................................................. 135

7.8.2 Register Configuration and Descriptions ............................................................. 135

7.9 Port 8.................................................................................................................................. 136

7.9.1 Overview.............................................................................................................. 136

7.9.2 Register Configuration and Descriptions ............................................................. 137

7.9.3 Pin Functions........................................................................................................ 139

7.10 Port 9.................................................................................................................................. 141

7.10.1 Overview.............................................................................................................. 141

7.10.2 Register Configuration and Descriptions ............................................................. 142

7.10.3 Pin Functions........................................................................................................ 144

7.11 Port A................................................................................................................................. 146

7.11.1 Overview.............................................................................................................. 146

7.11.2 Register Configuration and Descriptions ............................................................. 146

7.11.3 Pin Functions in Each Mode ................................................................................ 148

7.11.4 Input Pull-Up Transistors ..................................................................................... 149

7.12 Port B................................................................................................................................. 150

7.12.1 Overview.............................................................................................................. 150

7.12.2 Register Configuration and Descriptions ............................................................. 151

7.12.3 Pin Functions in Each Mode ................................................................................ 153

7.12.4 Input Pull-Up Transistors ..................................................................................... 154

Section 8 16-Bit Free-Running Timer......................................................................... 155

8.1 Overview............................................................................................................................ 155

8.1.1 Features ................................................................................................................ 155

8.1.2 Block Diagram...................................................................................................... 156

8.1.3 Input and Output Pins........................................................................................... 157

8.1.4 Register Configuration ......................................................................................... 158

8.2 Register Descriptions......................................................................................................... 159

8.2.1 Free-Running Counter (FRC)............................................................................... 159

8.2.2 Output Compare Registers A and B (OCRA and OCRB).................................... 159

8.2.3 Input Capture Registers A to D (ICRA to ICRD)................................................ 160

8.2.4 Timer Interrupt Enable Register (TIER).............................................................. 162

8.2.5 Timer Control/Status Register (TCSR)................................................................ 164

8.2.6 Timer Control Register (TCR) ............................................................................. 166

8.2.7 Timer Output Compare Control Register (TOCR) .............................................. 168

8.3 CPU Interface.................................................................................................................... 170

8.4 Operation ........................................................................................................................... 173

8.4.1 FRC Increment Timing ........................................................................................ 173

8.4.2 Output Compare Timing ...................................................................................... 175

8.4.3 FRC Clear Timing................................................................................................ 176

8.4.4 Input Capture Timing........................................................................................... 176

8.4.5 Timing of Input Capture Flag (ICF) Setting ........................................................ 179

8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB).......................... 179

8.4.7 Setting of FRC Overflow Flag (OVF).................................................................. 180

8.5 Interrupts............................................................................................................................ 181

8.6 Sample Application ........................................................................................................... 182

8.7 Application Notes.............................................................................................................. 183

Section 9 8-Bit Timers ..................................................................................................... 189

9.1 Overview............................................................................................................................ 189

9.1.1 Features ................................................................................................................ 189

9.1.2 Block Diagram...................................................................................................... 190

9.1.3 Input and Output Pins........................................................................................... 191

9.1.4 Register Configuration ......................................................................................... 191

9.2 Register Descriptions......................................................................................................... 192

9.2.1 Timer Counter (TCNT)........................................................................................ 192

9.2.2 Time Constant Registers A and B (TCORA and TCORB).................................. 192

9.2.3 Timer Control Register (TCR) ............................................................................. 193

9.2.4 Timer Control/Status Register (TCSR)................................................................ 196

9.2.5 Serial/Timer Control Register (STCR) ................................................................ 198

9.3 Operation ........................................................................................................................... 199

9.3.1 TCNT Increment Timing...................................................................................... 199

9.3.2 Compare-Match Timing....................................................................................... 201

9.3.3 External Reset of TCNT....................................................................................... 203

9.3.4 Setting of TCSR Overflow Flag (OVF) ............................................................... 203

9.4 Interrupts............................................................................................................................ 204

9.5 Sample Application ........................................................................................................... 204

9.6 Application Notes.............................................................................................................. 205

9.6.1 Contention between TCNT Write and Clear........................................................ 205

9.6.2 Contention between TCNT Write and Increment ................................................ 206

9.6.3 Contention between TCOR Write and Compare-Match...................................... 207

9.6.4 Contention between Compare-Match A and Compare-Match B ......................... 208

9.6.5 Increment Caused by Changing of Internal Clock Source................................... 208

Section 10 PWM Timers.................................................................................................... 211

10.1 Overview............................................................................................................................ 211

10.1.1 Features ................................................................................................................ 211

10.1.2 Block Diagram...................................................................................................... 212

10.1.3 Input and Output Pins........................................................................................... 212

10.1.4 Register Configuration ......................................................................................... 213

10.2 Register Descriptions......................................................................................................... 213

10.2.1 Timer Counter (TCNT)........................................................................................ 213

10.2.2 Duty Register (DTR)............................................................................................ 214

10.2.3 Timer Control Register (TCR) ............................................................................. 215

10.3 Operation ........................................................................................................................... 217

10.3.1 Timer Increment................................................................................................... 217

10.3.2 PWM Operation.................................................................................................... 218

10.4 Application Notes.............................................................................................................. 219

Section 11 Watchdog Timer ............................................................................................. 221

11.1 Overview............................................................................................................................ 221

11.1.1 Features ................................................................................................................ 221

11.1.2 Block Diagram...................................................................................................... 222

11.1.3 Output Pin ............................................................................................................ 222

11.1.4 Register Configuration ......................................................................................... 223

11.2 Register Descriptions......................................................................................................... 223

11.2.1 Timer Counter (TCNT)........................................................................................ 223

11.2.2 Timer Control/Status Register (TCSR)................................................................ 224

11.2.3 System Control Register (SYSCR) ...................................................................... 226

11.2.4 Register Access .................................................................................................... 226

11.3 Operation ........................................................................................................................... 227

11.3.1 Watchdog Timer Mode ........................................................................................ 227

11.3.2 Interval Timer Mode ............................................................................................ 228

11.3.3 Setting the Overflow Flag.................................................................................... 228

11.3.4 RESO Signal Output Timing................................................................................ 229

11.4 Application Notes.............................................................................................................. 230

11.4.1 Contention between TCNT Write and Increment ................................................ 230

11.4.2 Changing the Clock Select Bits (CKS2 to CKS0)................................................ 230

11.4.3 Recovery from Software Standby Mode.............................................................. 230

11.4.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 231

11.4.5 System Reset by RESO Signal............................................................................. 231

11.4.6 Detection of Program Runaway ........................................................................... 231

Section 12 Serial Communication Interface................................................................ 233

12.1 Overview............................................................................................................................ 233

12.1.1 Features ................................................................................................................ 233

12.1.2 Block Diagram...................................................................................................... 234

12.1.3 Input and Output Pins........................................................................................... 235

12.1.4 Register Configuration ......................................................................................... 236

12.2 Register Descriptions......................................................................................................... 237

12.2.1 Receive Shift Register (RSR)............................................................................... 237

12.2.2 Receive Data Register (RDR) .............................................................................. 237

12.2.3 Transmit Shift Register (TSR).............................................................................. 237

12.2.4 Transmit Data Register (TDR)............................................................................. 238

12.2.5 Serial Mode Register (SMR)................................................................................ 238

12.2.6 Serial Control Register (SCR).............................................................................. 240

12.2.7 Serial Status Register (SSR)................................................................................. 243

12.2.8 Bit Rate Register (BRR)....................................................................................... 246

12.2.9 Serial/Timer Control Register (STCR) ................................................................ 257

12.3 Operation ........................................................................................................................... 258

12.3.1 Overview.............................................................................................................. 258

12.3.2 Asynchronous Mode ............................................................................................ 260

12.3.3 Synchronous Mode............................................................................................... 273

12.4 Interrupts............................................................................................................................ 279

12.5 Application Notes.............................................................................................................. 279

Section 13 I2C Bus Interface [Option]........................................................................... 283

13.1 Overview............................................................................................................................ 283

13.1.1 Features ................................................................................................................ 283

13.1.2 Block Diagram...................................................................................................... 285

vii

13.1.3 Input/Output Pins.................................................................................................. 286

13.1.4 Register Configuration ......................................................................................... 286

13.2 Register Descriptions......................................................................................................... 287

13.2.1 I2C Bus Data Register (ICDR).............................................................................. 287

13.2.2 Slave Address Register (SAR) ............................................................................. 287

13.2.3 I2C Bus Mode Register (ICMR)........................................................................... 288

13.2.4 I2C Bus Control Register (ICCR)......................................................................... 289

13.2.5 I2C Bus Status Register (ICSR)............................................................................ 292

13.2.6 Serial/Timer Control Register (STCR) ................................................................ 296

13.3 Operation ........................................................................................................................... 297

13.3.1 I2C Bus Data Format............................................................................................. 297

13.3.2 Master Transmit Operation .................................................................................. 298

13.3.3 Master Receive Operation.................................................................................... 300

13.3.4 Slave Transmit Operation..................................................................................... 302

13.3.5 Slave Receive Operation...................................................................................... 304

13.3.6 IRIC Set Timing and SCL Control....................................................................... 305

13.3.7 Noise Canceler...................................................................................................... 306

13.3.8 Sample Flowcharts ............................................................................................... 307

13.4 Application Notes.............................................................................................................. 311

Section 14 Host Interface................................................................................................... 317

14.1 Overview............................................................................................................................ 317

14.1.1 Block Diagram...................................................................................................... 318

14.1.2 Input and Output Pins........................................................................................... 319

14.1.3 Register Configuration ......................................................................................... 320

14.2 Register Descriptions......................................................................................................... 321

14.2.1 System Control Register (SYSCR) ...................................................................... 321

14.2.2 Host Interface Control Register (HICR) .............................................................. 321

14.2.3 Input Data Register 1 (IDR1) ............................................................................... 322

14.2.4 Output Data Register 1 (ODR1)........................................................................... 323

14.2.5 Status Register 1 (STR1)...................................................................................... 323

14.2.6 Input Data Register 2 (IDR2) ............................................................................... 324

14.2.7 Output Data Register 2 (ODR2)........................................................................... 325

14.2.8 Status Register 2 (STR2)...................................................................................... 325

14.2.9 Serial/Timer Control Register (STCR) ................................................................ 327

14.3 Operation ........................................................................................................................... 328

14.3.1 Host Interface Operation...................................................................................... 328

14.3.2 Control States ....................................................................................................... 328

14.3.3 A20 Gate................................................................................................................ 329

14.4 Interrupts............................................................................................................................ 332

14.4.1 IBF1, IBF2............................................................................................................ 332

14.4.2 HIRQ11, HIRQ1, and HIRQ12................................................................................ 332

14.5 Application Note................................................................................................................ 333

viii

Section 15 A/D Converter ................................................................................................. 335

15.1 Overview............................................................................................................................ 335

15.1.1 Features ................................................................................................................ 335

15.1.2 Block Diagram...................................................................................................... 336

15.1.3 Input Pins.............................................................................................................. 337

15.1.4 Register Configuration ......................................................................................... 338

15.2 Register Descriptions......................................................................................................... 339

15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 339

15.2.2 A/D Control/Status Register (ADCSR)................................................................ 340

15.2.3 A/D Control Register (ADCR)............................................................................. 342

15.3 CPU Interface.................................................................................................................... 342

15.4 Operation ........................................................................................................................... 344

15.4.1 Single Mode (SCAN = 0)..................................................................................... 344

15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 346

15.4.3 Input Sampling and A/D Conversion Time.......................................................... 348

15.4.4 External Trigger Input Timing ............................................................................. 349

15.5 Interrupts............................................................................................................................ 350

15.6 Application Notes.............................................................................................................. 350

Section 16 D/A Converter ................................................................................................. 355

16.1 Overview............................................................................................................................ 355

16.1.1 Features ................................................................................................................ 355

16.1.2 Block Diagram...................................................................................................... 356

16.1.3 Input and Output Pins........................................................................................... 357

16.1.4 Register Configuration............................................................................................ 357

16.2 Register Descriptions......................................................................................................... 358

16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 358

16.2.2 D/A Control Register (DACR)............................................................................. 358

16.3 Operation ........................................................................................................................... 360

Section 17 RAM................................................................................................................... 361

17.1 Overview............................................................................................................................ 361

17.1.1 Block Diagram...................................................................................................... 361

17.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR)....................... 362

17.2 Operation ........................................................................................................................... 362

17.2.1 Expanded Modes (Modes 1 and 2)....................................................................... 362

17.2.2 Single-Chip Mode (Mode 3) ................................................................................ 362

Section 18 ROM (Mask ROM Version/ZTAT Version).......................................... 363

18.1 Overview............................................................................................................................ 363

18.1.1 Block Diagram...................................................................................................... 364

18.2 Writer Mode (H8/3437, H8/3434)..................................................................................... 364

18.2.1 Writer Mode Setup ............................................................................................... 364

18.2.2 Socket Adapter Pin Assignments and Memory Map ........................................... 365

18.3 PROM Programming......................................................................................................... 368

18.3.1 Programming and Verification............................................................................. 368

18.3.2 Notes on Programming......................................................................................... 373

18.3.3 Reliability of Programmed Data .......................................................................... 374

Section 19 ROM (32-kbyte Dual-Power-Supply Flash Memory Version)........ 375

19.1 Flash Memory Overview................................................................................................... 375

19.1.1 Flash Memory Operating Principle...................................................................... 375

19.1.2 Mode Programming and Flash Memory Address Space...................................... 376

19.1.3 Features ................................................................................................................ 376

19.1.4 Block Diagram...................................................................................................... 377

19.1.5 Input/Output Pins.................................................................................................. 378

19.1.6 Register Configuration ......................................................................................... 378

19.2 Flash Memory Register Descriptions................................................................................ 379

19.2.1 Flash Memory Control Register (FLMCR).......................................................... 379

19.2.2 Erase Block Register 1 (EBR1)............................................................................ 380

19.2.3 Erase Block Register 2 (EBR2)............................................................................ 381

19.2.4 Wait-State Control Register (WSCR) .................................................................. 382

19.3 On-Board Programming Modes ........................................................................................ 385

19.3.1 Boot Mode............................................................................................................ 386

19.3.2 User Programming Mode ..................................................................................... 392

19.4 Programming and Erasing Flash Memory......................................................................... 394

19.4.1 Program Mode...................................................................................................... 394

19.4.2 Program-Verify Mode.......................................................................................... 395

19.4.3 Programming Flowchart and Sample Program.................................................... 396

19.4.4 Erase Mode........................................................................................................... 398

19.4.5 Erase-Verify Mode............................................................................................... 398

19.4.6 Erasing Flowchart and Sample Program.............................................................. 399

19.4.7 Prewrite Verify Mode........................................................................................... 412

19.4.8 Protect Modes....................................................................................................... 412

19.4.9 Interrupt Handling during Flash Memory Programming and Erasing ................. 413

19.5 Flash Memory Emulation by RAM................................................................................... 415

19.6 Flash Memory Writer Mode (H8/3434F).......................................................................... 418

19.6.1 Writer Mode Setting............................................................................................. 418

19.6.2 Socket Adapter and Memory Map ....................................................................... 418

19.6.3 Operation in Writer Mode.................................................................................... 420

19.7 Flash Memory Programming and Erasing Precautions ..................................................... 428

Section 20 ROM (60-kbyte Dual-Power-Supply Flash Memory Version)........ 437

20.1 Flash Memory Overview................................................................................................... 437

20.1.1 Flash Memory Operating Principle...................................................................... 437

20.1.2 Mode Programming and Flash Memory Address Space...................................... 438

20.1.3 Features ................................................................................................................ 438

20.1.4 Block Diagram...................................................................................................... 439

20.1.5 Input/Output Pins.................................................................................................. 440

20.1.6 Register Configuration ......................................................................................... 440

20.2 Flash Memory Register Descriptions................................................................................ 441

20.2.1 Flash Memory Control Register (FLMCR).......................................................... 441

20.2.2 Erase Block Register 1 (EBR1)............................................................................ 442

20.2.3 Erase Block Register 2 (EBR2)............................................................................ 443

20.2.4 Wait-State Control Register (WSCR) .................................................................. 444

20.3 On-Board Programming Modes ........................................................................................ 447

20.3.1 Boot Mode............................................................................................................ 448

20.3.2 User Programming Mode ..................................................................................... 454

20.4 Programming and Erasing Flash Memory......................................................................... 456

20.4.1 Program Mode...................................................................................................... 456

20.4.2 Program-Verify Mode.......................................................................................... 457

20.4.3 Programming Flowchart and Sample Program.................................................... 458

20.4.4 Erase Mode........................................................................................................... 460

20.4.5 Erase-Verify Mode............................................................................................... 460

20.4.6 Erasing Flowchart and Sample Program.............................................................. 461

20.4.7 Prewrite Verify Mode........................................................................................... 474

20.4.8 Protect Modes....................................................................................................... 474

20.4.9 Interrupt Handling during Flash Memory Programming and Erasing ................. 475

20.5 Flash Memory Emulation by RAM................................................................................... 477

20.6 Flash Memory Writer Mode (H8/3437F).......................................................................... 480

20.6.1 Writer Mode Setting............................................................................................. 480

20.6.2 Socket Adapter and Memory Map ....................................................................... 480

20.6.3 Operation in Writer Mode.................................................................................... 482

20.7 Flash Memory Programming and Erasing Precautions ..................................................... 490

Section 21 ROM (60-kbyte Single-Power-Supply Flash Memory Version) ..... 499

21.1 Flash Memory Overview................................................................................................... 499

21.1.1 Mode Pin Settings and ROM Space..................................................................... 499

21.1.2 Features ................................................................................................................ 500

21.1.3 Block Diagram...................................................................................................... 501

21.1.4 Input/Output Pins.................................................................................................. 502

21.1.5 Register Configuration ......................................................................................... 502

21.1.6 Mode Control Register (MDCR).......................................................................... 503

21.1.7 Flash Memory Operating Modes.......................................................................... 504

21.2 Flash Memory Register Descriptions................................................................................ 508

21.2.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 508

21.2.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 510

21.2.3 Erase Block Register 2 (EBR2)............................................................................ 511

21.2.4 Wait-State Control Register (WSCR) .................................................................. 512

21.3 On-Board Programming Modes ........................................................................................ 513

21.3.1 Boot Mode............................................................................................................ 513

21.3.2 User Programming Mode ..................................................................................... 519

21.4 Programming/Erasing Flash Memory................................................................................ 520

21.4.1 Program Mode...................................................................................................... 520

21.4.2 Program-Verify Mode.......................................................................................... 521

21.4.3 Erase Mode........................................................................................................... 523

21.4.4 Erase-Verify Mode............................................................................................... 523

21.4.5 Protect Modes....................................................................................................... 525

21.4.6 Interrupt Handling during Flash Memory Programming and Erasing ................. 527

21.5 Flash Memory Writer Mode (H8/3437SF)........................................................................ 528

21.5.1 Writer Mode Setting............................................................................................. 528

21.5.2 Socket Adapter and Memory Map ....................................................................... 528

21.5.3 Operation in Writer Mode.................................................................................... 529

21.6 Flash Memory Programming and Erasing Precautions ..................................................... 540

Section 22 Power-Down State.......................................................................................... 543

22.1 Overview............................................................................................................................ 543

22.1.1 System Control Register (SYSCR) ...................................................................... 544

22.2 Sleep Mode........................................................................................................................ 546

22.2.1 Transition to Sleep Mode ..................................................................................... 546

22.2.2 Exit from Sleep Mode .......................................................................................... 546

22.3 Software Standby Mode .................................................................................................... 547

22.3.1 Transition to Software Standby Mode.................................................................. 547

22.3.2 Exit from Software Standby Mode....................................................................... 547

22.3.3 Clock Settling Time for Exit from Software Standby Mode................................ 548

22.3.4 Sample Application of Software Standby Mode.................................................. 549

22.3.5 Application Note .................................................................................................. 550

22.4 Hardware Standby Mode................................................................................................... 551

22.4.1 Transition to Hardware Standby Mode................................................................ 551

22.4.2 Recovery from Hardware Standby Mode............................................................. 551

22.4.3 Timing Relationships............................................................................................ 552

Section 23 Electrical Specifications............................................................................... 553

23.1 Absolute Maximum Ratings.............................................................................................. 553

23.2 Electrical Characteristics................................................................................................... 554

23.2.1 DC Characteristics................................................................................................ 554

23.2.2 AC Characteristics................................................................................................ 567

23.2.3 A/D Converter Characteristics ............................................................................. 575

23.2.4 D/A Converter Characteristics ............................................................................. 576

23.2.5 Flash Memory Characteristics (H8/3437SF Only)............................................... 577

23.3 Absolute Maximum Ratings (H8/3437SF Low-Voltage Version).................................... 579

23.4 Electrical Characteristics (H8/3437SF Low-Voltage Version)......................................... 580

xii

23.4.1 DC Characteristics................................................................................................ 580

23.4.2 AC Characteristics................................................................................................ 585

23.4.3 A/D Converter Characteristics ............................................................................. 591

23.4.4 D/A Converter Characteristics ............................................................................. 592

23.4.5 Flash Memory Characteristics.............................................................................. 593

23.5 MCU Operational Timing.................................................................................................. 595

23.5.1 Bus Timing........................................................................................................... 595

23.5.2 Control Signal Timing.......................................................................................... 596

23.5.3 16-Bit Free-Running Timer Timing..................................................................... 598

23.5.4 8-Bit Timer Timing.............................................................................................. 599

23.5.5 Pulse Width Modulation Timer Timing............................................................... 600

23.5.6 Serial Communication Interface Timing.............................................................. 601

23.5.7 I/O Port Timing.................................................................................................... 602

23.5.8 Host Interface Timing .......................................................................................... 602

23.5.9 I2C Bus Timing (Option)...................................................................................... 603

23.5.10 Reset Output Timing............................................................................................ 604

23.5.11 External Clock Output Timing............................................................................. 604

Appendix A CPU Instruction Set ................................................................................... 605

A.1 Instruction Set List ............................................................................................................ 605

A.2 Operation Code Map.......................................................................................................... 613

A.3 Number of States Required for Execution......................................................................... 615

Appendix B Internal I/O Register.................................................................................. 621

B.1 Addresses........................................................................................................................... 621

B.2 Function............................................................................................................................. 626

Appendix C I/O Port Block Diagrams.......................................................................... 684

C.1 Port 1 Block Diagram........................................................................................................ 684

C.2 Port 2 Block Diagram........................................................................................................ 685

C.3 Port 3 Block Diagram........................................................................................................ 686

C.4 Port 4 Block Diagrams ...................................................................................................... 687

C.5 Port 5 Block Diagrams ...................................................................................................... 691

C.6 Port 6 Block Diagrams ...................................................................................................... 694

C.7 Port 7 Block Diagrams ...................................................................................................... 698

C.8 Port 8 Block Diagrams ...................................................................................................... 699

C.9 Port 9 Block Diagrams ...................................................................................................... 705

C.10 Port A Block Diagram....................................................................................................... 711

C.11 Port B Block Diagram ....................................................................................................... 712

Appendix D Port States in Each Processing State..................................................... 713

xiii

Appendix E Timing of Transition to and Recovery

from Hardware Standby Mode............................................................... 715

Appendix F Option Lists.................................................................................................. 716

Appendix G Product Code Lineup................................................................................. 718

Appendix H Package Dimensions.................................................................................. 720

xiv

Section 1 Overview

1.1 Overview

The H8/3437 Series of single-chip microcomputers features an H8/300 CPU core and a

complement of on-chip supporting modules implementing a variety of system functions.

The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-

manipulation instructions, ideally suited for realtime control applications. The on-chip supporting

modules implement peripheral functions needed in system configurations. These include ROM,

RAM, four types of timers (a 16-bit free-running timer, 8-bit timers, PWM timers, and a watchdog

timer), a serial communication interface (SCI), an I2C bus interface [option], a host interface

(HIF), an A/D converter, a D/A converter, and I/O ports.

The H8/3437 Series can operate in single-chip mode or in two expanded modes, depending on the

requirements of the application.

Besides the mask-ROM versions of the H8/3437 Series, there are ZTAT™*1 versions with on-chip

PROM, and an F-ZTAT™*2 version with on-chip flash memory. The F-ZTAT™ version can be

programmed or reprogrammed on-board in application systems.

Notes: *1 ZTAT™ (zero turn-around time) is a trademark of Hitachi, Ltd.

*2 F-ZTAT™ (flexible-ZTAT) is a trademark of Hitachi, Ltd.

The guaranteed voltage range is different for the F-ZTAT LH version.

LH Version General Version

VCC

AVCC

3.0 V to 5.5 V 2.7 V to 5.5 V

Table 1.1 lists the features of the H8/3437 Series.

Table 1.1 Features

Item Specification

CPU Two-way general register configuration

• Eight 16-bit registers, or

• Sixteen 8-bit registers

High-speed operation

• Maximum clock rate (ø clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz

at 3 V

• 8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns

(12 MHz), 200 ns (10 MHz)

• 8 × 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)

• 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)

Streamlined, concise instruction set

• Instruction length: 2 or 4 bytes

• Register-register arithmetic and logic operations

• MOV instruction for data transfer between registers and memory

Instruction set features

• Multiply instruction (8 bits × 8 bits)

• Divide instruction (16 bits ÷ 8 bits)

• Bit-accumulator instructions

• Register-indirect specification of bit positions

Memory • H8/3437: 60-kbyte ROM; 2-kbyte RAM

• H8/3436: 48-kbyte ROM; 2-kbyte RAM

• H8/3434: 32-kbyte ROM; 1-kbyte RAM

16-bit free-running

timer (1 channel) • One 16-bit free-running counter (can also count external events)

• Two output-compare lines

• Four input capture lines (can be buffered)

8-bit timer

(2 channels) Each channel has

• One 8-bit up-counter (can also count external events)

• Two time constant registers

PWM timer

(2 channels) • Duty cycle can be set from 0 to 100%

• Resolution: 1/250

Watchdog timer

(WDT) (1 channel) • Overflow can generate a reset or NMI interrupt

• Also usable as interval timer

Item Specification

Serial communication

interface (SCI)

(2 channels)

• Asynchronous or synchronous mode (selectable)

• Full duplex: can transmit and receive simultaneously

• On-chip baud rate generator

I2C bus interface

(1 channel) [option] • Conforms to Philips I2C bus interface

• Includes single master mode and slave mode

Host interface (HIF) • 8-bit host interface port

• Three host interrupt requests (HIRQ1, HIRQ11, HIRQ12)

• Regular and fast A20 gate output

• Two register sets, each with two data registers and a status register

Keyboard controller • Controls a matrix-scan keyboard by providing a keyboard scan function

with wake-up interrupts and sense ports

A/D converter • 10-bit resolution

• Eight channels: single or scan mode (selectable)

• Start of A/D conversion can be externally triggered

• Sample-and-hold function

D/A converter • 8-bit resolution

• Two channels

I/O ports • 74 input/output lines (16 of which can drive LEDs)

• 8 input-only lines

Interrupts • Nine external interrupt lines: NMI, IRQ0 to IRQ7

• 26 on-chip interrupt sources

Wait control • Three selectable wait modes

Operating modes • Expanded mode with on-chip ROM disabled (mode 1)

• Expanded mode with on-chip ROM disabled (mode 1)

• Single-chip mode (mode 3)

Power-down modes • Sleep mode

• Software standby mode

• Hardware standby mode

Other features • On-chip clock pulse generator

Item Specification

Series lineup Part Number

Product

Name 5-V Version (16 MHz)

4-V Version (12 MHz) 3-V Version (10 MHz) Package ROM

H8/3437 HD64F3437F16 HD64F3437F16 100-pin QFP Flash memory

F-ZTAT HD64F3437FLH16 HD64F3437FLH16 (FP-100B) (dual-power-

HD64F3437TF16 HD64F3437TF16 100-pin TQFP supply product)

HD64F3437TFLH16 HD64F3437TFLH16 (TFP-100B)

HD64F3437SF16 HD64F3437SF16 100-pin QFP

(FP-100B) Flash memory

(single-power-

HD64F3437STF16 HD64F3437STF16 100-pin TQFP

(TFP-100B)

supply product)

H8/3437

ZTAT HD6473437F16 HD6473437F16 100-pin QFP

(FP-100B) PROM

HD6473437TF16 HD6473437TF16 100-pin TQFP

(TFP-100B)

H8/3437 HD6433437F16

HD6433437F12 HD6433437VF10 100-pin QFP

(FP-100B) Mask ROM

HD6433437TF16

HD6433437TF12 HD6433437VTF10 100-pin TQFP

(TFP-100B)

H8/3436 HD6433436F16

HD6433436F12 HD6433436VF10 100-pin QFP

(FP-100B) Mask ROM

HD6433436TF16

HD6433436TF12 HD6433436VTF10 100-pin TQFP

(TFP-100B)

H8/3434 HD64F3434F16 HD64F3434F16 100-pin QFP Flash memory

F-ZTAT HD64F3434FLH16 HD64F3434FLH16 (FP-100B) (dual-power-

HD64F3434TF16 HD64F3434TF16 100-pin TQFP supply product)

HD64F3434TFLH16 HD64F3434TFLH16 (TFP-100B)

H8/3434

ZTAT HD6473434F16 HD6473434F16 100-pin QFP

(FP-100B) PROM

HD6473434TF16 HD6473434TF16 100-pin TQFP

(TFP-100B)

H8/3434 HD6433434F16

HD6433434F12 HD6433434VF10 100-pin QFP

(FP-100B) Mask ROM

HD6433434TF16

HD6433434TF12 HD6433434VTF10 100-pin TQFP

(TFP-100B)

The I2C bus interface is an available option. Please note the following points regarding this option.

In mask ROM versions, chips featuring the I2C bus interface include a W in the part number.

Example: HD6433437WTF, HD6433434WF, etc.

1.2 Block Diagram

Figure 1.1 shows a block diagram of the H8/3437 Series.

PB0/XDB0

PB1/XDB1

PB2/XDB2

PB3/XDB3

PB4/XDB4

PB5/XDB5

PB6/XDB6

PB7/XDB7

P90/ADTRG/ECS2/IRQ2

P91/IRQ1/EIOW

P92/IRQ0

P93/RD

P94/WR

P95/AS

P96/ø

P97/WAIT/SDA

P30/D0/HDB0

P31/D1/HDB1

P32/D2/HDB2

P33/D3/HDB3

P34/D4/HDB4

P35/D5/HDB5

P36/D6/HDB6

P37/D7/HDB7

P80/HA0

P81/GA20

P82/CS1

P83/IOR

P84/TxD1/IRQ3/IOW

P85/RxD1/IRQ4/CS2

P86/SCK1/IRQ5/SCL

PA0/KEYIN8

PA1/KEYIN9

PA2/KEYIN10

PA3/KEYIN11

PA4/KEYIN12

PA5/KEYIN13

PA6/KEYIN14

PA7/KEYIN15

P10/A0

P11/A1

P12/A2

P13/A3

P14/A4

P15/A5

P16/A6

P17/A7

P20/A8

P21/A9

P22/A10

P23/A11

P24/A12

P25/A13

P26/A14

P27/A15

KEYIN0/P60/FTCI

KEYIN1/P61/FTOA

KEYIN2/P62/FTIA

KEYIN3/P63/FTIB

KEYIN4/P64/FTIC

KEYIN5/P65/FTID

KEYIN6/P66/FTOB/IRQ6

KEYIN7/P67/IRQ7

P40/TMCI0

P41/TMO0

P42/TMRI0

HIRQ11/P43/TMCI1

HIRQ1/P44/TMO1

HIRQ12/P45/TMRI1

P46/PW0

P47/PW1

P77/AN7/DA1

P76/AN6/DA0

P75/AN5

P74/AN4

P73/AN3

P72/AN2

P71/AN1

P70/AN0

P50/TxD0

P51/RxD0

P52/SCK0

AVref

AVCC

AVSS

RESO

RES

STBY

NMI

MD0

MD1

VCCB

VCC

VSS

XTAL

EXTA

Port 6 Port 2 Port 1 Port A

Data bus (low)

RAM

H8/3437: 2 kbytes

H8/3436: 2 kbytes

H8/3434: 1 kbyte

10-bit

A/D converter

(8 channels)

8-bit

D/A converter

(2 channels)

16-bit

free-running

timer

8-bit timer

(2 channels)

PWM timer

(2 channels)

Clock pulse

generator

H8/3437

60 kbytes

2 kbytes

H8/3436

48 kbytes

2 kbytes

H8/3434

32 kbytes

1 kbyte

Memory Sizes

ROM

RAM

ROM

(flash memory,

PROM, or

mask ROM)

H8/3437: 60 kbytes

H8/3436: 48 kbytes

H8/3434: 32 kbytes

Watchdog

timer Host

interface

Serial

communication

interface (2 channels)

I2C bus interface

(1 channel) [option]

Port 4 Port 7 Port 5

Port 8 Port 3 Port 9 Port B

CPU

H8/300

Data bus (high)

Address bus

Figure 1.1 Block Diagram

1.3 Pin Assignments and Functions

1.3.1 Pin Arrangement

Figure 1.2 shows the pin arrangement of the FP-100B and TFP-100B packages.

P14/A4

P15/A5

P16/A6

P17/A7

VSS

PB4/XDB4

PB5/XDB5

P20/A8

P21/A9

P22/A10

P23/A11

P24/A12

P25/A13

P26/A14

P27/A15

VCC

PB6/XDB6

PB7/XDB7

P47/PW1

P46/PW0

P45/TMRI1/HIRQ12

P44/TMO1/HIRQ1

P43/TMCI1/HIRQ11

P42/TMRI0

P41/TMO0

P40/TMCI0

PA0/KEYIN8

PA1/KEYIN9

AVSS

P77/AN7/DA1

P76/AN6/DA0

P75/AN5

P74/AN4

P73/AN3

P72/AN2

P71/AN1

P70/AN0

AVCC

AVref

P67/KEYIN7/IRQ7

P66/KEYIN6/IRQ6/FTOB

P65/KEYIN5/FTID

P64/KEYIN4/FTIC

PA2/KEYIN10

PA3/KEYIN11

P63/KEYIN3/FTIB

P62/KEYIN2/FTIA

P61/KEYIN1/FTOA

P60/KEYIN0/FTCI

A3/P13

A2/P12

A1/P11

A0/P10

XDB3/PB3

XDB2/PB2

D0/HDB0/P30

D1/HDB1/P31

D2/HDB2/P32

D3/HDB3/P33

D4/HDB4/P34

D5/HDB5/P35

D6/HDB6/P36

D7/HDB7/P37

XDB1/PB1

XDB0/PB0

VSS

HA0/P80

GA20/P81

CS1/P82

IOR/P83

IOW/TxD1/IRQ3/P84

CS2/RxD1/IRQ4/P85

SCL/SCK1/IRQ5/P86

RESO

RES

XTAL

EXTAL

VCCB

MD1

MD0

NMI

FVPP*/STBY

VCC

KEYIN15/PA7

KEYIN14/PA6

SCK0/P52

RxD0/P51

TxD0/P50

VSS

SDA/WAIT/P97

ø/P96

AS/P95

WR/P94

KEYIN13/PA5

KEYIN12/PA4

RD/P93

IRQ0/P92

EIOW/IRQ1/P91

ADTRG/ECS2/IRQ2/P90

100

FP-100B, TFP-100B

(top view)

Note: * In the S-mask model (single-power-supply model), pin 8 functions only as the STBY pin.

Figure 1.2 Pin Arrangement (FP-100B, TFP-100B, Top View)

1.3.2 Pin Functions

Pin Assignments in Each Operating Mode: Table 1.2 lists the assignments of the pins of the

FP-100B and TFP-100B packages in each operating mode.

Table 1.2 Pin Assignments in Each Operating Mode

Pin No. Expanded Modes Single-Chip Mode EPROM Flash

Memory

FP-100B, Mode 3 Writer Writer

TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode

1RES RES RES RES VPP RES

2 XTAL XTAL XTAL XTAL NC XTAL

3 EXTAL EXTAL EXTAL EXTAL NC EXTAL

CCBV

CC VCC

5MD

1MD1MD1MD1VSS VSS

6MD

0MD0MD0MD0VSS VSS

7NMI NMI NMI NMI EA9FA9

8STBY STBY/FVPP STBY/FVPP STBY/FVPP VSS FVPP

CC VCC VCC VCC VCC VCC

10 PA7/KEYIN15 PA7/KEYIN15 PA7/KEYIN15 PA7/KEYIN15 NC NC

11 PA6/KEYIN14 PA6/KEYIN14 PA6/KEYIN14 PA6/KEYIN14 NC NC

12 P52/SCK0P52/SCK0P52/SCK0P52/SCK0NC NC

13 P51/RxD0P51/RxD0P51/RxD0P51/RxD0NC NC

14 P50/TxD0P50/TxD0P50/TxD0P50/TxD0NC NC

15 VSS VSS VSS VSS VSS VSS

16 P97/WAIT/SDA P97/WAIT/SDA P97/SDA P97/SDA NC VCC

17 øø P96/øP96/øNC NC

18 AS AS P95P95NC FA16

19 WR WR P94P94NC FA15

20 PA5/KEYIN13 PA5/KEYIN13 PA5/KEYIN13 PA5/KEYIN13 NC NC

21 PA4/KEYIN12 PA4/KEYIN12 PA4/KEYIN12 PA4/KEYIN12 NC NC

22 RD RD P93P93NC WE

23 P92/IRQ0P92/IRQ0P92/IRQ0P92/IRQ0PGM VSS

Pin No. Expanded Modes Single-Chip Mode EPROM Flash

Memory

FP-100B, Mode 3 Writer Writer

TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode

24 P91/IRQ1 when HIF is disabled or STAC bit is 0 in STCR;

EIOW/IRQ1 when HIF is enabled and STAC bit is 1 in STCR EA15 VCC

25 P90/IRQ2/ADTRG when HIF is disabled or STAC bit is 0 in

STCR; ECS2/IRQ2 when HIF is enabled and STAC bit is 1 in

STCR

EA16 VCC

26 P60/FTCI/

KEYIN0

P60/FTCI/

KEYIN0

P60/FTCI/

KEYIN0

P60/FTCI/

KEYIN0

NC NC

27 P61/FTOA/

KEYIN1

P61/FTOA/

KEYIN1

P61/FTOA/

KEYIN1

P61/FTOA/

KEYIN1

NC NC

28 P62/FTIA/

KEYIN2

P62/FTIA/

KEYIN2

P62/FTIA/

KEYIN2

P62/FTIA/

KEYIN2

NC NC

29 P63/FTIB/

KEYIN3

P63/FTIB/

KEYIN3

P63/FTIB/

KEYIN3

P63/FTIB/

KEYIN3

VCC VCC

30 PA3/KEYIN11 PA3/KEYIN11 PA3/KEYIN11 PA3/KEYIN11 NC NC

31 PA2/KEYIN10 PA2/KEYIN10 PA2/KEYIN10 PA2/KEYIN10 NC NC

32 P64/FTIC/

KEYIN4

P64/FTIC/

KEYIN4

P64/FTIC/

KEYIN4

P64/FTIC/

KEYIN4

VCC VCC

33 P65/FTID/

KEYIN5

P65/FTID/

KEYIN5

P65/FTID/

KEYIN5

P65/FTID/

KEYIN5

NC NC

34 P66/FTOB/

IRQ6/KEYIN6

P66/FTOB/

IRQ6/KEYIN6

P66/FTOB/

IRQ6/KEYIN6

P66/FTOB/

IRQ6/KEYIN6

NC NC

35 P67/IRQ7/

KEYIN7

P67/IRQ7/

KEYIN7

P67/IRQ7/

KEYIN7

P67/IRQ7/

KEYIN7

NC VSS

36 AVref AVref AVref AVref VCC VSS

37 AVCC AVCC AVCC AVCC VCC VCC

38 P70/AN0P70/AN0P70/AN0P70/AN0NC NC

39 P71/AN1P71/AN1P71/AN1P71/AN1NC NC

40 P72/AN2P72/AN2P72/AN2P72/AN2NC NC

41 P73/AN3P73/AN3P73/AN3P73/AN3NC NC

42 P74/AN4P74/AN4P74/AN4P74/AN4NC NC

43 P75/AN5P75/AN5P75/AN5P75/AN5NC NC

44 P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0NC NC

Pin No. Expanded Modes Single-Chip Mode EPROM Flash

Memory

FP-100B, Mode 3 Writer Writer

TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode

45 P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1NC NC

46 AVSS AVSS AVSS AVSS VSS VSS

47 PA1/KEYIN9PA1/KEYIN9PA1/KEYIN9PA1/KEYIN9NC NC

48 PA0/KEYIN8PA0/KEYIN8PA0/KEYIN8PA0/KEYIN8NC NC

49 P40/TMCI0P40/TMCI0P40/TMCI0P40/TMCI0NC NC

50 P41/TMO0P41/TMO0P41/TMO0P41/TMO0NC NC

51 P42/TMRI0P42/TMRI0P42/TMRI0P42/TMRI0NC NC

52 P43/TMCI1/

HIRQ11*1P43/TMCI1/

HIRQ11*1P43/TMCI1HIRQ11/TMCI1NC NC

53 P44/TMO1/

HIRQ1*1P44/TMO1/

HIRQ1*1P44/TMO1HIRQ1/TMO1NC NC

54 P45/TMRI1/

HIRQ12*1P45/TMRI1/

HIRQ12*1P45/TMRI1HIRQ12/TMRI1NC NC

55 P46/PW0P46/PW0P46/PW0P46/PW0NC NC

56 P47/PW1P47/PW1P47/PW1P47/PW1NC NC

57 PB7/XDB7*2PB7/XDB7*2PB7PB7NC NC

58 PB6/XDB6*2PB6/XDB6*2PB6PB6NC NC

59 VCC VCC VCC VCC VCC VCC

60 A15 P27/A15 P27P27CE CE

61 A14 P26/A14 P26P26EA14 FA14

62 A13 P25/A13 P25P25EA13 FA13

63 A12 P24/A12 P24P24EA12 FA12

64 A11 P23/A11 P23P23EA11 FA11

65 A10 P22/A10 P22P22EA10 FA10

66 A9P21/A9P21P21OE OE

67 A8P20/A8P20P20EA8FA8

68 PB5/XDB5*2PB5/XDB5*2PB5PB5NC NC

69 PB4/XDB4*2PB4/XDB4*2PB4PB4NC NC

70 VSS VSS VSS VSS VSS VSS

Pin No. Expanded Modes Single-Chip Mode EPROM Flash

Memory

FP-100B, Mode 3 Writer Writer

TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode

71 VSS VSS VSS VSS VSS VSS

72 A7P17/A7P17P17EA7FA7

73 A6P16/A6P16P16EA6FA6

74 A5P15/A5P15P15EA5FA5

75 A4P14/A4P14P14EA4FA4

76 A3P13/A3P13P13EA3FA3

77 A2P12/A2P12P12EA2FA2

78 A1P11/A1P11P11EA1FA1

79 A0P10/A0P10P10EA0FA0

80 PB3/XDB3*2PB3/XDB3*2PB3PB3NC NC

81 PB2/XDB2*2PB2/XDB2*2PB2PB2NC NC

82 D0D0P30HDB0EO0FO0

83 D1D1P31HDB1EO1FO1

84 D2D2P32HDB2EO2FO2

85 D3D3P33HDB3EO3FO3

86 D4D4P34HDB4EO4FO4

87 D5D5P35HDB5EO5FO5

88 D6D6P36HDB6EO6FO6

89 D7D7P37HDB7EO7FO7

90 PB1/XDB1*2PB1/XDB1*2PB1PB1NC NC

91 PB0/XDB0*2PB0/XDB0*2PB0PB0NC NC

92 VSS VSS VSS VSS VSS VSS

93 P80/HA0*1P80/HA0*1P80HA0NC NC

94 P81/GA20*1P81/GA20*1P81P81/GA20 NC NC

95 P82/CS1*1P82/CS1*1P82CS1NC NC

96 P83/IOR*1P83/IOR*1P83IOR NC NC

Pin No. Expanded Modes Single-Chip Mode EPROM Flash

Memory

FP-100B, Mode 3 Writer Writer

TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode

97 P84/IRQ3/TxD1 when HIF is disabled or STAC bit is 1 in STCR;

IOW/IRQ3 when HIF is enabled and STAC bit is 0 in STCR NC NC

98 P85/IRQ4/RxD1 when HIF is disabled or STAC bit is 1 in STCR;

CS2/IRQ4 when HIF is enabled and STAC bit is 0 in STCR NC NC

99 P86/SCK1/

IRQ5/SCL P86/SCK1/

IRQ5/SCL NC NC

100 RESO RESO RESO RESO NC NC

Note: Pins marked NC should be left unconnected.

For details on writer mode, refer to 18.2, Writer Mode, 19.6, Flash Memory Writer Mode

(H8/3434F), 20.6, Flash Memory Writer Mode (H8/3437F) and 21.5, Flash Memory Writer

Mode (H8/3437SF).

In this chip, except for the S-mask model (single-power-supply specification), the same pin

is used for STBY and FVPP. When this pin is driven low, a transition is made to hardware

standby mode. This occurs not only in the normal operating modes (modes 1, 2, and 3), but

also when programming flash memory with a PROM writer. When using a PROM

programmer to program dual-power-supply flash memory, therefore, the PROM

programmer specifications should provide for this pin to be held at the VCC level except

when programming (FVPP = 12 V).

*1 Differs as in mode 3, depending on whether the host interface is enabled or disabled.

*2 XDB7 to XDB6 can only be used when the host interface is enabled.

Pin Functions: Table 1.3 gives a concise description of the function of each pin.

Table 1.3 Pin Functions

Pin No.

Type Symbol FP-100B,

TFP-100B I/O Name and Function

Power VCC 9, 59 I Power: Connected to the power supply.

Connect both VCC pins to the system power

supply.

VCCB4 II/O buffer power supply: Power supply for

input/output buffers at pins P86, P97, and

PA4 to PA7.

VSS 15, 70, 71,

92 IGround: Connected to ground (0 V).

Connect all VSS pins to system ground (0 V).

Clock XTAL 2 I Crystal: Connected to a crystal oscillator.

The crystal frequency should be the same

as the desired system clock frequency. If an

external clock is input at the EXTAL pin, a

reverse-phase clock should be input at the

XTAL pin.

EXTAL 3 I External crystal: Connected to a crystal

oscillator or external clock. The frequency of

the external clock should be the same as

the desired system clock frequency. See

section 6.2, Oscillator Circuit, for examples

of connections to a crystal and external

clock.

ø17 O System clock: Supplies the system clock to

peripheral devices.

System control RES 1IReset: A low input causes the chip to reset.

RESO 100 O Reset output: Outputs a reset signal to

external devices.

STBY 8IStandby: A transition to the hardware

standby mode (a power-down state) occurs

when a low input is received at the STBY

pin.

Address bus A15 to A060 to 67,

72 to 79 OAddress bus: Address output pins.

Data bus D7 to D089 to 82 I/O Data bus: 8-bit bidirectional data bus.

Pin No.

Type Symbol FP-100B,

TFP-100B I/O Name and Function

Bus control WAIT 16 I Wait: Requests the CPU to insert wait

states into the bus cycle when an external

address is accessed.

RD 22 O Read: Goes low to indicate that the CPU is

reading an external address.

WR 19 O Write: Goes low to indicate that the CPU is

writing to an external address.

AS 18 O Address strobe: Goes low to indicate that

there is a valid address on the address bus.

Interrupt signals NMI 7INonmaskable interrupt: Highest-priority

interrupt request. The NMIEG bit in the

system control register (SYSCR) determines

whether the interrupt is recognized at the

rising or falling edge of the NMI input.

IRQ0 to

IRQ7

23 to 25,

97 to 99,

34, 35

IInterrupt request 0 to 7: Maskable interrupt

request pins.

Operating mode

control MD1

MD0

6IMode: Input pins for setting the MCU mode

operating mode according to the table

below.

MD1MD0Mode Description

0 0 Mode 0 Illegal setting*

0 1 Mode 1 Expanded mode

with on-chip ROM

disabled

1 0 Mode 2 Expanded mode

with on-chip ROM

enabled

1 1 Mode 3 Single-chip mode

Note: *In the H8/3437SF (S-mask model,

single-power-supply on-chip flash

memory version), the settings MD1 =

MD0 = 0 are used when boot mode is

set. For details, see section 21.3,

On-Board Programming Modes.

Do not change the mode pin settings while

the chip is operating.

Pin No.

Type Symbol FP-100B,

TFP-100B I/O Name and Function

16-bit free-

running timer

(FRT)

FTOA

FTOB 27

34 OFRT output compare A and B: Output pins

controlled by comparators A and B of the

free-running timer.

FTCI 26 I FRT counter clock input: Input pin for an

external clock signal for the free-running

timer.

FTIA to

FTID 28, 29, 32,

33 IFRT input capture A to D: Input capture

pins for the free-running timer.

8-bit timer TMO0

TMO1

53 O8-bit timer output (channels 0 and 1):

Compare-match output pins for the 8-bit

timers.

TMCI0

TMCI1

52 I8-bit timer counter clock input (channels

0 and 1): External clock input pins for the 8-

bit timer counters.

TMRI0

TMRI1

54 I8-bit timer counter reset input (channels

0 and 1): A high input at these pins resets

the 8-bit timer counters.

PWM timer PW0

PW1

56 OPWM timer output (channels 0 and 1):

Pulse-width modulation timer output pins.

Serial communi-

cation interface

(SCI)

TxD0

TxD1

97 OTransmit data (channels 0 and 1): Data

output pins for the serial communication

interface.

RxD0

RxD1

98 IReceive data (channels 0 and 1): Data

input pins for the serial communication

interface.

SCK0

SCK1

99 I/O Serial clock (channels 0 and 1):

Input/output pins for the serial clock.

Host interface

(HIF) HDB0 to

HDB7

82 to 89 I/O Host interface data bus: 8-bit bidirectional

bus by which a host processor accesses the

host interface.

CS1, CS295, 98 I Chip select 1 and 2: Input pins for selecting

host interface channels 1 and 2.

IOR 96 I I/O read: Read strobe input pin for the host

interface.

IOW 97 I I/O write: Write strobe input pin for the host

interface.

Pin No.

Type Symbol FP-100B,

TFP-100B I/O Name and Function

Host interface

(HIF) HA093 I Command/data: Input pin indicating data

access or command access.

GA20 94 O Gate A20: A20 gate control signal output pin.

HIRQ1

HIRQ11

HIRQ12

OHost interrupts 1, 11, and 12: Output pins

for interrupt request signals to the host

processor.

Keyboard control KEYIN0 to

KEYIN15

26 to 29,

32 to 35,

48, 47,

31, 30,

21, 20,

11, 10

IKeyboard input: Input pins from a matrix

keyboard. (Keyboard scan signals are

normally output from P10 to P17 and P20 to

P27, allowing a maximum 16 × 16 key

matrix. The number of keys can be further

increased by use of other output ports.)

Host interface

(expanded

modes)

XDB0 to

XDB7

91, 90, 81,

80, 69, 68,

58, 57

I/O Host interface data bus: 8-bit bidirectional

bus by which a host processor accesses the

host interface.

Host interface

(if enabled when ECS225 I Host chip select 2: Input pin for selecting

host interface channel 2.

STAC bit is 1 in

STCR) EIOW 24 I I/O write: Write strobe input pin for the host

interface.

A/D converter AN7 to

AN0

38 to 45 I Analog input: Analog signal input pins for

the A/D converter.

ADTRG 25 I A/D trigger: External trigger input for

starting the A/D converter.

D/A converter DA0

DA1

45 OAnalog output: Analog signal output pins

for the D/A converter.

A/D and D/A

converters AVCC 37 I Analog reference voltage: Reference

voltage pin for the A/D and D/A converters.

If the A/D and D/A converters are not used,

connect AVCC to the system power supply.

AVSS 46 I Analog ground: Ground pin for the A/D and

D/A converters. Connect to system ground

(0 V).

AVref 36 I Analog reference voltage: Analog

reference voltage input pins for A/D and D/A

converters.

Pin No.

Type Symbol FP-100B,

TFP-100B I/O Name and Function

Flash memory

[H8/3434,

H8/3437 F-ZTAT]

FVPP 8IProgramming power supply for on-board

programming: Connect to a flash memory

programming power supply (+12 V)

I2C bus interface

[option] SCL 99 I/O I2C clock I/O: Input/output pin for I2C clock.

Power is supplied by I/O buffer power

supply VCCB. Features a bus drive function.

SDA 16 I/O I2C data I/O: Input/output pin for I2C data.

Power is supplied by I/O buffer power

supply VCCB. Features a bus drive function.

I/O ports P17 to P1072 to 79 I/O Port 1: An 8-bit input/output port with

programmable MOS input pull-ups and LED

driving capability. The direction of each bit

can be selected in the port 1 data direction

P27 to P2060 to 67 I/O Port 2: An 8-bit input/output port with

programmable MOS input pull-ups and LED

driving capability. The direction of each bit

can be selected in the port 2 data direction

P37 to P3089 to 82 I/O Port 3: An 8-bit input/output port with

programmable MOS input pull-ups. The

direction of each bit can be selected in the

port 3 data direction register (P3DDR).

P47 to P4056 to 49 I/O Port 4: An 8-bit input/output port. The

direction of each bit can be selected in the

port 4 data direction register (P4DDR).

P52 to P5012 to 14 I/O Port 5: A 3-bit input/output port. The

direction of each bit can be selected in the

port 5 data direction register (P5DDR).

P67 to P6035 to 32,

29 to 26 I/O Port 6: An 8-bit input/output port with

programming MOS input pull-ups. The

direction of each bit can be selected in the

port 6 data direction register (P6DDR).

P77 to P7045 to 38 I Port 7: An 8-bit input port.

P86 to P8099 to 93 I/O Port 8: A 7-bit input/output port. The

direction of each bit can be selected in the

port 8 data direction register (P8DDR). P86

is powered by I/O buffer power supply VCCB.

Pin No.

Type Symbol FP-100B,

TFP-100B I/O Name and Function

I/O ports P97 to P9016 to 19,

22 to 25 I/O Port 9: An 8-bit input/output port. The

direction of each bit (except for P96) can be

selected in the port 9 data direction register

(P9DDR). P97 is powered by I/O buffer

power supply VCCB.

PA7 to PA010, 11, 20,

21, 30, 31,

47, 48

I/O Port A: An 8-bit input/output port with

programming MOS input pull-ups. The

direction of each bit can be selected in the

port A data direction register (PADDR). PA7

to PA4 are powered by I/O buffer power

supply VCCB. Features a bus drive function.

PB7 to PB057, 58, 68,

69, 80, 81,

90, 91

I/O Port B: An 8-bit input/output port with

programming MOS input pull-ups. The

direction of each bit can be selected in the

port B data direction register (PBDDR).

Note: In this chip, except for the S-mask model (single-power-supply specification), the same pin

is used for STBY and FVPP. When this pin is driven low, a transition is made to hardware

standby mode. This occurs not only in the normal operating modes (modes 1, 2, and 3), but

also when programming flash memory with a PROM writer. When using a PROM

programmer to program dual-power-supply flash memory, therefore, the PROM

programmer specifications should provide for this pin to be held at the VCC level except

when programming (FVPP = 12 V).

Section 2 CPU

2.1 Overview

The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also

configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed

operation.

2.1.1 Features

The main features of the H8/300 CPU are listed below.

• Two-way register configuration

 Sixteen 8-bit general registers, or

 Eight 16-bit general registers

• Instruction set with 57 basic instructions, including:

 Multiply and divide instructions

 Powerful bit-manipulation instructions

• Eight addressing modes

 Register direct (Rn)

 Register indirect (@Rn)

 Register indirect with displacement (@(d:16, Rn))

 Register indirect with post-increment or pre-decrement (@Rn+ or @–Rn)

 Absolute address (@aa:8 or @aa:16)

 Immediate (#xx:8 or #xx:16)

 PC-relative (@(d:8, PC))

 Memory indirect (@@aa:8)

• Maximum 64-kbyte address space

• High-speed operation

 All frequently-used instructions are executed in two to four states

• Maximum clock rate (ø clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V

 8- or 16-bit register-register add or subtract: 125 ns (16 MHz), 167 ns (12 MHz), 200 ns

(10 MHz)

 8 × 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)

 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)

• Power-down mode

 SLEEP instruction

2.1.2 Address Space

The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code

and data combined. The memory map differs depending on the mode (mode 1, 2, or 3). For details,

see section 3.4, Address Space Map in Each Operating Mode.

2.1.3 Register Configuration

Figure 2.1 shows the internal register structure of the H8/300 CPU. There are two groups of

registers: the general registers and control registers.

7070

15 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

(SP) SP: Stack pointer

PC: Program counter

CCR: Condition code register

Carry flag

Overflow flag

Zero flag

Negative flag

Half-carry flag

Interrupt mask bit

User bit

CCR I U H U N Z V C

General registers (Rn)

Control registers

75321064

Figure 2.1 CPU Registers

2.2 Register Descriptions

2.2.1 General Registers

All the general registers can be used as both data registers and address registers. When used as

address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as

data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed

separately as 8-bit registers (R0H to R7H and R0L to R7L).

R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and

subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As

indicated in figure 2.2, R7 (SP) points to the top of the stack.

Unused area

Stack area

SP (R7)

Figure 2.2 Stack Pointer

2.2.2 Control Registers

The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code

(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the

CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of

the PC is ignored (always regarded as 0).

(2) Condition Code Register (CCR): This 8-bit register contains internal status information,

including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt

mask bit (I).

Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked.

This bit is set to 1 automatically by a reset and at the start of interrupt handling.

Bit 6—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC,

ORC, and XORC instructions).

Bit 5—Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B,

NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise.

Similarly, it is set to 1 when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow

out of bit 11, and cleared to 0 otherwise. It is used implicitly in the DAA and DAS instructions.

Bit 4—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC,

ORC, and XORC instructions).

Bit 3—Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an

instruction.

Bit 2—Zero Flag (Z): This flag is set to 1 to indicate a zero result and cleared to 0 to indicate a

nonzero result.

Bit 1—Overflow Flag (V): This flag is set to 1 when an arithmetic overflow occurs, and cleared

to 0 at other times.

Bit 0—Carry Flag (C): This flag is used by:

• Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the

result

• Shift and rotate instructions, to store the value shifted out of the most significant or least

significant bit

• Bit manipulation and bit load instructions, as a bit accumulator

The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR,

and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in

conditional branching instructions (BCC).

For the action of each instruction on the flag bits, see the H8/300 Series Programming Manual.

2.2.3 Initial Register Values

When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt

mask bit (I) in the CCR is set to 1. The other CCR bits and the general registers are not initialized.

In particular, the stack pointer (R7) is not initialized. The stack pointer and CCR should be

initialized by software, by the first instruction executed after a reset.

2.3 Data Formats

The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)

data.

• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte

operand.

• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.

• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed

BCD form. Each nibble of the byte is treated as a decimal digit.

• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and

DIVXU (16 bits ÷ 8 bits) instructions operate on word data.

2.3.1 Data Formats in General Registers

Data of all the sizes above can be stored in general registers as shown in figure 2.3.

76543210 Don’t care

Data Type Register No. Data Format

1-bit data RnH

76543210

Don’t care

1-bit data RnL

MSB LSB

Don’t care

Byte data RnH

Byte data RnL

Word data Rn

4-bit BCD data RnH

4-bit BCD data RnL

Legend:

RnH:

RnL:

MSB:

LSB:

Upper digit of general register

Lower digit of general register

Most significant bit

Least significant bit

MSB LSB

Don’t care

MSB LSB

15 0

Upper digit Lower digit

Don’t care

7034

Don’t care

Upper digit Lower digit

Figure 2.3 Register Data Formats

2.3.2 Memory Data Formats

Figure 2.4 indicates the data formats in memory.

Word data stored in memory must always begin at an even address. In word access the least

significant bit of the address is regarded as 0. If an odd address is specified, no address error

occurs but the access is performed at the preceding even address. This rule affects MOV.W

instructions and branching instructions, and implies that only even addresses should be stored in

the vector table.

Data Format

76543210

AddressData Type

Address n

MSB LSB

MSB

LSB

Upper 8 bits

Lower 8 bits

MSB LSBCCR

CCR*

MSB

LSB

MSB LSB

Address n

Even address

Odd address

Even address

Odd address

Even address

Odd address

1-bit data

Byte data

Word data

Byte data (CCR) on stack

Word data on stack

Note: * Ignored on return

Legend:

CCR: Condition code register

Figure 2.4 Memory Data Formats

When the stack is addressed by register R7, it must always be accessed a word at a time. When the

CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word.

When they are restored, the lower byte is ignored.

2.4 Addressing Modes

2.4.1 Addressing Mode

The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these

addressing modes.

Table 2.1 Addressing Modes

No. Addressing Mode Symbol

(1) Register direct Rn

(2) Register indirect @Rn

(3) Register indirect with displacement @(d:16, Rn)

(4) Register indirect with post-increment

@–Rn

(5) Absolute address @aa:8 or @aa:16

(6) Immediate #xx:8 or #xx:16

(7) Program-counter-relative @(d:8, PC)

(8) Memory indirect @@aa:8

(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general

Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and

DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.

(2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general

(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in

MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3 and

4) which is added to the contents of the specified general register to obtain the operand address.

For the MOV.W instruction, the resulting address must be even.

(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:

• Register indirect with Post-Increment—@Rn+

The @Rn+ mode is used with MOV instructions that load registers from memory.

It is similar to the register indirect mode, but the 16-bit general register specified in the register

field of the instruction is incremented after the operand is accessed. The size of the increment

is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the

original contents of the 16-bit general register must be even.

• Register Indirect with Pre-Decrement—@–Rn

The @–Rn mode is used with MOV instructions that store register contents to memory.

It is similar to the register indirect mode, but the 16-bit general register specified in the register

field of the instruction is decremented before the operand is accessed. The size of the

decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For

MOV.W, the original contents of the 16-bit general register must be even.

(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the

operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx.

The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to

65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.

(6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or

a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit

immediate values.

The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit

manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the

instruction, specifying a bit number.

(7) Program-Counter-Relative—@(d:8, PC): This mode is used to generate branch addresses

in the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a

sign-extended value to the program counter contents. The result must be an even number. The

possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address.

(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0

to 255). The word located at this address contains the branch address. The upper 8 bits of the

absolute address are 0 (H'00), thus the branch address is limited to values from 0 to 255 (H'0000 to

H'00FF). Note that some of the addresses in this range are also used in the vector table. Refer to

section 3.4, Address Space Map in Each Operating Mode.

If an odd address is specified as a branch destination or as the operand address of a MOV.W

instruction, the least significant bit is regarded as 0, causing word access to be performed at the

address preceding the specified address. See section 2.3.2, Memory Data Formats, for further

information.

2.4.2 Calculation of Effective Address

Table 2.2 shows how the H8/300 calculates effective addresses in each addressing mode.

Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B,

SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also use immediate addressing (6).

The MOV instruction uses all the addressing modes except program-counter relative (7) and

memory indirect (8).

Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute (5)

addressing to identify a byte operand, and 3-bit immediate addressing to identify a bit within the

byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1)

to identify the bit.

Table 2.2 Effective Address Calculation

No. Addressing Mode and

Instruction Format Effective Address

Calculation Effective Address

Operands are contained in

registers regm and regn

op regm regn

87 34015 regm

regn

op reg

76 34015

015

3Register indirect with

displacement, @(d:16, Rn)

op reg

76 34015

disp

015

disp

015

16-bit register contents

op reg

76 34015

post-increment, @Rn+

op reg

76 34015

pre-decrement, @–Rn

Note: *1 for a byte operand,

2 for a word operand

015

1 or 2*

015

16-bit register contents

No. Addressing Mode and

Instruction Format Effective Address

Calculation Effective Address

5Absolute address

@aa:8

@aa:16

87 015

015

abs

H'FF

87 015

015

abs

015

IMM

#xx:16

87 015

IMM

Immediate

#xx:8 Operand is 1- or 2-byte

immediate data

op disp

7015

PC-relative

@(d:8, PC) PC contents

015

8Sign

extension disp

No. Addressing Mode and

Instruction Format Effective Address

Calculation Effective Address

8Memory indirect, @@aa:8

87 015

Memory contents

(16 bits)

015

abs

H'00

87 015

Legend:

reg: General register

op: Operation code

disp: Displacement

IMM: Immediate data

abs: Absolute address

2.5 Instruction Set

The H8/300 CPU has 57 types of instructions, which are classified by function in table 2.3.

Table 2.3 Instruction Classification

Function Instructions Types

Data transfer MOV, MOVTPE*3, MOVFPE*3, PUSH*1, POP*13

Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS,

DAA, DAS, MULXU, DIVXU, CMP, NEG 14

Logic operations AND, OR, XOR, NOT 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

ROTXR 8

Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,

BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 14

Branch Bcc*2, JMP, BSR, JSR, RTS 5

System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8

Block data transfer EEPMOV 1

Total 57

Notes: *1 PUSH Rn is equivalent to MOV.W Rn, @–SP.

POP Rn is equivalent to MOV.W @SP+, Rn.

*2 Bcc is a conditional branch instruction in which cc represents a condition code.

*3 Not supported by the H8/3437 Series.

The following sections give a concise summary of the instructions in each category, and indicate

the bit patterns of their object code. The notation used is defined next.

Operation Notation

Rd General register (destination)

Rs General register (source)

Rn General register

(EAd) Destination operand

(EAs) Source operand

SP Stack pointer

PC Program counter

CCR Condition code register

N N (negative) flag of CCR

Z Z (zero) flag of CCR

V V (overflow) flag of CCR

C C (carry) flag of CCR

#imm Immediate data

#xx:3 3-bit immediate data

#xx:8 8-bit immediate data

#xx:16 16-bit immediate data

disp Displacement

+ Addition

–Subtraction

×Multiplication

÷Division

∧AND logical

∨OR logical

⊕Exclusive OR logical

→Move

¬Not

2.5.1 Data Transfer Instructions

Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats.

Table 2.4 Data Transfer Instructions

Instruction Size*Function

MOV B/W (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general

The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and

@Rn+ addressing modes are available for byte or word data. The

@aa:8 addressing mode is available for byte data only.

The @–R7 and @R7+ modes require word operands. Do not specify

byte size for these two modes.

MOVTPE B Not supported by the H8/3437 Series.

MOVFPE B Not supported by the H8/3437 Series.

PUSH W Rn → @–SP

Pushes a 16-bit general register onto the stack. Equivalent to

MOV.W Rn, @–SP.

POP W @SP+ → Rn

Pops a 16-bit general register from the stack. Equivalent to MOV.W

@SP+, Rn.

Note: *Size: Operand size

B: Byte

W: Word

15 087

op rm rn MOV

Rm→Rn

15 087

op rm rn @Rm←→Rn

15 087

op rm rn @(d:16, Rm)←→Rn

disp

15 087

op rm rn @Rm+→Rn, or

Rn→@–Rm

15 087

op rn abs @aa:8←→Rn

15 087

op rn @aa:16←→Rn

abs

15 087

op rn IMM #xx:8→Rn

15 087

op rn #xx:16→Rn

IMM

15 087

op rn POP, PUSH

Legend:

op:

rm, rn:

disp:

abs:

IMM:

Operation field

Displacement

Absolute address

Immediate data

15 087

op rn MOVFPE, MOVTPE

abs

Figure 2.5 Data Transfer Instruction Codes

2.5.2 Arithmetic Operations

Table 2.5 describes the arithmetic instructions. See figure 2.6 in section 2.5.4, Shift Operations,

for their object codes.

Table 2.5 Arithmetic Instructions

Instruction Size*Function

ADD

SUB B/W Rd ± Rs → Rd, Rd + #imm → Rd

Performs addition or subtraction on data in two general registers, or

addition on immediate data and data in a general register.

Immediate data cannot be subtracted from data in a general register.

Word data can be added or subtracted only when both words are in

general registers.

ADDX

SUBX B Rd ± Rs ± C → Rd, Rd ± #imm ± C → Rd

Performs addition or subtraction with carry or borrow on byte data in

two general registers, or addition or subtraction on immediate data

and data in a general register.

INC

DEC B Rd ± #1 → Rd

Increments or decrements a general register.

ADDS

SUBS W Rd ± #imm → Rd

Adds or subtracts immediate data to or from data in a general

DAA

DAS B Rd decimal adjust → Rd

Decimal-adjusts (adjusts to packed BCD) an addition or subtraction

result in a general register by referring to the CCR.

MULXU B Rd × Rs → Rd

Performs 8-bit × 8-bit unsigned multiplication on data in two general

registers, providing a 16-bit result.

DIVXU B Rd ÷ Rs → Rd

Performs 16-bit ÷ 8-bit unsigned division on data in two general

registers, providing an 8-bit quotient and 8-bit remainder.

CMP B/W Rd – Rs, Rd – #imm

Compares data in a general register with data in another general

between two general registers.

NEG B 0 – Rd → Rd

Obtains the two’s complement (arithmetic complement) of data in a

general register.

Note: *Size: Operand size

B: Byte

W: Word

2.5.3 Logic Operations

Table 2.6 describes the four instructions that perform logic operations. See figure 2.6 in section

2.5.4, Shift Operations, for their object codes.

Table 2.6 Logic Operation Instructions

Instruction Size*Function

AND B Rd ∧ Rs → Rd, Rd ∧ #imm → Rd

Performs a logical AND operation on a general register and another

general register or immediate data.

OR B Rd ∨ Rs → Rd, Rd ∨ #imm → Rd

Performs a logical OR operation on a general register and another

general register or immediate data.

XOR B Rd ⊕ Rs → Rd, Rd ⊕ #imm → Rd

Performs a logical exclusive OR operation on a general register and

another general register or immediate data.

NOT B ¬ (Rd) → (Rd)

Obtains the one’s complement (logical complement) of general

Note: *Size: Operand size

B: Byte

2.5.4 Shift Operations

Table 2.7 describes the eight shift instructions. Figure 2.6 shows the object code formats of the

arithmetic, logic, and shift instructions.

Table 2.7 Shift Instructions

Instruction Size*Function

SHAL

SHAR B Rd shift → Rd

Performs an arithmetic shift operation on general register contents.

SHLL

SHLR B Rd shift → Rd

Performs a logical shift operation on general register contents.

ROTL

ROTR B Rd rotate → Rd

Rotates general register contents.

ROTXL

ROTXR B Rd rotate through carry → Rd

Rotates general register contents through the C (carry) bit.

Note: *Size: Operand size

B: Byte

15 087

op rm rn ADD, SUB, CMP,

ADDX, SUBX (Rm)

Legend:

op:

rm, rn:

IMM:

Operation field

Immediate data

15 087

op rn ADDS, SUBS, INC, DEC,

DAA, DAS, NEG, NOT

15 087

op rn MULXU, DIVXU

15 087

rn IMM ADD, ADDX, SUBX,

CMP (#xx:8)

15 087

op rn AND, OR, XOR (Rm)

15 087

rn IMM AND, OR, XOR (#xx:8)

15 087 rn SHAL, SHAR, SHLL, SHLR,

ROTL, ROTR, ROTXL, ROTXR

Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes

2.5.5 Bit Manipulations

Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats.

Table 2.8 Bit-Manipulation Instructions

Instruction Size*Function

BSET B 1 → (<bit no.> of <EAd>)

Sets a specified bit in a general register or memory to 1. The bit is

specified by a bit number, given in 3-bit immediate data or the lower

three bits of a general register.

BCLR B 0 → (<bit no.> of <EAd>)

Clears a specified bit in a general register or memory to 0. The bit is

specified by a bit number, given in 3-bit immediate data or the lower

three bits of a general register.

BNOT B ¬ (<bit no.> of <EAd>) → (<bit no.> of <EAd>)

Inverts a specified bit in a general register or memory. The bit is

specified by a bit number, given in 3-bit immediate data or the lower

three bits of a general register.

BTST B ¬ (<bit no.> of <EAd>) → Z

Tests a specified bit in a general register or memory and sets or

clears the Z flag accordingly. The bit is specified by a bit number,

given in 3-bit immediate data or the lower three bits of a general

BAND B C ∧ (<bit no.> of <EAd>) → C

ANDs the C flag with a specified bit in a general register or memory.

BIAND C ∧ [¬ (<bit no.> of <EAd>)] → C

ANDs the C flag with the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit no.> of <EAd>) → C

ORs the C flag with a specified bit in a general register or memory.

BIOR C ∨ [¬ (<bit no.> of <EAd>)] → C

ORs the C flag with the inverse of a specified bit in a general register

or memory.

The bit number is specified by 3-bit immediate data.

BXOR B C ⊕ (<bit no.> of <EAd>) → C

XORs the C flag with a specified bit in a general register or memory.

Note: *Size: Operand size

B: Byte

Instruction Size*Function

BIXOR B C ⊕ ¬ [(<bit no.> of <EAd>)] → C

XORs the C flag with the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BLD B (<bit no.> of <EAd>) → C

Copies a specified bit in a general register or memory to the C flag.

BILD ¬ (<bit no.> of <EAd>) → C

Copies the inverse of a specified bit in a general register or memory

to the C flag.

The bit number is specified by 3-bit immediate data.

BST B C → (<bit no.> of <EAd>)

Copies the C flag to a specified bit in a general register or memory.

BIST ¬ C → (<bit no.> of <EAd>)

Copies the inverse of the C flag to a specified bit in a general

The bit number is specified by 3-bit immediate data.

Note: *Size: Operand size

B: Byte

Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-

modify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte

back. Care is required when these instructions are applied to registers with write-only bits and to

the I/O port registers.

Step Description

1 Read Read one data byte at the specified address

2 Modify Modify one bit in the data byte

3 Write Write the modified data byte back to the specified address

Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under

the following conditions.

P47: Input pin, low

P46: Input pin, high

P45 – P40: Output pins, low

The intended purpose of this BCLR instruction is to switch P40 from output to input.

Before Execution of BCLR Instruction

P47P46P45P44P43P42P41P40

Input/output Input Input Output Output Output Output Output Output

Pin state Low High Low Low Low Low Low Low

DDR 00111111

DR 10000000

Execution of BCLR Instruction

BCLR #0, @P4DDR ; clear bit 0 in data direction register

After Execution of BCLR Instruction

P47P46P45P44P43P42P41P40

Input/output Output Output Output Output Output Output Output Input

Pin state Low High Low Low Low Low Low High

DDR 1 1111110

DR 10000000

Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since

P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.

Next the CPU clears bit 0 of the read data, changing the value to H'FE.

Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.

As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR

are set to 1, making P47 and P46 output pins.

15 087

op IMM rn Operand:

Bit no.:

Legend:

op:

rm, rn:

abs:

IMM:

Operation field

Absolute address

Immediate data

15 087

op rn

BSET, BCLR, BNOT, BTST

immediate (#xx:3)

Operand:

Bit no.: register direct (Rn)

15 087

op 0 Operand:

Bit no.:

immediate (#xx:3)

0IMM

15 087

op 0 Operand:

Bit no.:

0rmop

15 087

op Operand:

Bit no.:

absolute (@aa:8)

immediate (#xx:3)

abs

0000IMM

15 087

op Operand:

Bit no.:

absolute (@aa:8)

abs

0000rmop

15 087

op IMM rn Operand:

Bit no.: register direct (Rn)

immediate (#xx:3)

BAND, BOR, BXOR, BLD, BST

15 087

op 0 Operand:

Bit no.:

immediate (#xx:3)

0IMMop

15 087

op Operand:

Bit no.:

absolute (@aa:8)

immediate (#xx:3)

abs

0000IMMop

Figure 2.7 Bit Manipulation Instruction Codes

Legend:

op:

rm, rn:

abs:

IMM:

Operation field

Absolute address

Immediate data

15 087

op IMM rn Operand:

Bit no.: register direct (Rn)

immediate (#xx:3)

BIAND, BIOR, BIXOR, BILD, BIST

15 087

op 0 Operand:

Bit no.:

immediate (#xx:3)

0IMMop

15 087

op Operand:

Bit no.:

absolute (@aa:8)

immediate (#xx:3)

abs

0000IMMop

Figure 2.7 Bit Manipulation Instruction Codes (cont)

2.5.6 Branching Instructions

Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats.

Table 2.9 Branching Instructions

Instruction Size Function

Bcc —Branches if condition cc is true.

Mnemonic cc field Description Condition

BRA (BT) 0 0 0 0 Always (true) Always

BRN (BF) 0 0 0 1 Never (false) Never

BHI 0 0 1 0 High C ∨ Z = 0

BLS 0 0 1 1 Low or same C ∨ Z = 1

BCC (BHS) 0 1 0 0 Carry clear

(High or same) C = 0

BCS (BLO) 0 1 0 1 Carry set (low) C = 1

BNE 0 1 1 0 Not equal Z = 0

BEQ 0 1 1 1 Equal Z = 1

BVC 1 0 0 0 Overflow clear V = 0

BVS 1 0 0 1 Overflow set V = 1

BPL 1 0 1 0 Plus N = 0

BMI 1 0 1 1 Minus N = 1

BGE 1 1 0 0 Greater or equal N ⊕ V = 0

BLT 1 1 0 1 Less than N ⊕ V = 1

BGT 1 1 1 0 Greater than Z ∨ (N ⊕ V) = 0

BLE 1 1 1 1 Less or equal Z ∨ (N ⊕ V) = 1

JMP —Branches unconditionally to a specified address.

JSR —Branches to a subroutine at a specified address.

BSR —Branches to a subroutine at a specified displacement from the

current address.

RTS —Returns from a subroutine.

Legend:

op:

cc:

rm:

disp:

abs:

Operation field

Condition field

Displacement

Absolute address

15 087

op cc disp Bcc

15 087

op rm 0 JMP (@Rm)

000

15 087

op JMP (@aa:16)

abs

15 087

op abs JMP (@@aa:8)

15 087

op disp BSR

15 087

op rm 0 JSR (@Rm)

000

15 087

op JSR (@aa:16)

abs

15 087

op abs JSR (@@aa:8)

15 087

op RTS

Figure 2.8 Branching Instruction Codes

2.5.7 System Control Instructions

Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats.

Table 2.10 System Control Instructions

Instruction Size*Function

RTE —Returns from an exception-handling routine.

SLEEP —Causes a transition to the power-down state.

LDC B Rs → CCR, #imm → CCR

Moves immediate data or general register contents to the condition

code register.

STC B CCR → Rd

Copies the condition code register to a specified general register.

ANDC B CCR ∧ #imm → CCR

Logically ANDs the condition code register with immediate data.

ORC B CCR ∨ #imm → CCR

Logically ORs the condition code register with immediate data.

XORC B CCR ⊕ #imm → CCR

Logically exclusive-ORs the condition code register with immediate

data.

NOP —PC + 2 → PC

Only increments the program counter.

Note: *Size: Operand size

B: Byte

Legend:

op:

rn:

IMM:

Operation field

Immediate data

15 087

op RTE, SLEEP, NOP

15 087

op rn LDC, STC (Rn)

15 087

op IMM ANDC, ORC,

XORC, LDC (#xx:8)

Figure 2.9 System Control Instruction Codes

2.5.8 Block Data Transfer Instruction

Table 2.11 describes the EEPMOV instruction. Figure 2.10 shows its object code format.

Table 2.11 Block Data Transfer Instruction/EEPROM Write Operation

Instruction Size Function

EEPMOV —if R4L ≠ 0 then

repeat @R5+ → @R6+

R4L – 1 → R4L

until R4L = 0

else next;

Moves a data block according to parameters set in general registers

R4L, R5, and R6.

R4L: size of block (bytes)

R5: starting source address

R6: starting destination address

Execution of the next instruction starts as soon as the block transfer

is completed.

Legend:

op: Operation field

15 087

Figure 2.10 Block Data Transfer Instruction/EEPROM Write Operation Code

Notes on EEPMOV Instruction

1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes

specified by R4L from the address specified by R5 to the address specified by R6.

←R6

←R6 + R4L

R5 →

R5 + R4L →

2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not

exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of

the instruction.

H'FFFF

Not allowed

←R6

←R6 + R4L

R5 →

R5 + R4L →

2.6 CPU States

2.6.1 Overview

The CPU has three states: the program execution state, exception-handling state, and power-down

state. The power-down state is further divided into three modes: sleep mode, software standby

mode, and hardware standby mode. Figure 2.11 summarizes these states, and figure 2.12 shows a

map of the state transitions.

State Program execution state

The CPU executes successive program instructions.

Exception-handling state

A transient state triggered by a reset or interrupt. The CPU executes

a hardware sequence that includes loading the program counter from

the vector table.

Power-down state

A state in which some or

all of the chip functions are

stopped to conserve power.

Sleep mode

Software standby mode

Hardware standby mode

Figure 2.11 Operating States

Reset state Hardware

standby mode

Interrupt request

RES = 1

Power-down state

Sleep mode

Exception-

handling state

Program

execution state

Exception

handling

request Exception

handing

SLEEP instruction

with SSBY bit set

STBY = 1, RES = 0

SLEEP

instruction

Software

standby mode

NMI, IRQ0

to IRQ2 or IRQ6

Notes: 1.

A transition to the reset state occurs when RES goes low, except when the chip

is in the hardware standby mode.

A transition from any state to the hardware standby mode occurs when STBY

goes low.

Figure 2.12 State Transitions

2.6.2 Program Execution State

In this state the CPU executes program instructions.

2.6.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU is reset or interrupted

and changes its normal processing flow. In interrupt exception handling, the CPU references the

stack pointer (R7) and saves the program counter and condition code register on the stack. For

further details see section 4, Exception Handling.

2.6.4 Power-Down State

The power-down state includes three modes: sleep mode, software standby mode, and hardware

standby mode.

Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register

contents remain unchanged and the on-chip supporting modules continue to function.

Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY

(Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip

supporting modules halt. The on-chip supporting modules are initialized, but the contents of the

on-chip RAM and CPU registers remain unchanged as long as a specified voltage is supplied. I/O

port outputs also remain unchanged.

Hardware Standby Mode: Is entered when the input at the STBY pin goes low. All chip

functions halt, including I/O port output. The on-chip supporting modules are initialized, but on-

chip RAM contents are held.

See section 22, Power-Down State, for further information.

2.7 Access Timing and Bus Cycle

The CPU is driven by the system clock (ø). The period from one rising edge of the system clock to

the next is referred to as a “state.” Memory access is performed in a two- or three-state bus cycle.

On-chip memory, on-chip supporting modules, and external devices are accessed in different bus

cycles as described below.

2.7.1 Access to On-Chip Memory (RAM and ROM)

On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or

word data can be accessed, via a 16-bit data bus. Figure 2.13 shows the on-chip memory access

cycle. Figure 2.14 shows the associated pin states.

Bus cycle

Internal data bus (read)

Internal address bus

Internal read signal

Internal write signal

Internal data bus (write)

Address

T1 state T2 state

Write data

Read data

Figure 2.13 On-Chip Memory Access Cycle

Bus cycle

T1 state T2 state

Address

Address bus

AS: High

RD: High

WR: High

Data bus:

high impedance state

Figure 2.14 Pin States during On-Chip Memory Access Cycle

2.7.2 Access to On-Chip Register Field and External Devices

The on-chip supporting module registers and external devices are accessed in a cycle consisting of

three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data bus.

Access to word data or instruction codes requires two consecutive cycles (six states).

Figure 2.15 shows the access cycle for the on-chip register field. Figure 2.16 shows the associated

pin states. Figures 2.17 (a) and (b) show the read and write access timing for external devices.

Bus cycle

Internal data bus

(read)

Internal address

bus

Internal read

signal

Internal write

signal

Internal data bus

(write)

Address

Write data

T1 state T2 state T3 state

Read data

Figure 2.15 On-Chip Register Field Access Cycle

Address

Bus cycle

T3 stateT2 state

T1 state

Address bus

AS: High

RD: High

WR: High

Data bus:

h impedance state

Figure 2.16 Pin States during On-Chip Register Field Access Cycle

Read cycle

Address

Read data

T1 state T2 state T3 state

Address bus

WR: High

Data bus

Figure 2.17 (a) External Device Access Timing (Read)

Write cycle

Address

Write data

T1 state T2 state T3 state

Address bus

Data bus

RD: High

Figure 2.17 (b) External Device Access Timing (Write)

Section 3 MCU Operating Modes and Address Space

3.1 Overview

3.1.1 Mode Selection

The H8/3437 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the

inputs at the mode pins (MD1 and MD0). See table 3.1.

Table 3.1 Operating Modes

Mode MD1MD0Address Space On-Chip ROM On-Chip RAM

Mode 0 Low Low — — —

Mode 1 Low High Expanded Disabled Enabled*

Mode 2 High Low Expanded Enabled Enabled*

Mode 3 High High Single-chip Enabled Enabled

Note: *If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory can

be accessed instead.

Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices.

The maximum address space supported by these externally expanded modes is 64 kbytes.

In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are

used. All ports are available for general-purpose input and output.

Mode 0 is inoperative in the H8/3437 Series. Avoid setting the mode pins to mode 0, and do not

change the mode pin settings while the chip is operating.

3.1.2 Mode and System Control Registers

Table 3.2 lists the registers related to the chip’s operating mode: the system control register

(SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the

mode pins MD1 and MD0.

Table 3.2 Mode and System Control Registers

Name Abbreviation Read/Write Address

System control register SYSCR R/W H'FFC4

Mode control register MDCR R H'FFC5

3.2 System Control Register (SYSCR)

Bit 76543210

SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME

Initial value 0 0 0 0 1 0 0 1

Read/Write R/W R/W R/W R/W R R/W R/W R/W

The system control register (SYSCR) is an 8-bit register that controls the operation of the chip.

Bit 7—Software Standby (SSBY): Enables transition to the software standby mode. For details,

see section 22, Power-Down State.

On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1.

It can be cleared by writing 0.

Bit 7: SSBY Description

0 The SLEEP instruction causes a transition to sleep mode. (Initial value)

1 The SLEEP instruction causes a transition to software standby mode.

Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling

time when the chip recovers from the software standby mode by an external interrupt. During the

selected time the CPU and on-chip supporting modules continue to stand by. These bits should be

set according to the clock frequency so that the settling time is at least 8 ms. For specific settings,

see section 22.3.3, Clock Settling Time for Exit from Software Standby Mode.

• ZTAT and Mask ROM Versions

Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description

0 0 0 Settling time = 8,192 states (Initial value)

1 Settling time = 16,384 states

1 0 Settling time = 32,768 states

1 Settling time = 65,536 states

1 0 — Settling time = 131,072 states

1 — Unused

• F-ZTAT Version

Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description

0 0 0 Settling time = 8,192 states (Initial value)

1 Settling time = 16,384 states

1 0 Settling time = 32,768 states

1 Settling time = 65,536 states

1 0 0 Settling time = 131,072 states

1 Settling time = 1,024 states

1 — Unused

Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted.

If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer,

PWM timer, or watchdog timer clock, the counter in the timer will not count up normally

when 1,024 states is specified for the settling time. To avoid this problem, set the STS value

just before the transition to software standby mode (before executing the SLEEP

instruction), and re-set the value of STS2 to STS0 to a value from 000 to 100 directly after

software standby mode is cleared by an interrupt.

Bit 3—External Reset (XRST): Indicates the source of a reset. A reset can be generated by input

of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used.

XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer

overflow.

Bit 3: XRST Description

0 Reset was caused by watchdog timer overflow.

1 Reset was caused by external input. (Initial value)

Bit 2—NMI Edge (NMIEG): Selects the valid edge of the NMI input.

Bit 2: NMIEG Description

0 An interrupt is requested on the falling edge of the NMI input. (Initial value)

1 An interrupt is requested on the rising edge of the NMI input.

Bit 1—Host Interface Enable (HIE): Enables or disables the host interface function. When

enabled, the host interface processes host-slave data transfers, operating in slave mode.

Bit 1: HIE Description

0 The host interface is disabled. (Initial value)

1 The host interface is enabled (slave mode).

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized by a reset, but is not initialized in the software standby mode.

Bit 0: RAME Description

0 The on-chip RAM is disabled.

1 The on-chip RAM is enabled. (Initial value)

3.3 Mode Control Register (MDCR)

Bit 76543210

EXPE*1— — — — — MDS1 MDS0

Initial value —*211001—

*2—*2

Read/Write R/W*2————— R R

Notes: *1 H8/3437SF (S-mask model, single-power-supply on-chip flash memory version) only.

Otherwise, this is a reserved bit that is always read as 1.

*2 Determined by the mode pins (MD1 and MD0).

The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the

chip.

Bit 7—Expanded Mode Enable (EXPE): Functions only in the H8/3437SF (S-mask model,

single-power-supply on-chip flash memory version). For details, see section 21.1.6, Mode Control

In models other than the H8/3437SF, this is a reserved bit that cannot be modified and is always

read as 1.

Bits 6 and 5—Reserved: These bits cannot be modified and are always read as 1.

Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.

Bit 2—Reserved: This bit cannot be modified and is always read as 1.

Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the

mode pins (MD1 and MD0), thereby indicating the current operating mode of the chip. MDS1

corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode

control register is read, the levels at the mode pins (MD1 and MD0) are latched in these bits.

3.4 Address Space Map in Each Operating Mode

Figures 3.1 and 3.2 show memory maps of the H8/3437, H8/3436, and H8/3434 in modes 1, 2,

and 3.

H'FFFF

H'FF88

H'FF87

H'FF80

H'FF7F

H'F780

H'F77F

H'004C

H'004B

H'0000

H'FFFF

H'FF88

H'FF87

H'FF80

H'FF7F

H'F780

H'F77F

H'FFFF

H'FF88

H'FF7F

H'FF80

H'EF80

H'EF7F

H'004C

H'004B

H'0000

H'004C

H'004B

H'0000

Mode 1

Expanded Mode without

On-Chip ROM

Mode 2

Expanded Mode with

On-Chip ROM

Mode 3

Single-Chip Mode

Vector table

On-chip ROM

61,312 bytes

Vector tableVector table

External address space

On-chip RAM*,

2,048 bytes On-chip RAM,

2,048 bytes

External address space

On-chip RAM*,

2,048 bytes

On-chip register field On-chip register field On-chip register field

External memory can be accessed at these addresses when the RAME bit in the system

control register (SYSCR) is cleared to 0.

Note: *

On-chip ROM

63,360 bytes

H'FF7F

Figure 3.1 H8/3437 Address Space Map

H'FFFF

H'FF88

H'FF87

H'FF80

H'FF7F

H'F780

H'F77F

H'004C

H'004B

H'0000

H'FFFF

H'FF88

H'FF87

H'FF80

H'FF7F

H'F780

H'F77F

H'FFFF

H'FF88

H'FF7F

H'EF80

H'EF7F

H'BFFF

H'C000

H'004C

H'004B

H'0000

H'004C

H'004B

H'0000

Mode 1

Expanded Mode without

On-Chip ROM

Mode 2

Expanded Mode with

On-Chip ROM

Mode 3

Single-Chip Mode

Vector table

On-chip ROM

49,152 bytes

Vector tableVector table

Reserved*1

External address space

On-chip RAM*2,

2,048 bytes On-chip RAM

2,048 bytes

External address space

On-chip RAM*2,

2,048 bytes

On-chip register field On-chip register field On-chip register field

Do not access reserved areas.

External memory can be accessed at these addresses when the RAME bit in the system

control register (SYSCR) is cleared to 0.

Notes: *1

H'BFFF

H'C000

On-chip ROM

49,152 bytes

Reserved*1

H'F780

H'F77F

Figure 3.2 H8/3436 Address Space Map

H'FFFF

H'FF88

H'FF87

H'FF80

H'FF7F

H'FB80

H'FB7F

H'F780

H'F77F

H'004C

H'004B

H'0000

H'FFFF

H'FF88

H'FF87

H'FF80

H'FF7F

H'FB80

H'FB7F

H'F780

H'F77F

H'FFFF

H'FF88

H'FF7F

H'FB80

H'EF80

H'EF7F

H'8000 H'8000

H'7FFF

H'004C

H'004B

H'0000

H'004C

H'004B

H'0000

Mode 1

Expanded Mode without

On-Chip ROM

Mode 2

Expanded Mode with

On-Chip ROM

Mode 3

Single-Chip Mode

Vector table

On-chip ROM

32,768 bytes

Vector tableVector table

Reserved*1

Reserved*1, *2Reserved*1, *2

External address space

On-chip RAM*2,

1,024 bytes On-chip RAM

1,024 bytes

External address space

On-chip RAM*2,

1,024 bytes

On-chip register field On-chip register field On-chip register field

Do not access reserved areas.

External memory can be accessed at these addresses when the RAME bit in the system

control register (SYSCR) is cleared to 0.

Notes: *1

H'7FFF

On-chip ROM

32,768 bytes

Reserved*1

H'F780

H'F77F

Figure 3.3 H8/3434 Address Space Map

Section 4 Exception Handling

4.1 Overview

The H8/3437 Series recognizes two kinds of exceptions: interrupts and the reset. Table 4.1

indicates their priority and the timing of their hardware exception-handling sequence.

Table 4.1 Hardware Exception-Handling Sequences and Priority

Priority Type of

Exception Detection

Timing Timing of Exception-Handling Sequence

High Reset Synchronized

with clock The hardware exception-handling sequence begins

as soon as RES changes from low to high.

Low

Interrupt End of instruction

execution*When an interrupt is requested, the hardware

exception-handling sequence begins at the end of

the current instruction, or at the end of the current

hardware exception-handling sequence.

Note: *Not detected after ANDC, ORC, XORC, and LDC instructions.

4.2 Reset

4.2.1 Overview

A reset has the highest exception-handling priority. When the RES pin goes low or when there is a

watchdog timer reset (when the reset option is selected for watchdog timer overflow), all current

processing stops and the chip enters the reset state. The internal state of the CPU and the registers

of the on-chip supporting modules are initialized. The reset exception-handling sequence starts

when RES returns from low to high, or at the end of a watchdog reset pulse.

4.2.2 Reset Sequence

The reset state begins when RES goes low or a watchdog reset is generated. To ensure correct

resetting, at power-on the RES pin should be held low for at least 20 ms. In a reset during

operation, the RES pin should be held low for at least 10 system clock cycles. The watchdog reset

pulse width is always 518 system clocks. For the pin states during a reset, see appendix D, Pin

States.

The following sequence is carried out when reset exception handling begins.

1. The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, and the I bit in the condition code register (CCR) is set to 1.

2. The CPU loads the program counter with the first word in the vector table (stored at addresses

H'0000 and H'0001) and starts program execution.

The RES pin should be held low when power is switched off, as well as when power is switched

on.

Figure 4.1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4.2 indicates the

timing in mode 1.

(1)

RES/watchdog timer

reset (internal)

(2)

Internal address

bus

Internal read

signal

Internal write

signal

Internal data bus

(16 bits)

(1) Reset vector address (H'0000)

(2) Starting address of program

(3) First instruction of program

Vector

fetch Internal

processing Instruction

prefetch

(2) (3)

Figure 4.1 Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM)

(1) (3) (5) (7)

(1), (3) Reset vector address: (1) = H'0000, (3) = H'0001

(2), (4) Starting address of program (contents of reset vector): (2) = upper byte, (4) = lower byte

(5), (7) Starting address of program: (5) = (2) (4), (7) = (2) (4) + 1

(6), (8) First instruction of program: (6) = first byte, (8) = second byte

Vector fetch

Internal

process-

ing Instruction prefetch

RES/watchdog timer

reset (internal)

D7 to D0

(8 bits)

A15 to A0

(2) (4) (6) (8)

Figure 4.2 Reset Sequence (Mode 1)

4.2.3 Disabling of Interrupts after Reset

After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7),

the program counter and condition code register might not be saved correctly, leading to a

program crash. To prevent this, all interrupts, including NMI, are disabled immediately after a

reset. The first program instruction is therefore always executed. This instruction should initialize

the stack pointer (example: MOV.W #xx:16, SP).

After reset exception handling, in order to initialize the contents of CCR, a CCR manipulation

instruction can be executed before an instruction to initialize the stack pointer. Immediately after

execution of a CCR manipulation instruction, all interrupts including NMI are disabled. Use the

next instruction to initialize the stack pointer.

4.3 Interrupts

4.3.1 Overview

The interrupt sources include nine external sources from 23 input pins (NMI, IRQ0 to IRQ7, and

KEYIN0 to KEYIN15), and 26 internal sources in the on-chip supporting modules. Table 4.2 lists

the interrupt sources in priority order and gives their vector addresses. When two or more

interrupts are requested, the interrupt with highest priority is served first.

The features of these interrupts are:

• NMI has the highest priority and is always accepted. All internal and external interrupts except

NMI can be masked by the I bit in the CCR. When the I bit is set to 1, interrupts other than

NMI are not accepted.

• IRQ0 to IRQ7 can be sensed on the falling edge of the input signal, or level-sensed. The type of

sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the

rising or falling edge can be selected.

• All interrupts are individually vectored. The software interrupt-handling routine does not have

to determine what type of interrupt has occurred.

• IRQ6 is multiplexed with 16 external sources (KEYIN0 to KEYIN15). KEYIN0 to KEYIN15 can

be masked individually by user software.

• The watchdog timer can generate either an NMI or overflow interrupt, depending on the needs

of the application. For details, see section 11, Watchdog Timer.

Table 4.2 Interrupts

Interrupt source No. Vector Table Address Priority

NMI

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

H'0006 to H'0007

H'0008 to H'0009

H'000A to H'000B

H'000C to H'000D

H'000E to H'000F

H'0010 to H'0011

H'0012 to H'0013

H'0014 to H'0015

H'0016 to H'0017

High

16-bit free-running

timer ICIA (Input capture A)

ICIB (Input capture B)

ICIC (Input capture C)

ICID (Input capture D)

OCIA (Output compare A)

OCIB (Output compare B)

FOVI (Overflow)

H'0018 to H'0019

H'001A to H'001B

H'001C to H'001D

H'001E to H'001F

H'0020 to H'0021

H'0022 to H'0023

H'0024 to H'0025

8-bit timer 0 CMI0A (Compare-match A)

CMI0B (Compare-match B)

OVI0 (Overflow)

H'0026 to H'0027

H'0028 to H'0029

H'002A to H'002B

8-bit timer 1 CMI1A (Compare-match A)

CMI1B (Compare-match B)

OVI1 (Overflow)

H'002C to H'002D

H'002E to H'002F

H'0030 to H'0031

Host interface IBF1 (IDR1 receive end)

IBF2 (IDR2 receive end) 25

26 H'0032 to H'0033

H'0034 to H'0035

Serial

communication

interface 0

ERI0 (Receive error)

RXI0 (Receive end)

TXI0 (TDR empty)

TEI0 (TSR empty)

H'0036 to H'0037

H'0038 to H'0039

H'003A to H'003B

H'003C to H'003D

Serial

communication

interface 1

ERI1 (Receive error)

RXI1 (Receive end)

TXI1 (TDR empty)

TEI1 (TSR empty)

H'003E to H'003F

H'0040 to H'0041

H'0042 to H'0043

H'0044 to H'0045

A/D converter ADI (Conversion end) 35 H'0046 to H'0047

Watchdog timer WOVF (WDT overflow) 36 H'0048 to H'0049

I2C bus interface IICI (Transfer end) 37 H'004A to H'004B Low

Notes: 1. H'0000 and H'0001 contain the reset vector.

2. H'0002 to H'0005 are reserved in the H8/3437 Series and are not available to the user.

4.3.2 Interrupt-Related Registers

The interrupt-related registers are the system control register (SYSCR), IRQ sense control register

(ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask registers (KMIMR and

KMIMRA).

Table 4.3 Registers Read by Interrupt Controller

Name Abbreviation Read/Write Address

System control register SYSCR R/W H'FFC4

IRQ sense control register ISCR R/W H'FFC6

IRQ enable register IER R/W H'FFC7

Keyboard matrix interrupt mask register KMIMR R/W H'FFF1

Keyboard matrix interrupt mask register A KMIMRA R/W H'FFF3

System Control Register (SYSCR)

Bit 76543210

SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME

Initial value 0 0 0 0 1 0 0 1

Read/Write R/W R/W R/W R/W R R/W R/W R/W

The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register.

Bit 2—NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the

falling or rising edge of the NMI input signal.

Bit 2: NMIEG Description

0 An interrupt is generated on the falling edge of NMI. (Initial state)

1 An interrupt is generated on the rising edge of NMI.

See section 3.2, System Control Register, for information on the other SYSCR bits.

IRQ Sense Control Register (ISCR)

Bit 76543210

IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7 to 0—IRQ7 to IRQ0 Sense Control (IRQ7SC to IRQ0SC): These bits determine whether

IRQ7 to IRQ0 are level-sensed or sensed on the falling edge.

Bits 7 to 0:

IRQ7SC to IRQ0SC Description

0 An interrupt is generated when IRQ7 to IRQ0 inputs are low. (Initial state)

1 An interrupt is generated by the falling edge of the IRQ7 to IRQ0 inputs.

IRQ Enable Register (IER)

Bit 76543210

IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

Initial value 0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable the IRQ7 to

IRQ0 interrupts individually.

Bits 7 to 0:

IRQ7E to IRQ0E Description

0 IRQ7 to IRQ0 interrupt requests are disabled. (Initial state)

1 IRQ7 to IRQ0 interrupt requests are enabled.

When edge sensing is selected (by setting bits IRQ7SC to IRQ0SC to 1), it is possible for an

interrupt-handling routine to be executed even though the corresponding enable bit (IRQ7E to

IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit

(IRQ7E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is

cleared to 0 while the request is still pending, the request will remain pending, although new

requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the

interrupt-handling routine can be executed even though the enable bit is now 0.

If execution of interrupt-handling routines under these conditions is not desired, it can be avoided

by using the following procedure to disable and clear interrupt requests.

1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically

when execution jumps to an interrupt vector.

2. Clear the desired bits from IRQ7E to IRQ0E to 0 to disable new interrupt requests.

3. Clear the corresponding IRQ7SC to IRQ0SC bits to 0, then set them to 1 again. Pending IRQn

interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0.

Keyboard Matrix Interrupt Mask Register (KMIMR)

To control interrupts from a 16 × 16 matrix keyboard at key-sense input pins KEYIN0 to KEYIN15,

there are two keyboard matrix interrupt mask registers, KMIMR and KMIMRA. Bits KMIMR7 to

KMIMR0 in KMIMR correspond to key-sense inputs KEYIN7 to KEYIN0. Bits KMIMR15 to

KMIMR8 in KMIMRA correspond to key-sense inputs KEYIN15 to KEYIN8. Initially, the

KMIMR6 bit that corresponds to the IRQ6/KEYIN6 pin is in the interrupt-enabled state, and the

other interrupt mask bits are in the interrupt-disabled state.

KMIMR is an 8-bit readable/writable register used in keyboard matrix scanning and sensing. This

sense input interrupts from two or more pins during keyboard scanning and sensing, clear the

corresponding mask bits to 0.

Bit 76543210

KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0

Initial value 1 0 1 1 1 1 1 1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control

key-sense input interrupt requests KEYIN7 to KEYIN0.

Bits 7 to 0:

KMIMR7 to KMIMR0 Description

0 Key-sense input interrupt request is enabled.

1 Key-sense input interrupt request is disabled. (Initial value)*

Note: *Except KMIMR6, which is initially 0.

Bit 76543210

KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8

Initial value 1 1 1 1 1 1 1 1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR15 to KMIMR8): These bits control

key-sense input interrupt requests KEYIN15 to KEYIN8.

Bits 7 to 0:

KMIMR15 to KMIMR8 Description

0 Key-sense input interrupt request is enabled.

1 Key-sense input interrupt request is disabled. (Initial value)

Figure 4.3 shows the relationship between the IRQ6 interrupt, KMIMR, and KMIMRA.

IRQ6E

IRQ6SC

KMIMR0 (1)

P60/KEYIN0

KMIMR6 (0)

P66/KEYIN6/IRQ6

KMIMR7 (1)

P67/KEYIN7

KMIMR15 (1)

PA7/KEYIN15

KMIMR8 (1)

PA0/KEYIN8

IRQ6 internal signal

Edge/level select

and enable/

disable control

IRQ6

interrupt

Initial values are given in parentheses

Figure 4.3 KMIMR, KMIMRA, and IRQ6 Interrupt

4.3.3 External Interrupts

The nine external interrupts are NMI and IRQ0 to IRQ7. NMI, IRQ0, IRQ1, IRQ2, and IRQ6 can be

used to recover from software standby mode.

NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal

regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected by the

NMIEG bit in the system control register. The NMI vector number is 3. In the NMI hardware

exception-handling sequence the I bit in the CCR is set to 1.

IRQ0 to IRQ7: These interrupt signals are level-sensed or sensed on the falling edge of the input,

as selected by ISCR bits IRQ0SC to IRQ7SC. These interrupts can be masked collectively by the I

bit in the CCR, and can be enabled and disabled individually by setting and clearing bits IRQ0E to

IRQ7E in the IRQ enable register.

The IRQ6 input signal can be logically ORed internally with the key sense input signals. When

KEYIN0 to KEYIN15 pins (P60 to P67 and PA0 to PA7) are used for key sense input, the

corresponding KMIMR bits should be cleared to 0 to enable the corresponding key sense input

interrupts. KMIMR bits corresponding to unused key sense inputs should be set to 1 to disable the

interrupts. All 16 key sense interrupts are combined into a single IRQ6 interrupt.

When one of these interrupts is accepted, the I bit is set to 1. IRQ0 to IRQ7 have interrupt vector

numbers 4 to 11. They are prioritized in order from IRQ7 (low) to IRQ0 (high). For details, see

table 4.2.

Interrupts IRQ0 to IRQ7 do not depend on whether pins IRQ0 to IRQ7 are input or output pins.

When using external interrupts IRQ0 to IRQ7, clear the corresponding DDR bits to 0 to set these

pins to the input state, and do not use these pins as input or output pins for the timers, serial

communication interface, I2C bus interface, host interface, or A/D converter.

4.3.4 Internal Interrupts

Twenty-six internal interrupts can be requested by the on-chip supporting modules. Each interrupt

source has its own vector number, so the interrupt-handling routine does not have to determine

which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to

1. When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except

NMI). The vector numbers are 12 to 37. For the priority order, see table 4.2.

4.3.5 Interrupt Handling

Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt

requests, commands the CPU to start the hardware interrupt exception-handling sequence, and

furnishes the necessary vector number. Figure 4.4 shows a block diagram of the interrupt

controller.

IRQ0 flag

IRQ0E

IRIC

IEIC

CPU

I (CCR)

NMI interrupt Interrupt

controller

Priority

decision

IRQ0

interrupt Interrupt request

Vector number

IICI

interrupt

Note: *

For edge-sensed interrupts, these AND gates change to the circuit shown below.

IRQ0 edge

IRQ0E SQ

IRQ0 flag

IRQ0 interrupt

Figure 4.4 Block Diagram of Interrupt Controller

The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected

for a watchdog timer overflow) all have corresponding enable bits. When the enable bit is cleared

to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These

interrupts can also all be masked by setting the CPU’s interrupt mask bit (I) to 1. Accordingly,

these interrupts are accepted only when their enable bit is set to 1 and the I bit is cleared to 0.

The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware

standby mode.

When an NMI or another enabled interrupt is requested, the interrupt controller transfers the

interrupt request to the CPU and indicates the corresponding vector number. (When two or more

interrupts are requested, the interrupt controller selects the vector number of the interrupt with the

highest priority.) When notified of an interrupt request, at the end of the current instruction or

current hardware exception-handling sequence, the CPU starts the hardware exception-handling

sequence for the interrupt and latches the vector number.

Figure 4.5 is a flowchart of the interrupt (and reset) operations. Figure 4.7 shows the interrupt

timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM

and the stack is in on-chip RAM.

1. An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when

an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the

enable bit of that interrupt is set to 1.

2. The interrupt controller checks the I bit in CCR and accepts the interrupt request if the I bit is

cleared to 0. If the I bit is set to 1 only NMI requests are accepted; other interrupt requests

remain pending.

3. Among all accepted interrupt requests, the interrupt controller selects the request with the

highest priority and passes it to the CPU. Other interrupt requests remain pending.

4. When it receives the interrupt request, the CPU waits until completion of the current

instruction or hardware exception-handling sequence, then starts the hardware exception-

handling sequence for the interrupt and latches the interrupt vector number.

5. In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the

stack. See figure 4.6. The stacked PC indicates the address of the first instruction that will be

executed on return from the software interrupt-handling routine.

6. Next the I bit in CCR is set to 1, masking all further interrupts except NMI.

7. The vector address corresponding to the vector number is generated, the vector table entry at

this vector address is loaded into the program counter, and execution branches to the software

interrupt-handling routine at the address indicated by that entry.

Program execution

Yes

NMI?

I = 0?

IRQ0?

IRQ1?

IICI?

Reset

I← 1

Interrupt

requested?

Pending

Latch vector no.

Save PC

Save CCR

Read vector address

Branch to software

interrupt-handling

routine

Yes

Figure 4.5 Hardware Interrupt-Handling Sequence

SP(R7)SP – 4

SP – 3

SP – 2

SP – 1

SP (R7)

SP + 1

SP + 2

SP + 3

SP + 4 Even address

CCR

CCR*

PC (upper byte)

Before interrupt

is accepted After interrupt

is accepted

Pushed onto stack

Program counter

Condition code register

Stack pointer

PC:

CCR:

SP:

The PC contains the address of the first instruction executed after return.

Registers must be saved and restored by word access at an even address.

Notes: 1.

* Ignored on return.

Stack area

PC (lower byte)

Figure 4.6 Usage of Stack in Interrupt Handling

The CCR is comprised of one byte, but when it is saved to the stack, it is treated as one word of

data. During interrupt processing, two identical bytes of CCR data are saved to the stack to create

one word of data. When the RTE instruction is executed to restore the value from the stack, the

byte located at the even address is loaded into CCR, and the byte located at the odd address is

ignored.

(3) (5) (6) (8) (9)(1)

Interrupt priority

decision. Wait for

end of instruction.

Interrupt

accepted

Internal

process-

ing Stack Vector

fetch Internal

process-

ing

Instruction prefetch

(first instruction of

interrupt-handling

routine)

Interrupt request

signal

Internal address

bus

Internal write

signal

Internal read

signal

Internal 16-bit

data bus

(1)(2) (4) (7) (9) (10)

Instruction

prefetch

(1)

(2) (4)

(3)

(5)

(6)

(7)

(8)

(9)

(

)

Instruction prefetch address (Pushed on stack. Instruction is executed on return from interrupt-handling routine.)

Instruction code (Not executed)

Instruction prefetch address (Not executed)

SP–2

SP–4

CCR

Address of vector table entry

Vector table entry (address of first instruction of interrupt-handling routine)

First instruction of interrupt-handlin

routine

Figure 4.7 Timing of Interrupt Sequence

4.3.6 Interrupt Response Time

Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first

instruction of the software interrupt-handling routine is executed. Since on-chip memory is

accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling

routines in on-chip ROM and the stack in on-chip RAM.

Table 4.4 Number of States before Interrupt Service

Number of States

No. Reason for Wait On-Chip Memory External Memory

1 Interrupt priority decision 2*32*3

2 Wait for completion of current

instruction*11 to 13 5 to 17*2

3 Save PC and CCR 4 12*2

4 Fetch vector 2 6*2

5 Fetch instruction 4 12*2

6 Internal processing 4 4

Total 17 to 29 41 to 53*2

Notes: *1 These values do not apply if the current instruction is EEPMOV.

*2 If wait states are inserted in external memory access, add the number of wait states.

*3 1 for internal interrupts.

4.3.7 Precaution

Note that the following type of contention can occur in interrupt handling.

When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt

becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR

or MOV instruction, for example, and the interrupt is requested during execution of that

instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution

of the instruction, the hardware exception-handling sequence is executed for the interrupt. If a

higher-priority interrupt is requested at the same time, however, the hardware exception-handling

sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored.

Similar considerations apply when an interrupt request flag is cleared to 0.

Figure 4.8 shows an example in which the OCIAE bit is cleared to 0.

Internal address bus

OCIAE

OCIA interrupt handling

OCIA interrupt signal

OCFA

CPU write

cycle to TIER

Internal write signal

TIER address

Figure 4.8 Contention between Interrupt and Disabling Instruction

The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt

mask bit (I) is set to 1.

4.4 Note on Stack Handling

In word access, the least significant bit of the address is always assumed to be 0. The stack is

always accessed by word access. Care should be taken to keep an even value in the stack pointer

(general register R7). Use the PUSH and POP (or MOV.W Rn, @–SP and MOV.W @SP+, Rn)

instructions to push and pop registers on the stack.

Setting the stack pointer to an odd value can cause programs to crash. Figure 4.9 shows an

example of damage caused when the stack pointer contains an odd address.

PCH

SP PCLH'FECD

H'FECF

H'FECC

BSR instruction MOV.B R1L, @–R7

PC is improperly stored

beyond top of stack

H'FECF set in SP PCH is lost

PCH:

PCL:

R1L:

SP:

Upper byte of program counter

Lower byte of program counter

General register

Stack pointer

R1L

PCL

Figure 4.9 Example of Damage Caused by Setting an Odd Address in R7

Section 5 Wait-State Controller

5.1 Overview

The H8/3437 Series has an on-chip wait-state controller that enables insertion of wait states into

bus cycles for interfacing to low-speed external devices.

5.1.1 Features

Features of the wait-state controller are listed below.

• Three selectable wait modes: programmable wait mode, pin auto-wait mode, and pin wait

mode

• Automatic insertion of zero to three wait states

5.1.2 Block Diagram

Figure 5.1 shows a block diagram of the wait-state controller.

WAIT Wait-state controller

(WSC)

WSCR

Internal data bus

Wait request

signal

Legend:

WSCR: Wait-state control register

Figure 5.1 Block Diagram of Wait-State Controller

5.1.3 Input/Output Pins

Table 5.1 summarizes the wait-state controller’s input pin.

Table 5.1 Wait-State Controller Pins

Name Abbreviation I/O Function

Wait WAIT Input Wait request signal for access to external addresses

5.1.4 Register Configuration

Table 5.2 summarizes the wait-state controller’s register.

Table 5.2 Register Configuration

Address Name Abbreviation R/W Initial Value

H'FFC2 Wait-state control register WSCR R/W H'08

5.2 Register Description

5.2.1 Wait-State Control Register (WSCR)

WSCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller

(WSC) and specifies the number of wait states. It also controls RAM area setting for dual-power-

supply flash memory, selection/non-selection of single-power-supply flash memory control

registers, and frequency division of the clock signals supplied to the supporting modules.

Bit 76543210

RAMS*1RAM0*1CKDBL FLSHE*2WMS1 WMS0 WC1 WC0

Initial value 0 0 0 0 1 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Notes: *1 These bits are valid only in the H8/3437F and H8/3434F (dual-power-supply on-chip

flash memory versions).

*2 This bit is valid only in the H8/3437SF (S-mask model, single-power-supply on-chip

flash memory version).

WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—RAM Select (RAMS)

Bit 6—RAM Area Select (RAM0)

Bits 7 and 6 select a RAM area for emulation of dual-power-supply flash memory updates. For

details, see the flash memory description in section 19, 20, ROM.

Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to

supporting modules. For details, see section 6, Clock Pulse Generator.

Bit 4—Flash Memory Control Register Enable (FLSHE): Controls selection/non-selection of

single-power-supply flash memory control registers. For details, see the description of flash

memory in section 21, ROM. In models other than the H8/3437SF, this bit is reserved, but it can

be written and read; its initial value is 0.

Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.

Bit 3: WMS1 Bit 2: WMS0 Description

0 0 Programmable wait mode

1 No wait states inserted by wait-state controller

1 0 Pin wait mode (Initial value)

1 Pin auto-wait mode

Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted

in access to external address areas.

Bit 1: WC1 Bit 0: WC0 Description

0 0 No wait states inserted by wait-state controller (Initial value)

1 1 state inserted

1 0 2 states inserted

1 3 states inserted

5.3 Wait Modes

Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are

inserted in all accesses to external addresses. Figure 5.2 shows the timing when the wait count is 1

(WC1 = 0, WC0 = 1).

T1 T2 TW T3

Address bus

Data bus

External address

Read data

Write data

Read

access

Write

access

Figure 5.2 Programmable Wait Mode

Pin Wait Mode: In all accesses to external addresses, the number of wait states (TW) selected by

bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the

last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait

states continue to be inserted until the WAIT signal goes high.

Pin wait mode is useful for inserting four or more wait states, or for inserting different numbers of

wait states for different external devices.

Figure 5.3 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait

state is inserted by WAIT input.

Address bus

Data bus

1 T

2 T

W T

Write data

Read data

Read

access

Write

access

Note: Arrows indicate time of sampling of the pin.*WAIT

pinWAIT

Data bus

External address

Write data

Inserted by

wait count Inserted by

signalWAIT

Figure 5.3 Pin Wait Mode

Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits

WC1 and WC0 are inserted.

In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the T2 state, the

number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait states

are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy

interface to low-speed memory, simply by routing the chip select signal to the WAIT pin.

Figure 5.4 shows the timing when the wait count is 1.

Address bus

Data bus

T1 T2 T3 T1 T2 TW T3

Read data Read data

Write data Write data

Read

access

Write

access

Note: Arrows indicate time of sampling of the pin.*WAIT

External address External address

WAIT

Figure 5.4 Pin Auto-Wait Mode

Section 6 Clock Pulse Generator

6.1 Overview

The H8/3437 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a

duty adjustment circuit, and a divider and a prescaler that generates clock signals for the on-chip

supporting modules.

6.1.1 Block Diagram

Figure 6.1 shows a block diagram of the clock pulse generator.

XTAL

EXTAL Oscillator

circuit

Duty

adjustment

circuit

Frequency

divider (1/2) CKDBL

(system

clock)

øP

(for sup-

porting

modules) Prescaler

øP/2 to øP/4096

Figure 6.1 Block Diagram of Clock Pulse Generator

Input an external clock signal to the EXTAL pin, or connect a crystal resonator to the XTAL and

EXTAL pins. The system clock frequency (ø) will be the same as the input frequency. This same

system clock frequency (øP) can be supplied to timers and other supporting modules, or it can be

divided by two. The selection is made by software, by controlling the CKDBL bit.

6.1.2 Wait-State Control Register (WSCR)

WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals

supplied to the supporting modules. It also controls wait state controller wait settings, RAM area

setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply

flash memory control registers.

WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 76543210

RAMS*1RAM0*1CKDBL FLSHE*2WMS1 WMS0 WC1 WC0

Initial value 0 0 0 0 1 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Notes: *1 These bits are valid only in the H8/3437F and H8/3434F (dual-power-supply on-chip

flash memory versions).

*2 This bit is valid only in the H8/3437SF (S-mask model, single-power-supply on-chip

flash memory version).

Bit 7—RAM Select (RAMS)

Bit 6—RAM Area Select (RAM0)

Bits 7 and 6 select a RAM area for emulation of dual-power-supply flash memory updates. For

details, see the flash memory description in section 19, 20, ROM.

Bit 5—Clock Double (CKDBL): Controls the frequency division of clock signals supplied to

supporting modules.

Bit 5: CKDBL Description

0 The undivided system clock (ø) is supplied as the clock (øP) for supporting

modules. (Initial value)

1 The system clock (ø) is divided by two and supplied as the clock (øP) for

supporting modules.

Bit 4—Flash Memory Control Register Enable (FLSHE): Controls selection/non-selection of

single-power-supply flash memory control registers. For details, see the description of flash

memory in section 21, ROM. In models other than the H8/3437SF, this bit is reserved, but it can

be written and read; its initial value is 0.

Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0)

Bits 1 and 0—Wait Count 1 and 0 (WC1/0)

These bits control wait-state insertion. For details, see section 5, Wait-State Controller.

6.2 Oscillator Circuit

6.2.1 Oscillator (Generic Device)

If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit

generates a system clock signal. Alternatively, an external clock signal can be applied to the

EXTAL pin.

Connecting an External Crystal

Circuit Configuration: An external crystal can be connected as in the example in figure 6.2.

Table 6.1 indicates the appropriate damping resistance Rd. An AT-cut parallel resonance crystal

should be used.

EXTAL

XTAL

CL1

CL2 CL1 = C L2 = 10 pF to 22 pF

Figure 6.2 Connection of Crystal Oscillator (Example)

Table 6.1 Damping Resistance

Frequency (MHz) 248101216

Rd max (Ω) 1 k 500 200 0 0 0

Crystal Oscillator: Figure 6.3 shows an equivalent circuit of the crystal resonator. The crystal

resonator should have the characteristics listed in table 6.2.

XTAL

LRs

EXTAL

AT-cut parallel resonating crystal

Figure 6.3 Equivalent Circuit of External Crystal

Table 6.2 External Crystal Parameters

Frequency (MHz) 248101216

Rs max (Ω) 500 120 80 70 60 50

C0 (pF) 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max

Use a crystal with the same frequency as the desired system clock frequency (ø).

Note on Board Design: When an external crystal is connected, other signal lines should be kept

away from the crystal circuit to prevent induction from interfering with correct oscillation. See

figure 6.4. The crystal and its load capacitors should be placed as close as possible to the XTAL

and EXTAL pins.

XTAL

EXTAL

CL2

CL1

Not allowed Signal A Signal B

Figure 6.4 Notes on Board Design around External Crystal

Input of External Clock Signal

Circuit Configuration: An external clock signal can be input as shown in the examples in figure

6.5. In example (b) in figure 6.5, the external clock signal should be kept high during standby.

If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF.

EXTAL

XTAL

EXTAL

XTAL

74HC04

External clock input

Open

External clock input

(a) Connections with XTAL pin left open

(b) Connections with inverted clock input at XTAL pin

Figure 6.5 External Clock Input (Example)

External Clock Input: The external clock signal should have the same frequency as the desired

system clock (ø). Clock timing parameters are given in table 6.3 and figure 6.6.

Table 6.3 Clock Timing

VCC = 2.7 to

5.5 V VCC = 4.0 to

5.5 V VCC = 5.0 V

±10%

Item Symbol Min Max Min Max Min Max Unit Test Conditions

Low pulse

width of external

clock input

tEXL 40 —30 —20 —ns Figure 6.6

High pulse

width of external

clock input

tEXH 40 —30 —20 —ns

External clock

rise time tEXr —10 —10 —5ns

External clock

fall time tEXf —10 —10 —5ns

Clock pulse tCL 0.3 0.7 0.3 0.7 0.3 0.7 tcyc ø ≥ 5 MHz Figure

width low 0.4 0.6 0.4 0.6 0.4 0.6 tcyc ø < 5 MHz 23.7

Clock pulse tCH 0.3 0.7 0.3 0.7 0.3 0.7 tcyc ø ≥ 5 MHz

width high 0.4 0.6 0.4 0.6 0.4 0.6 tcyc ø < 5 MHz

tEXH tEXL

tEXt

tEXr

VCC × 0.5

EXTAL

Figure 6.6 External Clock Input Timing

Table 6.4 lists the external clock output stabilization delay time. Figure 6.7 shows the timing for

the external clock output stabilization delay time. The oscillator and duty correction circuit have

the function of regulating the waveform of the external clock input to the EXTAL pin. When the

specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after

the elapse of the external clock output stabilization delay time (tDEXT). As clock signal output is not

confirmed during the tDEXT period, the reset signal should be driven low and the reset state

maintained during this time.

Table 6.4 External Clock Output Stabilization Delay Time

Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VSS = AVSS = 0 V

Item Symbol Min Max Unit Notes

External clock output stabilization

delay time tDEXT*500 —µs Figure 6.7

Note: *tDEXT includes a 10 tcyc RES pulse width (tRESW).

VCC

STBY

EXTAL

ø (internal and

external)

RES

tDEXT*

Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).

2.7 V

VIH

Figure 6.7 External Clock Output Stabilization Delay Time

6.2.2 Oscillator Circuit (H8/3437S)

If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit

generates a system clock signal. Alternatively, an external clock signal can be applied to the

EXTAL pin.

Connecting an External Crystal

Circuit Configuration: An external crystal can be connected as in the example in figure 6.8.

Table 6.5 indicates the appropriate damping resistance Rd. An AT-cut parallel resonance crystal

should be used.

EXTAL

XTAL

CL1

CL2 CL1 = C L2 = 10 pF to 22 pF

Figure 6.8 Connection of Crystal Oscillator (Example)

Table 6.5 Damping Resistance

Frequency (MHz) 2 4 8 10

Rd max (Ω) 1 k 500 200 0

Crystal Oscillator: Figure 6.9 shows an equivalent circuit of the crystal resonator. The crystal

resonator should have the characteristics listed in table 6.6.

XTAL

LRs

EXTAL

AT-cut parallel resonating crystal

Figure 6.9 Equivalent Circuit of External Crystal

Table 6.6 External Crystal Parameters

Frequency (MHz) 2 4 8 10

Rs max (Ω) 500 120 80 70

C0 (pF) 7 pF max 7 pF max 7 pF max 7 pF max

Use a crystal with the same frequency as the desired system clock frequency (ø).

Note on Board Design: When an external crystal is connected, other signal lines should be kept

away from the crystal circuit to prevent induction from interfering with correct oscillation. See

figure 6.10. The crystal and its load capacitors should be placed as close as possible to the XTAL

and EXTAL pins.

XTAL

EXTAL

CL2

CL1

Not allowed Signal A Signal B

Figure 6.10 Notes on Board Design around External Crystal

Input of External Clock Signal

Circuit Configuration: An external clock signal can be input as shown in the examples in figure

6.11. In example (b) in figure 6.11, the external clock signal should be kept high during standby.

If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF.

EXTAL

XTAL

EXTAL

XTAL

74HC04

External clock input

Open

External clock input

(a) Connections with XTAL pin left open

(b) Connections with inverted clock input at XTAL pin

Figure 6.11 External Clock Input (Example)

External Clock Input: The external clock signal should have the same frequency as the desired

system clock (ø). Clock timing parameters are given in table 6.7 and figure 6.12.

Table 6.7 Clock Timing

VCC = 3.0 to 5.5 V

Item Symbol Min Max Unit Test Conditions

Low pulse width of external

clock input tEXL 40 —ns Figure 6.12

High pulse width of external

clock input tEXH 40 —ns

External clock rise time tEXr —10 ns

External clock fall time tEXf —10 ns

Clock pulse tCL 0.3 0.7 tcyc ø ≥ 5 MHz Figure 23.7

width low 0.4 0.6 tcyc ø < 5 MHz

Clock pulse tCH 0.3 0.7 tcyc ø ≥ 5 MHz

width high 0.4 0.6 tcyc ø < 5 MHz

tEXH tEXL

tEXt

tEXr

VCC × 0.5

EXTAL

Figure 6.12 External Clock Input Timing

Table 6.8 lists the external clock output stabilization delay time. Figure 6.13 shows the timing for

the external clock output stabilization delay time. The oscillator and duty correction circuit have

the function of regulating the waveform of the external clock input to the EXTAL pin. When the

specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after

the elapse of the external clock output stabilization delay time (tDEXT). As clock signal output is not

confirmed during the tDEXT period, the reset signal should be driven low and the reset state

maintained during this time.

Table 6.8 External Clock Output Stabilization Delay Time

Conditions: VCC = 3.0 to 5.5 V, AVCC = 2.7 to 5.5 V, VSS = AVSS = 0 V

Item Symbol Min Max Unit Notes

External clock output stabilization

delay time tDEXT*500 —µs Figure 6.13

Note: *tDEXT includes a 10 tcyc RES pulse width (tRESW).

VCC

STBY

EXTAL

ø (internal and

external)

RES

tDEXT*

Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).

3.0 V

VIH

Figure 6.13 External Clock Output Stabilization Delay Time

6.3 Duty Adjustment Circuit

When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle of

the signal from the oscillator circuit to generate the system clock (ø).

6.4 Prescaler

The clock for the on-chip supporting modules (øP) has either the same frequency as the system

clock (ø) or this frequency divided by two, depending on the CKDBL bit. The prescaler divides

the frequency of øP to generate internal clock signals with frequencies from øP/2 to øP/4096.

100

101

Section 7 I/O Ports

7.1 Overview

The H8/3437 Series has eight 8-bit input/output ports, one 7-bit input/output port, and one 3-bit

input/output port, and are 8-bit input port.

Table 7.1 lists the functions of each port in each operating mode. As table 7.1 indicates, the port

pins are multiplexed, and the pin functions differ depending on the operating mode.

Each port has a data direction register (DDR) that selects input or output, and a data register (DR)

that stores output data. If bit manipulation instructions will be executed on the port data direction

registers, see “Notes on Bit Manipulation Instructions” in section 2.5.5, Bit Manipulations.

Ports 1, 2, 3, 4, 6, 9, A, and B can drive one TTL load and a 90-pF capacitive load. Ports 5 and 8

can drive one TTL load and a 30-pF capacitive load. Ports 1 and 2 can drive LEDs (with 10-mA

current sink). Ports 1 to 6, 8, 9, A, and B can drive a darlington transistor. Ports 1 to 3, 6, A, and B

have built-in MOS pull-up transistors.

For block diagrams of the ports, see appendix C, I/O Port Block Diagrams.

Pins P86 in port 8, P97 in port 9, and PA4, PA5, PA6, and PA7 in port A can be driven to operate as

bus buffers. For details, see section 13, I2C Bus Interface.

102

Table 7.1 Port Functions

Expanded

Modes Single-Chip

Mode

Port Description Pins Mode 1 Mode 2 Mode 3

Port 1 • 8-bit I/O port

• Can drive LEDs

• Built-in input

pull-ups

P17 to P10/A7 to A0Lower address

output (A7 to A0)Lower address

output (A7 to A0)

or general input

General

input/output

Port 2 • 8-bit I/O port

• Can drive LEDs

• Built-in input

pull-ups

P27 to P20/A15 to A8Upper address

output (A15 to A8)Upper address

output (A15 to A8)

or general input

General

input/output

Port 3 • 8-bit I/O port

• Built-in input

pull-ups

• HIF data bus

P37 to P30/

D7 to D0/

HDB7 to HDB0

Data bus

(D7 to D0)Data bus

(D7 to D0)HIF data bus

(HDB7 to

HDB0) or

general input/

output

Port 4 • 8-bit I/O port P47/PW1

P46/PW0

PWM timer 0/1 output (PW0, PW1), or general

input/output

P45/TMRI1/HIRQ12

P44/TMO1/HIRQ1

P43/TMCI1/HIRQ11

8-bit timer 1 input/output (TMCI1, TMO1, TMRI1), host

processor interrupt request output from HIF (HIRQ11,

HIRQ1, HIRQ12), or general input/output

P42/TMRI0

P41/TMO0

P40/TMCI0

8-bit timer 0 input/output (TMCI0, TMO0, TMRI0) or

general input/output

Port 5 • 3-bit I/O port P52/SCK0

P51/RxD0

P50/TxD0

Serial communication interface 0 input/output (TxD0,

RxD0, SCK0) or general input/output

Port 6 • 8-bit I/O port

• Built-in input

pull-ups

• Key-sense

interrupt inputs

P67/KEYIN7/IRQ7

P66/KEYIN6/FTOB/IRQ6

P65/KEYIN5/FTID

P64/KEYIN4/FTIC

P63/KEYIN3/FTIB

P62/KEYIN2/FTIA

P61/KEYIN1/FTOA

P60/KEYIN0/FTCI

16-bit free-running timer input/output (FTCI, FTOA,

FTIA, FTIB, FTIC, FTID, FTOB), key-sense interrupt

input (KEYIN7 to KEYIN0), external interrupt input (IRQ7,

IRQ6), or general input/output

Port 7 • 8-bit I/O port P77/AN7/DA1

P76/AN6/DA0

Analog input to A/D converter (AN7, AN6), analog output

from D/A converter (DA1, DA0), or general input

P75 to P70/

AN5 to AN0

Analog input to A/D converter (AN5 to AN0) or general

input

103

Expanded

Modes Single-Chip

Mode

Port Description Pins Mode 1 Mode 2 Mode 3

Port 8 • 7-bit I/O port

• Can drive a bus

line (P86)

P86/IRQ5/SCK1/SCL

P85/IRQ4/RxD1/CS2

P84/IRQ3/TxD1/IOW

Serial communication interface 1 input/output (TxD1,

RxD1, SCK1), HIF control input (CS2, IOW), I2C clock

input/output (SCL), external interrupt input (IRQ5 to

IRQ3), or general input/output

P83/IOR

P82/CS1

P81/GA20

P80/HA0

HIF control input/output (HA0, GA20, CS1, IOR), or

general input/output

Port 9 • 8-bit I/O port

• Can drive a bus

line (P97)

P97/WAIT/SDA Expanded data bus control input

(WAIT), I2C data input/output (SDA),

or general input/output

I2C data

input/output

(SDA) or

general input/

output

P96/ø System clock (ø)

output System clock (ø)

output ø output or

general input

P95/AS

P94/WR

P93/RD

Expanded data bus control output

(RD, WR, AS)General

input/output

P92/IRQ0

P91/IRQ1/EIOW

P90/IRQ2/ECS2/ADTRG

HIF control input (ECS2, EIOW), trigger input to A/D

converter (ADTRG), external interrupt input (IRQ2 to

IRQ0), or general input/output

Port A • 8-bit I/O port

• Built-in input

pull-ups

• Key-sense

interrupt inputs

• Can drive bus

lines (PA4, PA5,

PA6, PA7)

PA7 to PA0/

KEYIN15 to KEYIN8

Key-sense interrupt input (KEYIN15 to KEYIN8) or

general input/output

Port B • 8-bit I/O port

• HIF data bus

• Built-in input

pull-up MOS

PB7 to PB0/

XDB7 to XDB0

HIF data bus (XDB7 to XDB0) or

general input/output General

input/output

104

7.2 Port 1

7.2.1 Overview

Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7.1. The pin

functions differ depending on the operating mode.

Port 1 has built-in, programmable MOS input pull-up transistors that can be used in modes 2 and

Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and

darlington transistors.

P17/A7

P16/A6

P15/A5

P14/A4

P13/A3

P12/A2

P11/A1

P10/A0

Port 1

Port 1 pins

A7 (output)

A6 (output)

A5 (output)

A4 (output)

A3 (output)

A2 (output)

A1 (output)

A0 (output)

Pin configuration

in mode 1

(expanded mode

with on-chip ROM

disabled)

A7 (output)/P17 (input)

A6 (output)/P16 (input)

A5 (output)/P15 (input)

A4 (output)/P14 (input)

A3 (output)/P13 (input)

A2 (output)/P12 (input)

A1 (output)/P11 (input)

A0 (output)/P10 (input)

Pin configuration

in mode 2

(expanded mode

with on-chip ROM

enabled)

P17 (input/output)

P16 (input/output)

P15 (input/output)

P14 (input/output)

P13 (input/output)

P12 (input/output)

P11 (input/output)

P10 (input/output)

Pin configuration in mode 3

(single-chip mode)

Figure 7.1 Port 1 Pin Configuration

105

7.2.2 Register Configuration and Descriptions

Table 7.2 summarizes the port 1 registers.

Table 7.2 Port 1 Registers

Name Abbreviation Read/Write Initial Value Address

Port 1 data direction register P1DDR W H'FF (mode 1)

H'00 (modes 2 and 3) H'FFB0

Port 1 data register P1DR R/W H'00 H'FFB2

Port 1 input pull-up control

Port 1 Data Direction Register (P1DDR)

Bit 76543210

P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR

Mode 1

Initial value 1 1 1 1 1 1 1 1

Read/Write ————————

Modes 2 and 3

Initial value 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

P1DDR controls the input/output direction of each pin in port 1.

Mode 1: The P1DDR values are fixed at 1. Port 1 consists of lower address output pins. P1DDR

values cannot be modified and are always read as 1.

In hardware standby mode, the address bus is in the high-impedance state.

Mode 2: A pin in port 1 is used for address output if the corresponding P1DDR bit is set to 1, and

for general input if this bit is cleared to 0.

Mode 3: A pin in port 1 is used for general output if the corresponding P1DDR bit is set to 1, and

for general input if this bit is cleared to 0.

In modes 2 and 3, P1DDR is a write-only register. Read data is invalid. If read, all bits always read

1. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby

mode it retains its existing values, so if a transition to software standby mode occurs while a

P1DDR bit is set to 1, the corresponding pin remains in the output state.

106

Port 1 Data Register (P1DR)

Bit 76543210

P17P16P15P14P13P12P11P10

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

P1DR is an 8-bit register that stores data for pins P17 to P10. When a P1DDR bit is set to 1, if port

1 is read, the value in P1DR is obtained directly, regardless of the actual pin state. When a P1DDR

bit is cleared to 0, if port 1 is read the pin state is obtained.

P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

Port 1 Input Pull-Up Control Register (P1PCR)

Bit 76543210

P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. If

a P1DDR bit is cleared to 0 (designating input) and the corresponding P1PCR bit is set to 1, the

input pull-up transistor is turned on.

P1PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

107

7.2.3 Pin Functions in Each Mode

Port 1 has different pin functions in different modes. A separate description for each mode is given

below.

Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 is

automatically used for lower address output (A7 to A0). Figure 7.2 shows the pin functions in

mode 1.

A7 (output)

A6 (output)

A5 (output)

A4 (output)

A3 (output)

A2 (output)

A1 (output)

A0 (output)

Port 1

Figure 7.2 Pin Functions in Mode 1 (Port 1)

108

Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower

address output pins and general input pins. Each pin becomes a lower address output pin if its

P1DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins

are input pins. To be used for address output, their P1DDR bits must be set to 1. Figure 7.3 shows

the pin functions in mode 2.

A7 (output)

A6 (output)

A5 (output)

A4 (output)

A3 (output)

A2 (output)

A1 (output)

A0 (output)

When P1DDR = 1

P17 (input)

P16 (input)

P15 (input)

P14 (input)

P13 (input)

P12 (input)

P11 (input)

P10 (input)

When P1DDR = 0

Port 1

Figure 7.3 Pin Functions in Mode 2 (Port 1)

Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected

individually. A pin becomes a general input pin when its P1DDR bit is cleared to 0 and a general

output pin when this bit is set to 1. Figure 7.4 shows the pin functions in mode 3.

P17 (input/output)

P16 (input/output)

P15 (input/output)

P14 (input/output)

P13 (input/output)

P12 (input/output)

P11 (input/output)

P10 (input/output)

Port 1

Figure 7.4 Pin Functions in Mode 3 (Port 1)

109

7.2.4 Input Pull-Up Transistors

Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The

pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or

3, set the corresponding P1PCR bit to 1 and clear the corresponding P1DDR bit to 0. P1PCR is

cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software

standby mode, the previous state is maintained.

Table 7.3 indicates the states of the input pull-up transistors in each operating mode.

Table 7.3 States of Input Pull-Up Transistors (Port 1)

Mode Reset Hardware Standby Software Standby Other Operating Modes

1 Off Off Off Off

2 Off Off On/off On/off

3 Off Off On/off On/off

Notes: Off: The input pull-up transistor is always off.

On/off: The input pull-up transistor is on if P1PCR = 1 and P1DDR = 0, but off otherwise.

110

7.3 Port 2

7.3.1 Overview

Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7.5. The pin

functions differ depending on the operating mode.

Port 2 has built-in, programmable MOS input pull-up transistors that can be used in modes 2 and

Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and

darlington transistors.

P27/A15

P26/A14

P25/A13

P24/A12

P23/A11

P22/A10

P21/A9

P20/A8

Port 2

Port 2 pins

A15 (output)

A14 (output)

A13 (output)

A12 (output)

A11 (output)

A10 (output)

A9 (output)

A8 (output)

Pin configuration

in mode 1

(expanded mode

with on-chip ROM

disabled)

A15 (output)/P27 (input)

A14 (output)/P26 (input)

A13 (output)/P25 (input)

A12 (output)/P24 (input)

A11 (output)/P23 (input)

A10 (output)/P22 (input)

A9 (output)/P21 (input)

A8 (output)/P20 (input)

Pin configuration

in mode 2

(expanded mode

with on-chip ROM

enabled)

P27 (input/output)

P26 (input/output)

P25 (input/output)

P24 (input/output)

P23 (input/output)

P22 (input/output)

P21 (input/output)

P20 (input/output)

Pin configuration in mode 3

(single-chip mode)

Figure 7.5 Port 2 Pin Configuration

111

7.3.2 Register Configuration and Descriptions

Table 7.4 summarizes the port 2 registers.

Table 7.4 Port 2 Registers

Name Abbreviation Read/Write Initial Value Address

Port 2 data direction register P2DDR W H'FF (mode 1)

H'00 (modes 2 and 3) H'FFB1

Port 2 data register P2DR R/W H'00 H'FFB3

Port 2 input pull-up control

Port 2 Data Direction Register (P2DDR)

Bit 76543210

P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR

Mode 1

Initial value 1 1 1 1 1 1 1 1

Read/Write ————————

Modes 2 and 3

Initial value 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

P2DDR controls the input/output direction of each pin in port 2.

Mode 1: The P2DDR values are fixed at 1. Port 2 consists of upper address output pins. P2DDR

values cannot be modified and are always read as 1.

In hardware standby mode, the address bus is in the high-impedance state.

Mode 2: A pin in port 2 is used for address output if the corresponding P2DDR bit is set to 1, and

for general input if this bit is cleared to 0.

Mode 3: A pin in port 2 is used for general output if the corresponding P2DDR bit is set to 1, and

for general input if this bit is cleared to 0.

In modes 2 and 3, P2DDR is a write-only register. Read data is invalid. If read, all bits always read

1. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby

mode it retains its existing values, so if a transition to software standby mode occurs while a

P2DDR bit is set to 1, the corresponding pin remains in the output state.

112

Port 2 Data Register (P2DR)

Bit 76543210

P27P26P25P24P23P22P21P20

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

P2DR is an 8-bit register that stores data for pins P27 to P20. When a P2DDR bit is set to 1, if port

2 is read, the value in P2DR is obtained directly, regardless of the actual pin state. When a P2DDR

bit is cleared to 0, if port 2 is read the pin state is obtained.

P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

Port 2 Input Pull-Up Control Register (P2PCR)

Bit 76543210

P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P10PCR

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. If

a P2DDR bit is cleared to 0 (designating input) and the corresponding P2PCR bit is set to 1, the

input pull-up transistor is turned on.

P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

113

7.3.3 Pin Functions in Each Mode

Port 2 has different pin functions in different modes. A separate description for each mode is given

below.

Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 is

automatically used for upper address output (A15 to A8). Figure 7.6 shows the pin functions in

mode 1.

A15 (output)

A14 (output)

A13 (output)

A12 (output)

A11 (output)

A10 (output)

A9 (output)

A8 (output)

Port 2

Figure 7.6 Pin Functions in Mode 1 (Port 2)

114

Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper

address output pins and general input pins. Each pin becomes an upper address output pin if its

P2DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins

are input pins. To be used for address output, their P2DDR bits must be set to 1. Figure 7.7 shows

the pin functions in mode 2.

A15 (output)

A14 (output)

A13 (output)

A12 (output)

A11 (output)

A10 (output)

A9 (output)

A8 (output)

When P2DDR = 1

P27 (input)

P26 (input)

P25 (input)

P24 (input)

P23 (input)

P22 (input)

P21 (input)

P20 (input)

When P2DDR = 0

Port 2

Figure 7.7 Pin Functions in Mode 2 (Port 2)

Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected

individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0, and a general

output pin when this bit is set to 1. Figure 7.8 shows the pin functions in mode 3.

P27 (input/output)

P26 (input/output)

P25 (input/output)

P24 (input/output)

P23 (input/output)

P22 (input/output)

P21 (input/output)

P20 (input/output)

Port 2

Figure 7.8 Pin Functions in Mode 3 (Port 2)

115

7.3.4 Input Pull-Up Transistors

Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The

pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or

3, set the corresponding P2PCR bit to 1 and clear the corresponding P2DDR bit to 0. P2PCR is

cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software

standby mode, the previous state is maintained.

Table 7.5 indicates the states of the input pull-up transistors in each operating mode.

Table 7.5 States of Input Pull-Up Transistors (Port 2)

Mode Reset Hardware Standby Software Standby Other Operating Modes

1 Off Off Off Off

2 Off Off On/off On/off

3 Off Off On/off On/off

Notes: Off: The input pull-up transistor is always off.

On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0, but off otherwise.

116

7.4 Port 3

7.4.1 Overview

Port 3 is an 8-bit input/output port that is multiplexed with the data bus and host interface data bus.

Figure 7.9 shows the pin configuration of port 3. The pin functions differ depending on the

operating mode.

Port 3 has built-in, programmable MOS input pull-up transistors that can be used in mode 3.

Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor.

P37/D7/HDB7

P36/D6/HDB6

P35/D5/HDB5

P34/D4/HDB4

P33/D3/HDB3

P32/D2/HDB2

P31/D1/HDB1

P30/D0/HDB0

Port 3

Port 3 pins

D7 (input/output)

D6 (input/output)

D5 (input/output)

D4 (input/output)

D3 (input/output)

D2 (input/output)

D1 (input/output)

D0 (input/output)

Pin configuration in mode 1

(expanded mode with on-chip

ROM disabled) and mode 2

(expanded mode with on-chip

ROM enabled)

P37 (input/output)

P36 (input/output)

P35 (input/output)

P34 (input/output)

P33 (input/output)

P32 (input/output)

P31 (input/output)

P30 (input/output)

Pin configuration in mode 3 (single-chip mode)

Master mode

HDB7 (input/output)

HDB6 (input/output)

HDB5 (input/output)

HDB4 (input/output)

HDB3 (input/output)

HDB2 (input/output)

HDB1 (input/output)

HDB0 (input/output)

Slave mode

Figure 7.9 Port 3 Pin Configuration

117

7.4.2 Register Configuration and Descriptions

Table 7.6 summarizes the port 3 registers.

Table 7.6 Port 3 Registers

Name Abbreviation Read/Write Initial Value Address

Port 3 data direction register P3DDR W H'00 H'FFB4

Port 3 data register P3DR R/W H'00 H'FFB6

Port 3 input pull-up control

Port 3 Data Direction Register (P3DDR)

Bit 76543210

P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR

Initial value 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

P3DDR is an 8-bit register that controls the input/output direction of each pin in port 3. P3DDR is

a write-only register. Read data is invalid. If read, all bits always read 1.

Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded

mode with on-chip ROM enabled), the input/output directions designated by P3DDR are ignored.

Port 3 automatically consists of the input/output pins of the 8-bit data bus (D7 to D0).

The data bus is in the high-impedance state during reset, and during hardware and software

standby.

Mode 3: A pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1, and

for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in hardware

standby mode. In software standby mode it retains its existing values, so if a transition to software

standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in the output

state.

118

Port 3 Data Register (P3DR)

Bit 76543210

P37P36P35P34P33P32P31P30

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

P3DR is an 8-bit register that stores data for pins P37 to P30. When a P3DDR bit is set to 1, if port

3 is read, the value in P3DR is obtained directly, regardless of the actual pin state. When a P3DDR

bit is cleared to 0, if port 3 is read the pin state is obtained.

P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

Port 3 Input Pull-Up Control Register (P3PCR)

Bit 76543210

P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

P3PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. If

a P3DDR bit is cleared to 0 (designating input) and the corresponding P3PCR bit is set to 1, the

input pull-up transistor is turned on.

P3PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

The input pull-ups cannot be used in slave mode (when the host interface is enabled).

119

7.4.3 Pin Functions in Each Mode

Port 3 has different pin functions in different modes. A separate description for each mode is given

below.

Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and

mode 2 (expanded mode with on-chip ROM enabled), port 3 is automatically used for the

input/output pins of the data bus (D7 to D0). Figure 7.10 shows the pin functions in modes 1 and 2.

D7 (input/output)

D6 (input/output)

D5 (input/output)

D4 (input/output)

D3 (input/output)

D2 (input/output)

D1 (input/output)

D0 (input/output)

Port 3

Modes 1 and 2

Figure 7.10 Pin Functions in Modes 1 and 2 (Port 3)

120

Mode 3: In mode 3 (single-chip mode), when the host interface enable bit (HIE) is cleared to 0 in

the system control register (SYSCR), port 3 is a general-purpose input/output port. A pin becomes

an output pin when its P3DDR bit is set to 1, and an input pin when this bit is cleared to 0.

When the HIE bit is set to 1, selecting slave mode, port 3 becomes the host interface data bus

(HDB7 to HDB0). For details, see section 14, Host Interface.

Figure 7.11 shows the pin functions in mode 3.

P37 (input/output)/HDB7 (input/output)

P36 (input/output)/HDB6 (input/output)

P35 (input/output)/HDB5 (input/output)

P34 (input/output)/HDB4 (input/output)

P33 (input/output)/HDB3 (input/output)

P32 (input/output)/HDB2 (input/output)

P31 (input/output)/HDB1 (input/output)

P30 (input/output)/HDB0 (input/output)

Port 3

Figure 7.11 Pin Functions in Mode 3 (Port 3)

7.4.4 Input Pull-Up Transistors

Port 3 has built-in programmable input pull-up transistors that are available in mode 3. The pull-up

for each bit can be turned on and off individually. To turn on an input pull-up in mode 3, set the

corresponding P3PCR bit to 1 and clear the corresponding P3DDR bit to 0. P3PCR is cleared to

H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby

mode, the previous state is maintained.

Table 7.7 indicates the states of the input pull-up transistors in each operating mode.

Table 7.7 States of Input Pull-Up Transistors (Port 3)

Mode Reset Hardware Standby Software Standby Other Operating Modes

1 Off Off Off Off

2 Off Off Off Off

3 Off Off On/off On/off

Notes: Off: The input pull-up transistor is always off.

On/off: The input pull-up transistor is on if P3PCR = 1 and P3DDR = 0, but off otherwise.

121

7.5 Port 4

7.5.1 Overview

Port 4 is an 8-bit input/output port that is multiplexed with input/output pins (TMRI0, TMRI1,

TMCI0, TMCI1, TMO0, TMO1) of 8-bit timers 0 and 1 and output pins (PW0, PW1) of PWM timers

0 and 1. In slave mode, P43 to P45 output host interrupt requests. Pins not used by timers or for

host interrupt requests are available for general input/output.

Figure 7.12 shows the pin configuration of port 4.

Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor.

P47/PW1

P46/PW0

P45/TMRI1/HIRQ12

P44/TMO1/HIRQ1

P43/TMCI1/HIRQ11

P42/TMRI0

P41/TMO0

P40/TMCI0

Port 4

Port 4 pins

P47 (input/output)/PW1 (output)

P46 (input/output)/PW0 (output)

P45 (input/output)/TMRI1 (input)

P44 (input/output)/TMO1 (output)

P43 (input/output)/TMCI1 (input)

P42 (input/output)/TMRI0 (input)

P41 (input/output)/TMO0 (output)

P40 (input/output)/TMCI0 (input)

Pin configuration in modes 1 to 3

Master mode

P47 (input/output)/PW1 (output)

P46 (input/output)/PW0 (output)

HIRQ12 (output)/TMRI1 (input)

HIRQ1 (output)/TMO1 (output)

HIRQ11 (output)/TMCI1 (input)

P42 (input/output)/TMRI0 (input)

P41 (input/output)/TMO0 (output)

P40 (input/output)/TMCI0 (input)

Slave mode

Figure 7.12 Port 4 Pin Configuration

122

7.5.2 Register Configuration and Descriptions

Table 7.8 summarizes the port 4 registers.

Table 7.8 Port 4 Registers

Name Abbreviation Read/Write Initial Value Address

Port 4 data direction register P4DDR W H'00 H'FFB5

Port 4 data register P4DR R/W H'00 H'FFB7

Port 4 Data Direction Register (P4DDR)

Bit 76543210

P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR

Initial value 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

P4DDR is an 8-bit register that controls the input/output direction of each pin in port 4. A pin

functions as an output pin if the corresponding P4DDR bit is set to 1, and as an input pin if this bit

is cleared to 0.

P4DDR is a write-only register. Read data is invalid. If read, all bits always read 1.

P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its existing values, so if a transition to software standby mode occurs while a P4DDR bit

is set to 1, the corresponding pin remains in the output state.

If a transition to software standby mode occurs while port 4 is being used by an on-chip

supporting module (for example, for 8-bit timer output), the on-chip supporting module will be

initialized, so the pin will revert to general-purpose input/output, controlled by P4DDR and P4DR.

123

Port 4 Data Register (P4DR)

Bit 76543210

P47P46P45P44P43P42P41P40

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

P4DR is an 8-bit register that stores data for pins P47 to P40. When a P4DDR bit is set to 1, if port

4 is read, the value in P4DR is obtained directly, regardless of the actual pin state. When a P4DDR

bit is cleared to 0, if port 4 is read the pin state is obtained. This also applies to pins used by on-

chip supporting modules.

P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

124

7.5.3 Pin Functions

Port 4 has different pin functions depending on whether the chip is or is not operating in slave

mode. Table 7.9 indicates the pin functions of port 4.

Table 7.9 Port 4 Pin Functions

Pin Pin Functions and Selection Method

P47/PW1Bit OE in TCR of PWM timer 1 and bit P47DDR select the pin function as follows

OE 0 1

P47DDR 0101

Pin function P47 input P47 output PW1 output

P46/PW0Bit OE in TCR of PWM timer 0 and bit P46DDR select the pin function as follows

OE 0 1

P46DDR 0101

Pin function P46 input P46 output PW0 output

P45/TMRI1/ Bit P45DDR and the operating mode select the pin function as follows

HIRQ12 P45DDR 0 1

Operating mode —Not slave mode Slave mode

Pin function P45 input P45 output HIRQ12 output

TMRI1 input*

Note: *TMRI1 input is usable when bits CCLR1 and CCLR0 are both set to 1 in

TCR of 8-bit timer 1

P44/TMO1/

HIRQ1

Bits OS3 to OS0 in TCSR of 8-bit timer 1, bit P44DDR, and the operating mode

select the pin function as follows

OS3 to 0 All 0 Not all 0

P44DDR 0 1 —

Operating mode —Not slave

mode Slave mode —

Pin function P44 input P44 output HIRQ1 output TMO1 output

125

Pin Pin Functions and Selection Method

P43/TMCI1/ Bit P43DDR and the operating mode select the pin function as follows

HIRQ11 P43DDR 0 1

Operating mode —Not slave mode Slave mode

Pin function P43 input P43 output HIRQ11 output

TMCI1 input*

Note: *TMCI1 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1

select an external clock source

P42/TMRI0P42DDR 0 1

Pin function P42 input P42 output

TMRI0 input*

Note: *TMRI0 input is usable when bits CCLR1 and CCLR0 are both set to 1 in

TCR of 8-bit timer 0

P41/TMO0Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit P41DDR select the pin function

as follows

OS3 to 0 All 0 Not all 0

P41DDR 0101

Pin function P41 input P41 output TMO0 output

P40/TMCI0

P40DDR 0 1

Pin function P40 input P40 output

TMCI0 input*

Note: *TMCI0 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0

select an external clock source

126

7.6 Port 5

7.6.1 Overview

Port 5 is a 3-bit input/output port that is multiplexed with input/output pins (TxD0, RxD0, SCK0) of

serial communication interface 0. The port 5 pin functions are the same in all operating modes.

Figure 7.13 shows the pin configuration of port 5.

Pins in port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a

darlington transistor.

P52 (input/output)/SCK0 (input/output)

P51 (input/output)/RxD0 (input)

P50 (input/output)/TxD0 (output)

Port 5 pins

Port 5

Figure 7.13 Port 5 Pin Configuration

7.6.2 Register Configuration and Descriptions

Table 7.10 summarizes the port 5 registers.

Table 7.10 Port 5 Registers

Name Abbreviation Read/Write Initial Value Address

Port 5 data direction register P5DDR W H'F8 H'FFB8

Port 5 data register P5DR R/W H'F8 H'FFBA

127

Port 5 Data Direction Register (P5DDR)

Bit 76543210

—————P52DDR P51DDR P50DDR

Initial value 1 1 1 1 1 0 0 0

Read/Write —————WWW

P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin

functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this bit

is cleared to 0.

P5DDR is a write-only register. Read data is invalid. If read, all bits always read 1.

P5DDR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode

it retains its existing values, so if a transition to software standby mode occurs while a P5DDR bit

is set to 1, the corresponding pin remains in the output state.

If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI will

be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR and

P5DR.

Port 5 Data Register (P5DR)

Bit 76543210

—————P52P51P50

Initial value 1 1 1 1 1 0 0 0

Read/Write —————R/W R/W R/W

P5DR is an 8-bit register that stores data for pins P52 to P50. Bits 7 to 3 are reserved. They cannot

be modified, and are always read as 1.

When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless

of the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is obtained.

This also applies to pins used as SCI pins.

P5DR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

128

7.6.3 Pin Functions

Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI0

input/output pins. Table 7.11 indicates the pin functions of port 5.

Table 7.11 Port 5 Pin Functions

Pin Pin Functions and Selection Method

P52/SCK0Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0, and bit P52DDR

select the pin function as follows

CKE1 0 1

C/A01—

CKE0 0 1 ——

P52DDR 0 1 ———

Pin function P52

input P52

output SCK0

input

P51/RxD0Bit RE in SCR of SCI0 and bit P51DDR select the pin function as follows

RE 0 1

P51DDR 0 1 —

Pin function P51 input P51 output RxD0 input

P50/TxD0Bit TE in SCR of SCI0 and bit P50DDR select the pin function as follows

TE 0 1

P50DDR 0 1 —

Pin function P50 input P50 output TxD0 output

129

7.7 Port 6

7.7.1 Overview

Port 6 is an 8-bit input/output port that is multiplexed with input/output pins (FTOA, FTOB, FTIA

to FTID, FTCI) of the 16-bit free-running timer (FRT), with key-sense input pins, and with IRQ6

and IRQ7 input pins. The port 6 pin functions are the same in all operating modes. Figure 7.14

shows the pin configuration of port 6.

Port 6 has built-in, programmable MOS input pull-up transistors.

Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor.

P67 (input/output)/IRQ7 (input)/KEYIN7 (input)

P66 (input/output)/FTOB (output)/IRQ6 (input)/KEYIN6 (input)

P65 (input/output)/FTID (input)/KEYIN5 (input)

P64 (input/output)/FTIC (input)/KEYIN4 (input)

P63 (input/output)/FTIB (input)/KEYIN3 (input)

P62 (input/output)/FTIA (input)/KEYIN2 (input)

P61 (input/output)/FTOA (output)/KEYIN1 (input)

P60 (input/output)/FTCI (input)/KEYIN0 (input)

Port 6

Port 6 pins

Figure 7.14 Port 6 Pin Configuration

7.7.2 Register Configuration and Descriptions

Table 7.12 summarizes the port 6 registers.

Table 7.12 Port 6 Registers

Name Abbreviation Read/Write Initial Value Address

Port 6 data direction register P6DDR W H'00 H'FFB9

Port 6 data register P6DR R/W H'00 H'FFBB

Port 6 input pull-up control

130

Port 6 Data Direction Register (P6DDR)

Bit 76543210

P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR

Initial value 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

P6DDR is an 8-bit register that controls the input/output direction of each pin in port 6. A pin

functions as an output pin if the corresponding P6DDR bit is set to 1, and as an input pin if this bit

is cleared to 0.

P6DDR is a write-only register. Read data is invalid. If read, all bits always read 1.

P6DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its existing values, so if a transition to software standby mode occurs while a P6DDR bit

is set to 1, the corresponding pin remains in the output state.

If a transition to software standby mode occurs while port 6 is being used by the free-running

timer, the timer will be initialized, so the pin will revert to general-purpose input/output,

controlled by P6DDR and P6DR.

Port 6 Data Register (P6DR)

Bit 76543210

P67P66P65P64P63P62P61P60

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

P6DR is an 8-bit register that stores data for pins P67 to P60. When a P6DDR bit is set to 1, if port

6 is read, the value in P6DR is obtained directly, regardless of the actual pin state. When a P6DDR

bit is cleared to 0, if port 6 is read the pin state is obtained. This also applies to pins used as FRT

pins.

P6DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

131

Port 6 Input Pull-Up Control Register (KMPCR)

Bit 76543210

KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

KMPCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 6. If

a P6DDR bit is cleared to 0 (designating input) and the corresponding KMPCR bit is set to 1, the

input pull-up transistor is turned on.

KMPCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its existing values.

132

7.7.3 Pin Functions

Port 6 has the same pin functions in all operating modes. The pins are multiplexed with FRT

input/output, IRQ6 and IRQ7 input, and key-sense input. Table 7.13 indicates the pin functions of

port 6.

Table 7.13 Port 6 Pin Functions

Pin Pin Functions and Selection Method

P67/IRQ7/

KEYIN7P67DDR 0 1

Pin function P67 input P67 output

IRQ7 input* or KEYIN7 input

Note: *IRQ7 input is usable when bit IRQ7E is set to 1 in IER

P66/FTOB/ Bit OEB in TOCR of the FRT and bit P66DDR select the pin function as follows

IRQ6/KEYIN6OEB 0 1

P66DDR 0101

Pin function P66 input P66 output FTOB output

IRQ6 input* or KEYIN6 input

Note: *IRQ6 input is usable when bit IRQ6E is set to 1 in IER

P65/FTID/

KEYIN5P65DDR 0 1

Pin function P65 input P65 output

FTID input or KEYIN5 input

P64/FTIC/

KEYIN4P64DDR 0 1

Pin function P64 input P64 output

FTIC input or KEYIN4 input

133

Pin Pin Functions and Selection Method

P63/FTIB/

KEYIN3P63DDR 0 1

Pin function P63 input P63 output

FTIB input or KEYIN3 input

P62/FTIA/

KEYIN2P62DDR 0 1

Pin function P62 input P62 output

FTIA input or KEYIN2 input

P61/FTOA/ Bit OEA in TOCR of the FRT and bit P61DDR select the pin function as follows

KEYIN1OEA 0 1

P61DDR 0101

Pin function P61 input P61 output FTOA output

KEYIN1 input

P60/FTCI/

KEYIN0P60DDR 0 1

Pin function P60 input P60 output

FTCI input* or KEYIN0 input

Note: *FTCI input is usable when bits CKS1 to CKS0 in TCR of the FRT select

an external clock source

134

7.7.4 Input Pull-Up Transistors

Port 6 has built-in programmable input pull-up transistors. The pull-up for each bit can be turned

on and off individually. To turn on an input pull-up, set the corresponding KMPCR bit to 1 and

clear the corresponding P6DDR bit to 0. KMPCR is cleared to H'00 by a reset and in hardware

standby mode, turning all input pull-ups off. In software standby mode, the previous state is

maintained.

Table 7.14 indicates the states of the input pull-up transistors in each operating mode.

Table 7.14 States of Input Pull-Up Transistors (Port 6)

Mode Reset Hardware Standby Software Standby Other Operating Modes

1 Off Off On/off On/off

2 Off Off On/off On/off

3 Off Off On/off On/off

Notes: Off: The input pull-up transistor is always off.

On/off: The input pull-up transistor is on if KMPCR = 1 and P6DDR = 0, but off otherwise.

135

7.8 Port 7

7.8.1 Overview

Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter and

analog output pins for the D/A converter. The pin functions are the same in all modes. Figure 7.15

shows the pin configuration of port 7.

P77 (input)/AN7 (input)/DA1 (output)

P76 (input)/AN6 (input)/DA0 (output)

P75 (input)/AN5 (input)

P74 (input)/AN4 (input)

P73 (input)/AN3 (input)

P72 (input)/AN2 (input)

P71 (input)/AN1 (input)

P70 (input)/AN0 (input)

Port 7

Port 7 pins

Figure 7.15 Port 7 Pin Configuration

7.8.2 Register Configuration and Descriptions

Table 7.15 summarizes the port 7 registers. Port 7 is an input port, so there is no data direction

Table 7.15 Port 7 Register

Name Abbreviation Read/Write Initial Value Address

Port 7 input data register P7PIN R Undetermined H'FFBE

Note: The port 7 input data register (P7PIN) has the same address as the port B data direction

136

Port 7 Input Data Register (P7PIN)

Bit 76543210

P77P76P75P74P73P72P71P70

Initial value —*—*—*—*—*—*—*—*

Read/Write R R R R R R R R

Note: *Depends on the levels of pins P77 to P70.

When P7PIN is read, the pin states are always read. P7PIN is a read-only register and cannot be

written to. Write access results in writing to PBDDR.

7.9 Port 8

7.9.1 Overview

Port 8 is a 7-bit input/output port that is multiplexed with host interface (HIF) input pins (HA0,

GA20, CS1, IOR, IOW, CS2), with input/output pins (TxD1, RxD1, SCK1) of serial communication

interface 1, with the I2C clock input/output pin (SCL), and with interrupt input pins (IRQ5 to

IRQ3).

Figure 7.16 shows the pin configuration of port 8. The configuration of the pin functions of pins

P85 and P84 will depend on the value of bit STAC in STCR. Pins P86 and P83 to P80 are unaffected

by bit STAC.

Pins in port 8 can drive one TTL load and a 30-pF capacitive load. They can also drive a

darlington transistor. Pin P86 can be driven as a bus buffer, as shown in section 13, I2C Bus

Interface.

137

P86/SCK1/IRQ5/SCL

P85/RxD1/IRQ4/CS2

P84/TxD1/IRQ3/IOW

P83/IOR

P82/CS1

P81/GA20

P80/HA0

Port 8

Port 8 pins

P86 (input/output)/IRQ5 (input)/SCK1 (input/output)/SCL (output)

P85 (input/output)/IRQ4 (input)/RxD1 (input)

P84 (input/output)/IRQ3 (input)/TxD1 (output)

P83 (input/output)

P82 (input/output)

P81 (input/output)

P80 (input/output)

Pin configuration in master mode,

or when STAC bit is 1

Pin configuration in slave mode

When STAC bit is 0

P86 (input/output)/IRQ5 (input)/SCK1 (input/output)/SCL (input/output)

IRQ4 (input)/CS2 (input)

IRQ3 (input)/IOW (input)

IOR (input)

CS1 (input)

P81 (input/output)/GA20 (output)

HA0 (input)

Figure 7.16 Port 8 Pin Configuration

7.9.2 Register Configuration and Descriptions

Table 7.16 summarizes the port 8 registers.

Table 7.16 Port 8 Registers

Name Abbreviation Read/Write Initial Value Address

Port 8 data direction register P8DDR W H'80 H'FFBD

Port 8 data register P8DR R/W H'80 H'FFBF

Note: The port 8 data direction register (P8DDR) has the same address as the port B input data

138

Port 8 Data Direction Register (P8DDR)

Bit 76543210

—P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR

Initial value 1 0 0 0 0 0 0 0

Read/Write —WWWWWWW

P8DDR is an 8-bit register that controls the input/output direction of each pin in port 8. A pin

functions as an output pin if the corresponding P8DDR bit is set to 1, and as an input pin if this bit

is cleared to 0. P8DDR is a write-only register. Read data is invalid. If read, all bits always read 1.

Bit 7 is a reserved bit that always reads 1.

P8DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode

P8DDR retains its existing values, so if a transition to software standby mode occurs while a

P8DDR bit is set to 1, the corresponding pin remains in the output state.

Port 8 Data Register (P8DR)

Bit 76543210

—P86P85P84P83P82P81P80

Initial value 1 0 0 0 0 0 0 0

Read/Write —R/W R/W R/W R/W R/W R/W R/W

P8DR is an 8-bit register that stores data for pins P86 to P80. Bit 7 is a reserved bit that always

When a P8DDR bit is set to 1, if port 8 is read, the value in P8DR is obtained directly, regardless

of the actual pin state. When a P8DDR bit is cleared to 0, if port 8 is read the pin state is obtained.

This also applies to pins used by on-chip supporting modules.

P8DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it

retains its existing values.

139

7.9.3 Pin Functions

Pins P86 to P80 are multiplexed with HIF input/output, SCI1 input/output, I2C clock input/output,

and IRQ5 to IRQ3 input. Table 7.17 indicates the functions of pins P86 to P80.

Table 7.17 Port 8 Pin Functions

Pin Pin Functions and Selection Method

P86/IRQ5/

SCK1/SCL Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, bit ICE in ICCR,

and bit P86DDR select the pin function as follows

ICE 0 1

CKE1 0 1 —

C/A01——

CKE0 0 1 ———

P86DDR 0 1 ————

Pin function P86

input P86

output SCK1

intput SCL

input/

output

IRQ5 input*

Note: *IRQ5 input is usable when bit IRQ5E is set to 1 in IER

P85/IRQ4/

CS2/RxD1

Bit RE in SCR of SCI1, bit STAC in STCR, bit P85DDR, and the operating mode

select the pin function as follows

Operating mode Slave mode Not slave mode

STAC 0 1 —

RE —0101

P85DDR —01—01—

Pin function CS2

input P85

output RxD1

input P85

output RxD1

input

IRQ4 input*

Note: *IRQ4 input is usable when bit IRQ4E is set to 1 in IER

140

Pin Pin Functions and Selection Method

P84/IRQ3/

IOW/TxD1

Bit TE in SCR of SCI1, bit STAC in STCR, bit P84DDR, and the operating mode

select the pin function as follows

Operating mode Slave mode Not slave mode

STAC 0 1 —

TE —0101

P84DDR —01—01—

Pin function IOW

input P84

output TxD1

output P84

input P84

output TxD1

output

IRQ3 input*

Note: *IRQ3 input is usable when bit IRQ3E is set to 1 in IER

P83/IOR Bit P83DDR and the operating mode select the pin function as follows

Operating mode Slave mode Not slave mode

P83DDR —01

Pin function IOR input P83 input P83 output

P82/CS1Bit P82DDR and the operating mode select the pin function as follows

Operating mode Slave mode Not slave mode

P82DDR —01

Pin function CS1 input P82 input P82 output

P81/GA20 Bit P81DDR and the operating mode select the pin function as follows

P81DDR 0 1

FGA20E —01

Operating mode —Not slave

mode Slave mode

Pin function P81 input P81 output GA20 output

P80/HA0Bit P80DDR and the operating mode select the pin function as follows

Operating mode Slave mode Not slave mode

P80DDR —01

Pin function HA0 input P80 input P80 output

141

7.10 Port 9

7.10.1 Overview

Port 9 is an 8-bit input/output port that is multiplexed with interrupt input pins (IRQ0 to IRQ2),

input/output pins for bus control signals (RD, WR, AS, WAIT), an input pin (ADTRG) for the

A/D converter, an output pin (ø) for the system clock, host interface (HIF) input pins (ECS2,

EIOW), and the I2C data input/output pin (SDA). Figure 7.17 shows the pin configuration of port

9. The functions of pins P91 and P90 are configured according to bit STAC in STCR. Pins P97 to

P92 are unaffected by bit STAC.

Pins in port 9 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor. Pin P97 can be driven as a bus buffer, as shown in section 13, I2C Bus

Interface.

P97/WAIT/SDA

P96/ø

P95/AS

P94/WR

P93/RD

P92/IRQ0

Port 9

Port 9 pins

P97 (input/output)/WAIT (input)/SDA (input/output)

ø (output)

AS (output)

WR (output)

RD (output)

P92 (input/output)/IRQ0 (input)

Pin configuration in mode 1 (expanded mode

with on-chip ROM disabled) and mode 2

(expanded mode with on-chip ROM enabled)

P97 (input/output)/SDA (input/output)

P96 (input)/ø (output)

P95 (input/output)

P94 (input/output)

P93 (input/output)

P92 (input/output)/IRQ0 (input)

Pin configuration in mode 3 (single-chip mode)

Figure 7.17 Port 9 Pin Configuration

142

P91/IRQ1/EIOW

P90/IRQ2/ADTRG/ECS2

Port 9

P91 (input/output)/IRQ1 (input)

P90 (input/output)/IRQ2 (input)/ADTRG (input)

Pin configuration in master mode,

or when STAC bit is 0

Pin configuration in slave mode

when STAC bit is 1

IRQ1 (input)/EIOW (input)

IRQ2 (input)/ECS2 (input)

Figure 7.17 Port 9 Pin Configuration (cont)

7.10.2 Register Configuration and Descriptions

Table 7.18 summarizes the port 9 registers.

Table 7.18 Port 9 Registers

Name Abbreviation Read/Write Initial Value Address

Port 9 data direction register P9DDR W H'40 (modes 1 and 2)

H'00 (mode 3) H'FFC0

Port 9 data register P9DR R/W*1Undetermined*2H'FFC1

Notes: *1 Bit 6 is read-only.

*2 Bit 6 is undetermined. Other bits are initially 0.

143

Port 9 Data Direction Register (P9DDR)

Bit 76543210

P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR

Modes 1 and 2

Initial value 0 1 0 0 0 0 0 0

Read/Write W —WWWWWW

Mode 3

Initial value 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

P9DDR is an 8-bit register that controls the input/output direction of each pin in port 9. A pin

functions as an output pin if the corresponding P9DDR bit is set to 1, and as an input pin if this bit

is cleared to 0. In modes 1 and 2, P96DDR is fixed at 1 and cannot be modified.

P9DDR is a write-only register. Read data is invalid. If read, all bits always read 1.

P9DDR is initialized by a reset and in hardware standby mode. The initial value is H'40 in modes

1 and 2, and H'00 in mode 3. In software standby mode P9DDR retains its existing values, so if a

transition to software standby mode occurs while a P9DDR bit is set to 1, the corresponding pin

remains in the output state.

Port 9 Data Register (P9DR)

Bit 76543210

P97P96P95P94P93P92P91P90

Initial value 0 —*000000

Read/Write R/W R R/W R/W R/W R/W R/W R/W

Note: *Determined by the level at pin P96.

P9DR is an 8-bit register that stores data for pins P97 to P90. When a P9DDR bit is set to 1, if port

9 is read, the value in P9DR is obtained directly, regardless of the actual pin state, except for P96.

When a P9DDR bit is cleared to 0, if port 9 is read the pin state is obtained. This also applies to

pins used by on-chip supporting modules and for bus control signals. P96 always returns the pin

state.

P9DR pins other than P96 are initialized to 0 by a reset and in hardware standby mode. In software

standby mode it retains its existing values.

144

7.10.3 Pin Functions

Port 9 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode 3.

The pins are multiplexed with IRQ0 to IRQ2 input, bus control signal input/output, A/D converter

input, system clock (ø) output, host interface input (ECS2, EIOW), and I2C data input/output

(SDA). Table 7.19 indicates the pin functions of port 9.

Table 7.19 Port 9 Pin Functions

P97/WAIT/SDA Bit ICE in ICCR, bit P97DDR, the wait mode as determined by WSCR, and the

operating mode select the pin function as follows

Operating mode Modes 1 and 2 Mode 3

Wait mode WAIT

used WAIT

not used —

ICE —0101

P97DDR —01—01—

Pin function WAIT

input P97

output SDA

input/

output

P97

input P97

output SDA

input/

output

P96/øBit P96DDR and the operating mode select the pin function as follows

Operating mode Modes 1 and 2 Mode 3

P96DDR Always 1 0 1

Pin function ø output P96 input ø output

P95/AS Bit P95DDR and the operating mode select the pin function as follows

Operating mode Modes 1 and 2 Mode 3

P95DDR —01

Pin function AS output P95 input P95 output

P94/WR Bit P94DDR and the operating mode select the pin function as follows

Operating mode Modes 1 and 2 Mode 3

P94DDR —01

Pin function WR output P94 input P94 output

145

Pin Pin Functions and Selection Method

P93/RD Bit P93DDR and the operating mode select the pin function as follows

Operating mode Modes 1 and 2 Mode 3

P93DDR —01

Pin function RD output P93 input P93 output

P92/IRQ0P92DDR 0 1

Pin function P92 input P92 output

IRQ0 input*

Note: *IRQ0 input can be used when bit IRQ0E is set to 1 in IER

P91/IRQ1/

EIOW Bit STAC in STCR, bit P91DDR, and the operating mode select the pin function

as follows

Operating mode Slave mode Not slave mode

STAC 0 1 —

P91DDR 0 1 —01

Pin function P91 input P91 output EIOW

input P91 input P91 output

IRQ1 input*

Note: *IRQ1 input can be used when bit IRQ1E is set to 1 in IER

P90/IRQ2/

ADTRG/ECS2

Bit STAC in STCR, bit P90DDR, and the operating mode select the pin function

as follows

Operating mode Slave mode Not slave mode

STAC 0 1 —

P90DDR 0 1 —01

Pin function P90 input P90 output ECS2 input P90 input P90 output

IRQ2 input*1 and

ADTRG input*2

IRQ2

input*1

IRQ2 input*1 and

ADTRG input*2

Notes: *1IRQ2 input can be used when bit IRQ2E is set to 1 in IER

*2ADTRG input can be used when bit TRGE is set to 1 in ADCR

146

7.11 Port A

7.11.1 Overview

Port A is an 8-bit input/output port that is multiplexed with key-sense input pins. The port A pin

functions are the same in all operating modes. Figure 7.18 shows the pin configuration of port A.

Port A has built-in, programming MOS input pull-up transistors.

Pins in port A can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor. Pins PA4, PA5, PA6, and PA7 can be driven as bus buffers, as shown in

section 13, I2C Bus Interface.

PA7 (input/output)/KEYIN15 (input)

PA6 (input/output)/KEYIN14 (input)

PA5 (input/output)/KEYIN13 (input)

PA4 (input/output)/KEYIN12 (input)

PA3 (input/output)/KEYIN11 (input)

PA2 (input/output)/KEYIN10 (input)

PA1 (input/output)/KEYIN9 (input)

PA0 (input/output)/KEYIN8 (input)

Port A

Port A pins

Figure 7.18 Port A Pin Configuration

7.11.2 Register Configuration and Descriptions

Table 7.20 summarizes the port A registers.

Table 7.20 Port A Registers

Name Abbreviation Read/Write Initial Value Address

Port A data direction register PADDR W H'00 H'FFAB

Port A output data register PAODR R/W H'00 H'FFAA

Port A input data register PAPIN R Undetermined H'FFAB

Note: The data direction register (PADDR) and input data register (PAPIN) have the same

address.

147

Port A Data Direction Register (PADDR)

Bit 76543210

PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR

Initial value 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

PADDR is an 8-bit register that controls the input/output direction of each pin in port A. A pin

functions as an output pin if the corresponding PADDR bit is set to 1, and as an input pin if this bit

is cleared to 0.

PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its existing values, so if a transition to software standby mode occurs while a PADDR bit

is set to 1, the corresponding pin remains in the output state.

Port A Output Data Register (PAODR)

Bit 76543210

PA7PA6PA5PA4PA3PA2PA1PA0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

PAODR is an 8-bit register that stores data for pins PA7 to PA0. PAODR can always be written to

and read, regardless of the PADDR settings.

PAODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its existing values.

Port A Input Data Register (PAPIN)

Bit 76543210

PA7PA6PA5PA4PA3PA2PA1PA0

Initial value —*—*—*—*—*—*—*—*

Read/Write R R R R R R R R

Note: *Depends on the levels of pins PA7 to PA0.

When PAPIN is read, the pin states are always read.

148

7.11.3 Pin Functions in Each Mode

Port A has the same pin functions in all operating modes. Table 7.21 indicates the pin functions of

port A.

Table 7.21 Port A Pin Functions

Pin Pin Functions and Selection Method

PA7/KEYIN15 PA7DDR 0 1

Pin function PA7 input PA7 output

KEYIN15 input

This pin is driven as a bus buffer when bit IICS is set to 1 in STCR

PA6/KEYIN14 PA6DDR 0 1

Pin function PA6 input PA6 output

KEYIN14 input

This pin is driven as a bus buffer when bit IICS is set to 1 in STCR

PA5/KEYIN13 PA5DDR 0 1

Pin function PA5 input PA5 output

KEYIN13 input

This pin is driven as a bus buffer when bit IICS is set to 1 in STCR

PA4/KEYIN12 PA4DDR 0 1

Pin function PA4 input PA4 output

KEYIN12 input

This pin is driven as a bus buffer when bit IICS is set to 1 in STCR

PA3/KEYIN11 PA3DDR 0 1

Pin function PA3 input PA3 output

KEYIN11 input

149

Pin Pin Functions and Selection Method

PA2/KEYIN10 PA2DDR 0 1

Pin function PA2 input PA2 output

KEYIN10 input

PA1/KEYIN9PA1DDR 0 1

Pin function PA1 input PA1 output

KEYIN9 input

PA0/KEYIN8PA0DDR 0 1

Pin function PA0 input PA0 output

KEYIN8 input

7.11.4 Input Pull-Up Transistors

Port A has built-in programmable input pull-up transistors that are available in all modes.

An input pull-up transistor is turned on if 1 is written in the corresponding PAODR bit while the

corresponding PADDR bit is cleared to 0. The input pull-ups are turned off by a reset and in

hardware standby mode.

Table 7.22 indicates the states of the input pull-up transistors in each operating mode.

Table 7.22 States of Input Pull-Up Transistors (Port A)

Mode Reset Hardware Standby Software Standby Other Operating Modes

1 Off Off On/off On/off

2 Off Off On/off On/off

3 Off Off On/off On/off

Notes: Off: The input pull-up transistor is always off.

On/off: The input pull-up transistor is on if PAODR = 1 and PADDR = 0, but off otherwise.

150

7.12 Port B

7.12.1 Overview

Port B is an 8-bit input/output port that is multiplexed with the host interface data bus. The pin

functions differ depending on the operating mode. Figure 7.19 shows the pin configuration of port

Port B has program-controllable built-in MOS input pull-up transistors.

Pins in port B can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor.

PB7/XDB7

PB6/XDB6

PB5/XDB5

PB4/XDB4

PB3/XDB3

PB2/XDB2

PB1/XDB1

PB0/XDB0

Port B

Port B pins

PB7 (input/output)

PB6 (input/output)

PB5 (input/output)

PB4 (input/output)

PB3 (input/output)

PB2 (input/output)

PB1 (input/output)

PB0 (input/output)

Pin configuration in mode 1

(expanded mode with on-chip ROM

disabled) and mode 2 (expanded

mode with on-chip ROM enabled)

PB7 (input/output)

PB6 (input/output)

PB5 (input/output)

PB4 (input/output)

PB3 (input/output)

PB2 (input/output)

PB1 (input/output)

PB0 (input/output)

Pin configuration in mode 3

(single-chip mode)

Master mode

XDB7 (input/output)

XDB6 (input/output)

XDB5 (input/output)

XDB4 (input/output)

XDB3 (input/output)

XDB2 (input/output)

XDB1 (input/output)

XDB0 (input/output)

Slave mode

Figure 7.19 Port B Pin Configuration

151

7.12.2 Register Configuration and Descriptions

Table 7.23 summarizes the port B registers.

Table 7.23 Port B Registers

Name Abbreviation Read/Write Initial Value Address

Port B data direction register PBDDR W H'00 H'FFBE

Port B output data register PBODR R/W H'00 H'FFBC

Port B input data register PBPIN R Undetermind H'FFBD

Note: The port B data direction register (PBDDR) and port 7 input data register 7 (P7PIN) have

the same address.

Port B Data Direction Register (PBDDR)

Bit 76543210

PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR

Initial value 0 0 0 0 0 0 0 0

Read/Write W W W W W W W W

PBDDR is an 8-bit register that controls the input/output direction of each pin in port B. A pin

functions as an output pin if the corresponding PBDDR bit is set to 1, and as an input pin if this bit

is cleared to 0.

PBDDR is a write-only register. Read data is invalid. If read, the values of the port 7 data input

PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its existing values, so if a transition to software standby mode occurs while a PBDDR bit

is set to 1, the corresponding pin remains in the output state.

152

Port B Output Data Register (PBODR)

Bit 76543210

PB7PB6PB5PB4PB3PB2PB1PB0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

PBODR is an 8-bit register that stores data for pins PB7 to PB0. PBODR can always be written to

and read, regardless of the PBDDR settings.

PBODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its existing values.

Port B Input Data Register (PBPIN)

Bit 76543210

PB7PB6PB5PB4PB3PB2PB1PB0

Initial value —*—*—*—*—*—*—*—*

Read/Write R R R R R R R R

Note: *Depends on the levels of pins PB7 to PB0.

When PBPIN is read, the pin states are always read.

153

7.12.3 Pin Functions in Each Mode

Port B has different pin functions in different modes. A separate description for each mode is

given below.

Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and

mode 2 (expanded mode with on-chip ROM enabled), when the host interface enable bit (HIE) is

cleared to 0 in the system control register (SYSCR), port B is a general-purpose input/output port.

When the HIE bit is set to 1, selecting slave mode, port B becomes the host interface data bus

(XDB7 to XDB0). PBODR and PBDDR should be cleared to H'00 in slave mode. For details, see

section 14, Host Interface.

Figure 7.20 shows the pin functions in modes 1 and 2.

PB7 (input/output)/XDB7 (input/output)

PB6 (input/output)/XDB6 (input/output)

PB5 (input/output)/XDB5 (input/output)

PB4 (input/output)/XDB4 (input/output)

PB3 (input/output)/XDB3 (input/output)

PB2 (input/output)/XDB2 (input/output)

PB1 (input/output)/XDB1 (input/output)

PB0 (input/output)/XDB0 (input/output)

Port B

Figure 7.20 Pin Functions in Modes 1 and 2 (Port B)

154

Pin Functions in Mode 3: In mode 3 (single-chip mode), each pin can be designated for general

input or output. A pin becomes an output pin when its PBDDR bit is set to 1, and an input pin

when this bit is cleared to 0. Figure 7.21 shows the pin functions in mode 3.

PB7 (input/output)

PB6 (input/output)

PB5 (input/output)

PB4 (input/output)

PB3 (input/output)

PB2 (input/output)

PB1 (input/output)

PB0 (input/output)

Port B

Mode 3

Figure 7.21 Pin Functions in Mode 3 (Port B)

7.12.4 Input Pull-Up Transistors

Port B has built-in programmable input pull-up transistors that are available in mode 3. The pull-

up for each bit can be turned on and off individually.

An input pull-up transistor is turned on in mode 3 if 1 is written in the corresponding PBODR bit

while the corresponding PBDDR bit is cleared to 0.

The input pull-ups are turned off by a reset and in hardware standby mode. In software standby

mode, the previous state is maintained.

Table 7.24 indicates the states of the input pull-up transistors in each operating mode.

Table 7.24 States of Input Pull-Up Transistors (Port B)

Mode Reset Hardware Standby Software Standby Other Operating Modes

1 Off Off On/off On/off

2 Off Off On/off On/off

3 Off Off On/off On/off

Notes: Off: The input pull-up transistor is always off.

On/off: The input pull-up transistor is on if PBDR = 1 and PBDDR = 0, but off otherwise.

155

Section 8 16-Bit Free-Running Timer

8.1 Overview

The H8/3437 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-

running counter as a time base. Applications of the FRT module include rectangular-wave output

(up to two independent waveforms), input pulse width measurement, and measurement of external

clock periods.

8.1.1 Features

The features of the free-running timer module are listed below.

• Selection of four clock sources

The free-running counter can be driven by an internal clock source (øP/2, øP/8, or øP/32), or an

external clock input (enabling use as an external event counter).

• Two independent comparators

Each comparator can generate an independent waveform.

• Four input capture channels

The current count can be captured on the rising or falling edge (selectable) of an input signal.

The four input capture registers can be used separately, or in a buffer mode.

• Counter can be cleared under program control

The free-running counters can be cleared on compare-match A.

• Seven independent interrupts

Compare-match A and B, input capture A to D, and overflow interrupts are requested

independently.

156

8.1.2 Block Diagram

Figure 8.1 shows a block diagram of the free-running timer.

External

clock source

Internal

clock sources

Clock select

Comparator A

OCRA (H/L)

Comparator B

OCRB (H/L)

Bus interface

Internal

data bus

øP/2

øP/8

øP/32

FTCI

Compare-

match A

Clear

Clock

FTOA

FTOB

Overflow

ICRA (H/L)

Compare-

match B

Capture

FRC (H/L)

TCSR

FTIA

FTIB

FTIC

FTID

Control

logic

Module data bus

TIER

TCR

TOCR

Interrupt signals

ICIA

ICIB

ICIC

ICID

OCIA

OCIB

FOVI

Legend:

FRC:

OCRA, B:

ICRA, B, C, D:

TCSR:

Free-running counter (16 bits)

Output compare register A, B (16 bits)

Input capture register A, B, C, D (16 bits)

Timer control/status register (8 bits)

TIER:

TCR:

TOCR:

Timer interrupt enable register (8 bits)

Timer control register (8 bits)

Timer output compare control

ICRB (H/L)

ICRC (H/L)

ICRD (H/L)

Figure 8.1 Block Diagram of 16-Bit Free-Running Timer

157

8.1.3 Input and Output Pins

Table 8.1 lists the input and output pins of the free-running timer module.

Table 8.1 Input and Output Pins of Free-Running Timer Module

Name Abbreviation I/O Function

Counter clock input FTCI Input Input of external free-running counter

clock signal

Output compare A FTOA Output Output controlled by comparator A

Output compare B FTOB Output Output controlled by comparator B

Input capture A FTIA Input Trigger for capturing current count into

input capture register A

Input capture B FTIB Input Trigger for capturing current count into

input capture register B

Input capture C FTIC Input Trigger for capturing current count into

input capture register C

Input capture D FTID Input Trigger for capturing current count into

input capture register D

158

8.1.4 Register Configuration

Table 8.2 lists the registers of the free-running timer module.

Table 8.2 Register Configuration

Name Abbreviation R/W Initial

Value Address

Timer interrupt enable register TIER R/W H'01 H'FF90

Timer control/status register TCSR R/(W)*1H'00 H'FF91

Free-running counter (high) FRC (H) R/W H'00 H'FF92

Free-running counter (low) FRC (L) R/W H'00 H'FF93

Output compare register A/B (high)*2OCRA/B (H) R/W H'FF H'FF94*2

Output compare register A/B (low)*2OCRA/B (L) R/W H'FF H'FF95*2

Timer control register TCR R/W H'00 H'FF96

Timer output compare control register TOCR R/W H'E0 H'FF97

Input capture register A (high) ICRA (H) R H'00 H'FF98

Input capture register A (low) ICRA (L) R H'00 H'FF99

Input capture register B (high) ICRB (H) R H'00 H'FF9A

Input capture register B (low) ICRB (L) R H'00 H'FF9B

Input capture register C (high) ICRC (H) R H'00 H'FF9C

Input capture register C (low) ICRC (L) R H'00 H'FF9D

Input capture register D (high) ICRD (H) R H'00 H'FF9E

Input capture register D (low) ICRD (L) R H'00 H'FF9F

Notes: *1 Software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits.

*2 OCRA and OCRB share the same addresses. Access is controlled by the OCRS

bit in TOCR.

159

8.2 Register Descriptions

8.2.1 Free-Running Counter (FRC)

Bit 1514131211109876543210

Initial value 0 0 0 0000000000000

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a

clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the

timer control register (TCR).

When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status

Because FRC is a 16-bit register, a temporary register (TEMP) is used when FRC is written or

read. See section 8.3, CPU Interface, for details.

FRC is initialized to H'0000 by a reset and in the standby modes.

8.2.2 Output Compare Registers A and B (OCRA and OCRB)

Bit 1514131211109876543210

Initial value 1 1 1 1111111111111

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually

compared with the value in the FRC. When a match is detected, the corresponding output compare

flag (OCFA or OCFB) is set in the timer control/status register (TCSR).

In addition, if the output enable bit (OEA or OEB) in the timer output compare control register

(TOCR) is set to 1, when the output compare register and FRC values match, the logic level

selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin

(FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first

compare-match.

OCRA and OCRB share the same address. They are differentiated by the OCRS bit in TOCR. A

temporary register (TEMP) is used for write access, as explained in section 8.3, CPU Interface.

OCRA and OCRB are initialized to H'FFFF by a reset and in the standby modes.

160

8.2.3 Input Capture Registers A to D (ICRA to ICRD)

Bit 1514131211109876543210

Initial value 0 0 0 0000000000000

Read/Write R R R RRRRRRRRRRRRR

There are four input capture registers A to D, each of which is a 16-bit read-only register.

When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected,

the current FRC value is copied to the corresponding input capture register (ICRA to ICRD).* At

the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status

(IEDGA to IEDGD) in the timer control register (TCR).

Note: * The FRC contents are transferred to the input capture register regardless of the value of the

input capture flag (ICFA/B/C/D).

Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in

TCR is set to 1, ICRC is used as a buffer register for ICRA as shown in figure 8.2. When an FTIA

input is received, the old ICRA contents are moved into ICRC, and the new FRC count is copied

into ICRA.

BUFEA:

IEDGA:

IEDGC:

ICRC:

ICRA:

FRC:

Buffer enable A

Input edge select A

Input edge select C

Input capture register C

Input capture register A

Free-running counter

BUFEA

IEDGA IEDGC

FTIA Edge detect and

capture signal

generating circuit

FRCICRC ICRA

Figure 8.2 Input Capture Buffering (Example)

161

Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB.

When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠

IEDGC or IEDGB ≠ IEDGD), then input capture is triggered on both the rising and falling edges

of the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =

IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge. See table 8.3.

Table 8.3 Buffered Input Capture Edge Selection (Example)

IEDGA IEDGC Input Capture Edge

0 0 Captured on falling edge of input capture A (FTIA) (Initial value)

1 Captured on both rising and falling edges of input capture A (FTIA)

1 Captured on rising edge of input capture A (FTIA)

Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when

they are read. See section 8.3, CPU Interface, for details.

To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock

periods (1.5·ø). When triggering is enabled on both edges, the input capture pulse width should be

at least 2.5 system clock periods.

The input capture registers are initialized to H'0000 by a reset and in the standby modes.

162

8.2.4 Timer Interrupt Enable Register (TIER)

Bit 76543210

ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE —

Initial value 0 0 0 0 0 0 0 1

Read/Write R/W R/W R/W R/W R/W R/W R/W —

TIER is an 8-bit readable/writable register that enables and disables interrupts.

TIER is initialized to H'01 by a reset and in the standby modes.

Bit 7—Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input

capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register

(TCSR) is set to 1.

Bit 7: ICIAE Description

0 Input capture interrupt request A (ICIA) is disabled. (Initial value)

1 Input capture interrupt request A (ICIA) is enabled.

Bit 6—Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input

capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.

Bit 6: ICIBE Description

0 Input capture interrupt request B (ICIB) is disabled. (Initial value)

1 Input capture interrupt request B (ICIB) is enabled.

Bit 5—Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input

capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.

Bit 5: ICICE Description

0 Input capture interrupt request C (ICIC) is disabled. (Initial value)

1 Input capture interrupt request C (ICIC) is enabled.

Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input

capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.

Bit 4: ICIDE Description

0 Input capture interrupt request D (ICID) is disabled. (Initial value)

1 Input capture interrupt request D (ICID) is enabled.

163

Bit 3—Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request

output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.

Bit 3: OCIAE Description

0 Output compare interrupt request A (OCIA) is disabled. (Initial value)

1 Output compare interrupt request A (OCIA) is enabled.

Bit 2—Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request

output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.

Bit 2: OCIBE Description

0 Output compare interrupt request B (OCIB) is disabled. (Initial value)

1 Output compare interrupt request B (OCIB) is enabled.

Bit 1—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a free-

running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.

Bit 1: OVIE Description

0 Timer overflow interrupt request (FOVI) is disabled. (Initial value)

1 Timer overflow interrupt request (FOVI) is enabled.

Bit 0—Reserved: This bit cannot be modified and is always read as 1.

164

8.2.5 Timer Control/Status Register (TCSR)

Bit 76543210

ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA

Initial value 0 0 0 0 0 0 0 0

Read/Write R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/W

Note: *Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.

TCSR is an 8-bit readable and partially writable register that contains the seven interrupt flags and

specifies whether to clear the counter on compare-match A (when the FRC and OCRA values

match).

TCSR is initialized to H'00 by a reset and in the standby modes.

Timing is described in section 8.4, Operation.

Bit 7—Input Capture Flag A (ICFA): This status bit is set to 1 to flag an input capture A event.

If BUFEA = 0, ICFA indicates that the FRC value has been copied to ICRA. If BUFEA = 1, ICFA

indicates that the old ICRA value has been moved into ICRC and the new FRC value has been

copied to ICRA.

ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.

Bit 7: ICFA Description

0 To clear ICFA, the CPU must read ICFA after it has been set to 1, then write a

0 in this bit. (Initial value)

1 This bit is set to 1 when an FTIA input signal causes the FRC value to be

copied to ICRA.

Bit 6—Input Capture Flag B (ICFB): This status bit is set to 1 to flag an input capture B event.

If BUFEB = 0, ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = 1, ICFB

indicates that the old ICRB value has been moved into ICRD and the new FRC value has been

copied to ICRB.

ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.

Bit 6: ICFB Description

0 To clear ICFB, the CPU must read ICFB after it has been set to 1, then write a

0 in this bit. (Initial value)

1 This bit is set to 1 when an FTIB input signal causes the FRC value to be

copied to ICRB.

165

Bit 5—Input Capture Flag C (ICFC): This status bit is set to 1 to flag input of a rising or falling

edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC

count in ICRC. When BUFEA = 1, however, the FRC count is not captured, so ICFC becomes

simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a general-

purpose interrupt signal (which can be enabled or disabled by the ICICE bit).

ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.

Bit 5: ICFC Description

0 To clear ICFC, the CPU must read ICFC after it has been set to 1, then write a

0 in this bit. (Initial value)

1 This bit is set to 1 when an FTIC input signal is received.

Bit 4—Input Capture Flag D (ICFD): This status bit is set to 1 to flag input of a rising or falling

edge of FTID as selected by the IEDGD bit. When BUFEB = 0, this indicates capture of the FRC

count in ICRD. When BUFEB = 1, however, the FRC count is not captured, so ICFD becomes

simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a general-

purpose interrupt signal (which can be enabled or disabled by the ICIDE bit).

ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.

Bit 4: ICFD Description

0 To clear ICFD, the CPU must read ICFD after it has been set to 1, then write a

0 in this bit. (Initial value)

1 This bit is set to 1 when an FTID input signal is received.

Bit 3—Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value

matches the OCRA value. This flag must be cleared by software. It is set by hardware, however,

and cannot be set by software.

Bit 3: OCFA Description

0 To clear OCFA, the CPU must read OCFA after it has been set to 1, then write

a 0 in this bit. (Initial value)

1 This bit is set to 1 when FRC = OCRA.

166

Bit 2—Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value

matches the OCRB value. This flag must be cleared by software. It is set by hardware, however,

and cannot be set by software.

Bit 2: OCFB Description

0 To clear OCFB, the CPU must read OCFB after it has been set to 1, then write

a 0 in this bit. (Initial value)

1 This bit is set to 1 when FRC = OCRB.

Bit 1—Timer Overflow Flag (OVF): This status flag is set to 1 when FRC overflows (changes

from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however,

and cannot be set by software.

Bit 1: OVF Description

0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0

in this bit. (Initial value)

1 This bit is set to 1 when FRC changes from H'FFFF to H'0000.

Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear FRC at compare-match A

(when the FRC and OCRA values match).

Bit 0: CCLRA Description

0 The FRC is not cleared. (Initial value)

1 The FRC is cleared at compare-match A.

8.2.6 Timer Control Register (TCR)

Bit 76543210

IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture

signals, enables the input capture buffer mode, and selects the FRC clock source.

TCR is initialized to H'00 by a reset and in the standby modes.

167

Bit 7—Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input

capture A signal (FTIA).

Bit 7: IEDGA Description

0 Input capture A events are recognized on the falling edge of FTIA. (Initial value)

1 Input capture A events are recognized on the rising edge of FTIA.

Bit 6—Input Edge Select B (IEDGB): This bit selects the rising or falling edge of the input

capture B signal (FTIB).

Bit 6: IEDGB Description

0 Input capture B events are recognized on the falling edge of FTIB. (Initial value)

1 Input capture B events are recognized on the rising edge of FTIB.

Bit 5—Input Edge Select C (IEDGC): This bit selects the rising or falling edge of the input

capture C signal (FTIC).

Bit 5: IEDGC Description

0 Input capture C events are recognized on the falling edge of FTIC.(Initial value)

1 Input capture C events are recognized on the rising edge of FTIC.

Bit 4—Input Edge Select D (IEDGD): This bit selects the rising or falling edge of the input

capture D signal (FTID).

Bit 4: IEDGD Description

0 Input capture D events are recognized on the falling edge of FTID.(Initial value)

1 Input capture D events are recognized on the rising edge of FTID.

Bit 3—Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for

ICRA.

Bit 3: BUFEA Description

0 ICRC is used for input capture C. (Initial value)

1 ICRC is used as a buffer register for input capture A.

168

Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for

ICRB.

Bit 2: BUFEB Description

0 ICRD is used for input capture D. (Initial value)

1 ICRD is used as a buffer register for input capture B.

Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of

three internal clock sources for FRC. External clock pulses are counted on the rising edge of

signals input to pin FTCI.

Bit 1: CKS1 Bit 0: CKS0 Description

00øP/2 internal clock source (Initial value)

1øP/8 internal clock source

10øP/32 internal clock source

1 External clock source (rising edge)

8.2.7 Timer Output Compare Control Register (TOCR)

Bit 76543210

———OCRS OEA OEB OLVLA OLVLB

Initial value 1 1 1 0 0 0 0 0

Read/Write ———R/W R/W R/W R/W R/W

TOCR is an 8-bit readable/writable register that enables output from the output compare pins,

selects the output levels, and switches access between output compare registers A and B.

TOCR is initialized to H'E0 by a reset and in the standby modes.

Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.

Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.

When this address is accessed, the OCRS bit selects which register is accessed. This bit does not

affect the operation of OCRA or OCRB.

Bit 4: OCRS Description

0 OCRA is selected. (Initial value)

1 OCRB is selected.

169

Bit 3—Output Enable A (OEA): This bit enables or disables output of the output compare A

signal (FTOA).

Bit 3: OEA Description

0 Output compare A output is disabled. (Initial value)

1 Output compare A output is enabled.

Bit 2—Output Enable B (OEB): This bit enables or disables output of the output compare B

signal (FTOB).

Bit 2: OEB Description

0 Output compare B output is disabled. (Initial value)

1 Output compare B output is enabled.

Bit 1—Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin

when the FRC and OCRA values match.

Bit 1: OLVLA Description

0 A 0 logic level is output for compare-match A. (Initial value)

1 A 1 logic level is output for compare-match A.

Bit 0—Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin

when the FRC and OCRB values match.

Bit 0: OLVLB Description

0 A 0 logic level is output for compare-match B. (Initial value)

1 A 1 logic level is output for compare-match B.

170

8.3 CPU Interface

The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture

registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When

the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the

access is performed using an 8-bit temporary register (TEMP).

These registers are written and read as follows:

• Register Write

When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when

the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all

16 bits are written in the register simultaneously.

• Register Read

When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower

byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP.

Programs that access these registers should normally use word access. Equivalently, they may

access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be

transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed.

Figure 8.3 shows the data flow when FRC is accessed. The other registers are accessed in the same

way. As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower

bytes directly, without using TEMP.

Coding Examples

To write the contents of general register R0 to OCRA: MOV.W R0, @OCRA

To transfer the contents of ICRA to general register R0: MOV.W @ICRA, R0

171

CPU writes

data H'AA

(1) Upper byte write

(2) Lower byte write

CPU writes

data H'55

Bus

interface

Bus

interface

Module data bus

TEMP

[H'AA]

FRCH

[ ] FRCL

[ ]

TEMP

[H'AA]

FRCH

[H'AA] FRCL

[H'55]

Figure 8.3 (a) Write Access to FRC (when CPU Writes H'AA55)

172

CPU reads

data H'AA

(1) Upper byte read

(2) Lower byte read

CPU reads

data H'55

Bus

interface

Bus

interface

Module data bus

TEMP

[H'55]

FRCH

[H'AA] FRCL

[H'55]

TEMP

[H'55]

FRCH

[ ] FRCL

[ ]

Figure 8.3 (b) Read Access to FRC (when FRC Contains H'AA55)

173

8.4 Operation

8.4.1 FRC Increment Timing

FRC increments on a pulse generated once for each period of the selected (internal or external)

clock source. The clock source is selected by bits CKS0 and CKS1 in TCR.

Internal Clock: The internal clock sources (øP/2, øP/8, øP/32) are created from the system clock

(ø) by a prescaler. FRC increments on a pulse generated from the falling edge of the prescaler

output. See figure 8.4.

N – 1

FRC clock

pulse

FRC

Internal

clock

N N + 1

Figure 8.4 Increment Timing for Internal Clock Source

174

External Clock: If external clock input is selected, FRC increments on the rising edge of the

FTCI clock signal. Figure 8.5 shows the increment timing.

The pulse width of the external clock signal must be at least 1.5 system clock (ø) periods. The

counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.

N + 1N

FRC clock

pulse

FRC

External

clock

Figure 8.5 Increment Timing for External Clock Source

175

8.4.2 Output Compare Timing

When a compare-match occurs, the logic level selected by the output level bit (OLVLA or

OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 8.6 shows the

timing of this operation for compare-match A.

N + 1NN + 1N

OCRA

Internal compare-

match A signal

FRC

OLVLA

FTOA

Clear*

Note: * Cleared b

software

Figure 8.6 Timing of Output Compare A

176

8.4.3 FRC Clear Timing

If the CCLRA bit in TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure

8.7 shows the timing of this operation.

N H'0000

FRC

Internal compare-

match A signal

Figure 8.7 Clearing of FRC by Compare-Match A

8.4.4 Input Capture Timing

Input Capture Timing: An internal input capture signal is generated from the rising or falling

edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding

IEDGx bit in TCR. Figure 8.8 shows the usual input capture timing when the rising edge is

selected (IEDGx = 1).

Internal input

capture signal

Input data

FTI pin

Figure 8.8 Input Capture Timing (Usual Case)

If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal

arrives, the internal input capture signal is delayed by one state. Figure 8.9 shows the timing for

this case.

177

Internal input

capture signal

Input at FTI pin

T1T2T3

ICR upper byte read cycle

Figure 8.9 Input Capture Timing (1-State Delay Due to ICRA/B/C/D Read)

Buffered Input Capture Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB.

Figure 8.10 shows how input capture operates when ICRA and ICRC are used in buffer mode and

IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and

IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.

n n + 1 N N + 1

MnnN

mM Mn

FTIA

Internal input

capture signal

FRC

ICRA

ICRC

Figure 8.10 Buffered Input Capture with Both Edges Selected

178

When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected

transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge

transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and

if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to

ICRC, however.

In buffered input capture, if the upper byte of either of the two registers to which data will be

transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives,

input capture is delayed by one system clock (ø). Figure 8.11 shows the timing when BUFEA = 1.

Internal input

capture si

nal

Input at

FTIA pin

T1T2T3

Read cycle:

CPU reads upper byte of ICRA or ICRC

Figure 8.11 Input Capture Timing (1-State Delay, Buffer Mode)

179

8.4.5 Timing of Input Capture Flag (ICF) Setting

The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. Figure

8.12 shows the timing of this operation.

ICF

FRC

Internal input

capture signal

NICR

Figure 8.12 Setting of Input Capture Flag

8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB)

The output compare flags are set to 1 by an internal compare-match signal generated when the

FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last

state in which the two values match, just before FRC increments to a new value.

Accordingly, when the FRC and OCR values match, the compare-match signal is not generated

until the next period of the clock source. Figure 8.13 shows the timing of the setting of the output

compare flags.

180

OCRA or OCRB

Internal compare-

match signal

FRC N N + 1

OCFA or OCFB

Figure 8.13 Setting of Output Compare Flags

8.4.7 Setting of FRC Overflow Flag (OVF)

The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).

Figure 8.14 shows the timing of this operation.

H'FFFF H'0000

Internal overflow

signal

FRC

OVF

Figure 8.14 Setting of Overflow Flag (OVF)

181

8.5 Interrupts

The free-running timer can request seven interrupts (three types): input capture A to D (ICIA,

ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each

interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the

interrupt controller for each interrupt. Table 8.4 lists information about these interrupts.

Table 8.4 Free-Running Timer Interrupts

Interrupt Description Priority

ICIA Requested by ICFA High

ICIB Requested by ICFB

ICIC Requested by ICFC

ICID Requested by ICFD

OCIA Requested by OCFA

OCIB Requested by OCFB

FOVI Requested by OVF Low

182

8.6 Sample Application

In the example below, the free-running timer is used to generate two square-wave outputs with a

50% duty cycle and arbitrary phase relationship. The programming is as follows:

1. The CCLRA bit in TCSR is set to 1.

2. Each time a compare-match interrupt occurs, software inverts the corresponding output level

bit in TOCR (OLVLA or OLVLB).

FRC

Clear counter

H'FFFF

OCRA

OCRB

H'0000

FTOA

FTOB

Figure 8.15 Square-Wave Output (Example)

183

8.7 Application Notes

Application programmers should note that the following types of contention can occur in the free-

running timer.

Contention between FRC Write and Clear: If an internal counter clear signal is generated

during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal

takes priority and the write is not performed.

Figure 8.16 shows this type of contention.

T1T2T3

Write cycle:

CPU write to lower byte of FRC

Internal address

bus FRC address

Internal write

signal

FRC clear signal

FRC N H'0000

Figure 8.16 FRC Write-Clear Contention

184

Contention between FRC Write and Increment: If an FRC increment pulse is generated during

the T3 state of a write cycle to the lower byte of the free-running counter, the write takes priority

and FRC is not incremented.

Figure 8.17 shows this type of contention.

T1T2T3

Write cycle:

CPU write to lower byte of FRC

Internal address bus

Internal write signal

FRC clock pulse

FRC N M

Write data

FRC address

Figure 8.17 FRC Write-Increment Contention

185

Contention between OCR Write and Compare-Match: If a compare-match occurs during the

T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the

compare-match signal is inhibited.

Figure 8.18 shows this type of contention.

T1T2T3

Write cycle:

CPU write to lower byte of OCRA or OCRB

Internal address bus

Internal write signal

FRC

OCRA or OCRB N M

Write data

OCR address

N N + 1

Compare-match

A or B signal Inhibited

Figure 8.18 Contention between OCR Write and Compare-Match

186

Increment Caused by Changing of Internal Clock Source: When an internal clock source is

changed, the changeover may cause FRC to increment. This depends on the time at which the

clock select bits (CKS1 and CKS0) are rewritten, as shown in table 8.5.

The pulse that increments FRC is generated at the falling edge of the internal clock source. If

clock sources are changed when the old source is high and the new source is low, as in case no. 3

in table 8.5, the changeover generates a falling edge that triggers the FRC increment clock pulse.

Switching between an internal and external clock source can also cause FRC to increment.

Table 8.5 Effect of Changing Internal Clock Sources

No. Description Timing

1 Low → low:

CKS1 and CKS0 are

rewritten while both

clock sources are low.

N + 1

Old clock

source

New clock

source

FRC clock

pulse

FRC

CKS rewrite

2 Low → high:

CKS1 and CKS0 are

rewritten while old

clock source is low and

new clock source is high.

N + 1 N + 2

Old clock

source

New clock

source

FRC clock

pulse

FRC

CKS rewrite

187

No. Description Timing

3 High → low:

CKS1 and CKS0 are

rewritten while old clock

source is high and new

clock source is low.

N + 1N N + 2

Old clock

source

New clock

source

FRC clock

pulse

FRC

CKS rewrite

4 High → high:

CKS1 and CKS0 are

rewritten while both

clock sources are high.

N + 1 N + 2N

Old clock

source

New clock

source

FRC clock

pulse

CKS rewrite

FRC

Note: *The switching of clock sources is regarded as a falling edge that increments FRC.

188

189

Section 9 8-Bit Timers

9.1 Overview

The H8/3437 Series includes an 8-bit timer module with two channels (numbered 0 and 1). Each

channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that

are constantly compared with the TCNT value to detect compare-match events. One of the many

applications of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary

duty cycle.

9.1.1 Features

The features of the 8-bit timer module are listed below.

• Selection of seven clock sources

The counters can be driven by one of six internal clock signals or an external clock input

(enabling use as an external event counter).

• Selection of three ways to clear the counters

The counters can be cleared on compare-match A or B, or by an external reset signal.

• Timer output controlled by two time constants

The timer output signal in each channel is controlled by two independent time constants,

enabling the timer to generate output waveforms with an arbitrary duty cycle, or PWM

waveforms.

• Three independent interrupts

Compare-match A and B and overflow interrupts can be requested independently.

190

9.1.2 Block Diagram

Figure 9.1 shows a block diagram of one channel in the 8-bit timer module.

External

clock source

TMCI

TMO

TMRI

Internal

clock sources Channel 0 Channel 1

øP/2

øP/8

øP/32

øP/64

øP/256

øP/1024

øP/2

øP/8

øP/64

øP/128

øP/1024

øP/2048

Clock

Overflow

Clear

Compare-match B

Control

logic

Clock select TCORA

Comparator A

TCNT

Comparator B

TCORB

TCSR

TCR

Module data bus

Bus interface

Internal

data bus

CMIA

CMIB

OVI

Interrupt signals

TCR:

TCSR:

TCORA:

TCORB:

TCNT:

Timer control register (8 bits)

Timer control status register (8 bits)

Time constant register A (8 bits)

Time constant register B (8 bits)

Timer counter

Compare-match A

Figure 9.1 Block Diagram of 8-Bit Timer (1 Channel)

191

9.1.3 Input and Output Pins

Table 9.1 lists the input and output pins of the 8-bit timer.

Table 9.1 Input and Output Pins of 8-Bit Timer

Abbreviation*

Name Channel 0 Channel 1 I/O Function

Timer output TMO0TMO1Output Output controlled by compare-match

Timer clock input TMCI0TMCI1Input External clock source for the counter

Timer reset input TMRI0TMRI1Input External reset signal for the counter

Note: *In this manual, the channel subscript has been deleted, and only TMO TMCI, and TMRI are

used.

9.1.4 Register Configuration

Table 9.2 lists the registers of the 8-bit timer module. Each channel has an independent set of

registers.

Table 9.2 8-Bit Timer Registers

Channel Name Abbreviation R/W Initial Value Address

0 Timer control register TCR R/W H'00 H'FFC8

Timer control/status register TCSR R/(W)*H'10 H'FFC9

Time constant register A TCORA R/W H'FF H'FFCA

Time constant register B TCORB R/W H'FF H'FFCB

Timer counter TCNT R/W H'00 H'FFCC

1 Timer control register TCR R/W H'00 H'FFD0

Timer control/status register TCSR R/(W)*H'10 H'FFD1

Time constant register A TCORA R/W H'FF H'FFD2

Time constant register B TCORB R/W H'FF H'FFD3

Timer counter TCNT R/W H'00 H'FFD4

0, 1 Serial/timer control register STCR R/W H'00 H'FFC3

Note: *Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits.

192

9.2 Register Descriptions

9.2.1 Timer Counter (TCNT)

Bit 76543210

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an

internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer

control register (TCR). The CPU can always read or write the timer counter.

The timer counter can be cleared by an external reset input or by an internal compare-match signal

generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer

control register select the method of clearing.

When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer

control/status register (TCSR) is set to 1.

The timer counters are initialized to H'00 by a reset and in the standby modes.

9.2.2 Time Constant Registers A and B (TCORA and TCORB)

Bit 76543210

Initial value 1 1 1 1 1 1 1 1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually

compared with the constants written in these registers (except during the T3 state of a write cycle

to TCORA or TCORB). When a match is detected, the corresponding compare-match flag (CMFA

or CMFB) is set in the timer control/status register (TCSR).

The timer output signal is controlled by these compare-match signals as specified by output select

bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).

TCORA and TCORB are initialized to H'FF by a reset and in the standby modes.

193

9.2.3 Timer Control Register (TCR)

Bit 76543210

CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TCR is an 8-bit readable/writable register that selects the clock source and the time at which the

timer counter is cleared, and enables interrupts.

TCR is initialized to H'00 by a reset and in the standby modes.

For timing diagrams, see section 9.3, Operation.

Bit 7—Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request

compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer

control/status register (TCSR) is set to 1.

Bit 7: CMIEB Description

0 Compare-match interrupt request B (CMIB) is disabled. (Initial value)

1 Compare-match interrupt request B (CMIB) is enabled.

Bit 6—Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request

compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in TCSR is set to 1.

Bit 6: CMIEA Description

0 Compare-match interrupt request A (CMIA) is disabled. (Initial value)

1 Compare-match interrupt request A (CMIA) is enabled.

194

Bit 5—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer

overflow interrupt (OVI) when the overflow flag (OVF) in TCSR is set to 1.

Bit 5: OVIE Description

0 The timer overflow interrupt request (OVI) is disabled. (Initial value)

1 The timer overflow interrupt request (OVI) is enabled.

Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer

counter is cleared: by compare-match A or B or by an external reset input (TMRI).

Bit 4: CCLR1 Bit 3: CCLR0 Description

0 0 Not cleared. (Initial value)

1 Cleared on compare-match A.

1 0 Cleared on compare-match B.

1 Cleared on rising edge of external reset input signal.

195

Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and

ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for

the timer counter. Six internal clock sources, derived by prescaling the system clock, are available

for each timer channel. For internal clock sources the counter is incremented on the falling edge of

the internal clock. For an external clock source, these bits can select whether to increment the

counter on the rising or falling edge of the clock input (TMCI), or on both edges.

TCR STCR

Channel Bit 2:

CKS2 Bit 1:

CKS1 Bit 0:

CKS0 Bit 1:

ICKS1 Bit 0:

ICKS0 Description

0 0 0 0 — — No clock source (timer stopped) (Initial value)

10ø

P/8 internal clock, counted on falling edge

1ø

P/2 internal clock, counted on falling edge

10 0ø

P/64 internal clock, counted on falling edge

1ø

P/32 internal clock, counted on falling edge

10ø

P/1024 internal clock, counted on falling edge

1ø

P/256 internal clock, counted on falling edge

1 0 0 — No clock source (timer stopped)

1 External clock source, counted on rising edge

1 0 External clock source, counted on falling edge

1 External clock source, counted on both rising

and falling edges

1 0 0 0 — — No clock source (timer stopped) (Initial value)

10 ø

P/8 internal clock, counted on falling edge

1ø

P/2 internal clock, counted on falling edge

10 0 ø

P/64 internal clock, counted on falling edge

1ø

P/128 internal clock, counted on falling edge

10 ø

P/1024 internal clock, counted on falling edge

1ø

P/2048 internal clock, counted on falling edge

1 0 0 — No clock source (timer stopped)

1 External clock source, counted on rising edge

1 0 External clock source, counted on falling edge

1 External clock source, counted on both rising

and falling edges

196

9.2.4 Timer Control/Status Register (TCSR)

Bit 76543210

CMFB CMFA OVF — OS3 OS2 OS1 OS0

Initial value 0 0 0 1 0 0 0 0

Read/Write R/(W)*R/(W)*R/(W)*— R/W R/W R/W R/W

Note: *Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.

TCSR is an 8-bit readable and partially writable register that indicates compare-match and

overflow status and selects the effect of compare-match events on the timer output signal.

TCSR is initialized to H'10 by a reset and in the standby modes.

Bit 7—Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count

matches the time constant set in TCORB. CMFB must be cleared by software. It is set by

hardware, however, and cannot be set by software.

Bit 7: CMFB Description

0 To clear CMFB, the CPU must read CMFB after it has been set to 1 then write

a 0 in this bit. (Initial value)

1 This bit is set to 1 when TCNT = TCORB.

Bit 6—Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count

matches the time constant set in TCORA. CMFA must be cleared by software. It is set by

hardware, however, and cannot be set by software.

Bit 6: CMFA Description

0 To clear CMFA, the CPU must read CMFA after it has been set to 1, then write

a 0 in this bit. (Initial value)

1 This bit is set to 1 when TCNT = TCORA.

Bit 5—Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows

(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however,

and cannot be set by software.

Bit 5: OVF Description

0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0

in this bit. (Initial value)

1 This bit is set to 1 when TCNT changes from H'FF to H'00.

197

Bit 4—Reserved: This bit is always read as 1. It cannot be written.

Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of TCOR–TCNT

compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of

compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on

the output level.

If compare-match A and B occur simultaneously, any conflict is resolved according to the

following priority order: toggle > 1 output > 0 output.

When all four output select bits are cleared to 0 the timer output signal is disabled.

After a reset, the timer output is 0 until the first compare-match event.

Bit 3: OS3 Bit 2: OS2 Description

0 0 No change when compare-match B occurs. (Initial value)

1 Output changes to 0 when compare-match B occurs.

1 0 Output changes to 1 when compare-match B occurs.

1 Output inverts (toggles) when compare-match B occurs.

Bit 1: OS1 Bit 0: OS0 Description

0 0 No change when compare-match A occurs. (Initial value)

1 Output changes to 0 when compare-match A occurs.

1 0 Output changes to 1 when compare-match A occurs.

1 Output inverts (toggles) when compare-match A occurs.

198

9.2.5 Serial/Timer Control Register (STCR)

Bit 76543210

IICS IICD IICX IICE STAC MPE ICKS1 ICKS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

STCR is an 8-bit readable/writable register that controls the I2C bus interface and host interface,

controls the operating mode of the serial communication interface, and selects internal clock

sources for the timer counters.

STCR is initialized to H'00 by a reset.

Bits 7 to 4—I2C Control (IICS, IICD, IICX, IICE): These bits control operation of the I2C bus

interface. For details, see section 13, I2C Bus Interface.

Bit 3—Slave Input Switch (STAC): Controls the switching of the host interface input pins. For

details, see section 14, Host Interface.

Bit 2—Multiprocessor Enable (MPE): Controls the operating mode of serial communication

interfaces 0 and 1. For details, see section 12, Serial Communication Interface.

Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits and bits

CKS2 to CKS0 in the TCR select clock sources for the timer counters. For details, see section

9.2.3, Timer Control Register.

199

9.3 Operation

9.3.1 TCNT Increment Timing

The timer counter increments on a pulse generated once for each period of the selected (internal or

external) clock source.

Internal Clock: Internal clock sources are created from the system clock by a prescaler. The

counter increments on an internal TCNT clock pulse generated from the falling edge of the

prescaler output, as shown in figure 9.2. Bits CKS2 to CKS0 of TCR and bits ICKS1 and ICKS0

of STCR can select one of the six internal clocks.

N – 1

TCNT clock

pulse

TCNT

Internal

clock

N N + 1

Figure 9.2 Count Timing for Internal Clock Input

200

External Clock: If external clock input (TMCI) is selected, the timer counter can increment on

the rising edge, the falling edge, or both edges of the external clock signal. Figure 9.3 shows

incrementation on both edges of the external clock signal.

The external clock pulse width must be at least 1.5 system clock (ø) periods for incrementation on

a single edge, and at least 2.5 system clock periods for incrementation on both edges. The counter

will not increment correctly if the pulse width is shorter than these values.

N – 1 NN + 1

TCNT clock

pulse

TCNT

External clock

source (TMCI)

Figure 9.3 Count Timing for External Clock Input

201

9.3.2 Compare-Match Timing

Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are

set to 1 by an internal compare-match signal generated when the timer count matches the time

constant in TCORA or TCORB. The compare-match signal is generated at the last state in which

the match is true, just before the timer counter increments to a new value.

Accordingly, when the timer count matches one of the time constants, the compare-match signal is

not generated until the next period of the clock source. Figure 9.4 shows the timing of the setting

of the compare-match flags.

TCOR

Internal compare-

match signal

TCNT N

N + 1

CMF

Figure 9.4 Setting of Compare-Match Flags

202

Output Timing: When a compare-match event occurs, the timer output changes as specified by

the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain

the same, change to 0, change to 1, or toggle.

Figure 9.5 shows the timing when the output is set to toggle on compare-match A.

Timer output

(

TMO

)

Internal compare-

match A signal

Figure 9.5 Timing of Timer Output

Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in TCR, the timer

counter can be cleared when compare-match A or B occurs. Figure 9.6 shows the timing of this

operation.

TCNT

Internal compare-

match signal

N H'00

Figure 9.6 Timing of Compare-Match Clear

203

9.3.3 External Reset of TCNT

When the CCLR1 and CCLR0 bits in TCR are both set to 1, the timer counter is cleared on the

rising edge of an external reset input. Figure 9.7 shows the timing of this operation. The timer

reset pulse width must be at least 1.5 system clock (ø) periods.

Internal clear

pulse

TCNT

External reset

input (TMRI)

N – 1 N H'00

Figure 9.7 Timing of External Reset

9.3.4 Setting of TCSR Overflow Flag (OVF)

The overflow flag (OVF) is set to 1 when the timer count overflows (changes from H'FF to H'00).

Figure 9.8 shows the timing of this operation.

H'FF H'00

Internal overflow

signal

TCNT

OVF

Figure 9.8 Setting of Overflow Flag (OVF)

204

9.4 Interrupts

Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B

(CMIA and CMIB), and overflow (OVI). Each interrupt can be enabled or disabled by an enable

bit in TCR. Independent signals are sent to the interrupt controller for each interrupt. Table 9.3

lists information about these interrupts.

Table 9.3 8-Bit Timer Interrupts

Interrupt Description Priority

CMIA Requested by CMFA High

CMIB Requested by CMFB

OVI Requested by OVF Low

9.5 Sample Application

In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle.

The control bits are set as follows:

1. In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when

its value matches the constant in TCORA.

2. In TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-match

A and to 0 on compare-match B.

With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with

a pulse width determined by TCORB. No software intervention is required.

TCNT

Clear counter

H'FF

TCORA

TCORB

H'00

TMO pin

Figure 9.9 Example of Pulse Output

205

9.6 Application Notes

Application programmers should note that the following types of contention can occur in the 8-bit

timer.

9.6.1 Contention between TCNT Write and Clear

If an internal counter clear signal is generated during the T3 state of a write cycle to the timer

counter, the clear signal takes priority and the write is not performed.

Figure 9.10 shows this type of contention.

T1T2T3

Write cycle: CPU writes to TCNT

Internal address

bus TCNT address

Internal write

signal

Counter clear

signal

TCNT N H'00

Figure 9.10 TCNT Write-Clear Contention

206

9.6.2 Contention between TCNT Write and Increment

If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer

counter, the write takes priority and the timer counter is not incremented.

Figure 9.11 shows this type of contention.

T1T2T3

Write cycle: CPU writes to TCNT

Internal address bus

Internal write signal

TCNT clock pulse

TNCT N M

Write data

TCNT address

Figure 9.11 TCNT Write-Increment Contention

207

9.6.3 Contention between TCOR Write and Compare-Match

If a compare-match occurs during the T3 state of a write cycle to TCOR, the write takes priority

and the compare-match signal is inhibited.

Figure 9.12 shows this type of contention.

T1T2T3

Write cycle: CPU writes to TCOR

Internal address bus

Internal write signal

TCNT

TCOR N M

TCOR write data

TCOR address

N N + 1

Compare-match

A or B signal

Inhibited

Figure 9.12 Contention between TCOR Write and Compare-Match

208

9.6.4 Contention between Compare-Match A and Compare-Match B

If identical time constants are written in TCORA and TCORB, causing compare-match A and B to

occur simultaneously, any conflict between the output selections for compare-match A and B is

resolved by following the priority order in table 9.4.

Table 9.4 Priority of Timer Output

Output Selection Priority

Toggle High

1 output

0 output

No change Low

9.6.5 Increment Caused by Changing of Internal Clock Source

When an internal clock source is changed, the changeover may cause the timer counter to

increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten, as

shown in table 9.5.

The pulse that increments the timer counter is generated at the falling edge of the internal clock

source signal. If clock sources are changed when the old source is high and the new source is low,

as in case no. 3 in table 9.5, the changeover generates a falling edge that triggers the TCNT clock

pulse and increments the timer counter.

Switching between an internal and external clock source can also cause the timer counter to

increment.

209

Table 9.5 Effect of Changing Internal Clock Sources

No. Description Timing

1 Low → low*1

N + 1

Old clock

source

New clock

source

TCNT clock

pulse

TCNT

CKS rewrite

2 Low → high*2

N + 1 N + 2

Old clock

source

New clock

source

TCNT clock

pulse

TCNT

CKS rewrite

210

No. Description Timing

3 High → low*3

N + 1N N + 2

Old clock

source

New clock

source

TCNT clock

pulse

TCNT

CKS rewrite

4 High → high

N + 1 N + 2N

Old clock

source

New clock

source

TCNT clock

pulse

CKS rewrite

TCNT

Notes: *1 Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0), or a

transition from the stopped state to low.

*2 Including a transition from the stopped state to high.

*3 Including a transition from high to the stopped state.

*4 The switching of clock sources is regarded as a falling edge, and therefore a TCNT

clock pulse is generated and TCNT is incremented.

211

Section 10 PWM Timers

10.1 Overview

The H8/3437 Series has an on-chip pulse-width modulation (PWM) timer module with two

independent channels (PWM0 and PWM1). Both channels are functionally identical. Each PWM

channel generates a rectangular output pulse with a duty cycle of 0 to 100%. The duty cycle is

specified in an 8-bit duty register (DTR).

10.1.1 Features

The PWM timer module has the following features:

• Selection of eight clock sources

• Duty cycles from 0 to 100% with 1/250 resolution

• Output with positive or negative logic and software enable/disable control

212

10.1.2 Block Diagram

Figure 10.1 shows a block diagram of one PWM timer channel.

Comparator

DTR

Bus interface

Internal

data bus

Pulse

TCR

TCNT

Compare-match

øP/2

øP/8

øP/32

øP/128

øP/256

øP/1024

øP/2048

øP/4096

Output

control

Clock Clock

select

Internal clock sources

TCR:

DTR:

TCNT:

Timer control register (8 bits)

Duty register (8 bits)

Timer counter (8 bits)

Module data bus

Figure 10.1 Block Diagram of PWM Timer

10.1.3 Input and Output Pins

Table 10.1 lists the output pins of the PWM timer module. There are no input pins.

Table 10.1 Output Pins of PWM Timer Module

Name Abbreviation I/O Function

PWM0 output PW0Output Pulse output from PWM timer channel 0.

PWM1 output PW1Output Pulse output from PWM timer channel 1.

213

10.1.4 Register Configuration

The PWM timer module has three registers for each channel as listed in table 10.2.

Table 10.2 PWM Timer Registers

Initial Address

Name Abbreviation R/W Value PWM0 PWM1

Timer control register TCR R/W H'38 H'FFA0 H'FFA4

Duty register DTR R/W H'FF H'FFA1 H'FFA5

Timer counter TCNT R/W H'00 H'FFA2 H'FFA6

10.2 Register Descriptions

10.2.1 Timer Counter (TCNT)

Bit 76543210

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TCNT is an 8-bit readable/writable up-counter. When the output enable bit (OE) is set to 1 in

TCR, TCNT starts counting pulses of an internal clock source selected by clock select bits 2 to 0

(CKS2 to CKS0). After counting from H'00 to H'F9, the count repeats from H'00. When TCNT

changes from H'00 to to H'01, the PWM output is placed in the 1 state, unless the DTR value is

H'00, in which case the duty cycle is 0% and the PWM output remains in the 0 state.

TCNT is initialized to H'00 at a reset and in the standby modes, and when the OE bit is cleared to

214

10.2.2 Duty Register (DTR)

Bit 76543210

Initial value 1 1 1 1 1 1 1 1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

DTR is an 8-bit readable/writable register that specifies the duty cycle of the output pulse. Any

duty cycle from 0% to 100% can be output by setting the corresponding value in DTR. The

resolution is 1/250. Writing 0 (H'00) in DTR gives a 0% duty cycle. Writing 125 (H'7D) gives a

50% duty cycle. Writing 250 (H'FA) gives a 100% duty cycle.

The DTR and TCNT values are always compared. When the values match, the PWM output is

placed in the 0 state.

DTR is double-buffered. A new value written in DTR does not become valid until after the timer

count changes from H'F9 to H'00. While the OE bit is cleared to 0 in TCR, however, new values

written in DTR become valid immediately. When DTR is read, the value read is the currently valid

value.

DTR is initialized to H'FF by a reset and in the standby modes.

215

10.2.3 Timer Control Register (TCR)

Bit 76543210

OE OS — — — CKS2 CKS1 CKS0

Initial value 0 0 1 1 1 0 0 0

Read/Write R/W R/W — — — R/W R/W R/W

TCR is an 8-bit readable/writable register that selects the clock input to TCNT and controls PWM

output.

TCR is initialized to H'38 by a reset and in standby mode.

Bit 7—Output Enable (OE): This bit enables the timer counter and the PWM output.

Bit 7: OE Description

0 PWM output is disabled. TCNT is cleared to H'00 and stopped. (Initial value)

1 PWM output is enabled. TCNT runs.

Bit 6—Output Select (OS): This bit selects positive or negative logic for the PWM output.

Bit 6: OS Description

0 Positive logic; positive-going PWM pulse, 1 = high (Initial value)

1 Negative logic; negative-going PWM pulse, 1 = low

Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 1.

216

Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight internal

clock sources obtained by dividing the supporting-module clock (øP).

Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Description

000ø

P/2 (Initial value)

1ø

P/8

10ø

P/32

1ø

P/128

100ø

P/256

1ø

P/1024

10ø

P/2048

1ø

P/4096

From the clock source frequency, the resolution, period, and frequency of the PWM output can be

calculated as follows.

Resolution = 1/clock source frequency

PWM period = resolution × 250

PWM frequency = 1/PWM period

If the øP clock frequency is 10 MHz, then the resolution, period, and frequency of the PWM output

for each clock source are as shown in table 10.3.

Table 10.3 PWM Timer Parameters for 10 MHz System Clock

Internal Clock Frequency Resolution PWM Period PWM Frequency

øP/2 200 ns 50 µs 20 kHz

øP/8 800 ns 200 µs 5 kHz

øP/32 3.2 µs 800 µs 1.25 kHz

øP/128 12.8 µs 3.2 ms 312.5 Hz

øP/256 25.6 µs 6.4 ms 156.3 Hz

øP/1024 102.4 µs 25.6 ms 39.1 Hz

øP/2048 204.8 µs 51.2 ms 19.5 Hz

øP/4096 409.6 µs 102.4 ms 9.8 Hz

217

10.3 Operation

10.3.1 Timer Increment

The PWM clock source is created by dividing the system clock (ø). The timer counter increments

on a TCNT clock pulse generated from the falling edge of the prescaler output as shown in figure

10.2.

N – 1

TCNT clock

pulse

TCNT

Prescaler

output

N N + 1

Figure 10.2 TCNT Increment Timing

218

10.3.2 PWM Operation

Figure 10.3 is a timing chart of the PWM operation.

N – 1 N + 1

(a) H'00 (b) H'01 H'02 NH'F9 (d) H'00 H'01

N(d) M

H'FF

(c)

(a)*

(e)*

(b) (c)

N written in DTR M written in DTR

TCNT clock

pulses

TCNT

DTR

(OS = 0)

PWM output

(OS = 1)

PWM 1 cycle

Note: * Used for port 4 input/output: state depends on values in data register and data direction register.

Figure 10.3 PWM Timing

219

Positive Logic (OS = 0):

1. When (OE = 0)—(a) in Figure 10.3

The timer count is held at H'00 and PWM output is inhibited. [Pin 46 (for PW0) or pin 47 (for

PW1) is used for port 4 input/output, and its state depends on the corresponding port 4 data

becomes valid immediately.

2. When (OE = 1)

a. The timer counter begins incrementing. The PWM output goes high when TCNT changes

from H'00 to H'01, unless DTR = H'00. [(b) in figure 10.3]

b. When the count passes the DTR value, the PWM output goes low. [(c) in figure 10.3]

c. If the DTR value is changed (by writing the data “M” in figure 10.3), the new value

becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 10.3]

Negative Logic (OS = 1)—(e) in Figure 10.3: The operation is the same except that high and low

are reversed in the PWM output. [(e) in figure 10.3]

10.4 Application Notes

Some notes on the use of the PWM timer module are given below.

1. Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)

should be made before the output enable bit (OE) is set to 1.

2. If the DTR value is H'00, the duty cycle is 0% and PWM output remains constant at 0.

If the DTR value is H'FA to H'FF, the duty cycle is 100% and PWM output remains constant at

(For positive logic, 0 is low and 1 is high. For negative logic, 0 is high and 1 is low.)

220

221

Section 11 Watchdog Timer

11.1 Overview

The H8/3437 Series has an on-chip watchdog timer (WDT) that can monitor system operation by

resetting the CPU or generating a nonmaskable interrupt if a system crash allows the timer count

to overflow.

When this watchdog function is not needed, the watchdog timer module can be used as an interval

timer. In interval timer mode, it requests an WOVF interrupt at each counter overflow.

11.1.1 Features

WDT features are shown below.

• Selection of eight counter input clocks

• Switchable between watchdog timer mode and interval timer mode

• Timer counter overflow generates an internal reset or internal interrupt:

 Selection of internal reset or internal interrupt generation in watchdog timer mode

 WOVF interrupt request in interval timer mode

• RESO output in watchdog timer mode

 Low-level signal output from RESO pin when counter overflows in watchdog timer mode

(when internal reset is selected)

222

11.1.2 Block Diagram

Figure 11.1 is a block diagram of the watchdog timer.

System

interrupt

control

Internal reset or NMI

(watchdog timer mode)

WOVF interrupt

request signal

(interval timer mode)

RESO pin

Overflow TCNT

TCSR

Read/write

control

Internal

data bus

Clock

select

øP/2

øP/32

øP/64

øP/128

øP/256

øP/512

øP/2048

øP/4096

Internal clock source

Clock

TCNT:

TCSR: Timer counter

Timer control/status register

Figure 11.1 Block Diagram of Watchdog Timer

11.1.3 Output Pin

Table 11.1 Output Pin of Watchdog Timer

Name Abbreviation I/O Function

Reset out output pin RESO Output Counter overflow signal output in

watchdog timer mode

223

11.1.4 Register Configuration

Table 11.2 lists information on the watchdog timer registers.

Table 11.2 Register Configuration

Initial Addresses

Name Abbreviation R/W Value Write Read

Timer control/status register TCSR R/(W)*H'10 H'FFA8 H'FFA8

Timer counter TCNT R/W H'00 H'FFA8 H'FFA9

Note: *Software can write a 0 to clear the status flag bits, but cannot write 1.

11.2 Register Descriptions

11.2.1 Timer Counter (TCNT)

Bit 76543210

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer

control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal

clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count

overflows (changes from H'FF to H'00), an overflow flag (OVF) in TCSR is set to 1.

TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0.

Note: TCNT is more difficult to write to than other registers. See Section 11.2.4, Register

Access, for details.

224

11.2.2 Timer Control/Status Register (TCSR)

Bit 76543210

OVF WT/IT TME — RST/NMI CKS2 CKS1 CKS0

Initial value 0 0 0 1 0 0 0 0

Read/Write R/(W)*R/W R/W — R/W R/W R/W R/W

Note: *Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.

TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and

performs other functions. (TCSR is write-protected by a password. See section 11.2.3, Register

Access, for details.)

Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are

initialized to 0 by a reset, but retain their values in the standby modes.

Bit 7—Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed.

Bit 7: OVF Description

0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0

in this bit (Initial value)

1 Set to 1 when TCNT changes from H'FF to H'00

Bit 6—Timer Mode Select (WT/IT): Selects whether to operate in watchdog timer mode or

interval timer mode. When TCNT overflows, an WOVF interrupt request is sent to the CPU in

interval timer mode. For watchdog timer mode, a reset or NMI interrupt is requested.

Bit 6: WT/IT Description

0 Interval timer mode (WOVF request) (Initial value)

1 Watchdog timer mode (reset or NMI request)

Bit 5—Timer Enable (TME): Enables or disables the timer.

Bit 5: TME Description

0 TCNT is initialized to H'00 and stopped (Initial value)

1 TCNT runs and requests a reset or an interrupt when it overflows

225

Bit 4—Reserved: This bit cannot be modified and is always read as 1.

Bit 3: Reset or NMI Select (RST/NMI): Selects either an internal reset or the NMI function at

watchdog timer overflow.

Bit 3: RST/NMI Description

0 NMI function enabled (Initial value)

1 Reset function enabled

Bits 2–0—Clock Select (CKS2–CKS0): These bits select one of eight clock sources obtained by

dividing the system clock (ø).

The overflow interval is the time from when the watchdog timer counter begins counting from

H'00 until an overflow occurs. In interval timer mode, OVF interrupts are requested at this

interval.

Bit 2:

CKS2 Bit 1:

CKS1 Bit 0:

CKS0 Clock Source Overflow Interval (øP = 10 MHz)

000ø

P/2 51.2 µs (Initial value)

1ø

P/32 819.2 µs

10ø

P/64 1.6 ms

1ø

P/128 3.3 ms

100ø

P/256 6.6 ms

1ø

P/512 13.1 ms

10ø

P/2048 52.4 ms

1ø

P/4096 104.9 ms

226

11.2.3 System Control Register (SYSCR)

Bit 76543210

SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME

Initial value 0 0 0 0 1 0 0 1

Read/Write R/W R/W R/W R/W R R/W R/W R/W

Only bit 3 is described here. For details of other bits, see section 3.2., System Control Register

(SYSCR), and descriptions of the relevant modules.

Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a

reset can be generated by watchdog timer overflow as well as by external reset input.

XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by an internal reset due

to watchdog timer overflow when the RST/NMI bit is 1.

Bit 3: XRST Description

0 A reset is generated by an internal reset due to watchdog timer overflow

1 A reset is generated by external reset input (Initial value)

11.2.4 Register Access

The watchdog timer’s TCNT and TCSR registers are more difficult to write to than other registers.

The procedures for writing and reading these registers are given below.

Writing to TCNT and TCSR: Word access is required. Byte data transfer instructions cannot be

used for write access.

The TCNT and TCSR registers have the same write address. The write data must be contained in

the lower byte of a word written at this address. The upper byte must contain H'5A (password for

TCNT) or H'A5 (password for TCSR). See figure 11.2. The result of the access depicted in figure

11.2 is to transfer the write data from the lower byte to TCNT or TCSR.

Write dataH'5A

15 8 7 0

Write dataH'A5

15 8 7 0

H'FFA8

Writing to TCNT

Writing to TCSR

Figure 11.2 Writing to TCNT and TCSR

227

Reading TCNT and TCSR: The read addresses are H'FFA8 for TCSR and H'FFA9 for TCNT, as

indicated in table 11.3.

These two registers are read like other registers. Byte access instructions can be used.

Table 11.3 Read Addresses of TCNT and TCSR

Read Address Register

H'FFA8 TCSR

H'FFA9 TCNT

11.3 Operation

11.3.1 Watchdog Timer Mode

The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in

TCSR. Thereafter, software should periodically rewrite the contents of the timer counter (normally

by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count

to overflow, the entire chip is reset for 518 system clocks (518 ø), or an NMI interrupt is

requested. Figure 11.3 shows the operation.

NMI requests from the watchdog timer have the same vector as NMI requests from the NMI pin.

Avoid simultaneous handling of watchdog timer NMI requests and NMI requests from pin NMI.

A reset from the watchdog timer has the same vector as an external reset from the RES pin. The

reset source can be determined by the XRST bit in SYSCR.

H'FF

H'00

TCNT count

WDT overflow

WT/IT = 1

TME = 1 H'00 written

to TCNT

OVF = 1

Reset

518 ø

H'00 written

to TCNT

WT/IT = 1

TME = 1

Time t

Figure 11.3 Operation in Watchdog Timer Mode

228

11.3.2 Interval Timer Mode

Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1.

In interval timer mode, an WOVF request is generated each time the timer count overflows. This

function can be used to generate WOVF requests at regular intervals. See figure 11.4.

H'FF

H'00

WT/IT = 0

TME = 1

Time t

OVF

request OVF

request

TCNT count

Figure 11.4 Operation in Interval Timer Mode

11.3.3 Setting the Overflow Flag

The WOVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module

requests an internal reset, NMI, or OVF interrupt. The timing is shown in figure 11.5.

H'FF H'00

TCNT

Internal overflow

signal

OVF

Figure 11.5 Setting the OVF Bit

229

11.3.4 RESO Signal Output Timing

When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/NMI

bit is 1 at this time, an internal reset signal is generated for the entire chip. At the same time a low-

level signal is output from the RESO pin. The timing is shown in figure 11.6.

TCNT H'FF H'00

Overflow signal

(internal signal)

OVF

RESO signal

Internal reset

signal

132 states

518 states

Figure 11.6 RESO Signal Output Timing

230

11.4 Application Notes

11.4.1 Contention between TCNT Write and Increment

If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter,

the write takes priority and the timer counter is not incremented. See figure 11.7.

TCNT address

Counter write data

Internal address bus

Internal write signal

TCNT clock pulse

TCNT

Write cycle (CPU writes to TCNT)

Figure 11.7 TCNT Write-Increment Contention

11.4.2 Changing the Clock Select Bits (CKS2 to CKS0)

Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value

of the clock select bits. If the clock select bits are modified while the watchdog timer is running,

the timer count may be incremented incorrectly.

11.4.3 Recovery from Software Standby Mode

TCSR bits, except bits 0–2, and the TCNT counter are reset when the chip recovers from software

standby mode. Re-initialize the watchdog timer as necessary to resume normal operation.

231

11.4.4 Switching between Watchdog Timer Mode and Interval Timer Mode

If a switch is made between watchdog timer mode and interval timer mode while the WDT is

operating, correct operation may not be performed. The WDT must be stopped (by clearing the

TME bit to 0) before changing the timer mode.

11.4.5 System Reset by RESO Signal

If the RESO output signal is input to the chip’s RES pin, the chip will not be initialized correctly.

Ensure that the RESO signal is not logically input to the chip’s RES pin. When resetting the entire

system with the RESO signal, use a circuit such as that shown in figure 11.8.

Reset input

Reset signal to entire chip

H8/3437 Series chip

RES

RESO

Figure 11.8 Sample Circuit for System Reset by RESO Signal

11.4.6 Detection of Program Runaway

The following points should be noted when using the microcomputer’s on-chip watchdog timer to

detect program runaway.

During program runaway, instructions other than the usual instructions may be executed. If an

instruction reserved for system use is executed as a result of runaway, the watchdog timer may

sometimes stop, preventing detection of the runaway.

This problem can be avoided by making the following settings in the program.

1. Set code H'0004 in ROM address H'0002.

2. Set code H'56F0 in ROM address H'0004.

As system reserved addresses may be used by an emulator, the above settings should only be made

for the actual chip.

232

233

Section 12 Serial Communication Interface

12.1 Overview

The H8/3437 Series includes two serial communication interface channels (SCI0 and SCI1) for

transferring serial data to and from other chips. Either synchronous or asynchronous

communication can be selected.

12.1.1 Features

The features of the on-chip serial communication interface are:

• Asynchronous mode

The H8/3437 Series can communicate with a UART (Universal Asynchronous

Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip

that employs standard asynchronous serial communication. It also has a multiprocessor

communication function for communication with other processors. Twelve data formats are

available.

 Data length: 7 or 8 bits

 Stop bit length: 1 or 2 bits

 Parity: Even, odd, or none

 Multiprocessor bit: 1 or 0

 Error detection: Parity, overrun, and framing errors

 Break detection: When a framing error occurs, the break condition can be detected by

reading the level of the RxD line directly.

• Synchronous mode

The SCI can communicate with chips able to perform clocked synchronous data transfer.

 Data length: 8 bits

 Error detection: Overrun errors

• Full duplex communication

The transmitting and receiving sections are independent, so each channel can transmit and

receive simultaneously. Both the transmit and receive sections use double buffering, so

continuous data transfer is possible in either direction.

• Built-in baud rate generator

Any specified bit rate can be generated.

• Internal or external clock source

The SCI can operate on an internal clock signal from the baud rate generator, or an external

clock signal input at the SCK0 or SCK1 pin.

234

• Four interrupts

TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested

independently.

12.1.2 Block Diagram

Figure 12.1 shows a block diagram of one serial communication interface channel.

TDR

Bus interface

Internal

data bus

Parity

generate Clock

Parity check

TSR ø

øP/4

øP/16

øP/64

RxD

TxD

TXI

RXI

ERI

Interrupt signals

External clock source

Internal

clock

RDR

RSR

SCK

BRR

Communi-

cation

control

SSR

SCR

SMR Baud rate

generator

RSR:

RDR:

TSR:

TDR:

SMR:

SCR:

SSR:

BRR:

Receive shift register (8 bits)

Receive data register (8 bits)

Transmit shift register (8 bits)

Transmit data register (8 bits)

Serial mode register (8 bits)

Serial control register (8 bits)

Serial status register (8 bits)

Bit rate register (8 bits)

TEI

Module data bus

Figure 12.1 Block Diagram of Serial Communication Interface

235

12.1.3 Input and Output Pins

Table 12.1 lists the input and output pins used by the SCI module.

Table 12.1 SCI Input/Output Pins

Channel Name Abbreviation I/O Function

0 Serial clock input/output SCK0 Input/output SCI0 clock input and output

Receive data input RxD0 Input SCI0 receive data input

Transmit data output TxD0 Output SCI0 transmit data output

1 Serial clock input/output SCK1 Input/output SCI1 clock input and output

Receive data input RxD1 Input SCI1 receive data input

Transmit data output TxD1 Output SCI1 transmit data output

Note: In this manual, the channel subscript has been deleted, and only SCK, RxD, and TxD are

used.

236

12.1.4 Register Configuration

Table 12.2 lists the SCI registers. These registers specify the operating mode (synchronous or

asynchronous), data format and bit rate, and control the transmit and receive sections.

Table 12.2 SCI Registers

Channel Name Abbreviation R/W Initial

Value Address

0 Receive shift register RSR —*1—*1—*1

Receive data register RDR R H'00 H'FFDD

Transmit shift register TSR —*1—*1—*1

Transmit data register TDR R/W H'FF H'FFDB

Serial mode register SMR*3R/W H'00 H'FFD8

Serial control register SCR R/W H'00 H'FFDA

Serial status register SSR R/(W) *2H'84 H'FFDC

Bit rate register BRR*3R/W H'FF H'FFD9

1 Receive shift register RSR —*1—*1—*1

Receive data register RDR R H'00 H'FF8D

Transmit shift register TSR —*1—*1—*1

Transmit data register TDR R/W H'FF H'FF8B

Serial mode register SMR R/W H'00 H'FF88

Serial control register SCR R/W H'00 H'FF8A

Serial status register SSR R/(W) *2H'84 H'FF8C

Bit rate register BRR R/W H'FF H'FF89

0 and 1 Serial/timer control register STCR R/W H'00 H'FFC3

Notes: *1 Cannot be read or written to.

*2 Software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits.

*3 SMR and BRR have the same addresses as I2C bus interface registers ICCR and

ICSR. For the access switching method and other details, see section 13, I2C Bus

Interface.

237

12.2 Register Descriptions

12.2.1 Receive Shift Register (RSR)

Bit 76543210

Read/Write — — — — — — — —

RSR is a shift register that converts incoming serial data to parallel data. When one data character

has been received, it is transferred to the receive data register (RDR).

The CPU cannot read or write RSR directly.

12.2.2 Receive Data Register (RDR)

Bit 76543210

Initial value 0 0 0 0 0 0 0 0

Read/Write R R R R R R R R

RDR stores received data. As each character is received, it is transferred from RSR to RDR,

enabling RSR to receive the next character. This double-buffering allows the SCI to receive data

continuously.

RDR is a read-only register. RDR is initialized to H'00 by a reset and in the standby modes.

12.2.3 Transmit Shift Register (TSR)

Bit 76543210

Read/Write — — — — — — — —

TSR is a shift register that converts parallel data to serial transmit data. When transmission of one

character is completed, the next character is moved from the transmit data register (TDR) to TSR

and transmission of that character begins. If the TDRE bit is still set to 1, however, nothing is

transferred to TSR.

The CPU cannot read or write TSR directly.

238

12.2.4 Transmit Data Register (TDR)

Bit 76543210

Initial value 1 1 1 1 1 1 1 1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TDR is an 8-bit readable/writable register that holds the next data to be transmitted. When TSR

becomes empty, the data written in TDR is transferred to TSR. Continuous data transmission is

possible by writing the next data in TDR while the current data is being transmitted from TSR.

TDR is initialized to H'FF by a reset and in the standby modes.

12.2.5 Serial Mode Register (SMR)

Bit 76543210

C/ACHR PE O/ESTOP MP CKS1 CKS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

SMR is an 8-bit readable/writable register that controls the communication format and selects the

clock source of the on-chip baud rate generator. It is initialized to H'00 by a reset and in the

standby modes. For further information on the SMR settings and communication formats, see

tables 12.7 and 12.9 in section 12.3, Operation.

Bit 7—Communication Mode (C/A): This bit selects asynchronous or synchronous

communication mode.

Bit 7: C/ADescription

0 Asynchronous communication (Initial value)

1 Synchronous communication

Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode.

It is ignored in synchronous mode.

Bit 6: CHR Description

0 8 bits per character (Initial value)

1 7 bits per character (Bits 0 to 6 of TDR and RDR are used for transmitting and

receiving, respectively.)

239

Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode.

It is ignored in synchronous mode, and when a multiprocessor format is used.

Bit 5: PE Description

0 Transmit: No parity bit is added. (Initial value)

Receive: Parity is not checked.

1 Transmit: A parity bit is added.

Receive: Parity is checked.

Bit 4—Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = 1), this bit

selects even or odd parity.

Even parity means that a parity bit is added to the data bits for each character to make the total

number of 1’s even. Odd parity means that the total number of 1’s is made odd.

This bit is ignored when PE = 0, or when a multiprocessor format is used. It is also ignored in

synchronous mode.

Bit 4: O/EDescription

0 Even parity (Initial value)

1 Odd parity

Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in

synchronous mode.

Bit 3: STOP Description

0 One stop bit (Initial value)

Transmit: One stop bit is added.

Receive: One stop bit is checked to detect framing errors.

1 Two stop bits

Transmit: Two stop bits are added.

Receive: The first stop bit is checked to detect framing errors. If the second

stop bit is a space (0), it is regarded as the next start bit.

240

Bit 2—Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous

communication. When multiprocessor format is selected, the parity settings of the parity enable bit

(PE) and parity mode bit (O/E) are ignored. The MP bit is ignored in synchronous communication.

The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to 1.

When the MPE bit is cleared to 0, the multiprocessor communication function is disabled

regardless of the setting of the MP bit.

Bit 2: MP Description

0 Multiprocessor communication function is disabled. (Initial value)

1 Multiprocessor communication function is enabled.

Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the clock source of the

on-chip baud rate generator.

Bit 1: CKS1 Bit 0: CKS0 Description

0 0 ø clock (Initial value)

1ø

P/4 clock

10ø

P/16 clock

1ø

P/64 clock

12.2.6 Serial Control Register (SCR)

Bit 76543210

TIE RIE TE RE MPIE TEIE CKE1 CKE0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

SCR is an 8-bit readable/writable register that enables or disables various SCI functions.

It is initialized to H'00 by a reset and in the standby modes.

Bit 7—Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt

(TXI) requested when the transmit data register empty (TDRE) bit in the serial status register

(SSR) is set to 1.

Bit 7: TIE Description

0 The TDR-empty interrupt request (TXI) is disabled. (Initial value)

1 The TDR-empty interrupt request (TXI) is enabled.

241

Bit 6—Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt

(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is

set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER), framing

error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1.

Bit 6: RIE Description

0 The receive-end interrupt (RXI) and receive-error (ERI) requests are disabled.

(Initial value)

1 The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled.

Bit 5—Transmit Enable (TE): This bit enables or disables the transmit function. When the

transmit function is enabled, the TxD pin is automatically used for output. When the transmit

function is disabled, the TxD pin can be used as a general-purpose I/O port.

Bit 5: TE Description

0 The transmit function is disabled. (Initial value)

The TxD pin can be used for general-purpose I/O.

1 The transmit function is enabled. The TxD pin is used for output.

Bit 4—Receive Enable (RE): This bit enables or disables the receive function. When the receive

function is enabled, the RxD pin is automatically used for input. When the receive function is

disabled, the RxD pin is available as a general-purpose I/O port.

Bit 4: RE Description

0 The receive function is disabled. The RxD pin can be used for general-purpose

I/O. (Initial value)

1 The receive function is enabled. The RxD pin is used for input.

Bit 3—Multiprocessor Interrupt Enable (MPIE): When serial data is received in a

multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receive-

error interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or

disables the transfer of received data from RSR to RDR, and enables or disables setting of the

RDRF, FER, PER, and ORER bits in the serial status register (SSR).

The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode.

Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this condition

data is received regardless of the value of the multiprocessor bit in the receive data.

242

Setting the MPIE bit to 1 enables the multiprocessor receive interrupt function. In this condition, if

the multiprocessor bit in the receive data is 0, the receive-end interrupt (RXI) and receive-error

interrupt (ERI) are disabled, the receive data is not transferred from RSR to RDR, and the RDRF,

FER, PER, and ORER bits in the serial status register (SSR) are not set. If the multiprocessor bit is

1, however, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0, the receive data is

transferred from RSR to RDR, the FER, PER, and ORER bits can be set, and the receive-end and

receive-error interrupts are enabled.

Bit 3: MPIE Description

0 The multiprocessor receive interrupt function is disabled. (Initial value)

(Normal receive operation)

1 The multiprocessor receive interrupt function is enabled. During the interval

before data with the multiprocessor bit set to 1 is received, the receive interrupt

request (RXI) and receive-error interrupt request (ERI) are disabled, the RDRF,

FER, PER, and ORER bits are not set in the serial status register (SSR), and

no data is transferred from the RSR to the RDR. The MPIE bit is cleared at the

following times:

1. When 0 is written in MPIE.

2. When data with the multiprocessor bit set to 1 is received.

Bit 2—Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty

interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is

set to 1.

Bit 2: TEIE Description

0 The TSR-empty interrupt request (TEI) is disabled. (Initial value)

1 The TSR-empty interrupt request (TEI) is enabled.

Bit 1—Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud

rate generator. When the external clock source is selected, the SCK pin is automatically used for

input of the external clock signal.

Bit 1: CKE1 Description

0 Internal clock source (Initial value)

When C/A = 1, the serial clock signal is output at the SCK pin.

When C/A = 0, output depends on the CKE0 bit.

1 External clock source. The SCK pin is used for input.

243

Bit 0—Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode,

this bit enables or disables serial clock output at the SCK pin.

This bit is ignored when the external clock is selected, or when synchronous mode is selected.

For further information on the communication format and clock source selection, see table 12.8 in

section 12.3, Operation.

Bit 0: CKE0 Description

0 The SCK pin is not used by the SCI (and is available as a general-purpose I/O

port). (Initial value)

1 The SCK pin is used for serial clock output.

12.2.7 Serial Status Register (SSR)

Bit 76543210

TDRE RDRF ORER FER PER TEND MPB MPBT

Initial value 1 0 0 0 0 1 0 0

Read/Write R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R R R/W

Note: *Software can write a 0 to clear the flags, but cannot write a 1 in these bits.

SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 by a reset

and in the standby modes.

Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when transmit data can safely

be written in TDR.

Bit 7: TDRE Description

0 To clear TDRE, the CPU must read TDRE after it has been set to 1, then write

a 0 in this bit.

1 This bit is set to 1 at the following times: (Initial value)

1. When TDR contents are transferred to TSR.

2. When the TE bit in SCR is cleared to 0.

244

Bit 6—Receive Data Register Full (RDRF): This bit indicates when one character has been

received and transferred to RDR.

Bit 6: RDRF Description

0 To clear RDRF, the CPU must read RDRF after it has been set to 1, then write

a 0 in this bit. (Initial value)

1 This bit is set to 1 when one character is received without error and transferred

from RSR to RDR.

Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception.

Bit 5: ORER Description

0 To clear ORER, the CPU must read ORER after it has been set to 1, then write

a 0 in this bit. (Initial value)

1 This bit is set to 1 if reception of the next character ends while the receive data

Bit 4—Framing Error (FER): This bit indicates a framing error during data reception in

asynchronous mode. It has no meaning in synchronous mode.

Bit 4: FER Description

0 To clear FER, the CPU must read FER after it has been set to 1, then write a 0

in this bit. (Initial value)

1 This bit is set to 1 if a framing error occurs (stop bit = 0).

Bit 3—Parity Error (PER): This bit indicates a parity error during data reception in the

asynchronous mode, when a communication format with parity bits is used.

This bit has no meaning in the synchronous mode, or when a communication format without

parity bits is used.

Bit 3: PER Description

0 To clear PER, the CPU must read PER after it has been set to 1, then write a 0

in this bit. (Initial value)

1 This bit is set to 1 when a parity error occurs (the parity of the received data

does not match the parity selected by the O/E bit in SMR).

245

Bit 2—Transmit End (TEND): This bit indicates that the serial communication interface has

stopped transmitting because there was no valid data in TDR when the last bit of the current

character was transmitted. The TEND bit is also set to 1 when the TE bit in the serial control

The TEND bit is a read-only bit and cannot be modified directly. To use the TEI interrupt, first

start transmitting data, which clears TEND to 0, then set TEIE to 1.

Bit 2: TEND Description

0 To clear TEND, the CPU must read TDRE after TDRE has been set to 1, then

write a 0 in TDRE

1 This bit is set to 1 when: (Initial value)

1. TE = 0

2. TDRE = 1 at the end of transmission of a character

Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a

multiprocessor format in asynchronous communication mode. This bit retains its previous value in

synchronous mode, when a multiprocessor format is not used, or when the RE bit is cleared to 0

even if a multiprocessor format is used.

MPB can be read but not written.

Bit 1: MPB Description

0 Multiprocessor bit = 0 in receive data. (Initial value)

1 Multiprocessor bit = 1 in receive data.

Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted

in transmit data when a multiprocessor format is used in asynchronous communication mode. The

MPBT bit is double-buffered in the same way as TSR and TDR. The MPBT bit has no effect in

synchronous mode, or when a multiprocessor format is not used.

Bit 0: MPBT Description

0 Multiprocessor bit = 0 in transmit data. (Initial value)

Multiprocessor bit = 1 in transmit data.

246

12.2.8 Bit Rate Register (BRR)

Bit 76543210

Initial value 1 1 1 1 1 1 1 1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR, determines the bit

rate output by the baud rate generator.

BRR is initialized to H'FF by a reset and in the standby modes.

Tables 12.3 to 12.6 show examples of BRR settings.

247

Table 12.3 Examples of BRR Settings in Asynchronous Mode (When øP = ø)

ø (MHz)

2 2.097152

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 1 141 +0.03 1 148 –0.04

150 1 103 +0.16 1 108 +0.21

300 0 207 +0.16 0 217 +0.21

600 0 103 +0.16 0 108 +0.21

1200 0 51 +0.16 0 54 –0.70

2400 0 25 +0.16 0 26 +1.14

4800 0 12 +0.16 0 13 –2.48

9600 — — — 0 6 –2.48

19200 — — — — — —

31250 0 1 0 — — —

38400 — — — — — —

ø (MHz)

2.4576 3 3.6864 4

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 1 174 –0.26 2 52 +0.50 2 64 +0.70 2 70 +0.03

150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16

300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16

600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16

1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16

2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16

4800 0 15 0 0 19 –2.34 0 23 0 0 25 +0.16

9600 0 7 0 0 9 –2.34 0 11 0 0 12 +0.16

19200 0 3 0 0 4 –2.34 0 5 0 — — —

31250 — — — 0 2 0 — — — 0 3 0

38400 0 1 0 — — — 0 2 0 — — —

Note: If possible, the error should be within 1%.

248

ø (MHz)

4.9152 5 6 6.144

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 86 +0.31 2 88 –0.25 2 106 –0.44 2 108 +0.08

150 1 255 0 2 64 +0.16 2 77 0 2 79 0

300 1 127 0 1 129 +0.16 1 155 0 1 159 0

600 0 255 0 1 64 +0.16 1 77 0 1 79 0

1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0

2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0

4800 0 31 0 0 32 –1.36 0 38 +0.16 0 39 0

9600 0 15 0 0 15 +1.73 0 19 –2.34 0 19 0

19200 0 7 0 0 7 +1.73 0 9 –2.34 0 4 0

31250 0 4 –1.70 0 4 0 0 5 0 0 5 +2.40

38400 0 3 0 0 3 +1.73 0 4 –2.34 0 4 0

ø (MHz)

7.3728 8 9.8304 10

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 130 –0.07 2 141 +0.03 2 174 –0.26 3 43 +0.88

150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16

300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16

600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16

1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16

2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16

4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16

9600 0 23 0 0 25 +0.16 0 31 0 0 32 –1.36

19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73

31250 — — — 0 7 0 0 9 –1.70 0 9 0

38400 0 5 0 — — — 0 7 0 0 7 +1.73

Note: If possible, the error should be within 1%.

249

ø (MHz)

12 12.288 14.7456 16

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 212 +0.03 2 217 +0.08 3 64 +0.76 3 70 +0.03

150 2 155 +0.16 2 159 0 2 191 0 2 207 +0.16

300 2 77 +0.16 2 79 0 2 95 0 2 103 +0.16

600 1 155 +0.16 1 159 0 1 191 0 1 207 +0.16

1200 1 77 +0.16 1 79 0 1 95 0 1 103 +0.16

2400 0 155 +0.16 0 159 0 0 191 0 0 207 +0.16

4800 0 77 +0.16 0 79 0 0 95 0 0 103 +0.16

9600 0 38 +0.16 0 39 0 0 47 0 0 51 +0.16

19200 0 19 –2.34 0 19 0 0 23 0 0 25 +0.16

31250 0 11 0 0 11 +2.4 0 14 –1.7 0 15 0

38400 0 9 –2.34 0 9 0 0 11 0 0 12 +0.16

Note: If possible, the error should be within 1%.

250

Table 12.4 Examples of BRR Settings in Asynchronous Mode (When øP = ø/2)

ø (MHz)

2 2.097152

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 1 70 0.03 1 73 0.64

150 1 51 0.16 1 54 –0.70

300 0 207 0.16 0 217 0.21

600 0 103 0.16 0 108 0.21

1200 0 51 0.16 0 54 –0.70

2400 0 25 0.16 0 26 1.14

4800 0 12 0.16 0 13 –2.48

9600 — — — 0 6 –2.48

19200 — — — — — —

31250 0 1 0 — — —

38400 — — — — — —

ø (MHz)

2.4576 3 3.6864 4

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 1 86 0.31 1 106 –0.44 1 130 –0.07 1 141 0.03

150 1 63 0 1 77 0.16 1 95 0 1 103 0.16

300 0 255 0 1 38 0.16 1 47 0 1 51 0.16

600 0 127 0 0 155 0.16 0 191 0 0 207 0.16

1200 0 63 0 0 77 0.16 0 95 0 0 103 0.16

2400 0 31 0 0 38 0.16 0 47 0 0 51 0.16

4800 0 15 0 0 19 –2.34 0 23 0 0 25 0.16

9600 0 7 0 0 9 –2.34 0 11 0 0 12 0.16

19200 0 3 0 0 4 –2.34 0 5 0 — — —

31250 — — — 0 2 0 — — — 0 3 0

38400 0 1 0 — — — 0 2 0 0 2 8.51

251

ø (MHz)

4.9152 5 6 6.144

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 1 174 –0.26 1 177 –0.25 1 212 0.03 1 217 0.08

150 1 127 0 1 129 0.16 1 155 0.16 1 159 0

300 1 63 0 1 64 0.16 1 77 0.16 1 79 0

600 0 255 0 1 32 1.36 1 38 0.16 1 39 0

1200 0 127 0 0 129 0.16 0 155 0.16 0 159 0

2400 0 63 0 0 64 0.16 0 77 0.16 0 79 0

4800 0 31 0 0 32 –1.36 0 38 0.16 0 39 0

9600 0 15 0 0 15 1.73 0 19 –2.34 0 19 0

19200 0 7 0 0 7 1.73 0 9 –2.34 0 9 0

31250 0 4 –1.70 0 4 0 0 5 0 0 5 2.40

38400 0 3 0 0 3 1.73 0 4 –2.34 0 4 0

ø (MHz)

7.3728 8 9.8304 10

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25

150 1 191 0 1 207 0.16 1 255 0 2 64 0.16

300 1 95 0 1 103 0.16 1 127 0 1 129 0.16

600 1 47 0 1 51 0.16 1 63 0 1 64 0.16

1200 0 191 0 0 207 0.16 0 255 0 1 32 1.36

2400 0 95 0 0 103 0.16 0 127 0 0 129 0.16

4800 0 47 0 0 51 0.16 0 63 0 0 64 0.16

9600 0 23 0 0 25 0.16 0 31 0 0 32 –1.36

19200 0 11 0 0 12 0.16 0 15 0 0 15 1.73

31250 — — — 0 7 0 0 9 –1.70 0 9 0

38400 0 5 0 — — — 0 7 0 0 7 1.73

252

ø (MHz)

12 12.288 14.7456 16

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03

150 2 77 0.16 2 79 0 2 95 0 2 103 0.16

300 1 155 0.16 1 159 0 1 191 0 1 207 0.16

600 1 77 0.16 1 79 0 1 95 0 1 103 0.16

1200 1 38 0.16 1 39 0 1 47 0 1 51 0.16

2400 0 155 0.16 0 159 0 0 191 0 0 207 0.16

4800 0 77 0.16 0 79 0 0 95 0 0 103 0.16

9600 0 38 0.16 0 39 0 0 47 0 0 51 0.16

19200 0 19 –2.34 0 19 0 0 23 0 0 25 0.16

31250 0 11 0 0 11 2.40 0 14 –1.70 0 15 0

38400 0 9 –2.34 0 9 0 0 11 0 0 12 0.16

Legend:

Blank: No setting is available

—: A setting is available, but error occurs.

253

Note: If possible, the error should be within 1%.

N = 64 × 22n–1 × B× 106 – 1

B = FF

64 × 22n–1 × (N + 1) × 106

B: Bit rate (bits/second)

N: Baud rate generator BRR value (0 ≤ N ≤ 255)

F: øP (MHz) when n ≠ 0, or ø (MHz) when n = 0

n: Baud rate generator input clock (n = 0, 1, 2, 3)

The meaning of n is given below.

SMR WSCR

n CKS1 CKS0 CKDBL Clock

000 0ø

101 0ø/4

210 0ø/16

311 0ø/64

000 1ø

101 1ø/8

210 1ø/32

311 1ø/128

The bit rate error can be calculated with the formula below.

Error (%) = (N + 1) × B × 64 × 22n–1 – 1 × 100

F × 106

254

Table 12.5 Examples of BRR Settings in Synchronous Mode (When øP = ø)

ø (MHz)

Bit Rate 24581016

(bits/s) n N n N n N n N n N n N

100 —— —— —— —— —— ——

250 2 124 2 249 —— 3 124 —— 3 249

500 1 249 2 124 —— 2 249 —— 3 124

1 k 1 124 1 249 —— 2 124 —— 2 249

2.5 k 0 199 1 99 1 124 1 199 1 249 2 99

5 k 0 99 0 199 0 249 1 99 1 124 1 199

10 k 0 49 0 99 0 124 0 199 0 249 1 99

25 k 0 19 0 39 0 49 0 79 0 99 0 159

50 k 0 9 0 19 0 24 0 39 0 49 0 79

100 k 0 4 0 9 —— 019 024 039

250 k 0 1 0 3 0 4 0 7 0 9 0 15

500 k 0 0*01 —— 03 04 07

1 M 0 0*—— 01 —— 03

2.5 M 0 0*——

4 M 00*

Legend:

Blank: No setting is available

—: A setting is available, but error occurs.

*: Continuous transfer is not possible

255

Table 12.6 Examples of BRR Settings in Synchronous Mode (When øP = ø/2)

ø (MHz)

Bit Rate 24581016

(bits/s) n N n N n N n N n N n N

100 —— —— —— —— —— ——

250 1 249 2 124 —— 2 249 —— 3 124

500 1 124 1 249 —— 2 124 —— 2 249

1 k —— 1 124 —— 1 249 —— 2 124

2.5 k 0 199 1 49 —— 1 99 1 124 1 199

5 k 0 99 0 199 0 249 1 49 —— 199

10 k 0 49 0 99 0 124 0 199 0 249 1 49

25 k 0 19 0 39 0 49 0 79 0 99 0 159

50 k 0 9 0 19 0 24 0 39 0 49 0 79

100 k 0 4 0 9 —— 019 024 039

250 k 0 1 0 3 0 4 0 7 0 9 0 15

500 k 0 0*01 —— 03 04 07

1 M 0 0*—— 01 —— 03

2.5 M —— 00*——

4 M —— 00*

Legend:

Blank: No setting is available

—: A setting is available, but error occurs.

*: Continuous transfer is not possible

256

N = 8 × 22n–1 × B× 106 – 1

B = FF

8 × 22n–1 × (N + 1) × 106

B: Bit rate (bits/second)

N: Baud rate generator BRR value (0 ≤ N ≤ 255)

F: øP (MHz) when n ≠ 0, or ø (MHz) when n = 0

n: Baud rate generator input clock (n = 0, 1, 2, 3)

The meaning of n is given below.

SMR WSCR

n CKS1 CKS0 CKDBL Clock

000 0ø

101 0ø/4

210 0ø/16

311 0ø/64

000 1ø

101 1ø/8

210 1ø/32

311 1ø/128

257

12.2.9 Serial/Timer Control Register (STCR)

Bit 76543210

IICS IICD IICX IICE STAC MPE ICKS1 ICKS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the

TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset.

Bits 7 to 4—I2C Control (IICS, IICD, IICX, IICE): These bits control operation of the I2C bus

interface. For details, refer to section 13, I2C Bus Interface.

Bit 3—Slave Input Switch (STAC): Controls the input pin of the host interface. For details,

section 14, Host Interface.

Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication

function on channels SCI0 and SCI1.

Bit 2: MPE Description

0 The multiprocessor communication function is disabled, regardless of the

setting of the MP bit in SMR. (Initial value)

1 The multiprocessor communication function is enabled. The multi-processor

format can be selected by setting the MP bit in SMR to 1.

Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the

clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit

Timers.

258

12.3 Operation

12.3.1 Overview

The SCI supports serial data transfer in two modes. In asynchronous mode each character is

synchronized individually. In synchronous mode communication is synchronized with a clock

signal.

The selection of asynchronous or synchronous mode and the communication format depend on

SMR settings as indicated in table 12.7. The clock source depends on the settings of the C/A bit in

the SMR and the CKE1 and CKE0 bits in SCR as indicated in table 12.8.

Asynchronous Mode

• Data length: 7 or 8 bits can be selected.

• A parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be

selected. (These selections determine the communication format and character length.)

• Framing errors (FER), parity errors (PER), and overrun errors (ORER) can be detected in

receive data, and the line-break condition can be detected.

• SCI clock source: An internal or external clock source can be selected.

• Internal clock: The SCI is clocked by the on-chip baud rate generator and can output a clock

signal at the bit-rate frequency.

• External clock: The external clock frequency must be 16 times the bit rate. (The on-chip baud

rate generator is not used.)

Synchronous Mode

• Communication format: The data length is 8 bits.

• Overrun errors (ORER) can be detected in receive data.

• SCI clock source: An internal or external clock source can be selected.

• Internal clock: The SCI is clocked by the on-chip baud rate generator and outputs a serial clock

signal to external devices.

• External clock: The on-chip baud rate generator is not used. The SCI operates on the input

serial clock.

259

Table 12.7 Communication Formats Used by SCI

SMR Settings Communication Format

Bit 7:

C/ABit 6:

CHR Bit 2:

MP Bit 5:

PE Bit 3:

STOP Mode Data

Length

Multi-

processor

Bit Parity

Bit

Stop

Bit

Length

00000 Asynchronous 8 bits None None 1 bit

1mode 2 bits

1 0 Present 1 bit

1 2 bits

1 0 0 7 bits None 1 bit

1 2 bits

1 0 Present 1 bit

1 2 bits

01—0 Asynchronous 8 bits Present None 1 bit

1mode (multi- 2 bits

processor format) 7 bits 1 bit

1 2 bits

1———— Synchronous

mode 8 bits None None

Table 12.8 SCI Clock Source Selection

SMR SCR Serial Transmit/Receive Clock

Bit 7:

C/ABit 1:

CKE1 Bit 0:

CKE0 Mode Clock Source SCK Pin Function

0 0 0 Async Internal Input/output port (not used by SCI)

1 Serial clock output at bit rate

1 0 External Serial clock input at 16 × bit rate

1 0 0 Sync Internal Serial clock output

1 0 External Serial clock input

260

12.3.2 Asynchronous Mode

In asynchronous mode, each transmitted or received character is individually synchronized by

framing it with a start bit and stop bit.

Full duplex data transfer is possible because the SCI has independent transmit and receive

sections. Double buffering in both sections enables the SCI to be programmed for continuous data

transfer.

Figure 12.2 shows the general format of one character sent or received in asynchronous mode. The

communication channel is normally held in the mark state (high). Character transmission or

reception starts with a transition to the space state (low).

The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which

the least significant bit (LSB) comes first. The data bits are followed by the parity or

multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame.

In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the

center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).

D0 D1 DnStart bit

1 bit 7 or 8 bits

One unit of data (one character or frame)

Parity or

multipro-

cessor bit Stop bit

0 or 1 bit 1 or 2 bits

Idle state

(mark)

Figure 12.2 Data Format in Asynchronous Mode

261

Data Format

Table 12.9 lists the data formats that can be sent and received in asynchronous mode. Twelve

formats can be selected by bits in the serial mode register (SMR).

Table 12.9 Data Formats in Asynchronous Mode

SMR Bits

CHR PE MP STOP 123456789101112

0000 S 8-bit data STOP

0001 S 8-bit data STOP STOP

0100 S 8-bit data P STOP

0101 S 8-bit data P STOP STOP

1000 S 7-bit data STOP

1001 S 7-bit data STOP STOP

1100 S 7-bit data P STOP

1101 S 7-bit data P STOP STOP

0—1 0 S 8-bit data MPB STOP

0—1 1 S 8-bit data MPB STOP STOP

1—1 0 S 7-bit data MPB STOP

1—1 1 S 7-bit data MPB STOP STOP

Notes: SMR: Serial mode register

S: Start bit

STOP: Stop bit

P: Parity bit

MPB: Multiprocessor bit

262

Clock

In asynchronous mode it is possible to select either an internal clock created by the on-chip baud

rate generator, or an external clock input at the SCK pin. The selection is made by the C/A bit in

the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR).

Refer to table 12.8.

If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate.

If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is

used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises

at the center of the transmit data bits. Figure 12.3 shows the phase relationship between the output

clock and transmit data.

0 D0D1D2D3D4

One frame

D5 D6 D7 0/1 1 1

Figure 12.3 Phase Relationship between Clock Output and Transmit Data

(Asynchronous Mode)

Transmitting and Receiving Data

SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to 0

in the serial control register (SCR), then initialize the SCI following the procedure in figure 12.4.

Note: When changing the communication mode or format, always clear the TE and RE bits to 0

before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and

initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize

the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their

previous contents.

When an external clock is used, the clock should not be stopped during initialization or

subsequent operation. SCI operation becomes unreliable if the clock is stopped.

263

Clear TE and RE bits to

0 in SCR

1 bit interval

elapsed?

Start transmitting or receiving

Yes

Select interrupts and the clock source in the

serial control register (SCR). Leave TE and RE

cleared to 0. If clock output is selected, in

asynchronous mode, clock output starts

immediately after the setting is made in SCR.

Select the communication format in the serial

mode register (SMR).

Write the value corresponding to the bit rate in

the bit rate register (BRR). This step is not

necessary when an external clock is used.

Wait for at least the interval required to transmit

or receive one bit, then set TE or RE in the serial

control register (SCR). Setting TE or RE enables

the SCI to use the TxD or RxD pin.

Also set the RIE, TIE, TEIE, and MPIE bits as

necessary to enable interrupts. The initial states

are the mark transmit state, and the idle receive

state (waiting for a start bit).

Set CKE1 and CKE0 bits in

SCR (leaving TE and RE

cleared to 0)

Set TE or RE to 1 in SCR,

and set RIE, TIE, TEIE, and

MPIE as necessary

Initialization

Set value in BRR

Select communication

format in SMR

Figure 12.4 Sample Flowchart for SCI Initialization

264

Transmitting Serial Data: Follow the procedure in figure 12.5 for transmitting serial data.

Start transmitting

Read TDRE bit in SSR

TDRE = 1?

Write transmit data in TDR

End of

transmission?

End

Yes

SCI initialization: the transmit data output function

of the TxD pin is selected automatically.

After the TE bit is set to 1, one frame of 1s is output,

then transmission is possible.

SCI status check and transmit data write: read

the serial status register (SSR), check that the

TDRE bit is 1, then write transmit data in the

transmit data register (TDR) and clear TDRE to 0.

If a multiprocessor format is selected, after

writing the transmit data write 0 or 1 in the

multiprocessor bit transfer (MPBT) in SSR.

Transition of the TDRE bit from 0 to 1 can be

reported by an interrupt.

To continue transmitting serial data: read the

TDRE bit to check whether it is safe to write; if

TDRE = 1, write data in TDR, then clear TDRE

to 0.

To end serial transmission: end of transmission

can be confirmed by checking transition of the

TEND bit from 0 to 1. This can be reported by

a TEI interrupt.

To output a break signal at the end of serial

transmission: set the DDR bit to 1 and clear the

DR bit to 0 (DDR and DR are I/O port registers),

then clear TE to 0 in SCR.

(a)

(b)

If using multiprocessor format,

select MPBT value in SSR

Clear TDRE bit to 0

Read TEND bit in SSR

TEND = 1? No

Yes

Output break

signal? No

Yes

Clear TE bit in SCR to 0

Initialize

Set DR = 0, DDR = 1

Serial transmission

Figure 12.5 Sample Flowchart for Transmitting Serial Data

265

In transmitting serial data, the SCI operates as follows.

1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that

the transmit data register (TDR) contains new data, and loads this data from TDR into the

transmit shift register (TSR).

2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts

transmitting. If the TIE bit (TDR-empty interrupt enable) is set to 1 in SCR, the SCI requests a

TXI interrupt (TDR-empty interrupt) at this time.

Serial transmit data are transmitted in the following order from the TxD pin:

a. Start bit: One 0 bit is output.

b. Transmit data: Seven or eight bits are output, LSB first.

c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor

bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can

also be selected.

d. Stop bit: One or two 1 bits (stop bits) are output.

e. Mark state: Output of 1 bits continues until the start bit of the next transmit data.

3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, after loading new data

from TDR into TSR and transmitting the stop bit, the SCI begins serial transmission of the next

frame. If TDRE is 1, after setting the TEND bit to 1 in SSR and transmitting the stop bit, the

SCI continues 1-level output in the mark state, and if the TEIE bit (TSR-empty interrupt

enable) in SCR is set to 1, the SCI generates a TEI interrupt request (TSR-empty interrupt).

Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.

266

1Start

bit

0 D0 D1 D7 0/1

Stop

bit

Data Parity

bit Start

bit

0 D0 D1 D7 0/1

Stop

bit

Data Parity

bit 1

Idle state

(mark)

TDRE

TEND

TXI

request TXI interrupt handler

writes data in TDR and

clears TDRE to 0

TXI

request

1 frame

TEI request

Figure 12.6 Example of SCI Transmit Operation

(8-Bit Data with Parity and One Stop Bit)

267

Receiving Serial Data: Follow the procedure in figure 12.7 for receiving serial data.

Start receiving

RDRF = 1?

Read receive data from RDR,

and clear RDRF bit to 0

in SSR

PER ∨ RER ∨

ORER = 1?

Clear RE to 0 in SCR

Finished

receiving?

End

Error handling

Start error handling

FER = 1?

Discriminate and

process error, and

clear flags

Return

Break?

Clear RE to 0

in SCR

End

Yes

SCI initialization: the receive data function of the RxD

pin is selected automatically.

To continue receiving serial data: read RDR and

clear RDRF to 0 before the stop bit of the current

frame is received.

SCI status check and receive data read: read the

serial status register (SSR), check that RDRF is set

to 1, then read receive data from the receive data

the RDRF bit from 0 to 1 can be reported by an RXI

interrupt.

Receive error handling and break detection: if a

receive error occurs, read the ORER, PER, and

FER bits in SSR to identify the error. After executing

the necessary error handling, clear ORER, PER, and

FER all to 0. Transmitting and receiving cannot

resume if ORER, PER, or FER remains set to 1.

When a framing error occurs, the RxD pin can be

read to detect the break state.

Yes

Initialize

Read ORER, PER, and

FER in SSR

Read RDRF bit in SSR

Figure 12.7 Sample Flowchart for Receiving Serial Data

268

In receiving, the SCI operates as follows.

1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit.

2. Receive data is shifted into RSR in order from LSB to MSB.

3. The parity bit and stop bit are received.

After receiving these bits, the SCI makes the following checks:

a. Parity check: The number of 1s in the receive data must match the even or odd parity

setting of the O/E bit in SMR.

b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit

is checked.

c. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR.

If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of

the checks fails (receive error), the SCI operates as indicated in table 12.10.

Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1.

Be sure to clear the error flags.

4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the

SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is

set to 1 and the RIE bit in SCR is also set to 1, the SCI requests an ERI (receive-error)

interrupt.

Table 12.10 Receive Error Conditions and SCI Operation

Receive Error Abbreviation Condition Data Transfer

Overrun error ORER Receiving of next data ends

while RDRF is still set to 1

in SSR

Receive data not loaded from

RSR into RDR

Framing error FER Stop bit is 0 Receive data loaded from

RSR into RDR

Parity error PER Parity of receive data differs

from even/odd parity setting

in SMR

Receive data loaded from

RSR into RDR

269

Figure 12.8 shows an example of SCI receive operation in asynchronous mode.

1Start

bit

0 D0 D1 D7 0/1

Stop

bit

Data Parity

bit Start

bit

0 D0 D1 D7 0/1

Stop

bit

Data Parity

bit 1

Idle state

(mark)

RDRF

FER

1 frame

Framing error,

ERI request

RXI interrupt handler

reads data in RDR and

clears RDRF to 0

RXI

request

Figure 12.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)

Multiprocessor Communication

The multiprocessor communication function enables several processors to share a single serial

communication line. The processors communicate in asynchronous mode using a format with an

additional multiprocessor bit (multiprocessor format).

In multiprocessor communication, each receiving processor is addressed by an ID.

A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the

receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending

cycles from data-sending cycles.

The transmitting processor starts by sending the ID of the receiving processor with which it wants

to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends

transmit data with the multiprocessor bit cleared to 0.

Receiving processors skip incoming data until they receive data with the multiprocessor bit set to

After receiving data with the multiprocessor bit set to 1, the receiving processor with an ID

matching the received data continues to receive further incoming data. Multiple processors can

send and receive data in this way.

Four formats are available. Parity-bit settings are ignored when a multiprocessor format is

selected. For details see table 12.9.

270

Transmitting

processor

Receiving

processor A

Serial communication line

Receiving

processor B Receiving

processor C Receiving

processor D

(ID = 01) (ID = 02) (ID = 03) (ID = 04)

Serial data H'01 H'AA

(MPB = 1) (MPB = 0)

ID-sending cycle:

receiving processor address Data-sending cycle:

data sent to receiving

processor specified by ID

MPB: Multiprocessor bit

Figure 12.9 Example of Communication among Processors using Multiprocessor Format

(Sending Data H'AA to Receiving Processor A)

271

Transmitting Multiprocessor Serial Data: See figures 12.5 and 12.6.

Receiving Multiprocessor Serial Data: Follow the procedure in figure 12.10 for receiving

multiprocessor serial data.

Start receiving

Set MPIE bit to 1 in SCR

FER ∨

ORER = 1?

FER +

ORER = 1?

Finished

receiving?

Clear RE to 0 in SCR

End

Error handling FER = 1?

Discriminate and

process error, and

clear flags

Return

Break?

Clear RE bit to

0 in SCR

End

Yes

1. SCI initialization: the receive data function of the RxD pin is

selected automatically.

2. ID receive cycle: Set the MPIE bit in the serial control register

(SCR) to 1.

3. SCI status check and ID check: read the serial status register

(SSR), check that RDRF is set to 1, then read receive data

from the receive data register (RDR) and compare with the

processor’s own ID. Transition of the RDRF bit from 0 to

1 can be reported by an RXI interrupt. If the ID does not match

the receive data, set MPIE to 1 again and clear RDRF to 0.

If the ID matches the receive data, clear RDRF to 0.

4. SCI status check and data receiving: read SSR, check that

RDRF is set to 1, then read data from the receive data register

(RDR) and write 0 in the RDRF bit. Transition of the RDRF bit

from 0 to 1 can be reported by an RXI interrupt.

5. Receive error handling and break detection: if a receive error

occurs, read the ORER and FER bits in SSR to identify the error.

After executing the necessary error handling, clear both ORER

and FER to 0. Receiving cannot resume while ORER or FER

remains set to 1. When a framing error occurs, the RxD pin

can be read to detect the break state.

Yes

Initialize

Start error handling

Read RDRF bit in SSR

RDRF = 1?

Read ORER and FER

bits in SSR

Own ID? No

Yes

Read RDRF bit in SSR

RDRF = 1?

Read ORER and FER

bits in SSR

Read receive data from RDR

Figure 12.10 Sample Flowchart for Receiving Multiprocessor Serial Data

272

Figure 12.11 shows an example of an SCI receive operation using a multiprocessor format (8-bit

data with multiprocessor bit and one stop bit).

1Start

bit

0D0D1 D71

Stop

bit

Data (ID1) MPB Start

bit

0D0D1 D70

Stop

bit

Data (Data1) MPB 1

Idle state

(mark)

MPIE

RDRF

RDR value ID1

RXI requestMPB detection

MPIE = 0

RXI requestMPB detection

MPIE = 0

RXI handler reads

RDR data and clears

RDRF to 0

Not own ID, so

MPIE is set to

1 again

No RXI request,

RDR not updated

(Multiprocessor interrupt)

(a) Own ID does not match data

1Start

bit

0D0D1 D71

Stop

bit

Data (ID2) MPB Start

bit

0D0D1 D70

Stop

bit

Data (Data2) MPB 1

Idle state

(mark)

MPIE

RDRF

RDR value ID2

RXI handler reads

RDR data and clears

RDRF to 0

Own ID, so receiving

continues, with data

received at each RXI

MPIE set to

1 again

(Multiprocessor interrupt)

(b) Own ID matches data

Data 2

Figure 12.11 Example of SCI Receive Operation

(8-Bit Data with Multiprocessor Bit and One Stop Bit)

273

12.3.3 Synchronous Mode

Overview

In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.

This mode is suitable for high-speed serial communication.

The SCI transmitter and receiver share the same clock but are otherwise independent, so full

duplex communication is possible. The transmitter and receiver are also double buffered, so

continuous transmitting or receiving is possible by reading or writing data while transmitting or

receiving is in progress.

Figure 12.12 shows the general format in synchronous serial communication.

Serial clock

Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

LSB MSB

Don’t care Don’t care

One unit (character or frame) of serial data

Note: High except in continuous transmitting or receiving*

Figure 12.12 Data Format in Synchronous Communication

In synchronous serial communication, each data bit is sent on the communication line from one

falling edge of the serial clock to the next. Data is received in synchronization with the rising edge

of the serial clock.

In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After

output of the MSB, the communication line remains in the state of the MSB.

Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit

can be added.

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register

(SCR). See table 12.8.

When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock

pulses are output per transmitted or received character. When the SCI is not transmitting or

receiving, the clock signal remains at the high level.

274

Transmitting and Receiving Data

SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See

figure 12.4. When switching from asynchronous mode to synchronous mode, check that the

ORER, FER, and PER bits are cleared to 0. Transmitting and receiving cannot begin if ORER,

FER, or PER is set to 1.

Transmitting Serial Data: Follow the procedure in figure 12.13 for transmitting serial data.

Start transmitting

Read TDRE bit in SSR

TDRE = 1?

Write transmit data in

TDR and clear TDRE bit to

0 in SSR

End of

transmission?

End

Yes

SCI initialization: the transmit data output function

of the TxD pin is selected automatically.

SCI status check and transmit data write: read

the serial status register (SSR), check that the

TDRE bit is 1, then write transmit data in the

transmit data register (TDR) and clear TDRE to 0.

Transition of the TDRE bit from 0 to 1 can be

reported by a TXI interrupt.

To continue transmitting serial data: read the

TDRE bit to check whether it is safe to write; if

TDRE = 1, write data in TDR, then clear TDRE

to 0.

To end serial transmission: end of transmission

can be confirmed by checking transition of the

TEND bit from 0 to 1. This can be reported by

a TEI interrupt.

(a)

(b)

Read TEND bit in SSR

TEND = 1? No

Yes

Initialize

Clear TE bit to 0 in SCR

Serial transmission

Figure 12.13 Sample Flowchart for Serial Transmitting

275

In transmitting serial data, the SCI operates as follows.

1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that

the transmit data register (TDR) contains new data, and loads this data from TDR into the

transmit shift register (TSR).

2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts

transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to 1, the SCI requests a

TXI interrupt (TDR-empty interrupt) at this time.

If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of

the TDRE bit to 0. If an external clock source is selected, the SCI outputs data in

synchronization with the input clock.

Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).

3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads

data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the

SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the output in the MSB state.

If the TEIE bit (transmit-end interrupt enable) in SCR is set to 1, a TEI interrupt (TSR-empty

interrupt) is requested at this time.

4. After the end of serial transmission, the SCK pin is held at the high level.

Figure 12.14 shows an example of SCI transmit operation.

Serial clock

Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

TXI

request

TDRE

TEND

TXI interrupt

handler writes

data in TDR and

clears TDRE to 0

TXI

request TEI

request

1 frame

Figure 12.14 Example of SCI Transmit Operation

276

Receiving Serial Data: Follow the procedure in figure 12.15 for receiving serial data. When

switching from asynchronous mode to synchronous mode, be sure to check that PER and FER are

cleared to 0. If PER or FER is set to 1 the RDRF bit will not be set and both transmitting and

receiving will be disabled.

Start receiving

Read ORER bit in SSR

ORER = 1?

RDRF = 1?

Read RDRF in SSR

Finished

receiving?

Clear RE to 0 in SCR

End

Error handling

Yes

SCI initialization: the receive data function of the

RxD pin is selected automatically.

Receive error handling: if a receive error occurs,

read the ORER bit in SSR then, after executing

the necessary error handling, clear ORER to 0.

Neither transmitting nor receiving can resume

while ORER remains set to 1. When clock

output mode is selected, receiving can be halted

temporarily by receiving one dummy byte and

causing an overrun error. When preparations

to receive the next data are completed, clear

the ORER bit to 0. This causes receiving to

resume, so return to the step marked 2 in the

flowchart.

SCI status check and receive data read: read

the serial status register (SSR), check that

RDRF is set to 1, then read receive data from

the receive data register (RDR) and clear RDRF

to 0. Transition of the RDRF bit from 0 to 1

can be reported by an RXI interrupt.

To continue receiving serial data: read RDR and

clear RDRF to 0 before the MSB (bit 7) of the

current frame is received.

Clear ORER to 0 in SSR

Return

Overrun error handling

Start error handling

Initialize

Read receive data

from RDR, and clear

RDRF bit to 0 in SSR

Figure 12.15 Sample Flowchart for Serial Receiving

277

In receiving, the SCI operates as follows.

1. If an external clock is selected, data is input in synchronization with the input clock. If clock

output is selected, as soon as the RE bit is set to 1 the SCI begins outputting the serial clock

and inputting data. If clock output is stopped because the ORER bit is set to 1, output of the

serial clock and input of data resume as soon as the ORER bit is cleared to 0.

2. Receive data is shifted into RSR in order from LSB to MSB.

After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from

RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in

RDR. If the check does not pass (receive error), the SCI operates as indicated in

table 12.10.

Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF

bit is not set to 1. Be sure to clear the error flag.

3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the

SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and the RIE bit in SCR

is set to 1, the SCI requests an ERI (receive-error) interrupt.

When clock output mode is selected, clock output stops when the RE bit is cleared to 0 or the

ORER bit is set to 1. To prevent clock count errors, it is safest to receive one dummy byte and

generate an overrun error.

Figure 12.16 shows an example of SCI receive operation.

Serial clock

Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

RXI

request

RDRF

ORER

RXI interrupt

handler reads

data in RDR and

clears RDRF to 0

RXI

request Overrun error,

ERI request

1 frame

Figure 12.16 Example of SCI Receive Operation

278

Transmitting and Receiving Serial Data Simultaneously: Follow the procedure in figure 12.17

for transmitting and receiving serial data simultaneously. If clock output mode is selected, output

of the serial clock begins simultaneously with serial transmission.

Start

Read TDRE bit in SSR

TDRE = 1?

Write transmit data

in TDR and clear TDRE

bit to 0 in SSR

RDRF = 1?

Read ORER bit in SSR

End of

transmitting and

receiving?

Clear TE and RE bits

to 0 in SCR

End

Error handling

Yes

SCI initialization: the transmit data output function of

the TxD pin and receive data input function of the

RxD pin are selected, enabling simultaneous

transmitting and receiving.

SCI status check and transmit data write: read the

serial status register (SSR), check that the TDRE bit

is 1, then write transmit data in the transmit data

TDRE bit from 0 to 1 can be reported by a TXI interrupt.

SCI status check and receive data read: read the

serial status register (SSR), check that the RDRF

bit is 1, then read receive data from the receive data

the RDRF bit from 0 to 1 can be reported by an RXI

interrupt.

Receive error handling: if a receive error occurs, read

the ORER bit in SSR then, after executing the

necessary error handling, clear ORER to 0. Neither

transmitting nor receiving can resume while ORER

remains set to 1.

To continue transmitting and receiving serial data:

read RDR and clear RDRF to 0 before the MSB

(bit 7) of the current frame is received. Also read the

TDRE bit and check that it is set to 1, indicating that

it is safe to write; then write data in TDR and clear

TDRE to 0 before the MSB (bit 7) of the current frame

is transmitted.

ORER = 1?

Read RDRF bit in SSR

Initialize

Read receive data

from RDR and clear

RDRF bit to 0 in SSR

Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both

TE and RE to 0, then set TE and RE to 1 simultaneously using an MOV instruction. Do not use a

BEST instruction for this purpose.

Figure 12.17 Sample Flowchart for Serial Transmitting and Receiving

279

12.4 Interrupts

The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 12.11 indicates the

source and priority of these interrupts. The interrupt sources can be enabled or disabled by the

TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for

each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three

sources: overrun error, framing error, and parity error.

The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates

that the SCI has stopped transmitting data.

Table 12.11 SCI Interrupt Sources

Interrupt Description Priority

ERI Receive-error interrupt (ORER, FER, or PER) High

RXI Receive-end interrupt (RDRF)

TXI TDR-empty interrupt (TDRE)

TEI TSR-empty interrupt (TEND) Low

12.5 Application Notes

Application programmers should note the following features of the SCI.

TDR Write: The TDRE bit in SSR is simply a flag that indicates that the TDR contents have been

transferred to TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new

byte is written in TDR while the TDRE bit is 0, before the old TDR contents have been moved

into TSR, the old byte will be lost. Software should check that the TDRE bit is set to 1 before

writing to TDR.

Multiple Receive Errors: Table 12.12 lists the values of flag bits in the SSR when multiple

receive errors occur, and indicates whether the RSR contents are transferred to RDR.

280

Table 12.12 SSR Bit States and Data Transfer when Multiple Receive Errors Occur

SSR Bits RSR →

Receive Error RDRF ORER FER PER RDR*2

Overrun error 1*1100No

Framing error 0010Yes

Parity error 0001Yes

Overrun and framing errors 1*1110No

Overrun and parity errors 1*1101No

Framing and parity errors 0011Yes

Overrun, framing, and parity errors 1*1111No

Notes: *1 Set to 1 before the overrun error occurs.

*2 Yes: The RSR contents are transferred to RDR.

No: The RSR contents are not transferred to RDR.

Line Break Detection: When the RxD pin receives a continuous stream of 0’s in asynchronous

mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value

H'00 is transferred from RSR to RDR. Software can detect the line-break state as a framing error

accompanied by H'00 data in RDR.

The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will

occur.

Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the

SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is detected

by sampling the RxD input on the falling edge of this clock. After the start bit is detected, each bit

of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on

the rising edge of the serial clock pulse at the center of the bit. See figure 12.18.

It follows that the receive margin can be calculated as in equation (1).

When the absolute frequency deviation of the clock signal is 0 and the clock duty cycle is 0.5, data

can theoretically be received with distortion up to the margin given by equation (2). This is a

theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.

281

12 4

0567893 2123456789 111 12 1314 15 1610 13 14 1516 1210 11 3 4 5

Basic

clock

Sync

sampling

Data

sampling

D0 D1

Receive

data Start bit

–7.5 pulses +7.5 pulses

Figure 12.18 Sampling Timing (Asynchronous Mode)

M = {(0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} × 100 [%] ................................... (1)

M: Receive margin

N: Ratio of basic clock to bit rate (N=16)

D: Duty factor of clock—ratio of high pulse width to low width (0.5 to 1.0)

L: Frame length (9 to 12)

F: Absolute clock frequency deviation

When D = 0.5 and F = 0

M = (0.5 –1/2 × 16) × 100 [%] = 46.875% ......................................................... (2)

282

283

Section 13 I2C Bus Interface [Option]

An I2C bus interface is available as an option. Observe the following notes when using this option.

For mask-ROM versions, products that use this option have a “W” added to the product number.

Examples: HD6433437WTF, HD6433434WF

13.1 Overview

The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus)

interface functions. The register configuration that controls the I2C bus differs partly from the

Philips configuration, however.

The I2C bus interface uses only one data line (SDA) and one clock line (SCL) to transfer data, so it

can save board and connector space. Figure 13.1 shows typical I2C bus interface connections.

13.1.1 Features

• Conforms to Philips I2C bus interface

• Start and stop conditions generated automatically

• Selectable acknowledge output level when receiving

• Auto-loading of acknowledge bit when transmitting

• Selection of eight internal clocks (in master mode)

• Selection of acknowledgement mode, or serial mode without acknowledge bit

• Wait function: A wait can be inserted in acknowledgement mode by holding the SCL pin low

after a data transfer, before acknowledgement of the transfer.

• Three interrupt sources

 Data transfer end

 In slave receive mode: slave address matched, or general call address received

 In master transmit mode: bus arbitration lost

• Direct bus drive (pins SCL and SDA)

• In addition to pins SCL and SCA, four general port pins (PA4 to PA7) can also drive the bus

• Pins P86/SCK1/SCL, P97/WAIT/SDA, and PA4/KEYIN12 to PA7/KEYIN15 (total of 6 pins) are

all powered by bus power supply VCCB, separate from VCC. When the bus drive function is

selected, all output is NMOS output.

284

SCL in

SCL out

SDA in

SDA out

(Slave 1)

SCL

SDA

SCL in

SCL out

SDA in

SDA out

(Slave 2)

SCL

SDA

SCL in

SCL out

SDA in

SDA out

(Master)

SCL

SDA

SCL

SDA

VCC

VCC VCCB

VCCB

H8/3437

Figure 13.1 I2C Bus Interface Connection Example

(When the H8/3437 is the Master Chip)

285

13.1.2 Block Diagram

Figure 13.2 shows a block diagram of the I2C bus interface.

øPPS

Noise

canceler

Noise

canceler

Clock

control

Bus state

decision

circuit

Arbitration

decision

circuit

Output data

control

circuit

Address

comparator

SAR

Interrupt

generator

ICDR

ICSR

ICMR

ICCR

STCR

Internal data bus

Interrupt

request

SCL

SDA

Legend:

ICCR:

ICMR:

ICSR:

ICDR:

SAR:

PS:

STCR:

I2C bus control register

I2C bus mode register

I2C bus status register

I2C bus data register

Slave address register

Prescaler

Serial timer control re

ister

Figure 13.2 Block Diagram of I2C Bus Interface

286

13.1.3 Input/Output Pins

Table 13.1 summarizes the input/output pins used by the I2C bus interface.

Table 13.1 Wait-State Controller Pins

Name Abbreviation I/O Function

Serial clock SCL Input/output Serial clock input/output

Serial data SDA Input/output Serial data input/output

13.1.4 Register Configuration

Table 13.2 summarizes the registers of the I2C bus interface.

Table 13.2 Register Configuration

Name Abbreviation R/W Initial Value Address*2

I2C bus control register ICCR R/W H'00 H'FFD8

I2C bus status register ICSR R/W H'30 H'FFD9

I2C bus data register ICDR R/W — H'FFDE

I2C bus mode register ICMR R/W H'38 H'FFDF*1

Slave address register SAR R/W H'00 H'FFDF*1

Serial timer control register STCR R/W H'00 H'FFC3

Notes: *1 The register that can be written or read depends on the ICE bit in the I2C bus control

*2 The addresses assigned to the I2C bus interface registers are also assigned to other

registers. The accessible registers are selected with bit IICE in the serial/timer control

287

13.2 Register Descriptions

13.2.1 I2C Bus Data Register (ICDR)

Bit 76543210

ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0

Initial value — — — — — — — —

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

ICDR is an 8-bit readable/writable register that is used as a transmit data register when

transmitting and a receive data register when receiving. Transmitting is started by writing data in

ICDR. Receiving is started by reading data from ICDR.

ICDR is also used as a shift register, so it must not be written or read until data has been

completely transmitted or received. Read or write access while data is being transmitted or

received may result in incorrect data.

The ICDR value following a reset and in hardware standby mode is undetermined.

13.2.2 Slave Address Register (SAR)

Bit 76543210

SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

SAR is an 8-bit readable/writable register that stores the slave address and selects the

communication format. When the chip is in slave mode (and the addressing format is selected), if

the upper 7 bits of SAR match the upper 7 bits of the first byte received after a start condition, the

chip operates as the slave device specified by the master device. SAR is assigned to the same

address as ICMR. SAR can be written and read only when the ICE bit is cleared to 0 in ICCR.

SAR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,

differing from the addresses of other slave devices connected to the I2C bus.

288

Bit 0—Format Select (FS): Selects whether to use the addressing format or non-addressing

format in slave mode. The addressing format is used to recognize slave addresses.

Bit 0: FS Description

0 Addressing format, slave addresses recognized (Initial value)

1 Non-addressing format

13.2.3 I2C Bus Mode Register (ICMR)

Bit 76543210

MLS WAIT — — — BC2 BC1 BC0

Initial value 0 0 1 1 1 0 0 0

Read/Write R/W R/W — — — R/W R/W R/W

ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred

first, performs wait control, and selects the transfer bit count. ICMR is assigned to the same

address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR.

ICMR is initialized to H'38 by a reset and in hardware standby mode.

Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or

LSB-first.

Bit 7: MLS Description

0 MSB-first (Initial value)

1 LSB-first

Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data

and the acknowledge bit, in acknowledgement mode. When WAIT is set to 1, after the fall of the

clock for the final data bit, a wait state begins (with SCL staying at the low level). When bit IRIC

is cleared in ICSR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0,

data and acknowledge bits are transferred consecutively with no wait inserted.

Bit 6: WAIT Description

0 Data and acknowledge transferred consecutively (Initial value)

1 Wait inserted between data and acknowledge

289

Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 1.

Bits 2 to 0—Bit Counter (BC2 to BC0): BC2 to BC0 specify the number of bits to be transferred

next. When the ACK bit is cleared to 0 in ICCR (acknowledgement mode), the data is transferred

with one additional acknowledge bit. BC2 to BC0 settings should be made during an interval

between transfer frames. If BC2 to BC0 are set to a value other than 000, the setting should be

made while the SCL line is low.

The bit counter is initialized to 000 by a reset and when a start condition is detected. The value

returns to 000 at the end of a data transfer, including the acknowledge.

Bit 2: Bit 1: Bit 0: Bits/Frame

BC2 BC1 BC0 Serial Mode Acknowledgement Mode

0008 9 (Initial value)

11 2

102 3

13 4

1004 5

15 6

106 7

17 8

13.2.4 I2C Bus Control Register (ICCR)

Bit 76543210

ICE IEIC MST TRS ACK CKS2 CKS1 CKS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables or

disables interrupts, and selects master or slave mode, transmit or receive, acknowledgement or

serial mode, and the clock frequency.

ICCR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—I2C Bus Interface Enable (ICE): Selects whether or not to use the I2C bus interface.

When ICE is set to 1, the SCL and SDA signals are assigned to input/output pins and transfer

operations are enabled. When ICE is cleared to 0, the interface module is disabled.

290

The SAR register can be accessed when ICE is 0. The ICMR register can be accessed when ICE is

Bit 7: ICE Description

0 Interface module disabled, with SCL and SDA signals in high-impedance state

(Initial value)

1 Interface module enabled for transfer operations (pins SCL and SDA are

driving the bus*)

Note: *Pin SDA is multiplexed with the WAIT input pin. In expanded mode, WAIT input has priority

for this pin.

Bit 6—I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C

bus interface to the CPU.

Bit 6: IEIC Description

0 Interrupts disabled (Initial value)

1 Interrupts enabled

Bit 5—Master/Slave Select (MST)

Bit 4—Transmit/Receive Select (TRS)

MST selects whether the I2C bus interface operates in master mode or slave mode.

TRS selects whether the I2C bus interface operates in transmit mode or receive mode.

In master mode, when arbitration is lost, MST and TRS are both reset by hardware, causing a

transition to slave receive mode. In slave receive mode with the addressing format (FS = 0),

hardware automatically selects transmit or receive mode according to the R/W bit in the first byte

after a start condition.

MST and TRS select the operating mode as follows.

Bit 5: MST Bit 4: TRS Operating Mode

0 0 Slave receive mode (Initial value)

1 Slave transmit mode

1 0 Master receive mode

1 Master transmit mode

291

Bit 3—Acknowledgement Mode Select (ACK): Selects acknowledgement mode or serial mode.

In acknowledgement mode (ACK = 0), data is transferred in frames consisting of the number of

data bits selected by BC2 to BC0 in ICMR, plus an extra acknowledge bit. In serial mode (ACK =

1), the number of data bits selected by BC2 to BC0 in ICMR is transferred as one frame.

Bit 3: ACK Description

0 Acknowledgement mode (Initial value)

1 Serial mode

Bits 2 to 0—Serial Clock Select (CKS2 to CKS0): These bits, together with the ICCX bit in the

STCR register, select the serial clock frequency in master mode. They should be set according to

the required transfer rate.

(STCR) Bit 2: Bit 1: Bit 0: Transfer Rate*

IICX CKS2 CKS1 CKS0 Clock øP = 5 MHz øP = 8 MHz øP = 10 MHz øP = 16 MHz

0 000ø

P/28 179 kHz 286 kHz 357 kHz 571 kHz

1ø

P/40 125 kHz 200 kHz 250 kHz 400 kHz

10ø

P/48 104 kHz 167 kHz 208 kHz 333 kHz

1ø

P/64 78.1 kHz 125 kHz 156 kHz 250 kHz

100ø

P/80 62.5 kHz 100 kHz 125 kHz 200 kHz

1ø

P/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz

10ø

P/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz

1ø

P/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz

1 000ø

P/56 89.3 kHz 143 kHz 179 kHz 286 kHz

1ø

P/80 62.5 kHz 100 kHz 125 kHz 200 kHz

10ø

P/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz

1ø

P/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz

100ø

P/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz

1ø

P/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz

10ø

P/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz

1ø

P/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz

Note: *øP = ø.

The shaded setting exceeds the maximum transfer rate in the standard I2C bus

specifications.

292

13.2.5 I2C Bus Status Register (ICSR)

Bit 76543210

BBSY IRIC SCP — AL AAS ADZ ACKB

Initial value 0 0 1 1 0 0 0 0

Read/Write R/W R/(W)*W — R/(W)*R/(W)*R/(W)*R/W

Note: *Only 0 can be written, to clear the flag.

ICSR is an 8-bit readable/writable register with flags that indicate the status of the I2C bus

interface. It is also used for issuing start and stop conditions, and recognizing and controlling

acknowledge data.

ICSR is initialized to H'30 by a reset and in hardware standby mode.

Bit 7—Bus Busy (BBSY): This bit can be read to check whether the I2C bus (SCL and SDA) is

busy or free. In master mode this bit is also used in issuing start and stop conditions.

A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting

BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,

clearing BBSY to 0.

To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit

start condition is issued in the same way. To issue a stop condition, use a MOV instruction to

write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode.

Bit 7: BBSY Description

0 Bus is free (Initial value)

This bit is cleared when a stop condition is detected.

1 Bus is busy

This bit is set when a start condition is detected.

293

Bit 6—I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface

has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a

slave address or general call address is detected in slave receive mode, and when bus arbitration is

lost in master transmit mode. IRIC is set at different timings depending on the ACK bit in ICCR

and WAIT bit in ICMR. See the item on IRIC Set Timing and SCL Control in section 13.3.6

IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.

Bit 6: IRIC Description

0 Waiting for transfer, or transfer in progress (Initial value)

To clear this bit, the CPU must read IRIC when IRIC = 1, then write 0 in IRIC

1 Interrupt requested

This bit is set to 1 at the following times:

Master mode

• End of data transfer

• When bus arbitration is lost

Slave mode (when FS = 0)

• When the slave address is matched, and whenever a data transfer ends at

the timing of a retransmit start condition after address matching or a stop

condition is detected

• When a general call address is detected, and whenever a data transfer

ends at the timing of a retransmit start condition after address detection or a

stop condition is detected

Slave mode (when FS = 1)

• End of data transfer

Bit 5—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop

conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A start

condition for retransmit is issued in the same way. To issue a stop condition, write 0 in BBSY and

0 in SCP. This bit always reads 1. Written data is not stored.

Bit 5: SCP Description

0 Writing 0 issues a start or stop condition, in combination with BBSY

1 Reading always results in 1 (Initial value)

Writing is ignored

Bit 4—Reserved: This bit cannot be modified and is always read as 1.

294

Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The

I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at

nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL

to 1 to indicate that the bus has been taken by another master. At the same time, it sets the IRIC bit

in ICSR to generate an interrupt request.

AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is

reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive

mode.

Bit 3: AL Description

0 Bus arbitration won (Initial value)

This bit is cleared to 0 at the following times:

• When ICDR data is written (transmit mode) or read (receive mode)

• When AL is read while AL = 1, then 0 is written in AL

1 Arbitration lost

This bit is set to 1 at the following times:

• If the internal SDA signal and bus line disagree at the rise of SCL in master

transmit mode

• If the internal SCL is high at the fall of SCL in master transmit mode

Bit 2—Slave Address Recognition Flag (AAS): When the addressing format is selected (FS = 0)

in slave receive mode, this flag is set to 1 if the first byte following a start condition matches bits

SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.

AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS

is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive

mode.

Bit 2: AAS Description

0 Slave address or general call address not recognized (Initial value)

This bit is cleared to 0 at the following times:

• When ICDR data is written (transmit mode) or read (receive mode)

• When AAS is read while AAS = 1, then 0 is written in AAS

1 Slave address or general call address recognized

This bit is set to 1 at the following times:

• When the slave address or general call address is detected in slave receive

mode

295

Bit 1—General Call Address Recognition Flag (ADZ): When the addressing format is selected

(FS = 0) in slave receive mode, this flag is set to 1 if the first byte following a start condition is the

general call address (H'00).

ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ

is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive

mode.

Bit 1: ADZ Description

0 General call address not recognized (Initial value)

This bit is cleared to 0 at the following times:

• When ICDR data is written (transmit mode) or read (receive mode)

• When ADZ is read while ADZ = 1, then 0 is written in ADZ

1 General call address recognized

This bit is set to 1 when the general call address is detected in slave receive

mode

Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data in acknowledgement mode. In

transmit mode, after the receiving device receives data, it returns acknowledge data, and this data

is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in

this bit is sent to the transmitting device.

When this bit is read, if TRS = 1, the value loaded from the bus line is read. If TRS = 0, the value

set by internal software is read.

Bit 0: ACKB Description

0 Receive mode: 0 is output at acknowledge output timing (Initial value)

Transmit mode: indicates that the receiving device has acknowledged the data

1 Receive mode: 1 is output at acknowledge output timing

Transmit mode: indicates that the receiving device has not acknowledged the

data

296

13.2.6 Serial/Timer Control Register (STCR)

Bit 76543210

IICS IICD IICX IICE STAC MPE ICKS1 ICKS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the

TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset and in hardware

standby mode.

Bit 7—I2C Extra Buffer Select (IICS): Makes bits 7 to 4 of port A into output buffers similar to

SCL and SDA. Used when an I2C bus interface is implemented by software alone.

Bit 7: IICS Description

0PA

7 to PA4 are normal input/output pins (Initial value)

1PA

7 to PA4 are input/output pins that can drive the bus

Bit 6—I2C Extra Buffer Reserve (IICD): This bit is reserved, but it can be written and read. Its

initial value is 0.

Bit 5—I2C Transfer Rate Select (IICX): This bit, in combination with bits CKS2 to CKS0 in

ICCR, selects the transfer rate in master mode. For details regarding the transfer rate, refer to

section 13.2.4, I2C Bus Control Register (ICCR).

Bit 4—I2C Master Enable (IICE): Controls CPU access to the data and control registers (ICCR,

ICSR, ICDR, ICMR/SAR) of the I2C bus interface.

Bit 4: IICE Description

0 CPU access to I2C bus interface data and control registers is disabled

(Initial value)

1 CPU access to I2C bus interface data and control registers is enabled

Bit 3—Slave Input Switch (STAC): Switches host interface input pins. For details, see section

14, Host Interface.

Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication

function on channels SCI0 and SCI1. For details, see section 12, Serial Communication Interface.

Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits select the

clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit

Timers.

297

13.3 Operation

13.3.1 I2C Bus Data Format

The I2C bus interface has three data formats: two addressing formats, shown as (a) and (b) in

figure 13.3, and a non-addressing format, shown as (c) in figure 13.4. The first byte following a

start condition always consists of 8 bits. Figure 13.5 shows the I2C bus timing.

S SLA R/WA DATA A A/AP

111 1

(a) Addressing format (FS = 0)

(b) Addressing format (retransmit start condition, FS = 0)

n: Bit count

(n = 1 to 8)

m: Frame count

(m ≥ 1)

S SLA R/WA DATA

111 n1

1m1

S SLA R/WA DATA A/AP

111 n2

1m2

A/A

n1 and n2: Bit count (n1 and n2 = 1 to 8)

m1 and m2: Frame count (m1 and m2 ≥ 1)

Figure 13.3 I2C Bus Data Formats (Addressing Formats)

S DATA A DATA A A/AP

111

n: Bit count

(n = 1 to 8)

m: Frame count

(m ≥ 1)

Figure 13.4 I2C Bus Data Format (Non-Addressing Format)

Legend:

S: Start condition. The master device drives SDA from high to low while SCL is high.

SLA: Slave address, by which the master device selects a slave device.

R/W: Indicates the direction of data transfer: from the slave device to the master device when

R/W is 1, or from the master device to the slave device when R/W is 0.

298

A: Acknowledge. The receiving device (the slave in master transmit mode, or the master in

master receive mode) drives SDA low to acknowledge a transfer. If transfers need not be

acknowledged, set the ACK bit to 1 in ICCR to keep the interface from generating the

acknowledge signal and its clock pulse.

DATA: Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or

LSB-first format is selected by bit MLS in ICMR.

P: Stop condition. The master device drives SDA from low to high while SCL is high.

SDA

SCL

1-7

SLA

R/W

1-7

DATA

89 1-7 89

A DATA A/AP

Figure 13.5 I2C Bus Timing

13.3.2 Master Transmit Operation

In master transmit mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal. The transmit procedure and operations in master

transmit mode are described below.

1. Set bits MLS and WAIT in ICMR and bits ACK and CKS2 to CKS0 in ICCR according to the

operating mode. Set bit ICE in ICCR to 1.

2. Read BBSY in ICSR, check that the bus is free, then set MST and TRS to 1 in ICCR to select

master transmit mode. After that, write 1 in BBSY and 0 in SCP. This generates a start

condition by causing a high-to-low transition of SDA while SCL is high.

3. Write data in ICDR. The master device outputs the written data together with a sequence of

transmit clock pulses at the timing shown in figure 13.6. If FS is 0 in SAR, the first byte

following the start condition contains a 7-bit slave address and indicates the transmit/receive

direction. The selected slave device (the device with the matching slave address) drives SDA

low at the ninth transmit clock pulse to acknowledge the data.

4. When one byte of data has been transmitted, IRIC is set to 1 in ICSR at the rise of the ninth

transmit clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. After one frame

has been transferred, SCL is automatically brought to the low level in synchronization with the

internal clock and held low.

299

5. Software clears IRIC to 0 in ICSR.

6. To continue transmitting, write the next transmit data in ICDR. Transmission of the next byte

will begin in synchronization with the internal clock.

Steps 4 to 6 can be repeated to transmit data continuously. To end the transmission, write 0 in

BBSY and 0 in SCP in ICSR. This generates a stop condition by causing a low-to-high transition

of SDA while SCL is high.

1987654321

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7

SCL

SDA (master

output)

SDA (slave

output)

IRIC

User

processing 2. Write BBSY = 1

and SCP = 0

Interrupt

request

3. Write to ICDR 5. Clear IRIC 6. Write to ICDR

Figure 13.6 Timing in Master Transmit Mode

(MLS = WAIT = ACK = 0)

300

13.3.3 Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data, and returns an

acknowledge signal. The slave device transmits the data. The receive procedure and operations in

master receive mode are described below. See also figure 13.7.

1. Clear TRS to 0 in ICCR to switch from transmit mode to receive mode.

2. Read ICDR to start receiving. When ICDR is read, a receive clock is output in synchronization

with the internal clock, and data is received. At the ninth clock pulse the master device drives

SDA low to acknowledge the data.

3. When one byte of data has been received, IRIC is set to 1 in ICSR at the rise of the ninth

receive clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. After one frame

has been transferred, SCL is automatically brought to the low level in synchronization with the

internal clock and held low.

4. Software clears IRIC to 0 in ICSR.

5. When ICDR is read, receiving of the next data starts in synchronization with the internal clock.

Steps 3 to 5 can be repeated to receive data continuously. To stop receiving, set TRS to 1, read

ICDR, then write write 0 in BBSY and 0 in SCP in ICSR. This generates a stop condition by

causing a low-to-high transition of SDA while SCL is high. If it is not necessary to acknowledge

each byte of data, set ACKB to 1 in ICSR before receiving starts.

301

98765432119

ABit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7

Interrupt

request Interrupt

request

Master

transmit

mode Master receive mode

SCL

SDA (slave

output)

SDA (master

output)

IRIC

User processing 2. Read ICDR 4. Clear IRIC 5. Read ICDR

Figure 13.7 Timing in Master Receive Mode

(MLS = WAIT = ACK = ACKB = 0)

302

13.3.4 Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, and the master device outputs

the transmit clock and returns an acknowledge signal. The transmit procedure and operations in

slave transmit mode are described below.

1. Set bits MLS and WAIT in ICMR and bits MST, TRS, ACK, and CKS2 to CKS0 in ICCR

according to the operating mode. Set bit ICE in ICCR to 1, establishing slave receive mode.

2. After the slave device detects a start condition, if the first byte matches its slave address, at the

ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the same

time, IRIC is set to 1 in ICSR, generating an interrupt. If the eighth data bit (R/W) is 1, the

TRS bit is set to 1 in ICCR, automatically causing a transition to slave transmit mode. The

slave device holds SCL low from the fall of the transmit clock until data is written in ICDR.

3. Software clears IRIC to 0 in ICSR.

4. Write data in ICDR. The slave device outputs the written data serially in step with the clock

output by the master device, with the timing shown in figure 13.8.

5. When one byte of data has been transmitted, at the rise of the ninth transmit clock pulse IRIC

is set to 1 in ICSR. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. The slave device

holds SCL low from the fall of the transmit clock until data is written in ICDR. The master

device drives SDA low at the ninth clock pulse to acknowledge the data. The acknowledge

signal is stored in ACKB in ICSR, and can be used to check whether the transfer was carried

out normally.

6. Software clears IRIC to 0 in ICSR.

7. To continue transmitting, write the next transmit data in ICDR.

Steps 5 to 7 can be repeated to transmit continuously. To end the transmission, write H'FF in

ICDR. When a stop condition is detected (a low-to-high transition of SDA while SCL is high),

BBSY will be cleared to 0 in ICSR.

303

Slave receive

mode Slave transmit mode

SCL (master

output)

SCL (slave

output)

SDA (slave

output)

SDA (master

output)

89 123456789 1

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7

R/W A

Interrupt

request Interrupt

request

User processing 3. Clear IRIC 4. Write to ICDR 6. Clear IRIC 7. Write to ICDR

IRIC

Figure 13.8 Timing in Slave Transmit Mode

(MLS = WAIT = ACK = 0)

304

13.3.5 Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal. The receive procedure and operations in slave receive

mode are described below. See also figure 13.9.

1. Set bits MLS and WAIT in ICMR and bits MST, TRS, and ACK in ICCR according to the

operating mode. Set bit ICE in ICCR to 1, establishing slave receive mode.

2. A start condition output by the master device sets BBSY to 1 in ICSR.

3. After the slave device detects the start condition, if the first byte matches its slave address, at

the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the

same time, IRIC is set to 1 in ICSR. If IEIC is 1 in ICCR, a CPU interrupt is requested. The

slave device holds SCL low from the fall of the receive clock until it has read the data in

ICDR.

4. Software clears IRIC to 0 in ICSR.

5. When ICDR is read, receiving of the next data starts.

Steps 4 and 5 can be repeated to receive data continuously. When a stop condition is detected (a

low-to-high transition of SDA while SCL is high), BBSY is cleared to 0 in ICSR.

Start condition

SCL (master

output)

SCL (slave

output)

SDA (master

output

SDA (slave

output)

IRIC

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7

Interrupt

request

4. Clear IRIC 5. Read ICDR

User processing

1987654321

Figure 13.9 Timing in Slave Receive Mode

(MLS = WAIT = ACK = ACKB = 0)

305

13.3.6 IRIC Set Timing and SCL Control

The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR and

ACK bit in ICCR. SCL is automatically held low after one frame has been transferred; this timing

is synchronized with the internal clock. Figure 13.10 shows the IRIC set timing and SCL control.

(a) When WAIT = 0 and ACK = 0

SCL

SDA

IRIC

User processing Clear IRIC Write to ICDR (transmit)

or read ICDR (receive)

1A87

(b) When WAIT = 1 and ACK = 0

SCL

SDA

IRIC

User processing Clear IRIC Write to ICDR (transmit)

or read ICDR (receive)

Note: The ICDR write (transmit) or read (receive) following the clearing of IRIC

should be executed after the rise of SCL (ninth clock pulse).

SCL

SDA

IRIC

User processing

Clear IRIC Write to ICDR (transmit)

or read ICDR (receive)

A871

87 1

Figure 13.10 IRIC Set Timing and SCL Control

306

13.3.7 Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched

internally. Figure 13.11 shows a block diagram of the noise canceler.

The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)

input signal is sampled on the system clock, but is not passed forward to the next circuit unless the

outputs of both latches agree. If they do not agree, the previous value is held.

Sampling clock

Latch

SCL or

SDA input

signal Match

detector Internal

SCL or

SDA

signal

Sampling

clock

t: S

stem clock

Figure 13.11 Block Diagram of Noise Canceler

307

13.3.8 Sample Flowcharts

Figures 13.12 to 13.15 show typical flowcharts for using the I2C bus interface in each mode.

Start

Initialize

Read BBSY in ICSR

No BBSY = 0?

Yes

Set MST = 1 and

TRS = 1 in ICCR

Write BBSY = 1

and SCP = 0 in ICSR

Write transmit data in ICDR

Read IRIC in ICSR

Yes

IRIC = 1?

Clear IRIC in ICSR

Read ACKB in ICSR

ACKB = 0? No

Yes No

Yes

Transmit mode?

Write transmit data in ICDR

Read IRIC in ICSR

IRIC = 1?

Yes

Clear IRIC in ICSR

Read ACKB in ICSR

End of transmission

(ACKB = 1)?

Yes

Write BBSY = 0

and SCP = 0 in ICSR

End

Master receive mode

1. Test the status of the SCL and SDA lines.

2. Select master transmit mode.

3. Generate a start condition.

4. Set transmit data for the first byte (slave address + R/W).

5. Wait for 1 byte to be transmitted.

6. Test for acknowledgement by the designated slave device.

7. Set transmit data for the second and subsequent bytes.

8. Wait for 1 byte to be transmitted.

9. Test for end of transfer.

10. Generate a stop condition.

Figure 13.12 Flowchart for Master Transmit Mode (Example)

308

Master receive mode

Set TRS = 0 in ICCR

Set ACKB = 0 in ICSR

Last receive?

Read ICDR

Read IRIC in ICSR

Clear IRIC in ICSR

IRIC = 1?

Yes

Set ACKB = 1 in ICSR

Read ICDR

Read IRIC in ICSR

IRIC = 1?

Clear IRIC in ICSR

Set TRS = 1 in ICCR

Read ICDR

Write BBSY = 0

and SCP = 0 in ICSR

End

Yes

1. Select receive mode.

2. Set acknowledgement data.

3. Start receiving. The first read is a dummy read.

4. Wait for 1 byte to be received.

5. Set acknowledgement data for the last receive.

6. Start the last receive.

7. Wait for 1 byte to be received.

8. Select transmit mode.

9. Read the last receive data (if ICDR is read

without selecting transmit mode, receive

operations will resume).

10. Generate a stop condition.

Figure 13.13 Flowchart for Master Receive Mode (Example)

309

Slave transmit mode

Write transmit data in ICDR

Read IRIC in ICSR

IRIC = 1?

Clear IRIC in ICSR

Read ACKB in ICSR

Write TRS = 0 in ICCR

End

of transmission

(ACKB = 1?)

Yes

End

Read ICDR 5

1. Set transmit data for the second and

subsequent bytes.

2. Wait for 1 byte to be transmitted.

3. Test for end of transfer.

4. Select slave receive mode.

5. Dummy read (to release the SCL line).

Figure 13.14 Flowchart for Slave Transmit Mode (Example)

310

Start

Initialize

Set MST = 0

and TRS = 0 in ICCR

Write ACKB = 0 in ICSR

Read IRIC in ICSR

IRIC = 1? Yes

Clear IRIC in ICSR

Read AAS and ADZ in ICSR

AAS = 1

and ADZ = 0?

Read TRS in ICCR

TRS = 0?

Yes

Last receive?

Read ICDR

Read IRIC in ICSR

IRIC = 1?

Clear IRIC in ICSR

Set ACKB = 1 in ICSR

Read ICDR

Read IRIC in ICSR

Clear IRIC in ICSR

IRIC = 1?

Read ICDR

End

General call address processing

* Description omitted

Slave transmit mode

1. Select slave receive mode.

2. Wait for the first byte to be received.

3. Start receiving. The first read is a dummy read.

4. Wait for the transfer to end.

5. Set acknowledgement data for the last receive.

6. Start the last receive.

7. Wait for the transfer to end.

8. Read the last receive data.

Figure 13.15 Flowchart for Slave Receive Mode (Example)

311

13.4 Application Notes

• In master mode, if an instruction to generate a start condition is immediately followed by an

instruction to generate a stop condition, neither condition will be output correctly. To output

consecutive start and stop conditions, after issuing the instruction that generates the start

condition, read the relevant ports, check that SCL and SDA are both low, then issue the

instruction that generates the stop condition.

• Either of the following two conditions will start the next transfer. Pay attention to these

conditions when reading or writing to ICDR.

 Write access to ICDR when ICE = 1 and TRS = 1

 Read access to ICDR when ICE = 1 and TRS = 0

• The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-

speed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes

one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds

the time determined by the input clock of the I2C bus interface, the high period of SCL is

extended. SCL rise time is determined by the pull-up resistance and load capacitance of the

SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and

load capacitance so that the SCL rise time falls below the values given in the table below.

tcyc Time Display

CKDBL IICX Display ø = 5 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz

0 0 7.5tcyc Normal

mode 1000 ns 937 ns 750 ns 486 ns

High-speed

mode 300 ns 300 ns 300 ns 300 ns

0 1 17.5tcyc Normal

mode 1000 ns 1000 ns 1000 ns 1000 ns

1 0 High-speed

mode 300 ns 300 ns 300 ns 300 ns

1 1 37.5tcyc Normal

mode 1000 ns 1000 ns 1000 ns 1000 ns

High-speed

mode 300 ns 300 ns 300 ns 300 ns

• Note on Issuance of Retransmission Start Condition

When issuing a retransmission start condition, the condition must be issued after the SCL clock

falls during the acknowledge bit reception period. After the end of the acknowledge bit, the

next data should be written to ICDR after SCL goes high. Figure 13.16 shows the

recommended program flow for issuing a retransmission start condition. A timing chart for the

flowchart in figure 13.16 is shown in figure 13.17.

312

IRIC = 1?

Read IRIC in ICSR

Clear IRIC in ICSR

Retransmission?

Read SCL

SCL = 0?

Write 1 to BBSY and

0 to SCP in ICSR

Read SCL

Write data to ICDR

Other operation

Yes

SCL = 1?

Yes

(1) Confirm completion of 1-

byte transmission

(2) Confirm that SCL is low

(3) Issue retransmission

start condition

(4) Confirm that SCL is high

(5) Write transmit data

Note: “Read SCL” means

reading DR for the

SCL pin.

Figure 13.16 Recommended Program Flow for Retransmission Start Condition Issuance

SCL

SDA

IRIC

(1) IRIC check (2) SCL low level

determination (4) SCL high level

determination (5) Transmit data setting

(3) Retransmission start

condition issuance

ACK Bit 7

Figure 13.17 Timing Chart for Retransmission Start Condition Issuance

313

• Note on Issuance of Stop Condition

If the rise of SCL is weakened by external pull-up resistance R and bus load capacitance C in

master mode, or if SCL is pulled to the low level by a slave device, the timing at which SCL is

lowered by the internal bit synchronization circuit may be delayed by 1t SCL. If, in this case,

SCL is identified as being low at the bit synchronization circuit sampling timing, and a stop

condition issuing instruction is executed before the reference SCL clock next falls, as in figure

13.18, SDA will change from high to low to high while SCL remains high. As a result, a stop

condition will be issued before the end of the 9th clock.

Bit synchronization circuit sampling timing

VIH

Normal operation

Erroneous

operation

SCL output

SDA output

SCL output

SDA output

Normal

operation

Erroneous

operation

Reference clock

SCL

SDA

IRIC

Bus line

Stop condition issuing instruction

execution timing

9th clock not ended Stop condition

Stop condition

High interval secured

SCL identified as low

Figure 13.18 Stop Condition Erroneous Operation Timing

314

• Countermeasure

Figure 13.19 shows the recommended program flow.

IRIC = 1?

Read IRIC in ICSR

Read ACKB in ICSR

ACKB = 1?

Read SCL

SCL = 0?

Write 0 to BBSY and

0 to SCP in ICSR

Transmit

data present?

Write data to ICDR

Yes

Figure 13.19 Recommended Program Flow

• Additional Note

When switching from master receive mode to master transmit mode, ensure that TRS is set to 1

before the last receive data is latched by reading ICDR.

• Precautions when Clearing the IRIC Flag when Using the Wait Function

If the SCL rise time exceeds the specified duration when using the wait function in the I2C bus

interface’s master mode, or if there is a slave device that keeps SCL low and applies a wait

state, read SCL and clear the IRIC flag only after determining that SCL has gone low, as

shown below.

If the IRIC flag is cleared to 0 when WAIT is set to 1 and while the SCL high level duration is

being extended, the SDA value may change before SCL falls, erroneously resulting in a start or

stop condition.

315

SCL VIH

SDA

IRIC

IRIC clearedSCL determined to be low level

SCL low level detected

SCL high level duration maintained

Figure 13.20 IRIC Flag Clear Timing when WAIT = 1

Note that the clock may not be output properly during the next master send if receive data

(ICDR data) is read during the time between when the instruction to issue a stop condition is

executed (writing 0 to BBSY and SCP in ISSR) and when the stop condition is actually

generated.

In addition, overwriting of IIC control bits in order to change the send or receive operation

mode or to change settings, such as for example clearing the MST bit after completion of

master send or receive, should always be performed during the period indicated as (a) in Figure

13.21 below (after confirming that the BBSY bit in the ICCR register has been cleared to 0).

Master receive mode

ICDR read F

prohibited duration

BBSY bit

Internal clock

SCL

SDA A

(a)

Bit 0

Stop condition Start condition

Execution of issue

stop condition instruction

(BBSY = 0 and SCP = 0 written)

Stop condition generated

(BBSY = 0 read) Start condition issued

Figure 13.21 Precautions when Reading Master Receive Data

316

317

Section 14 Host Interface

14.1 Overview

The H8/3437 Series has an on-chip host interface (HIF) that provides a dual-channel parallel

interface between the on-chip CPU and a host processor. The host interface is available only when

the HIE bit is set to 1 in SYSCR. This mode is called slave mode, because it is designed for a

master-slave communication system in which the H8/3437-Series chip is slaved to a host

processor.

The host interface consists of four 1-byte data registers, two 1-byte status registers, a 1-byte

control register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried

out via five control signals from the host processor (CS1, CS2 or ECS2, HA0, IOR, and IOW or

EIOW), four output signals to the host processor (GA20, HIRQ1, HIRQ11, and HIRQ12), and an 8-

bit bidirectional command/data bus (HDB7 to HDB0, or XDB7 to XDB0). The CS1 and CS2 (or

ECS2) signals select one of the two interface channels.

Note: If one of the two interface channels will not be used, tie the unused CS pin to VCC. For

example, if interface channel 1 (IDR1, ODR1, STR1) is not used, tie CS1 to VCC.

318

14.1.1 Block Diagram

Figure 14.1 is a block diagram of the host interface.

(Internal interrupt signals)

IBF2 IBF1

Control

logic

HDB7–HDB0/

XDB7–XDB0

IDR1

ODR1

STR1

IDR2

ODR2

STR2

HICR

Module data bus

Host data bus

Host

interrupt

request

Fast

A20

gate

control

Port 4

Port 8

Internal data bus Bus

interface

CS1

ECS2/CS2

IOR

EIOW/IOW

HA0

HIRQ1

HIRQ11

HIRQ12

GA20

Legend:

IDR1:

IDR2:

ODR1:

ODR2:

STR1:

STR2:

HICR:

Input data register 1

Input data register 2

Output data register 1

Output data register 2

Status register 1

Status register 2

Host interface control register

Figure 14.1 Host Interface Block Diagram

319

14.1.2 Input and Output Pins

Table 14.1 lists the input and output pins of the host interface module.

Table 14.1 H/F Input/Output Pins

Name Abbreviation Port I/O Function

I/O read IOR P83Input Host interface read signal

I/O write*IOW P84Input Host interface write signal

EIOW P91

Chip select 1 CS1P82Input Host interface chip select signal for

IDR1, ODR1, STR1

Chip select 2*CS2P85Input Host interface chip select signal for

ECS2P90IDR2, ODR2, STR2

Command/data HA0P80Input Host interface address select signal

In host read access, this signal

selects the status registers (STR1,

STR2) or data registers (ODR1,

ODR2). In host write access to the

data registers (IDR1, IDR2), this

signal indicates whether the host is

writing a command or data.

Data bus HDB7–HDB0P37–P30I/O Host interface data bus (single-chip

mode)

XDB7–XDB0PB7–PB0I/O Host interface data bus (expanded

modes)

Host interrupt 1 HIRQ1P44Output Interrupt output 1 to host

Host interrupt 11 HIRQ11 P43Output Interrupt output 11 to host

Host interrupt 12 HIRQ12 P45Output Interrupt output 12 to host

Gate A20 GA20 P81Output A20 gate control signal output

Note: *Selection between IOW and EIOW, and between CS2 and ECS2, is by the STAC bit in

STCR. IOW and CS2 are used when STAC is 0. EIOW and ECS2 are used when STAC is 1.

In this manual, both are referred to as IOW and CS2.

320

14.1.3 Register Configuration

Table 14.2 lists the host interface registers.

Table 14.2 HIF Registers

R/W Initial Slave Master Address*4

Name Abbreviation Slave Host Value Address*3CS1CS2HA0

System control

Host interface control

Input data register 1 IDR1 R W — H'FFF4 0 1 0/1*5

Output data register 1 ODR1 R/W R — H'FFF5 0 1 0

Status register 1 STR1 R/(W) *2R H'00 H'FFF6 0 1 1

Input data register 2 IDR2 R W — H'FFFC 1 0 0/1*5

Output data register 2 ODR2 R/W R — H'FFFD 1 0 0

Status register 2 STR2 R/(W) *2R H'00 H'FFFE 1 0 1

Serial/timer control

Notes: *1 Bit 3 is a read-only bit.

*2 The user-defined bits (bits 7 to 4) are read/write accessible from the slave processor.

*3 Address when accessed from the slave processor.

*4 Pin inputs used in access from the host processor.

*5 The HA0 input discriminates between writing of commands and data.

321

14.2 Register Descriptions

14.2.1 System Control Register (SYSCR)

Bit 76543210

SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME

Initial value 0 0 0 0 1 0 0 1

Read/Write R/W R/W R/W R/W R R/W R/W R/W

SYSCR is an 8-bit read/write register which controls chip operations. Host interface functions are

enabled or disabled by the HIE bit of SYSCR. See section 3.2, System Control Register, for

information on other SYSCR bits. SYSCR is initialized to H'09 by an external reset and in

hardware standby mode.

Bit 1—Host Interface Enable (HIE): Enables or disables the host interface. When enabled, the

host interface handles host-slave data transfers, operating in slave mode.

Bit 1: HIE Description

0 The host interface is disabled (Initial value)

1 The host interface is enabled (slave mode)

14.2.2 Host Interface Control Register (HICR)

Bit 76543210

— — — — — IBFIE2 IBFIE1 FGA20E

Initial value 1 1 1 1 1 0 0 0

Slave Read/Write — — — — — R/W R/W R/W

Host Read/Write — — — — — — — —

HICR is an 8-bit read/write register which controls host interface interrupts and the fast A20 gate

function. HICR is initialized to H'F8 by a reset and in hardware standby mode.

Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.

322

Bit 2—Input Buffer Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2 interrupt

to the slave CPU.

Bit 2: IBFIE2 Description

0 IDR2 input buffer full interrupt is disabled (Initial value)

1 IDR2 input buffer full interrupt is enabled

Bit 1— Input Buffer Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1 interrupt

to the slave CPU.

Bit 1: IBFIE1 Description

0 IDR1 input buffer full interrupt is disabled (Initial value)

1 IDR1 input buffer full interrupt is enabled

Bit 0—Fast Gate A20 Enable (FGA20E): Enables or disables the fast A20 gate function. When the

fast A20 gate is disabled, a regular-speed A20 gate signal can be implemented by using software to

manipulate the P81 output.

Bit 0: FGA20E Description

0 Disables fast A20 gate function (Initial value)

1 Enables fast A20 gate function

14.2.3 Input Data Register 1 (IDR1)

Bit 76543210

IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0

Initial value — — — — — — — —

Slave Read/Write R R R R R R R R

Host Read/Write W W W W W W W W

IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the

host processor. When CS1 is low, information on the host data bus is written into IDR1 at the

rising edge of IOW. The HA0 state is also latched into the C/D bit in STR1 to indicate whether the

written information is a command or data.

The initial values of IDR1 after a reset or standby are undetermined.

323

14.2.4 Output Data Register 1 (ODR1)

Bit 76543210

ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0

Initial value — — — — — — — —

Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Host Read/Write R R R R R R R R

ODR1 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the

host processor. The ODR1 contents are output on the host data bus when HA0 is low, CS1 is low,

and IOR is low.

The initial values of ODR1 after a reset or standby are undetermined.

14.2.5 Status Register 1 (STR1)

Bit 76543210

DBU DBU DBU DBU C/DDBU IBF OBF

Initial value 0 0 0 0 0 0 0 0

Slave Read/Write R/W R/W R/W R/W R R/W R R

Host Read/Write R R R R R R R R

STR1 is an 8-bit register that indicates status information during host interface processing. Bits 3,

1, and 0 are read-only bits to both the host and slave processors.

STR1 is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.

Bit 3—Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR1,

and indicates whether IDR1 contains data or a command.

Bit 3: C/DDescription

0 Contents of IDR1 are data (Initial value)

1 Contents of IDR1 are a command

324

Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an

internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads

IDR1.

Bit 1: IBF Description

0 This bit is cleared when the slave processor reads IDR1 (Initial value)

1 This bit is set when the host processor writes to IDR1

Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to

0 when the host processor reads ODR1.

Bit 0: OBF Description

0 This bit is cleared when the host processor reads ODR1 (Initial value)

1 This bit is set when the slave processor writes to ODR1

Table 14.3 shows the conditions for setting and clearing the STR1 flags.

Table 14.3 Set/Clear Timing for STR1 Flags

Flag Setting Condition Clearing Condition

C/DRising edge of host’s write signal (IOW)

when HA0 is high Rising edge of host’s write signal (IOW)

when HA0 is low

IBF Rising edge of host’s write signal (IOW)

when writing to IDR1 Falling edge of slave’s internal read signal

(RD) when reading IDR1

OBF Falling edge of slave’s internal write

signal (WR) when writing to ODR1 Rising edge of host’s read signal (IOR)

when reading ODR1

14.2.6 Input Data Register 2 (IDR2)

Bit 76543210

IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0

Initial value — — — — — — — —

Slave Read/Write R R R R R R R R

Host Read/Write W W W W W W W W

IDR2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the

host processor. When CS2 is low, information on the host data bus is written into IDR2 at the

rising edge of IOW. The HA0 state is also latched into the C/D bit in STR2 to indicate whether the

written information is a command or data.

The initial values of IDR2 after a reset or standby are undetermined.

325

14.2.7 Output Data Register 2 (ODR2)

Bit 76543210

ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0

Initial value — — — — — — — —

Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Host Read/Write R R R R R R R R

ODR2 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the

host processor. The ODR2 contents are output on the host data bus when HA0 is low, CS2 is low,

and IOR is low.

The initial values of ODR2 after a reset or standby are undetermined.

14.2.8 Status Register 2 (STR2)

Bit 76543210

DBU DBU DBU DBU C/DDBU IBF OBF

Initial value 0 0 0 0 0 0 0 0

Slave Read/Write R/W R/W R/W R/W R R/W R R

Host Read/Write R R R R R R R R

STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3,

1, and 0 are read-only bits to both the host and slave processors.

STR2 is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.

Bit 3—Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR2,

and indicates whether IDR2 contains data or a command.

Bit 3: C/DDescription

0 Contents of IDR2 are data (Initial value)

1 Contents of IDR2 are a command

326

Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an

internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads

IDR2.

Bit 1: IBF Description

0 This bit is cleared when the slave processor reads IDR2 (Initial value)

1 This bit is set when the host processor writes to IDR2

Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to

0 when the host processor reads ODR2.

Bit 0: OBF Description

0 This bit is cleared when the host processor reads ODR2 (Initial value)

1 This bit is set when the slave processor writes to ODR2

Table 14.4 shows the conditions for setting and clearing the STR2 flags.

Table 14.4 Set/Clear Timing for STR2 Flags

Flag Setting Condition Clearing Condition

C/DRising edge of host’s write signal (IOW)

when HA0 is high Rising edge of host’s write signal (IOW)

when HA0 is low

IBF Rising edge of host’s write signal (IOW)

when writing to IDR2 Falling edge of slave’s internal read signal

(RD) when reading IDR2

OBF Falling edge of slave’s internal write

signal (WR) when writing to ODR2 Rising edge of host’s read signal (IOR)

when reading ODR2

327

14.2.9 Serial/Timer Control Register (STCR)

Bit 76543210

IICS IICD IICX IICE STAC MPE ICKS1 ICKS0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

STCR is an 8-bit readable/writable register that controls the I2C bus interface and host interface,

controls the SCI operating mode, and selects the TCNT clock source in the 8-bit timers. STCR is

initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 4—I2C Control (IICS, IICD, IICX, IICE): These bits are used to control the I2C bus

interface. For details, see section 13, I2C Bus Interface.

Bit 3—Slave Input Switch (STAC): Controls switching of host interface input pins. Settings of

this bit are valid only when the host interface is enabled (slave mode).

Bit 3: STAC Description

0 In port 8, P85 switches over to CS2, and P84 to IOW (Initial value)

1 In port 9, P91 switches over to EIOW, and P90 to ECS2

Bit 2—Multiprocessor Enable (MPE): Controls the operating mode of SCI0 and SCI1. For

details, see section 12, Serial Communication Interface.

Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): Together with bits CKS2

to CKS0 in TCR, these bits select timer counter clock inputs. For details, see section 9, 8-Bit

Timers.

328

14.3 Operation

14.3.1 Host Interface Operation

The host interface is activated by setting the HIE bit (bit 1) to 1 in SYSCR, establishing slave

mode. Activation of the host interface (entry to slave mode) appropriates the related I/O lines in

port 3 or B (data), port 8 or 9 (control) and port 4 (host interrupt requests) for interface use.

For host interface read/write timing diagrams, see section 23.3.8, Host Interface Timing.

14.3.2 Control States

Table 14.5 indicates the slave operations carried out in response to host interface signals from the

host processor.

Table 14.5 Host Interface Operation

CS2CS1IOR IOW HA0Slave Operation

10000Prohibited

1 Prohibited

1 0 Data read from output data register 1 (ODR1)

1 Status read from status register 1 (STR1)

1 0 0 Data write to input data register 1 (IDR1)

1 Command write to input data register 1 (IDR1)

1 0 Idle state

1 Idle state

01000Prohibited

1 Prohibited

1 0 Data read from output data register 2 (ODR2)

1 Status read from status register 2 (STR2)

1 0 0 Data write to input data register 2 (IDR2)

1 Command write to input data register 2 (IDR2)

1 0 Idle state

1 Idle state

329

14.3.3 A20 Gate

The A20 gate signal can mask address A20 to emulate an addressing mode used by personal

computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be

output under software control, or a fast A20 gate signal can be output under hardware control. Fast

A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0).

Note: * Intel microprocessor.

Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1

command followed by data. When the slave processor receives data, it normally uses an interrupt

routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command,

software copies bit 1 of the data and outputs it at the gate A20 pin (P81/GA20).

Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast

A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. The initial output from

this pin will be a logic 1, which is the initial DR value. Afterward, the host processor can

manipulate the output from this pin by sending commands and data. This function is available

only when register IDR1 is accessed using CS1. Slave logic decodes the commands input from the

host processor. When an H'D1 host command is detected, bit 1 of the data following the host

command is output from the GA20 output pin. This operation does not depend on software or

interrupts, and is faster than the regular processing using interrupts. Table 14.6 lists the conditions

that set and clear GA20 (P81). Figure 14.2 describes the GA20 output in flowchart form. Table 14.7

indicates the GA20 output signal values.

Table 14.6 GA20 (P81) Set/Clear Timing

Pin Name Setting Condition Clearing Condition

GA20 (P81) Rising edge of the host’s write signal

(IOW) when bit 1 of the written data

is 1 and the data follows an H'D1

host command

Rising edge of the host’s write signal

(IOW) when bit 1 of the written data is 0

and the data follows an H'D1 host

command

330

Start

Host write

H'D1 command

received?

Wait for next byte

Host write

Yes

Data byte?

Write bit 1 of data byte

to DR bit of P81/GA20

Yes

Figure 14.2 GA20 Output

331

Table 14.7 Fast A20 Gate Output Signal

HA0Data/Command Internal CPU

Interrupt Flag GA20

(PB1) Remarks

1 H'D1 command 0 Q Turn-on sequence

0“1” data*101

1 H'FF command 0 Q (1)

1 H'D1 command 0 Q Turn-off sequence

0“0” data*200

1 H'FF command 0 Q (0)

1 H'D1 command 0 Q Short turn-on sequence

0“1” data*101

1/0 Command other than H'FF

and H'D1 1 Q (1)

1 H'D1 command 0 Q Short turn-off sequence

0“0” data*200

1/0 Command other than H'FF

and H'D1 1 Q (0)

1 H'D1 command 0 Q Cancelled sequence

1 Command other than H'D1 1 Q

1 H'D1 command 0 Q Retriggered sequence

1 H'D1 command 0 Q

1 H'D1 command 0 Q Consecutively executed

0 Any data 0 1/0 sequences

1 H'D1 command 0 Q (1/0)

Notes: *1 Arbitrary data with bit 1 set to 1.

*2 Arbitrary data with bit 1 cleared to 0.

332

14.4 Interrupts

14.4.1 IBF1, IBF2

The host interface can request two interrupts to the slave CPU: IBF1 and IBF2. They are input

buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is

enabled when the corresponding enable bit is set (table 14.8).

Table 14.8 Input Buffer Full Interrupts

Interrupt Description

IBF1 Requested when IBFIE1 is set to 1 and IDR1 is full

IBF2 Requested when IBFIE2 is set to 1 and IDR2 is full

14.4.2 HIRQ11, HIRQ1, and HIRQ12

In slave mode (when HIE = 1 in SYSCR), three bits in the port 4 data register (P4DR) can be used

as host interrupt request latches.

These three P4DR bits are cleared to 0 by the host processor’s read signal (IOR). If CS1 and HA0

are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared to 0. If CS2

and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to 0. To

generate a host interrupt request, normally on-chip software writes 1 to the corresponding bit. In

processing the interrupt, the host’s interrupt-handling routine reads the output data register (ODR1

or ODR2), and this clears the host interrupt latch to 0.

Table 14.9 indicates how these bits are set and cleared. Figure 14.3 shows the processing in

flowchart form.

Table 14.9 Host Interrupt Set/Clear Conditions

Host Interrupt

Signal Setting Condition Clearing Condition

HIRQ11 (P43) Slave CPU reads 0 from P4DR bit 3,

then writes 1 Slave CPU writes 0 in P4DR bit 3, or

host reads output data register 2

HIRQ1 (P44) Slave CPU reads 0 from P4DR bit 4,

then writes 1 Slave CPU writes 0 in P4DR bit 4, or

host reads output data register 1

HIRQ12 (P45) Slave CPU reads 0 from P4DR bit 5,

then writes 1 Slave CPU writes 0 in P4DR bit 5, or

host reads output data register 1

333

Slave CPU Master CPU

Write to ODR

Write 1 to P4DR

P4DR = 0?

Yes

All bytes

transferred?

HIRQ output high

HIRQ output low

Interrupt initiation

ODR read

Hardware operations

Software operations

Figure 14.3 HIRQ Output Flowchart

14.5 Application Note

The host interface provides buffering of asynchronous data from the host and slave processors, but

an interface protocol must be followed to implement necessary functions and avoid data

contention. For example, if the host and slave processors try to access the same input or output

data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple

and effective protocol.

334

335

Section 15 A/D Converter

15.1 Overview

The H8/3437 Series includes a 10-bit successive-approximations A/D converter with a selection of

up to eight analog input channels.

15.1.1 Features

A/D converter features are listed below.

• 10-bit resolution

• Eight input channels

• Selectable analog conversion voltage range

The analog voltage conversion range can be programmed by input of an analog reference

voltage at the AVref pin.

• High-speed conversion

Conversion time: minimum 8.4 µs per channel (with 16-MHz system clock)

• Two conversion modes

Single mode: A/D conversion of one channel

Scan mode: continuous conversion on one to four channels

• Four 16-bit data registers

A/D conversion results are transferred for storage into data registers corresponding to the

channels.

• Sample-and-hold function

• A/D conversion can be externally triggered

• A/D interrupt requested at end of conversion

At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.

336

15.1.2 Block Diagram

Figure 15.1 shows a block diagram of the A/D converter.

Module data bus

Bus interface

Internal

data bus

ADDRA

ADDRB

ADDRC

ADDRD

ADCSR

ADCR

Successive-

approximations register

10-bit D/A

AVCC

AVref

AVSS

Analog

multi-

plexer

Sample-and-

hold circuit

Comparator

–

Control circuit

ADTRG

øP/8

øP/16

ADI

interrupt

signal

Legend:

ADCR:

ADCSR:

ADDRA:

ADDRB:

ADDRC:

ADDRD:

A/D control register

A/D control/status register

A/D data register A

A/D data register B

A/D data register C

A/D data register D

Figure 15.1 A/D Converter Block Diagram

337

15.1.3 Input Pins

Table 15.1 lists the A/D converter’s input pins. The eight analog input pins are divided into two

groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply

for the analog circuits in the A/D converter. AVref is the A/D conversion reference voltage.

Table 15.1 A/D Converter Pins

Pin Name Abbreviation I/O Function

Analog power supply pin AVCC Input Analog power supply

Analog ground pin AVSS Input Analog ground and reference voltage

Reference voltage pin AVref Input Analog reference voltage

Analog input pin 0 AN0Input Group 0 analog inputs

Analog input pin 1 AN1Input

Analog input pin 2 AN2Input

Analog input pin 3 AN3Input

Analog input pin 4 AN4Input Group 1 analog inputs

Analog input pin 5 AN5Input

Analog input pin 6 AN6Input

Analog input pin 7 AN7Input

A/D external trigger input pin ADTRG Input External trigger input for starting A/D

conversion

338

15.1.4 Register Configuration

Table 15.2 summarizes the A/D converter’s registers.

Table 15.2 A/D Converter Registers

Name Abbreviation R/W Initial Value Address

A/D data register A (high) ADDRAH R H'00 H'FFE0

A/D data register A (low) ADDRAL R H'00 H'FFE1

A/D data register B (high) ADDRBH R H'00 H'FFE2

A/D data register B (low) ADDRBL R H'00 H'FFE3

A/D data register C (high) ADDRCH R H'00 H'FFE4

A/D data register C (low) ADDRCL R H'00 H'FFE5

A/D data register D (high) ADDRDH R H'00 H'FFE6

A/D data register D (low) ADDRDL R H'00 H'FFE7

A/D control/status register ADCSR R/(W)*H'00 H'FFE8

A/D control register ADCR R/W H'7F H'FFE9

Note: *Only 0 can be written in bit 7, to clear the flag.

339

15.2 Register Descriptions

15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

Bit 1514131211109876543210

ADDRn AD9 AD8 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — —————

Initial value 0 0 0 0000000000000

Read/Write R R R RRRRRRRRRRRRR

Bits 15 to 6—A/D Conversion Data (AD9 to AD0): 10-bit data giving an A/D conversion result.

Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 0.

The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the

results of A/D conversion.

An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data

byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D

data register are reserved bits that always read 0. Table 15.3 indicates the pairings of analog input

channels and A/D data registers.

The CPU can always read the A/D data registers. The upper byte can be read directly, but the

lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU

Interface.

The A/D data registers are initialized to H'0000 by a reset and in standby mode.

Table 15.3 Analog Input Channels and A/D Data Registers

Analog Input Channel

Group 0 Group 1 A/D Data Register

AN0AN4ADDRA

AN1AN5ADDRB

AN2AN6ADDRC

AN3AN7ADDRD

340

15.2.2 A/D Control/Status Register (ADCSR)

Bit 76543210

ADF ADIE ADST SCAN CKS CH2 CH1 CH0

Initial value 0 0 0 0 0 0 0 0

Read/Write R/(W)*R/W R/W R/W R/W R/W R/W R/W

Note: *Only 0 can be written, to clear the flag.

ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.

ADCSR is initialized to H'00 by a reset and in standby mode.

Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.

Bit 7: ADF Description

0 Clearing condition: (Initial value)

Cleared by reading ADF while ADF = 1, then writing 0 in ADF

1 Setting conditions:

1. Single mode: A/D conversion ends

2. Scan mode: A/D conversion ends in all selected channels

Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the

end of A/D conversion.

Bit 6: ADIE Description

0 A/D end interrupt request (ADI) is disabled (Initial value)

1 A/D end interrupt request (ADI) is enabled

Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during

A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.

Bit 5: ADST Description

0 A/D conversion is stopped (Initial value)

1 1. Single mode: A/D conversion starts; ADST is automatically cleared to 0

when conversion ends

2. Scan mode: A/D conversion starts and continues, cycling among the

selected channels, until ADST is cleared to 0 by software, by a reset, or by

a transition to standby mode

341

Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on

operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching

the conversion mode.

Bit 4: SCAN Description

0 Single mode (Initial value)

1 Scan mode

Bit 3—Clock Select (CKS): Selects the A/D conversion time. When øP = ø/2, the conversion time

doubles. Clear the ADST bit to 0 before switching the conversion time.

Bit 3: CKS Description

0 Conversion time = 266 states (maximum) (when øP = ø) (Initial value)

1 Conversion time = 134 states (maximum) (when øP = ø)

Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog

input channels. Clear the ADST bit to 0 before changing the channel selection.

Group Selection Channel Selection Description

CH2 CH1 CH0 Single Mode Scan Mode

000AN

0 (initial value) AN0

1AN

1AN0, AN1

10 AN

2AN0 to AN2

1AN

3AN0 to AN3

100AN

4AN4

1AN

5AN4, AN5

10 AN

6AN4 to AN6

1AN

7AN4 to AN7

342

15.2.3 A/D Control Register (ADCR)

Bit 76543210

TRGE — — — — — — —

Initial value 0 1 1 1 1 1 1 1

Read/Write R/W — — — — — — —

ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D

conversion. ADCR is initialized to H'7F by a reset and in standby mode.

Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.

Bit 7: TRGE Description

0 A/D conversion cannot be externally triggered (Initial value)

1 Enables start of A/D conversion by the external trigger input (ADTRG).

(A/D conversion can be started either by an external trigger or by software.)

Bits 6 to 0—Reserved: These bits cannot be modified, and are always read as 1.

15.3 CPU Interface

ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.

Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read

through an 8-bit temporary register (TEMP).

An A/D data register is read as follows. When the upper byte is read, the upper-byte value is

transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the

lower byte is read, the TEMP contents are transferred to the CPU.

When reading an A/D data register, always read the upper byte before the lower byte. It is possible

to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.

Figure 15.2 shows the data flow for access to an A/D data register.

343

Upper-byte read

Bus interface Module data bus

CPU

(H'AA)

ADDRnH

(H'AA) ADDRnL

(H'40)

Lower-byte read

Bus interface Module data bus

CPU

(H'40)

ADDRnH

(H'AA) ADDRnL

(H'40)

TEMP

(H'40)

TEMP

(H'40)

(n = A to D)

Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)

344

15.4 Operation

The A/D converter operates by successive approximations with 10-bit resolution. It has two

operating modes: single mode and scan mode.

15.4.1 Single Mode (SCAN = 0)

Single mode should be selected when only one A/D conversion on one channel is required. A/D

conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The

ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when

conversion ends.

When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is

requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.

When the mode or analog input channel must be switched during analog conversion, to prevent

incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making

the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be

set at the same time as the mode or channel is changed.

Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure

15.3 shows a timing diagram for this example.

1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 =

1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).

2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time

the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.

3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.

4. The A/D interrupt handling routine starts.

5. The routine reads ADCSR, then writes 0 in the ADF flag.

6. The routine reads and processes the conversion result (ADDRB).

7. Execution of the A/D interrupt handling routine ends.

After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated.

345

ADIE

ADST

ADF

State of channel 0

(AN )

Set

Set Set

Clear Clear

Idle

A/D conversion (1) A/D conversion (2)

Idle

Read conversion result

A/D conversion result (1) Read conversion result

A/D conversion result (2)

Note: Vertical arrows ( ) indicate instructions executed by software.

A/D conversion

starts

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 1

(AN )

State of channel 2

(AN )

State of channel 3

(AN )

Idle

Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)

346

15.4.2 Scan Mode (SCAN = 1)

Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the

ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first

channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are

selected, after conversion of the first channel ends, conversion of the second channel (AN1 or

AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the

ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data

registers corresponding to the channels.

When the mode or analog input channel selection must be changed during analog conversion, to

prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After

making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the

first channel in the group. The ADST bit can be set at the same time as the mode or channel

selection is changed.

Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are

described next. Figure 15.4 shows a timing diagram for this example.

1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels

AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).

2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into

ADDRA. Next, conversion of the second channel (AN1) starts automatically.

3. Conversion proceeds in the same way through the third channel (AN2).

4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1

and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI

interrupt is requested at this time.

5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is

cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion

starts again from the first channel (AN0).

347

ADST

ADF

State of channel 0

(AN )

Continuous A/D conversion

Set Clear*1

Clear*1

Idle

A/D conversion (1)

Idle

A/D conversion (4)

Idle

A/D conversion (2)

Idle A/D conversion (5) Idle

A/D conversion (3)

Idle

Transfer A/D conversion result (1) A/D conversion result (4)

A/D conversion result (2)

A/D conversion result (3)

A/D conversion time

Notes:

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 1

(AN )

State of channel 2

(AN )

State of channel 3

(AN )

Vertical arrows ( ) indicate instructions executed by software.

Data currently being converted is ignored.

Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2

Selected)

348

15.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D

conversion timing. Table 15.4 indicates the A/D conversion time.

As indicated in figure 15.5, the A/D conversion time includes tD and the input sampling time. The

length of tD varies depending on the timing of the write access to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 15.4.

In scan mode, the values given in table 15.4 apply to the first conversion. In the second and

subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states

when CKS = 1 (when øP = ø).

Address bus

Write signal

Input sampling

timing

ADF

(1)

(2)

tDtSPL

tCONV

Legend:

(1):

(2):

t :

SPL

CONV

ADCSR write cycle

ADCSR address

Synchronization delay

Input sampling time

A/D conversion time

Figure 15.5 A/D Conversion Timing

349

Table 15.4 A/D Conversion Time (Single Mode)

CKS = 0 CKS = 1

Symbol Min Typ Max Min Typ Max

Synchronization delay tD10 —17 6 —9

Input sampling time*tSPL —80 ——40 —

A/D conversion time*tCONV 259 —266 131 —134

Note: Values in the table are numbers of states.

*Values for when øP = ø. When øP = ø/2, values are double those given in the table.

15.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external

trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the

ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan

modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the

timing.

ADTRG

Internal trigger

signal

ADST

A/D conversion

Figure 15.6 External Trigger Input Timing

350

15.5 Interrupts

The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt

request can be enabled or disabled by the ADIE bit in ADCSR.

15.6 Application Notes

When using the A/D converter, note the following points.

Setting Ranges of Analog Power Supply and Other Pins:

1. Analog Input Voltage Range

During A/D conversion, the voltages input to the analog input pins ANn should be in the range

AVSS ≤ ANn ≤ AVref. (n = 0 to 7)

2. AVCC and AVSS Input Voltages

AVSS should be equal to VSS. If the A/D converter is not used, the values should be AVCC = VCC

and AVSS = VSS

3. AVref Input Range

The analog reference voltage input at the AVref pin should be in the range AVref ≤ AVCC. If the

A/D converter is not used, the value should be AVref = VCC.

Notes on Board Design: In board design, digital circuitry and analog circuitry should be as

mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit

signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so

may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D

conversion values.

Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog

reference voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS). The

analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the

board.

Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an

abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) or analog

reference power supply pin (AVref) should be connected between AVCC and AVSS as shown in

figure 15.7.

Also, the bypass capacitors connected to AVCC, AVref and the filter capacitor connected to AN0 to

AN7 must be connected to AVSS.

If a filter capacitor is connected as shown in figure 15.7, the input currents at the analog input pins

(AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed

frequently, as in scan mode, if the current charged and discharged by the capacitance of the

sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance

351

(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required

when deciding the circuit constants.

AVCC

AVref

AN0 to AN7

AVSS

Notes: Figures are reference values.

*2 Rin: Input impedance

*1Rin*2100 Ω

0.1 µF

0.01 µF10 µF

Figure 15.7 Example of Analog Input Protection Circuit

A/D Conversion Precision Definitions: The H8/3437 Series A/D conversion precision definitions

are given below.

• Resolution

The number of A/D converter digital output codes

• Offset error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from the minimum voltage value B'0000000000 (H'000) to

B'0000000001 (H'001) (see figure 15.9).

• Full-scale error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see

figure 15.9).

352

• Quantization error

The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.8).

• Nonlinearity error

The error with respect to the ideal A/D conversion characteristic between the zero voltage and

the full-scale voltage. Does not include the offset error, full-scale error, or quantization error.

• Absolute precision

The deviation between the digital value and the analog input value. Includes the offset error,

full-scale error, quantization error, and nonlinearity error.

H'3FF

H'3FE

H'3FD

H'004

H'003

H'002

H'001

H'000 1

1024 2

1024 1023

1024

1022

1024 FS

Quantization error

Digital output

Ideal A/D conversion

characteristic

Analog

input voltage

Figure 15.8 A/D Conversion Precision Definitions (1)

353

Offset error

Nonlinearity

error

Actual A/D conversion

characteristic

Analog

input voltage

Digital output

Ideal A/D conversion

characteristic

Full-scale error

Figure 15.9 A/D Conversion Precision Definitions (2)

354

Permissible Signal Source Impedance: H8S/2148 Series and H8S/2144 Series analog input is

designed so that conversion precision is guaranteed for an input signal for which the signal source

impedance is 10 kΩ or less. This specification is provided to enable the A/D converter’s sample-

and-hold circuit input capacitance to be charged within the sampling time; if the sensor output

impedance exceeds 10 kΩ, charging may be insufficient and it may not be possible to guarantee

the A/D conversion precision.

However, if a large capacitance is provided externally, the input load will essentially comprise

only the internal input resistance of 10 kΩ, and the signal source impedance is ignored.

But since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog

signal with a large differential coefficient (e.g., 5 mV/µsec or greater).

When converting a high-speed analog signal, a low-impedance buffer should be inserted.

Influences on Absolute Precision: Adding capacitance results in coupling with GND, and

therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to

an electrically stable GND such as AVSS.

Care is also required to insure that filter circuits do not communicate with digital signals on the

mounting board, so acting as antennas.

A/D converter

equivalent circuit

H8/3437 Series

chip

20 pF

Cin =

15 pF

10 kΩ

Low-pass

filter C,

up to 0.1 µF

Sensor output

impedance,

up to 10 kΩ

Sensor input

Note: Figures are reference values.

Figure 15.10 Example of Analog Input Circuit

355

Section 16 D/A Converter

16.1 Overview

The H8/3437 Series has an on-chip D/A converter module with two channels.

16.1.1 Features

Features of the D/A converter module are listed below.

• Eight-bit resolution

• Two-channel output

• Maximum conversion time: 10 µs (with 20-pF load capacitance)

• Output voltage: 0 V to AVref

356

16.1.2 Block Diagram

Figure 16.1 shows a block diagram of the D/A converter.

Bus interface

Module data bus Internal data bus

8-bit D/A

DADR0

DADR1

DACR

Control

circuit

AVref

AVCC

DA0

DA1

AVSS

DACR:

DADR0:

DADR1:

D/A control register

D/A data register 0

D/A data register 1

Figure 16.1 D/A Converter Block Diagram

357

16.1.3 Input and Output Pins

Table 16.1 lists the input and output pins used by the D/A converter module.

Table 16.1 Input and Output Pins of D/A Converter Module

Name Abbreviation I/O Function

Reference voltage pin AVref Input Reference voltage for analog circuits

Analog supply voltage AVCC Input Power supply for analog circuits

Analog ground AVSS Input Ground and reference voltage for analog

circuits

Analog output 0 DA0Output Analog output channel 0

Analog output 1 DA1Output Analog output channel 1

16.1.4 Register Configuration

Table 16.2 lists the three registers of the D/A converter module.

Table 16.2 D/A Converter Registers

Name Abbreviation R/W Initial Value Address

D/A data register 0 DADR0 R/W H'00 H'FFF8

D/A data register 1 DADR1 R/W H'00 H'FFF9

D/A control register DACR R/W H'1F H'FFFA

358

16.2 Register Descriptions

16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1)

Bit 76543210

Initial value 0 0 0 0 0 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable and writable registers that

store data to be converted. When analog output is enabled, the value in the D/A data register is

converted and output continuously at the analog output pin.

The D/A data registers are initialized to H'00 by a reset and in the standby modes.

16.2.2 D/A Control Register (DACR)

Bit 76543210

DAOE1 DAOE0 DAE — — — — —

Initial value 0 0 0 1 1 1 1 1

Read/Write R/W R/W R/W — — — — —

DACR is an 8-bit readable and writable register that controls the operation of the D/A converter

module.

DACR is initialized to H'1F by a reset and in the standby modes.

Bit 7—D/A Output Enable 1 (DAOE1): Controls analog output from the D/A converter.

Bit 7: DAOE1 Description

0 Analog output at DA1 is disabled.

1 D/A conversion is enabled on channel 1. Analog output is enabled at DA1.

359

Bit 6—D/A Output Enable 0 (DAOE0): Controls analog output from the D/A converter.

Bit 6: DAOE0 Description

0 Analog output at DA0 is disabled.

1 D/A conversion is enabled on channel 0. Analog output is enabled at DA0.

Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and

DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0.

Channels 0 and 1 are controlled together when DAE = 1.

The decision to output the converted results is always controlled independently by DAOE0 and

DAOE1.

Bit 7: DAOE1 Bit 6: DAOE0 Bit 5: DAE D/A Conversion

0 0 — Disabled on channels 0 and 1.

1 0 Enabled on channel 0.

Disabled on channel 1.

1 Enabled on channels 0 and 1.

1 0 0 Disabled on channel 0.

Enabled on channel 1.

1 Enabled on channels 0 and 1.

1 — Enabled on channels 0 and 1.

When the DAE bit is set to 1, analog power supply current drain is the same as during A/D and

D/A conversion, even if the DAOE0 and DAOE1 bits in DACR and the ADST bit in ADSCR are

cleared to 0.

Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.

360

16.3 Operation

The D/A converter module has two built-in D/A converter circuits that can operate independently.

D/A conversion is performed continuously whenever enabled by the D/A control register. When a

new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The

converted result is output by setting the DAOE0 or DAOE1 bit to 1.

An example of conversion on channel 0 is given next. Figure 16.2 shows the timing.

1. Software writes the data to be converted in DADR0.

2. D/A conversion begins when the DAOE0 bit in DACR is set to 1. After a conversion delay,

analog output appears at the DA0 pin. The output value is AVref × (DADR0 value)/256.

This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0.

3. If a new value is written in DADR0, conversion begins immediately. Output of the converted

result begins after the conversion delay time.

4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.

DADR0

write cycle DACR

write cycle DADR0

write cycle DACR

write cycle

Address

DADR0

DAOE0

DA0

Conversion data (1) Conversion data (2)

High-impedance state

Conversion result (1) Conversion result (2)

tDCONVtDCONV

tDCONV: D/A conversion time

Figure 16.2 D/A Conversion (Example)

361

Section 17 RAM

17.1 Overview

The H8/3437 and H8/3436 have 2 kbytes of on-chip static RAM. The H8/3434 has 1 kbyte. The

RAM is connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip

RAM are performed in two states, enabling rapid data transfer and instruction execution.

The on-chip RAM is assigned to addresses H'F780 to H'FF7F in the address space of the H8/3437

and H8/3436, and addresses H'FB80 to H'FF7F in the address space of the H8/3434. The RAME

bit in the system control register (SYSCR) can enable or disable the on-chip RAM.

17.1.1 Block Diagram

Figure 17.1 is a block diagram of the on-chip RAM.

H'FF7E

Internal data bus (upper 8 bits)

H'FF7F

H'F782

H'F780

H'F783

H'F781

Even address Odd address

On-chip RAM

Internal data bus (lower 8 bits)

Figure 17.1 Block Diagram of On-Chip RAM (H8/3437)

362

17.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR)

Bit 76543210

SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME

Initial value 0 0 0 0 1 0 0 1

Read/Write R/W R/W R/W R/W R R/W R/W R/W

The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. See section 3.2, System

Control Register (SYSCR), for the other SYSCR bits.

Bit 0—RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is

initialized to 1 on the rising edge of the RES signal. The RAME bit is not initialized in software

standby mode.

Bit 0: RAME Description

0 On-chip RAM is disabled.

1 On-chip RAM is enabled. (Initial value)

17.2 Operation

17.2.1 Expanded Modes (Modes 1 and 2)

If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3437 and H8/3436

and addresses H'FB80 to H'FF7F in the H8/3434 are directed to the on-chip RAM. If the RAME

bit is cleared to 0, accesses to these addresses are directed to the external data bus.

17.2.2 Single-Chip Mode (Mode 3)

If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3437 and H8/3436

and addresses H'FB80 to H'FF7F in the H8/3434 are directed to the on-chip RAM.

If the RAME bit is cleared to 0, the on-chip RAM data cannot be accessed. Attempted write access

has no effect. Attempted read access always results in H'FF data being read.

Notes: 1. When VCC ≥ VRAM, on-chip RAM values can be retained by using the specified method.

See section 21.4.1 and Appendix E for details.

2. On-chip RAM values are not guaranteed if power is turned off, then on again, in any

state.

3. When specific bits in RAM are used as control bits, initial values must be set after

powering on.

363

Section 18 ROM (Mask ROM Version/ZTAT Version)

18.1 Overview

The size of the on-chip ROM is 60 kbytes in the H8/3437, 48 kbytes in the H8/3436, and 32

kbytes in the H8/3434. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte

data and word data are accessed in two states, enabling rapid data transfer.

The on-chip ROM is enabled or disabled depending on the inputs at the mode pins (MD1 and

MD0). See table 18.1.

Table 18.1 On-Chip ROM Usage in Each MCU Mode

Mode Pins

Mode MD1MD0On-Chip ROM

Mode 1 (expanded mode) 0 1 Disabled (external addresses)

Mode 2 (expanded mode) 1 0 Enabled

Mode 3 (single-chip mode) 1 1 Enabled

The PROM versions (H8/3437 ZTAT and H8/3434 ZTAT) and flash-memory version (H8/3437

F-ZTAT and H8/3434 F-ZTAT ) can be set to writer mode and programmed with a general-

purpose PROM programmer. In the H8/3437, the accessible ROM addresses are H'0000 to

H'EF7F (61,312 bytes) in mode 2, and H'0000 to H'F77F (63,360 bytes) in mode 3. For details, see

section 3, MCU Operating Modes and Address Space.

364

18.1.1 Block Diagram

Figure 18.1 is a block diagram of the on-chip ROM.

H'F77E

Internal data bus (upper 8 bits)

H'F77F

H'0002

H'0000

H'0003

H'0001

Even address Odd address

On-chip ROM

Internal data bus (lower 8 bits)

Figure 18.1 Block Diagram of On-Chip ROM (H8/3437 Single-Chip Mode)

18.2 Writer Mode (H8/3437, H8/3434)

18.2.1 Writer Mode Setup

In writer mode the PROM versions of the H8/3437 and H8/3434 suspend the usual microcomputer

functions to allow the on-chip PROM to be programmed. The programming method is the same as

for the HN27C101.

To select writer mode, apply the signal inputs listed in table 18.2.

Table 18.2 Selection of Writer Mode

Pin Input

Mode pin MD1Low

Mode pin MD0Low

STBY pin Low

Pins P63 and P64High

365

18.2.2 Socket Adapter Pin Assignments and Memory Map

The H8/3437 and H8/3434 can be programmed with a general-purpose PROM programmer by

using a socket adapter to change the pin-out to 32 pins. See table 18.3. The same socket adapter

can be used for both the H8/3437 and H8/3434. Figure 18.2 shows the socket adapter pin

assignments.

Table 18.3 Socket Adapter

Package Socket Adapter

100-pin QFP HS3437ESHS1H

100-pin TQFP HS3437ESNS1H

The PROM size is 60 kbytes for the H8/3437 and 32 kbytes for the H8/3434. Figures 18.3 and

18.4 show memory maps of the H8/3437 and H8/3434 in writer mode. H'FF data should be

specified for unused address areas in the on-chip PROM.

When programming with a PROM programmer, limit the program address range to H'0000 to

H'F77F for the H8/3437 and H'0000 to H'7FFF for the H8/3434. Specify H'FF data for addresses

H'F780 and above (H8/3437) or H'8000 and above (H8/3434). If these addresses are programmed

by mistake, it may become impossible to program or verify the PROM data. The same problem

may occur if an attempt is made to program the chip in page programming mode. Note that the

PROM versions are one-time programmable (OTP) microcomputers, packaged in plastic

packages, and cannot be reprogrammed.

366

FP-100B,

TFP-100B

RES

NMI

AVref

VCCB

VCC

STBY

PGM

HN27C101

(32 pins)

H8/3437, H8/3434 EPROM Socket

Note: All pins not listed in this figure should be left open.

Legend:

VPP:

EO7 to EO0:

EA16 to EA0:

OE:

CE:

PGM:

Programming power supply (12.5 V)

Data input/output

Address input

Output enable

Chip enable

Program enable

Figure 18.2 Socket Adapter Pin Assignments

367

H'F77F H'F77F

Undetermined

value output*

If this address area is read in writer mode, the output data is not guaranteed.

H'1FFFF

Address in writer modeAddress in MCU mode

H'0000 H'0000

On-chip

PROM

Note: *

Figure 18.3 H8/3437 Memory Map in Writer Mode

H'7FFF H'7FFF

Undetermined

value output*

If this address area is read in writer mode, the output data is not guaranteed.

H'1FFFF

Address in writer modeAddress in MCU mode

H'0000 H'0000

On-chip

PROM

Note: *

Figure 18.4 H8/3434 Memory Map in Writer Mode

368

18.3 PROM Programming

The write, verify, and other sub-modes of the writer mode are selected as shown in table 18.4.

Table 18.4 Selection of Sub-Modes in Writer Mode

Sub-Mode CE OE PGM VPP VCC EO7 to EO0EA16 to EA0

Write Low High Low VPP VCC Data input Address input

Verify Low Low High VPP VCC Data output Address input

Programming

inhibited Low

Low

High

Low

High

Low

High

Low

High

Low

High

VPP VCC High impedance Address input

The H8/3437 and H8/3434 PROM have the same standard read/write specifications as the

HN27C101 EPROM. Page programming is not supported, however, so do not select page

programming mode. PROM programmers that provide only page programming cannot be used.

When selecting a PROM programmer, check that it supports a byte-at-a-time high-speed

programming mode. Be sure to set the address range to H'0000 to H'F77F for the H8/3437, and to

H'0000 to H'7FFF for the H8/3434.

18.3.1 Programming and Verification

An efficient, high-speed programming procedure can be used to program and verify PROM data.

This procedure programs data quickly without subjecting the chip to voltage stress and without

sacrificing data reliability. It leaves the data H'FF in unused addresses.

Figure 18.5 shows the basic high-speed programming flowchart.

Tables 18.5 and 18.6 list the electrical characteristics of the chip in writer mode. Figure 18.6

shows a program/verify timing chart.

369

Start

Set program/verify mode

VCC = 6.0 V ±0.25 V,

VPP = 12.5 V ±0.3 V

Address = 0

→

Verify OK?

Program tOPW = 0.2n ms

Last address?

Set read mode

VCC = 5.0 V ±0.25 V,

VPP = VCC

Read all

addresses

End

Error

n < 25? Address + 1 address→

No Yes No

Yes

No go

Program tPW = 0.2 ms ±5%

n = 0

n + 1 n

Yes

Figure 18.5 High-Speed Programming Flowchart

370

Table 18.5 DC Characteristics

(when VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25˚C ±5˚C)

Item Symbol Min Typ Max Unit Test Conditions

Input high

voltage EO7–EO0,

EA16–EA0,

OE, CE, PGM

VIH 2.4 — VCC + 0.3 V

Input low

voltage EO7 – EO0,

EA16 – EA0,

OE, CE, PGM

VIL –0.3 — 0.8 V

Output high

voltage EO7–EO0VOH 2.4 — — V IOH = –200 µA

Output low

voltage EO7–EO0VOL — — 0.45 V IOL = 1.6 mA

Input leakage

current EO7 – EO0,

EA16 – EA0,

OE, CE, PGM

|ILI| ——2 µAV

in = 5.25 V/0.5 V

VCC current ICC ——40 mA

VPP current IPP ——40 mA

371

Table 18.6 AC Characteristics

(when VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25˚C ±5˚C)

Item Symbol Min Typ Max Unit Test Conditions

Address setup time tAS 2——µs See figure 18.6*

OE setup time tOES 2——µs

Data setup time tDS 2——µs

Address hold time tAH 0——µs

Data hold time tDH 2——µs

Data output disable time tDF — — 130 ns

VPP setup time tVPS 2——µs

Program pulse width tPW 0.19 0.20 0.21 ms

OE pulse width for

overwrite-programming tOPW 0.19 — 5.25 ms

VCC setup time tVCS 2——µs

CE setup time tCES 2——µs

Data output delay time tOE 0 — 150 ns

Note: *Input pulse level: 0.8 V to 2.2 V

Input rise/fall time ≤ 20 ns

Timing reference levels: input—1.0 V, 2.0 V; output—0.8 V, 2.0 V

372

Address

Data

VPP

VCC

PGM

VPP

VCC

Write Verify

Input data Output data

tAS

tDS

tVPS

tVCS

tCES

tPW

tOPW

tDH

tOES tOE

tDF

tAH

+ 1

Figure 18.6 PROM Program/Verify Timing

373

18.3.2 Notes on Programming

(1) A PROM programmer that does not allow start address setting cannot be used. If such a

PROM programmer is used, it will not be possible to perform verification at addresses H'10002,

H'10003, H'10004, and so on. Therefore a PROM programmer that allows address setting must be

used.

(2) Program with the specified voltages and timing. The programming voltage (VPP) is

12.5 V.

Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be

particularly careful about the PROM programmer’s overshoot characteristics.

If the PROM programmer is set to HN27C101 specifications, VPP will be 12.5 V.

(3) Before writing data, check that the socket adapter and chip are correctly mounted in the

PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM

programmer, socket adapter, and chip are not correctly aligned.

(4) Don’t touch the socket adapter or chip while writing. Touching either of these can cause

contact faults and write errors.

(5) Page programming is not supported. Do not select page programming mode.

(6) The H8/3437 PROM size is 60 kbytes. The H8/3434 PROM size is 32 kbytes. Set the

address range to H'0000 to H'F77F for the H8/3437, and to H'0000 to H'7FFF for the H8/3434.

When programming, specify H'FF data for unused address areas (H'F780 to H'1FFFF in the

H8/3437, H'8000 to H'1FFFF in the H8/3434).

374

18.3.3 Reliability of Programmed Data

An effective way to assure the data holding characteristics of the programmed chips is to bake

them at 150˚C, then screen them for data errors. This procedure quickly eliminates chips with

PROM memory cells prone to early failure.

Figure 18.7 shows the recommended screening procedure.

Write and verify program

Read and check program

Mount

Bake with power off

125° to 150°C, 24 to 48Hr

Figure 18.7 Recommended Screening Procedure

If a series of write errors occurs while the same PROM programmer is in use, stop programming

and check the PROM programmer and socket adapter for defects.

Please inform Hitachi of any abnormal conditions noted during programming or in screening of

program data after high-temperature baking.

375

Section 19 ROM

(32-kbyte Dual-Power-Supply Flash Memory Version)

19.1 Flash Memory Overview

19.1.1 Flash Memory Operating Principle

Table 19.1 illustrates the principle of operation of the H8/3434F’s on-chip flash memory.

Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws

hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a

programmed memory cell is therefore higher than that of an erased cell. Cells are erased by

grounding the gate and applying a high voltage to the source, causing the electrons stored in the

floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like

an EPROM cell, by driving the gate to the high level and detecting the drain current, which

depends on the threshold voltage. Erasing must be done carefully, because if a memory cell is

overerased, its threshold voltage may become negative, causing the cell to operate incorrectly.

Section 19.4.6 shows an optimal erase control flowchart and sample program.

Table 19.1 Principle of Memory Cell Operation

Program Erase Read

Memory

cell Vd

Vg = VPP Open

Vs = VPP Vd

Memory

array Vd 0 V

VPP

0 V

Open Open

0 V

VPP

0 V

Vd 0 V

VCC

0 V

376

19.1.2 Mode Programming and Flash Memory Address Space

As its on-chip ROM, the H8/3434F has 32 kbytes of flash memory. The flash memory is

connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two

states.

The H8/3434F’s flash memory is assigned to addresses H'0000 to H'7FFF. The mode pins enable

either on-chip flash memory or external memory to be selected for this area. Table 19.2

summarizes the mode pin settings and usage of the memory area.

Table 19.2 Mode Pin Settings and Flash Memory Area

Mode Pin Setting

Mode MD1MD0Memory Area Usage

Mode 0 0 0 Illegal setting

Mode 1 0 1 External memory area

Mode 2 1 0 On-chip flash memory area

Mode 3 1 1 On-chip flash memory area

19.1.3 Features

Features of the flash memory are listed below.

• Five flash memory operating modes

The flash memory has five operating modes: program mode, program-verify mode, erase

mode, erase-verify mode, and prewrite-verify mode.

• Block erase designation

Blocks to be erased in the flash memory address space can be selected by bit settings. The

address space includes a large-block area (four blocks with sizes from 4 kbytes to 8 kbytes)

and a small-block area (eight blocks with sizes from 128 bytes to 1 kbyte).

• Program and erase time

Programming one byte of flash memory typically takes 50 µs. Erasing all blocks (32 kbytes)

typically takes 1 s.

• Erase-program cycles

Flash memory contents can be erased and reprogrammed up to 100 times.

• On-board programming modes

These modes can be used to program, erase, and verify flash memory contents. There are two

modes: boot mode and user programming mode.

377

• Automatic bit-rate alignment

In boot-mode data transfer, the H8/3434F aligns its bit rate automatically to the host bit rate

(maximum 9600 bps).

• Flash memory emulation by RAM

Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates

in real time.

• Writer mode

As an alternative to on-board programming, the flash memory can be programmed and erased

in writer mode, using a general-purpose PROM programmer. Program, erase, verify, and other

specifications are the same as for HN28F101 standard flash memory.

19.1.4 Block Diagram

Figure 19.1 shows a block diagram of the flash memory.

FLMCR

EBR1

EBR2

H'0000

H'0002

H'0004

H'7FFC

H'7FFE

H'0001

H'0003

H'0005

H'7FFD

H'7FFF

MD1

MD0

Internal data bus (upper)

Internal data bus (lower)

Bus interface and control section Operating

mode

On-chip flash memory

(32 kbytes)

Upper byte

(even address) Lower byte

(odd address)

Legend:

FLMCR:

EBR1:

EBR2:

Flash memory control register

Erase block register 1

Erase block register 2

Figure 19.1 Flash Memory Block Diagram

378

19.1.5 Input/Output Pins

Flash memory is controlled by the pins listed in table 19.3.

Table 19.3 Flash Memory Pins

Pin Name Abbreviation Input/Output Function

Programming power FVPP Power supply Apply 12.0 V

Mode 1 MD1Input H8/3434F operating mode setting

Mode 0 MD0Input H8/3434F operating mode setting

Transmit data TxD1Output SCI1 transmit data output

Receive data RxD1Input SCI1 receive data input

The transmit data and receive data pins are used in boot mode.

19.1.6 Register Configuration

The flash memory is controlled by the registers listed in table 19.4.

Table 19.4 Flash Memory Registers

Name Abbreviation R/W Initial Value Address

Flash memory control register FLMCR R/W*2H'00*2H'FF80

Erase block register 1 EBR1 R/W*2H'F0*2H'FF82

Erase block register 2 EBR2 R/W*2H'00*2H'FF83

Wait-state control register*1WSCR R/W H'08 H'FFC2

Notes: *1 The wait-state control register controls the insertion of wait states by the wait-state

controller, frequency division of clock signals for the on-chip supporting modules by the

clock pulse generator, and emulation of flash-memory updates by RAM in on-board

programming mode.

*2 In modes 2 and 3 (on-chip flash memory enabled), the initial value is H'00 for FLMCR

and EBR2, and H'F0 for EBR1. In mode 1 (on-chip flash memory disabled), these

registers cannot be modified and always read H'FF.

Registers FLMCR, EBR1, and EBR2 are only valid when writing to or erasing flash memory, and

can only be accessed while 12 V is being applied to the FVPP pin.

When 12 V is not applied to the FVPP pin, in mode 2 addresses H'FF80 to H'FF83 are external

address space, and in mode 3 these addresses cannot be modified and always read H'FF.

379

19.2 Flash Memory Register Descriptions

19.2.1 Flash Memory Control Register (FLMCR)

FLMCR is an 8-bit register that controls the flash memory operating modes. Transitions to

program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits

in this register. FLMCR is initialized to H'00 by a reset, in the standby modes, and when 12 V is

not applied to FVPP. When 12 V is applied to the FVPP pin, a reset or entry to a standby mode

initializes FLMCR to H'80.

Bit 76543210

VPP ———EVPVE P

Initial value*00000000

Read/Write R — — — R/W*R/W*R/W*R/W*

Note: *The initial value is H'00 in modes 2 and 3 (on-chip flash memory enabled). In mode 1 (on-

chip flash memory disabled), this register cannot be modified and always reads H'FF. For

information on accessing this register, refer to in section 19.7, Flash Memory Programming

and Erasing Precautions (11).

Bit 7—Programming Power (VPP): This status flag indicates that 12 V is applied to the FVPP pin.

Refer to section 19.7, Flash Memory Programming and Erasing Precautions (5), for details on use.

Bit 7: VPP Description

0 Cleared when 12 V is not applied to FVPP (Initial value)

1 Set when 12 V is applied to FVPP

Bits 6 to 4—Reserved: Read-only bits, always read as 0.

Bit 3—Erase-Verify Mode (EV):*1 Selects transition to or exit from erase-verify mode.

Bit 3: EV Description

0 Exit from erase-verify mode (Initial value)

1 Transition to erase-verify mode

Bit 2—Program-Verify Mode (PV):*1 Selects transition to or exit from program-verify mode.

Bit 2: PV Description

0 Exit from program-verify mode (Initial value)

1 Transition to program-verify mode

380

Bit 1—Erase Mode (E):*1, *2 Selects transition to or exit from erase mode.

Bit 1: E Description

0 Exit from erase mode (Initial value)

1 Transition to erase mode

Bit 0—Program Mode (P):*1, *2 Selects transition to or exit from program mode.

Bit 0: P Description

0 Exit from program mode (Initial value)

1 Transition to program mode

Notes: *1 Do not set two or more of these bits simultaneously. Do not release or shut off the VCC

or VPP power supply when these bits are set.

*2 Set the P or E bit according to the instructions given in section 19.4, Programming and

Erasing Flash Memory.

Set the watchdog timer beforehand to make sure that these bits do not remain set for

longer than the specified times.

For notes on use, see section 19.7, Flash Memory Programming and Erasing

Precautions.

19.2.2 Erase Block Register 1 (EBR1)

EBR1 is an 8-bit register that designates large flash-memory blocks for programming and erasure.

EBR1 is initialized to H'F0 by a reset, in the standby modes, and when 12 V is not applied to FVPP

pin. When a bit in EBR1 is set to 1, the corresponding block is selected and can be programmed

and erased. Figure 19.2 and table 19.6 show details of a block map.

Bit 76543210

— — — — LB3 LB2 LB1 LB0

Initial value*11110000

Read/Write — — — — R/W*R/W*R/W*R/W*

Note: *The initial value is H'F0 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip ROM

disabled), this register cannot be modified and always reads H'FF. For information on

accessing this register, refer to in section 19.7, Flash Memory Programming and Erasing

Precautions (11).

381

Bits 7 to 4—Reserved: These bits cannot be modified, and are always read as 1.

Bits 3 to 0—Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be

programmed and erased.

Bits 3 to 0:

LB3 to LB0 Description

0 Block (LB3 to LB0) is not selected (Initial value)

1 Block (LB3 to LB0) is selected

19.2.3 Erase Block Register 2 (EBR2)

EBR2 is an 8-bit register that designates small flash-memory blocks for programming and erasure.

EBR2 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP

pin. When a bit in EBR2 is set to 1, the corresponding block is selected and can be programmed

and erased. Figure 19.2 and table 19.6 show a block map.

Bit 76543210

SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

Initial value*00000000

Read/Write R/W*R/W*R/W*R/W*R/W*R/W*R/W*R/W*

Note: *The initial value is H'00 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip ROM

disabled), this register cannot be modified and always reads H'FF. For information on

accessing this register, refer to in section 19.7, Flash Memory Programming and Erasing

Precautions (11).

Bits 7 to 0—Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be

programmed and erased.

Bits 7 to 0:

SB7 to SB0 Description

0 Block (SB7 to SB0) is not selected (Initial value)

1 Block (SB7 to SB0) is selected

382

19.2.4 Wait-State Control Register (WSCR)

WSCR is an 8-bit readable/writable register that enables flash-memory updates to be emulated in

RAM. It also controls frequency division of clock signals supplied to the on-chip supporting

modules and insertion of wait states by the wait-state controller.

WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 76543210

RAMS RAM0 CKDBL — WMS1 WMS0 WC1 WC0

Initial value 0 0 0 0 1 0 0 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7 and 6—RAM Select and RAM0 (RAMS and RAM0): These bits are used to reassign an

area to RAM (see table 19.5). These bits are write-enabled and their initial value is 0. They are

initialized by a reset and in hardware standby mode. They are not initialized in software standby

mode.

If only one of bits 7 and 6 is set, part of the RAM area can be overlapped onto the small-block

flash memory area. In that case, access is to RAM, not flash memory, and all flash memory blocks

are write/erase-protected (emulation protect*1). In this state, the mode cannot be changed to

program or erase mode, even if the P bit or E bit in the flash memory control register (FLMCR) is

set (although verify mode can be selected). Therefore, clear both of bits 7 and 6 before

programming or erasing the flash memory area.

If both of bits 7 and 6 are set, part of the RAM area can be overlapped onto the small-block flash

memory area, but this overlapping begins only when an interrupt signal is input while 12 V is

being applied to the FVPP pin. Up until that point, flash memory is accessed. Use this setting for

interrupt handling while flash memory is being programmed or erased.*2

Table 19.5 RAM Area Reassignment*3

Bit 7: RAMS Bit 6: RAM0 RAM Area ROM Area

0 0 None —

1 H'FC80 to H'FCFF H'0080 to H'00FF

1 0 H'FC80 to H'FD7F H'0080 to H'017F

1 H'FC00 to H'FC7F H'0000 to H'007F

383

Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to the on-

chip supporting modules. For details, see section 6, Clock Pulse Generator.

Bit 4—Reserved: This bit is reserved, but it can be written and read. Its initial value is 0.

Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1, WMS0)

Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0)

These bits control insertion of wait states by the wait-state controller. For details, see section 5,

Wait-State Controller.

Notes: *1 For details on emulation protect, see section 19.4.8, Protect Modes.

*2 For details on interrupt handling during programming and erasing of flash memory, see

section 19.4.9, Interrupt Handling during Flash Memory Programming and Erasing.

*3 RAM area that overlaps flash memory.

384

H'0000

H'01FF

H'0200

H'03FF

H'0400

H'07FF

H'0800

H'0BFF

H'0C00

H'0FFF

H'0000

H'0FFF

H'1000

H'1FFF

H'2000

H'3FFF

H'4000

H'5FFF

H'6000

H'7FFF

Small block

area

(4 kbytes)

Large block

area

(28 kbytes)

SB7 to SB0

4 kbytes

LB0

4 kbytes

LB1

8 kbytes

LB2

8 kbytes

LB3

8 kbytes

SB0 128 bytes

SB1 128 bytes

SB2 128 bytes

SB3 128 bytes

SB4

512 bytes

SB5

1 kbyte

SB6

1 kbyte

SB7

1 kbyte

Figure 19.2 Erase Block Map

385

Table 19.6 Erase Blocks and Corresponding Bits

EBR1 0 LB0 H'1000 to H'1FFF 4 kbytes

1 LB1 H'2000 to H'3FFF 8 kbytes

2 LB2 H'4000 to H'5FFF 8 kbytes

3 LB3 H'6000 to H'7FFF 8 kbytes

EBR2 0 SB0 H'0000 to H'007F 128 bytes

1 SB1 H'0080 to H'00FF 128 bytes

2 SB2 H'0100 to H'017F 128 bytes

3 SB3 H'0180 to H'01FF 128 bytes

4 SB4 H'0200 to H'03FF 512 bytes

5 SB5 H'0400 to H'07FF 1 kbyte

6 SB6 H'0800 to H'0BFF 1 kbyte

7 SB7 H'0C00 to H'0FFF 1 kbyte

19.3 On-Board Programming Modes

When an on-board programming mode is selected, the on-chip flash memory can be programmed,

erased, and verified. There are two on-board programming modes: boot mode, and user

programming mode. These modes are selected by inputs at the mode pins (MD1 and MD0) and

FVPP pin. Table 19.7 indicates how to select the on-board programming modes. For details on

applying voltage VPP, refer to section 19.7, Flash Memory Programming and Erasing Precautions

(5).

Table 19.7 On-Board Programming Mode Selection

Mode Selections FVPP MD1MD0Notes

Boot mode Mode 2 12 V*12 V*0 0: VIL

Mode 3 12 V*1 1: VIH

User programming Mode 2 1 0

mode Mode 3 1 1

Note: *For details on the timing of 12 V application, see notes 6 to 8 in the Notes on Use of Boot

Mode at the end of this section.

In boot mode, the mode control register (MDCR) can be used to monitor the mode (mode 2

or 3) in the same way as in normal mode.

Example: Set the mode pins for mode 2 boot mode (MD1 = 12 V, MD0 = 0 V).

If the mode select bits of MDCR are now read, they will indicate mode 2 (MDS1 = 1,

MDS0 = 0).

386

19.3.1 Boot Mode

To use boot mode, a user program for programming and erasing the flash memory must be

provided in advance on the host machine (which may be a personal computer). Serial

communication interface channel 1 is used in asynchronous mode. If the H8/3434F is placed in

boot mode, after it comes out of reset, a built-in boot program is activated. This program starts by

measuring the low period of data transmitted from the host and setting the bit rate register (BRR)

accordingly. The H8/3434F’s built-in serial communication interface (SCI) can then be used to

download the user program from the host machine. The user program is stored in on-chip RAM.

After the program has been stored, execution branches to address H'FBE0 in the on-chip RAM,

and the program stored on RAM is executed to program and erase the flash memory.

HOST

Receive data to be programmed

Transmit verification data

H8/3434F

RxD1

TxD1

SCI

Figure 19.3 Boot-Mode System Configuration

387

Boot-Mode Execution Procedure: Figure 19.4 shows the boot-mode execution procedure.

Start

Program H8/3434F pins for boot mode,

and reset

Host transmits H'00 data continuously

at desired bit rate

H8/3434F measures low period

of H'00 data transmitted from host

H8/3434F computes bit rate and

sets bit rate register

After completing bit-rate alignment, H8/3434F

sends one H'00 data byte to host to indicate

that alignment is completed

Host checks that this byte, indicating

completion of bit-rate alignment, is received

normally, then transmits one H'55 byte

After receiving H'55, H8/3434F sends part of

the boot program to RAM

H8/3434F transfers one user program

byte to RAM*2

H8/3434F calculates number of bytes left

to be transferred (N = N – 1)

All bytes transferred?

(N = 0?)

All data = H'FF?

Erase all flash

memory blocks*3

After transferring the user program to RAM,

H8/3434F transmits one H'AA data byte to host

Yes

H8/3434F branches to the RAM boot

area (H'FC00 to H'FF2F), then checks the

data in the user area of flash memory

H8/3434F receives two bytes indicating byte

length (N) of program to be downloaded

to on-chip RAM*1

After checking that all data in flash memory is H'FF,

H8/3434F transmits one H'AA data byte to host

H8/3434F branches to H'FBE0 in RAM area and

executes user program downloaded into RAM

1. Program the H8/3434F pins for boot mode, and start the

H8/3434F from a reset.

2. Set the host’s data format to 8 bits + 1 stop bit, select the

desired bit rate (2400, 4800, or 9600 bps), and transmit

H'00 data continuously.

3. The H8/3434F repeatedly measures the low period of the

RxD1 pin and calculates the host’s asynchronous-

communication bit rate.

4. When SCI bit-rate alignment is completed, the H8/3434F

transmits one H'00 data byte to indicate completion of

alignment.

5. The host should receive the byte transmitted from the

H8/3434F to indicate that bit-rate alignment is completed,

check that this byte is received normally, then transmit one

H'55 byte.

6. After receiving H'55, H8/3434F sends part of the boot

program to H'FB80 to H'FBDF and H'FC00 to H'FF2F of

RAM.

7. After branching to the boot program area (H'FC00 to

H'FF2F) in RAM, the H8/3434F checks whether the flash

memory already contains any programmed data. If so, all

blocks are erased.

8. After the H8/3434F transmits one H'AA data byte, the host

transmits the byte length of the user program to be

transferred to the H8/3434F. The byte length must be sent

as two-byte data, upper byte first and lower byte second.

After that, the host proceeds to transmit the user program.

As verification, the H8/3434F echoes each byte of the

received byte-length data and user program back to the

host.

9. The H8/3434F stores the received user program in on-chip

RAM in a 910-byte area from H'FBE0 to H'FF6D.

10. After transmitting one H'AA data byte, the H8/3434F

branches to address H'FBE0 in on-chip RAM and executes

the user program stored in the area from H'FBE0 to

H'FF6D.

Notes: *1 The user can use 910 bytes of RAM. The number

of bytes transferred must not exceed 910 bytes. Be

sure to transmit the byte length in two bytes, upper

byte first and lower byte second. For example, if the

byte length of the program to be transferred is 256

bytes (H'0100), transmit H'01 as the upper byte,

followed by H'00 as the lower byte.

*2 The part of the user program that controls the flash

memory should be coded according to the flash

memory program/erase algorithms given later.

*3 If a memory cell malfunctions and cannot be

erased, the H8/3434F transmits one H'FF byte to

report an erase error, halts erasing, and halts

further operations.

Figure 19.4 Boot Mode Flowchart

388

Automatic Alignment of SCI Bit Rate

D0 D1 D2 D3 D4 D5 D6 D7

Start

bit Stop

bit

This low period (9 bits) is measured (H'00 data)

High for at

least 1 bit

Figure 19.5 Measurement of Low Period in Data Transmitted from Host

When started in boot mode, the H8/3434F measures the low period in asynchronous SCI data

transmitted from the host (figure 19.5). The data format is eight data bits, one stop bit, and no

parity bit. From the measured low period (9 bits), the H8/3434F computes the host’s bit rate. After

aligning its own bit rate, the H8/3434F sends the host 1 byte of H'00 data to indicate that bit-rate

alignment is completed. The host should check that this alignment-completed indication is

received normally and send one byte of H'55 back to the H8/3434F. If the alignment-completed

indication is not received normally, the H8/3434F should be reset, then restarted in boot mode to

measure the low period again. There may be some alignment error between the host’s and

H8/3434F’s bit rates, depending on the host’s bit rate and the H8/3434F’s system clock frequency.

To have the SCI operate normally, set the host’s bit rate to 2400, 4800, or 9600 bps*1. Table 19.8

lists typical host bit rates and indicates the clock-frequency ranges over which the H8/3434F can

align its bit rate automatically. Boot mode should be used within these frequency ranges*2.

Table 19.8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by

H8/3434F

Host Bit Rate*1System Clock Frequencies Permitting Automatic Bit-Rate Alignment

by H8/3434F

9600 bps 8 MHz to 16 MHz

4800 bps 4 MHz to 16 MHz

2400 bps 2 MHz to 16 MHz

Notes: *1 Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be

used.

*2 Although the H8/3434F may also perform automatic bit-rate alignment with bit rate and

system clock combinations other than those shown in table 19.8, there will be a slight

difference between the bit rates of the host and the H8/3434F, and subsequent transfer

will not be performed normally. Therefore, only a combination of bit rate and system

clock frequency within one of the ranges shown in table 19.8 can be used for boot

mode execution.

389

RAM Area Allocation in Boot Mode: In boot mode, the 96 bytes from H'FB80 to H'FBDF and

the 18 bytes from H'FF6E to H'FF7F are reserved for use by the boot program, as shown in figure

19.6. The user program is transferred into the area from H'FBE0 to H'FF6D (910 bytes). The boot

program area can be used after the transition to execution of the user program transferred into

RAM. If a stack area is needed, set it within the user program.

Note: * This area cannot be used until the H8/3434F starts to execute the user program

transferred to RAM (until it has branched to H'FBE0 in RAM). Note that even after the

branch to the user program, the boot program area (H'FB80 to H'FBDF, H'FF6E to

H'FF7F) still contains the boot program.

Note also that 16 bytes (H'FB80 to H'FB8F) of this area cannot be used if an interrupt

handling routine is executed within the boot program. For details see section 19.4.9,

Interrupt Handling during Flash Memory Programming and Erasing.

User program

transfer area

(910 bytes)

Boot program

area* (18 bytes)

Boot program

area*

(96 bytes)

H'FB80

H'FBE0

H'FF6E

H'FF7F

Figure 19.6 RAM Areas in Boot Mode

390

Notes on Use of Boot Mode

1. When the H8/3434F comes out of reset in boot mode, it measures the low period of the input at

the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about

100 states for the H8/3434F to get ready to measure the low period of the RxD1 input.

2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF),

all flash memory blocks are erased. Boot mode is for use when user programming mode is

unavailable, e.g. the first time on-board programming is performed, or if the update program

activated in user programming mode is accidentally erased.

3. Interrupts cannot be used while the flash memory is being programmed or erased.

4. The RxD1 and TxD1 pins should be pulled up on-board.

5. Before branching to the user program (at address H'FBE0 in the RAM area), the H8/3434F

terminates transmit and receive operations by the on-chip SCI (by clearing the RE and TE bits

of the serial control register to 0 in channel 1), but the auto-aligned bit rate remains set in bit

rate register BRR. The transmit data output pin (TxD1) is in the high output state (in port 8, the

bits P84 DDR of the port 8 data direction register and P84 DR of the port 8 data register are set

to 1).

At this time, the values of general registers in the CPU are undetermined. Thus these registers

should be initialized immediately after branching to the user program. Especially in the case of

the stack pointer, which is used implicitly in subroutine calls, the stack area used by the user

program should be specified.

There are no other changes to the initialized values of other registers.

6. Boot mode can be entered by starting from a reset after 12 V is applied to the MD1 and FVPP

pins according to the mode setting conditions listed in table 19.7. Note the following points

when turning the VPP power on.

When reset is released (at the rise from low to high), the H8/3434F checks for 12-V input at

the MD1 and FVPP pins. If it detects that these pins are programmed for boot mode, it saves that

status internally. The threshold point of this voltage-level check is in the range from

approximately VCC + 2 V to 11.4 V, so boot mode will be entered even if the applied voltage is

insufficient for programming or erasure (11.4 V to 12.6 V). When the boot program is

executed, the VPP power supply must therefore be stabilized within the range of 11.4 V to

12.6 V before the branch to the RAM area occurs. See figure 19.20.

Make sure that the programming voltage VPP does not exceed 12.6 V during the transition to

boot mode (at the reset release timing) and does not go outside the range of 12 V ± 0.6 V while

in boot mode. Boot mode will not be executed correctly if these limits are exceeded. In

391

addition, make sure that VPP is not released or shut off while the boot program is executing or

the flash memory is being programmed or erased.*1

Boot mode can be released by driving the reset pin low, waiting at least ten system clock

cycles, then releasing the application of 12 V to the MD1 and FVPP pins and releasing the reset.

The settings of external pins must not change during operation in boot mode.

During boot mode, if input of 12 V to the MD1 pin stops but no reset input occurs at the RES

pin, the boot mode state is maintained within the chip and boot mode continues (but do not

stop applying 12 V to the FVPP pin during boot mode*1).

If a watchdog timer reset occurs during boot mode, this does not release the internal mode

state, but the internal boot program is restarted.

Therefore, to change from boot mode to another mode, the boot-mode state within the chip

must be released by a reset input at the RES pin before the mode transition can take place.

7. If the input level of the MD1 pin is changed during a reset (e.g., from 0 V to 5 V then to 12 V

while the input to the RES pin is low), the resultant switch in the microcontroller’s operating

mode will affect the bus control output signals (AS, RD, and WR) and the status of ports that

can be used for address output*2.

Therefore, either set these pins so that they do not output signals during the reset, or make sure

that their output signals do not collide with other signals outside the microcontroller.

8. When applying 12 V to the MD1 and FVPP pins, make sure that peak overshoot does not exceed

the rated limit of 13 V.

Also, be sure to connect a decoupling capacitor to the FVPP and MD1 pins.

Notes: *1 For details on applying, releasing, and shutting off VPP, see note (5) in section 19.7,

Flash Memory Programming and Erasing Precautions.

*2 These ports output low-level address signals if the mode pins are set to mode 1 during

the reset. In all other modes, these ports are in the high-impedance state. The bus

control output signals are high if the mode pins are set for mode 1 or 2 during the reset.

In mode 3, they are at high impedance.

392

19.3.2 User Programming Mode

When set to user programming mode, the H8/3434F can erase and program its flash memory by

executing a user program. On-board updates of the on-chip flash memory can be carried out by

providing on-board circuits for supplying VPP and data, and storing an update program in part of

the program area.

To select user programming mode, select a mode that enables the on-chip ROM (mode 2 or 3) and

apply 12 V to the FVPP pin, either during a reset, or after the reset has ended (been released) but

while flash memory is not being accessed. In user programming mode, the on-chip supporting

modules operate as they normally would in mode 2 or 3, except for the flash memory. However,

hardware standby mode cannot be set while 12 V is applied to the FVPP pin.

The flash memory cannot be read while it is being programmed or erased, so the update program

must either be stored in external memory, or transferred temporarily to the RAM area and

executed in RAM.

393

User Programming Mode Execution Procedure (Example)*: Figure 19.7 shows the execution

procedure for user programming mode when the on-board update routine is executed in RAM.

Note: * Do not apply 12 V to the FVPP pin during normal operation. To prevent flash memory

from being accidentally programmed or erased due to program runaway etc., apply 12 V

to FVPP only when programming or erasing flash memory. Overprogramming or

overerasing due to program runaway can cause memory cells to malfunction. While 12 V

is applied, the watchdog timer should be running and enabled to halt runaway program

execution, so that program runaway will not lead to overprogramming or overerasing. For

details on applying, releasing, and shutting off VPP, see section 19.7, Flash Memory

Programming and Erasing Precautions (5).

Set MD1 and MD0 to 10 or 11

(apply VIH to VCC to MD1)

Start from reset

Branch to flash memory on-board

update routine in RAM

FVPP = 12 V

(user programming mode)

Execute flash memory

on-board update routine in RAM

(update flash memory)

Branch to flash memory

on-board update program

Transfer on-board update routine

into RAM

Release FVPP

(exit user programming mode)

Branch to application program

in flash memory*

Procedure

The flash memory on-board update

program is written in flash memory ahead

of time by the user.

1. Set MD1 and MD0 of the H8/3434F to

10 or 11, and start from a reset.

2. Branch to the flash memory on-board

update program in flash memory.

3. Transfer the on-board update routine

into RAM.

4. Branch to the on-board update routine

that was transferred into RAM.

5. Apply 12 V to the FVPP pin, to enter

user programming mode.

6. Execute the flash memory on-board

update routine in RAM, to perform an

on-board update of the flash memory.

7. Change the voltage at the FVPP pin

from 12 V to VCC, to exit user

programming mode.

8. After the on-board update of flash

memory ends, execution branches to

an application program in flash

memory.

Note: *After the update is finished, when input of 12 V to the FVPP pin is released, the flash

memory read setup time (tFRS) must elapse before any program in flash memory is

executed. This is the required setup time from when the FVPP pin reaches the (VCC +

2 V) level after 12 V is released until flash memory can be read.

Figure 19.7 User Programming Mode Operation (Example)

394

19.4 Programming and Erasing Flash Memory

The H8/3434F’s on-chip flash memory is programmed and erased by software, using the CPU.

The flash memory can operate in program mode, erase mode, program-verify mode, erase-verify

mode, or prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV,

and EV bits in the flash memory control register (FLMCR).

The flash memory cannot be read while being programmed or erased. The program that controls

the programming and erasing of the flash memory must be stored and executed in on-chip RAM or

in external memory. A description of each mode is given below, with recommended flowcharts

and sample programs for programming and erasing.

For details on programming and erasing, refer to section 19.7, Flash Memory Programming and

Erasing Precautions.

19.4.1 Program Mode

To write data into the flash memory, follow the programming algorithm shown in figure 19.8. This

programming algorithm can write data without subjecting the device to voltage stress or impairing

the reliability of programmed data.

To program data, first specify the area to be written in flash memory with erase block registers

EBR1 and EBR2, then write the data to the address to be programmed, as in writing to RAM. The

flash memory latches the address and data in an address latch and data latch. Next set the P bit in

FLMCR, selecting program mode. The programming duration is the time during which the P bit is

set. A software timer should be used to provide a programming duration of about 10 to 20 µs. The

value of N, the number of attempts, should be set so that the total programming time does not

exceed 1 ms. Programming for too long a time, due to program runaway for example, can cause

device damage. Before selecting program mode, set up the watchdog timer so as to prevent

overprogramming.

395

19.4.2 Program-Verify Mode

In program-verify mode, after data has been programmed in program mode, the data is read to

check that it has been programmed correctly.

After the programming time has elapsed, exit programming mode (clear the P bit to 0) and select

program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is

applied to the memory cells at the latched address. If the flash memory is read in this state, the

data at the latched address will be read. After selecting program-verify mode, wait 4 µs or more

before reading, then compare the programmed data with the verify data. If they agree, exit

program-verify mode and program the next address. If they do not agree, select program mode

again and repeat the same program and program-verify sequence. Do not repeat the program and

program-verify sequence more than 50 times* for the same bit.

Note: * Keep the total programming time under 1 ms for each bit.

396

19.4.3 Programming Flowchart and Sample Program

Flowchart for Programming One Byte

Start

n = 1

Enable watchdog timer*2

Select program mode

(P bit = 1 in FLMCR)

Wait (x) µs*4

Clear P bit

Disable watchdog timer

Select program-verify mode

(PV bit = 1 in FLMCR)

Wait (tVS1) µs*4

Verify*3 (read memory) No go

Clear PV bit

End (1-byte data programmed)

End of programming

Clear PV bit

Programming error

n≥ N?*4

n + 1 → n

End of verification

Write data to flash memory (flash

memory latches write

address and data)*1

Set erase block register

(set bit of block to be programmed to 1)

Yes

Clear erase block register

(clear bit of programmed block to 0)

Notes: *1 Write the data to be programmed

with a byte transfer instruction.

*2 Set the timer overflow interval to the

shortest value (CKS2, CKS1, CKS0

all cleared to 0).

*3 Read the memory data to be verified

with a byte transfer instruction.

*4 x: 10 to 20 µs

tVS1: 4 µs or more

N: 50 (set N so that total

programming time does not

exceed 1 ms)

Figure 19.8 Programming Flowchart

397

Sample Program for Programming One Byte: This program uses the following registers.

R0H: Specifies blocks to be erased.

R1H: Stores data to be programmed.

R1L: Stores data to be read.

R3: Stores address to be programmed. Valid addresses are H'0000 to H'7FFF.

R4: Sets program and program-verify timing loop counters, and also stores register setting

value.

R5: Sets program timing loop counter.

R6L: Used for program-verify fail count.

Arbitrary data can be programmed at an arbitrary address by setting the address in R3 and the data

in R1H.

The setting of #a and #b values depends on the clock frequency. Set #a and #b values according to

tables 19.9 (1) and (2).

FLMCR: .EQU H'FF80

EBR1: .EQU H'FF82

EBR2: .EQU H'FF83

TCSR: .EQU H'FFA8

.ALIGN 2

PRGM: MOV.B #H'**, R0H ;

MOV.B R0H, @EBR*:8; Set EBR*

MOV.B #H'00, R6L ; Program-verify fail counter

MOV.W #H'a, R5 ; Set program loop counter

MOV.B R1H, @R3 ; Dummy write

PRGMS: INC R6L ; Program-verify fail counter + 1 → R6L

MOV.W #H'A578, R4 ;

MOV.W R4, @TCSR ; Start watchdog timer

MOV.W R5, R4 ; Set program loop counter

BSET #0, @FLMCR:8 ; Set P bit

LOOP1: SUBS #1, R4 ;

MOV.W R4, R4 ;

BNE LOOP1 ; Wait loop

BCLR #0, @FLMCR:8 ; Clear P bit

MOV.W #H'A500, R4 ;

MOV.W R4, @TCSR ; Stop watchdog timer

MOV.B #H'b , R4H ; Set program-verify loop counter

BSET #2, @FLMCR:8 ; Set PV bit

LOOP2: DEC R4H ;

BNE LOOP2 ; Wait loop

MOV.B @R3, R1L ; Read programmed address

CMP.B R1H, R1L ; Compare programmed data with read data

BEQ PVOK ; Program-verify decision

BCLR #2, @FLMCR:8 ; Clear PV bit

398

CMP.B #H'32, R6L ; Program-verify executed 50 times?

BEQ NGEND ; If program-verify executed 50 times, branch to NGEND

BRA PRGMS ; Program again

PVOK: BCLR #2, @FLMCR:8 ; Clear PV bit

MOV.B #H'00, R6L ;

MOV.B R6L, @EBR*:8; Clear EBR*

One byte programmed

NGEND: Programming error

19.4.4 Erase Mode

To erase the flash memory, follow the erasing flowchart shown in figure 19.9. This erasing flow

can erase data without subjecting the device to voltage stress or impairing the reliability of

programmed data.

To erase flash memory, before starting to erase, first place all memory data in all blocks to be

erased in the programmed state (program all memory data to H'00). If all memory data is not in the

programmed state, follow the sequence described later (figure 19.10) to program the memory data

to zero. Select the flash memory areas to be erased with erase block registers 1 and 2 (EBR1 and

EBR2). Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during

which the E bit is set. To prevent overerasing, use a software timer to divide the erase time into

repeated 10 ms intervals, and perform erase operations a maximum of 3000 times so that the total

erase time does not exceed 30 seconds. Overerasing, due to program runaway for example, can

give memory cells a negative threshold voltage and cause them to operate incorrectly. Before

selecting erase mode, set up the watchdog timer so as to prevent overerasing.

19.4.5 Erase-Verify Mode

In erase-verify mode, after data has been erased, it is read to check that it has been erased

correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0) and select erase-

verify mode (set the EV bit to 1). Before reading data in erase-verify mode, write H'FF dummy

data to the address to be read. This dummy write applies an erase-verify voltage to the memory

cells at the latched address. If the flash memory is read in this state, the data at the latched address

will be read. After the dummy write, wait 2 µs or more before reading. When performing the

initial dummy write, wait 4 µs or more after selecting erase-verify mode. If the read data has been

successfully erased, perform an erase-verify (dummy write, wait 2 µs or more, then read) for the

next address. If the read data has not been erased, select erase mode again and repeat the same

erase and erase-verify sequence through the last address, until all memory data has been erased to

1. Do not repeat the erase and erase-verify sequence more than 3000 times, however.

399

19.4.6 Erasing Flowchart and Sample Program

Flowchart for Erasing One Block

Start

Write 0 data in all addresses

to be erased (prewrite)*1

n = 1

Set erase block register

(set bit of block to be erased to 1)

Enable watchdog timer*2

Select erase mode

(E bit = 1 in FLMCR)

Wait (x) ms*5

Clear E bit

Disable watchdog timer

Set top address in block

as verify address

Select erase-verify mode

(EV bit = 1 in FLMCR)

Wait (tVS1) µs*5

Dummy write to verify address*3

(flash memory latches address)

Verify*4 (read data H'FF?)

Last address?

Address + 1 → address Yes

No go

Yes

Clear EV bit

Clear erase block register

(clear bit of erased block to 0)

End of block erase

Clear EV bit

Erase error

n≥ N?*5

Erase-verify ends

Erasing ends

n + 1 → n

Wait (tVS2) µs*5

Notes: *1 Program all addresses to be

erased by following the prewrite

flowchart.

*2 Set the watchdog timer overflow

interval to the value indicated in

table 19.10.

*3 For the erase-verify dummy write,

write H'FF with a byte transfer

instruction.

*4 Read the data to be verified with

a byte transfer instruction. When

erasing two or more blocks, clear

the bits of erased blocks in the

erase block registers, so that only

unerased blocks will be erased

again.

*5 x: 10 ms

tVS1: 4 µs or more

tVS2: 2 µs or more

N: 3000

Figure 19.9 Erasing Flowchart

400

Prewrite Flowchart

End of prewrite

n≥ N?*4

n + 1 → n

Start

Set start address*5

Write H'00 to flash memory

(Flash memory latches

write address and write data)*1

Enable watchdog timer*2

Select program mode

( P bit = 1 in FLMCR)

Wait (x) µs*4

Disable watchdog timer

Wait (tVS1) µs*4

Prewrite verify*3

(read data = H'00?) No go

Yes

Clear P bit End of programming

Programming error

Address + 1 → address

Yes

Set erase block register

(set bit of block to be programmed to 1)

Clear erase block register

(clear bit of programmed block to 0)

n = 1

Last address?*5

Notes: *1 Use a byte transfer instruction.

*2 Set the timer overflow interval to the

shortest value (CKS2, CKS1, CKS0

all cleared to 0).

*3 In prewrite-verify mode P, E, PV,

and EV are all cleared to 0 and 12 V

is applied to FVPP. Read the data

with a byte transfer instruction.

*4 x: 10 to 20 µs

tVS1: 4 µs or more

N: 50 (set N so that total

programming time does not

exceed 1 ms)

*5 Start and last addresses shall be top

and last addresses of the block to be

erased.

Figure 19.10 Prewrite Flowchart

401

Sample Block-Erase Program: This program uses the following registers.

R0: Specifies block to be erased, and also stores address used in prewrite and erase-verify.

R1H: Stores data to be read, and also used for dummy write.

R2: Stores last address of block to be erased.

R3: Stores address used in prewrite and erase-verify.

R4: Sets timing loop counters for prewrite, prewrite-verify, erase, and erase-verify, and also

stores register setting value.

R5: Sets prewrite and erase timing loop counters.

R6L: Used for prewrite-verify and erase-verify fail count.

The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a,

#b, #c, #d, and #e values according tables 19.9 (1) and (2), and 19.10. Erase block registers (EBR1

and EBR2) should be set according to sections 19.2.2 and 19.2.3. #BLKSTR and #BLKEND are

the top and last addresses of the block to be erased. Set #BLKSTR and #BLKEND according to

figure 19.2.

402

FLMCR: .EQU H'FF80

EBR1: .EQU H'FF82

EBR2: .EQU H'FF83

TCSR: .EQU H'FFA8

.ALIGN 2

MOV.B #H'**, ROH ;

MOV.B ROH, @EBR*:8; Set EBR*

; #BLKSTR is top address of block to be erased.

; #BLKEND is last address of block to be erased.

MOV.W #BLKSTR, R0 ; Top address of block to be erased

MOV.W #BLKEND, R2 ; Last address of block to be erased

ADDS #1, R2 ; Last address of block to be erased + 1 → R2

; Execute prewrite

MOV.W R0, R3 ; Top address of block to be erased

PREWRT: MOV.B #H'00, R6L ; Prewrite-verify fail counter

MOV.W #H'a, R5 ; Set prewrite loop counter

PREWRS: INC R6L ; Prewrite-verify fail counter + 1 → R6L

MOV.B #H'00 R1H ;

MOV.B R1H, @R3 ; Write H'00

MOV.W #H'A578, R4 ;

MOV.W R4, @TCSR ; Start watchdog timer

MOV.W R5, R4 ; Set prewrite loop counter

BSET #0, @FLMCR:8 ; Set P bit

LOOPR1: SUBS #1, R4 ;

MOV.W R4, R4 ;

BNE LOOPR1 ; Wait loop

BCLR #0, @FLMCR:8 ; Clear P bit

MOV.W #H'A500, R4 ;

MOV.W R4, @TCSR ; Stop watchdog timer

MOV.B #H'c, R4H ; Set prewrite-verify loop counter

LOOPR2: DEC R4H ;

BNE LOOPR2 ; Wait loop

MOV.B @R3, R1H ; Read data = H'00?

BEQ PWVFOK ; If read data = H'00 branch to PWVFOK

CMP.B #H'32, R6L ; Prewrite-verify executed 50 times?

BEQ ABEND1 ; If prewrite-verify executed 50 times, branch to ABEND1

BRA PREWRS ; Prewrite again

ABEND1: Programming error

PWVFOK: ADDS #1, R3 ; Address + 1 → R3

CMP.W R2, R3 ; Last address?

BNE PREWRT ; If not last address, prewrite next address

403

;Execute erase

ERASES: MOV.W #H'0000, R6 ; Erase-verify fail counter

MOV.W #H'd, R5 ; Set erase loop count

ERASE: ADDS #1, R6 ; Erase-verify fail counter + 1 → R6

MOV.W #H'e, R4 ;

MOV.W R4, @TCSR ; Start watchdog timer

MOV.W R5, R4 ; Set erase loop counter

BSET #1, @FLMCR:8 ; Set E bit

LOOPE: NOP

NOP

SUBS #1, R4 ;

MOV.W R4, R4 ;

BNE LOOPE ; Wait loop

BCLR #1, @FLMCR:8 ; Clear E bit

MOV.W #H'A500, R4 ;

MOV.W R4, @TCSR ; Stop watchdog timer

; Execute erase-verify

MOV.W R0, R3 ; Top address of block to be erased

MOV.B #H'b, R4H ; Set erase-verify loop counter

BSET #3, @FLMCR:8 ; Set EV bit

LOOPEV: DEC R4H ;

BNE LOOPEV ; Wait loop

EVR2: MOV.B #H'FF, R1H ;

MOV.B R1H, @R3 ; Dummy write

MOV.B #H'c, R4H ; Set erase-verify loop counter

LOOPDW: DEC R4H ;

BNE LOOPDW ; Wait loop

MOV.B @R3+, R1H ; Read

CMP.B #H'FF, R1H ; Read data = H'FF?

BNE RERASE ; If read data ≠ H'FF, branch to RERASE

CMP.W R2, R3 ; Last address of block?

BNE EVR2

BRA OKEND

RERASE: BCLR #3, @FLMCR:8 ; Clear EV bit

SUBS #1, R3 ; Erase-verify address – 1 → R3

BRER: MOV.W #H'0BB8, R4 ;

CMP.W R4, R6 ; Erase-verify executed 3000 times?

BNE ERASE ; If erase-verify not executed 3000 times, erase again

BRA ABEND2 ; If erase-verify executed 3000 times, branch to ABEND2

OKEND: BCLR #3, @FLMCR:8 ; Clear EV bit

MOV.B #H'00, R6L ;

MOV.B R6L, @EBR*:8; Clear EBR*

One block erased

ABEND2: Erase error

404

Flowchart for Erasing Multiple Blocks

Start

Write 0 data to all addresses to be

erased (prewrite)*1

n = 1

Set erase block registers

(set bits of blocks to be erased to 1)

Enable watchdog timer*2

Select erase mode (E bit = 1 in FLMCR)

Wait (X) ms*5

Clear E bit

Disable watchdog timer

Select erase-verify mode

(EV bit = 1 in FLMCR)

Wait (tVS1) µs*5

Set top address of block as

verify address

Dummy write to verify address*3

(flash memory latches address)

Erase-verify

next block

Verify*4

(read data H'FF?)

Last address

in block?

Address + 1 → address

Clear EBR bit of erased block

All erased blocks

verified?

Clear EV bit

All blocks erased?

(EBR1 = EBR2 = 0?)

End of erase

n≥ N?*5

Erase error n + 1 → n

Yes

No go

Erasing

ends

All erased blocks

verified?

Erase-verify next block

Yes

Wait (tVS2) µs*5

Notes: *1 Program all addresses to be

erased by following the prewrite

flowchart.

*2 Set the watchdog timer

overflow interval to the value

indicated in table 19.10.

*3 For the erase-verify dummy

write, write H'FF with a byte

transfer instruction.

*4 Read the data to be verified

with a byte transfer instruction.

When erasing two or more

blocks, clear the bits of erased

blocks in the erase block

blocks will be erased again.

*5 X: 10 ms

tVS1: 4 µs or more

tVS2: 2 µs or more

N: 3000

Figure 19.11 Multiple-Block Erase Flowchart

405

Sample Multiple-Block Erase Program: This program uses the following registers.

R0: Specifies blocks to be erased (set as explained below), and also stores address used in

prewrite and erase-verify.

R1H: Used to test bits 8 to 11 of R0 stores register read data, and also used for dummy write.

R1L: Used to test bits 0 to 11 of R0.

R2: Specifies address where address used in prewrite and erase-verify is stored.

R3: Stores address used in prewrite and erase-verify.

R4: Stores last address of block to be erased.

R5: Sets prewrite and erase timing loop counters.

R6L: Used for prewrite-verify and erase-verify fail count.

Arbitrary blocks can be erased by setting bits in R0. Write R0 with a word transfer instruction.

A bit map of R0 and a sample setting for erasing specific blocks are shown next.

Bit 1514131211109876543210

R0 ————LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

Corresponds to EBR1 Corresponds to EBR2

Note: Clear bits 15, 14, 13, and 12 to 0.

Example: to erase blocks LB2, SB7, and SB0

Bit 1514131211109876543210

R0 ————LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

Corresponds to EBR1 Corresponds to EBR2

Setting 0000010010000001

R0 is set as follows:

MOV.W #H'0481,R0

MOV.W R0, @EBR1

The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a,

#b, #c, #d, and #e values according to tables 19.9 (1), (2), and 19.10.

406

Notes: 1. In this sample program, the stack pointer (SP) is set at address H'FF80. As the stack

area, on-chip RAM addresses H'FF7E and H'FF7F are used. Therefore, when executing

this sample program, addresses H'FF7E and H'FF7F should not be used. In addition,

the on-chip RAM should not be disabled.

2. In this sample program, the program written in a ROM area (including external space)

is transferred into the RAM area and executed in the RAM to which the program is

transferred. #RAMSTR in the program is the starting destination address in RAM to

which the program is transferred. #RAMSTR must be set to an even number.

3. When executing this sample program in the on-chip ROM area or external space,

#RAMSTR should be set to #START.

FLMCR: .RQU H'FF80

EBR1: .EQU H'FF82

EBR2: .EQU H'FF83

TCSR: .EQU H'FFA8

STACK: .EQU H'FF80

.ALIGN 2

START: MOV.W #STACK, SP ; Set stack pointer

; Set the bits in R0 following the description on the previous page. This program is a sample program to erase

; all blocks.

MOV.W #H'0FFF, R0 ; Select blocks to be erased (R0: EBR1/EBR2)

MOV.W R0, @EBR1 ; Set EBR1/EBR2

; #RAMSTR is starting destination address to which program is transferred in RAM.

; Set #RAMSTR to even number.

MOV.W #RAMSTR, R2 ; Starting transfer destination address (RAM)

MOV.W #ERVADR, R3 ;

ADD.W R3, R2 ; #RAMSTR + #ERVADR → R2

MOV.W #START, R3 ;

SUB.W R3, R2 ; Address of data area used in RAM

MOV.B #H'00, R1L : Used to test R1L bit in R0

PRETST: CMP.B #H'0C, R1L ; R1L = H'0C?

BEQ ERASES ; If finished checking all R0 bits, branch to ERASES

CMP.B #H'08, R1L ;

BMI EBR2PW ; Test EBR1 if R1L ≥ 8, or EBR2 if R1L < 8

MOV.B R1L, R1H ;

SUBX #H'08, R1H ; R1L – 8 → R1H

BTST R1H, R0H ; Test R1H bit in EBR1 (R0H)

BNE PREWRT ; If R1H bit in EBR1 (R0H) is 1, branch to PREWRT

BRA PWADD1 ; If R1H bit in EBR1 (R0H) is 0, branch to PWADD1

EBR2PW: BTST R1L, R0L ; Test R1L bit in EBR2 (R0L)

BNE PREWRT ; If R1L bit in EBR2 (R0H) is 1, branch to PREWRT

PWADD1: INC R1L ; R1L + 1 → R1L

MOV.W @R2+, R3 ; Dummy-increment R2

BRA PRETST ;

407

; Execute prewrite

PREWRT: MOV.W @R2+, R3 ; Prewrite starting address

PREW: MOV.B #H'00, R6L ; Prewrite-verify fail counter

MOV.W #H'a, R5 ; Prewrite-verify loop counter

PREWRS: INC R6L ; Prewrite-verify fail counter + 1 → R6L

MOV.B #H'00 R1H ;

MOV.B R1H, @R3 ; Write H'00

MOV.W #H'A578, R4 ;

MOV.W R4, @TCSR ; Start watchdog timer

MOV.W R5, R4 ; Set prewrite loop counter

BSET #0, @FLMCR:8 ; Set P bit

LOOPR1: SUBS #1, R4 ;

MOV.W R4, R4 ;

BNE LOOPR1 ; Wait loop

BCLR #0, @FLMCR:8 ; Clear P bit

MOV.W #H'A500, R4 ;

MOV.W R4, @TCSR ; Stop watchdog timer

MOV.B #H'c, R4H ; Set prewrite-verify loop counter

LOOPR2: DEC R4H ;

BNE LOOPR2 ; Wait loop

MOV.B @R3, R1H ; Read data = H'00?

BEQ PWVFOK ; If read data = H'00 branch to PWVFOK

CMP.B #H'32, R6L ; Prewrite-verify executed 50 times?

BEQ ABEND1 ; If prewrite-verify executed 50 times, branch to ABEND1

BRA PREWRS ; Prewrite again

ABEND1: Programming error

PWVFOK: ADDS #1, R3 ; Address + 1 → R3

MOV.W @R2, R4 ; Top address of next block

CMP.W R4, R3 ; Last address?

BNE PREW ; If not last address, prewrite next address

PWADD2: INC R1L ; Used to test R1L+1 bit in R0

BRA PRETST ; Branch to PRETST

; Execute erase

ERASES: MOV.W #H'0000, R6 ; Erase-verify fail counter

MOV.W #H'd, R5 ; Set erase loop count

ERASE: ADDS #1, R6 ; Erase-verify fail counter + 1 → R6

MOV.W #H'e, R4 ;

MOV.W R4, @TCSR ; Start watchdog timer

MOV.W R5, R4 ; Set erase loop counter

BSET #1, @FLMCR:8 ; Set E bit

LOOPE: NOP

NOP

SUBS #1, R4 ;

MOV.W R4, R4 ;

BNE LOOPE ; Wait loop

BCLR #1, @FLMCR:8 ; Clear E bit

MOV.W #H'A500, R4 ;

MOV.W R4, @TCSR ; Stop watchdog timer

408

; Execute erase-verify

EVR: MOV.W #RAMSTR, R2 ; Starting transfer destination address (RAM)

MOV.W #ERVADR, R3 ;

ADD.W R3, R2 ; #RAMSTR + #ERVADR → R2

MOV.W #START, R3 ;

SUB.W R3, R2 ; Address of data area used in RAM

MOV.B #H'00, R1L ; Used to test R1L bit in R0

MOV.B #H'b, R4H ; Set erase-verify loop counter

BSET #3, @FLMCR:8 ; Set EV bit

LOOPEV: DEC R4H ;

BNE LOOPEV ; Wait loop

EBRTST: CMP.B #H'0C, R1L ; R1L = H'0C?

BEQ HANTEI ; If finished checking all R0 bits, branch to HANTEI

CMP.B #H'08, R1L ;

BMI EBR2EV ; Test EBR1 if R1L ≥ 8, or EBR2 if R1L < 8

MOV.B R1L, R1H ;

SUBX #H'08, R1H ; R1L – 8 → R1H

BTST R1H, R0H ; Test R1H bit in EBR1 (R0H)

BNE ERSEVF ; If R1H bit in EBR1 (R0H) is 1, branch to ERSEVF

BRA ADD01 ; If R1H bit in EBR1 (R0H) is 0, branch to ADD01

EBR2EV: BTST R1L, R0L ; Test R1L bit in EBR2 (R0L)

BNE ERSEVF ; If R1L bit in EBR2 (R0H) is 1, branch to ERSEVF

ADD01: INC R1L ; R1L + 1 → R1L

MOV.W @R2+, R3 ; Dummy-increment R2

BRA EBRTST ;

ERASE1: BRA ERASE ; Branch to ERASE via Erase 1

ERSEVF: MOV.W @R2+, R3 ; Top address of block to be erase-verified

EVR2: MOV.B #H'FF, R1H ;

MOV.B R1H, @R3 ; Dummy write

MOV.B #H'c, R4H ; Set erase-verify loop counter

LOOPEP: DEC R4H ;

BNE LOOPEP ; Wait loop

MOV.B @R3+, R1H ; Read

CMP.B #H'FF, R1H ; Read data = H'FF?

BNE BLKAD ; If read data ≠ H'FF branch to BLKAD

MOV.W @R2, R4 ; Top address of next block

CMP.W R4, R3 ; Last address of block?

BNE EVR2

CMP.B #H'08, R1L ;

BMI SBCLR ; Test EBR1 if R1L ≥ 8, or EBR2 if R1L < 8

MOV.B R1L, R1H ;

SUBX #H'08, R1H ; R1L – 8 → R1H

BCLR R1H, R0H ; Clear R1H bit in EBR1 (R0H)

BRA BLKAD ;

SBCLR: BCLR R1L, R0L ; Clear R1L bit in EBR2 (R0L)

BLKAD: INC R1L ; R1L + 1 →R1L

BRA EBRTST ;

HANTEI: BCLR #3, @FLMCR:8 ; Clear EV bit

MOV.W R0, @EBR1 ;

BEQ EOWARI ; If EBR1/EBR2 is all 0, erasing ended normally

409

BRER: MOV.W #H'0BB8, R4 ;

CMP.W R4, R6 ; Erase-verify executed 3000 times?

BNE ERASE1 ; If erase-verify not executed 3000 times, erase again

BRA ABEND2 ; If erase-verify executed 3000 times, branch to ABEND2

;———< Block address table used in erase-verify> ———

.ALIGN 2

ERVADR: .DATA.W H'0000 ; SB0

.DATA.W H'0080 ; SB1

.DATA.W H'0100 ; SB2

.DATA.W H'0180 ; SB3

.DATA.W H'0200 ; SB4

.DATA.W H'0400 ; SB5

.DATA.W H'0800 ; SB6

.DATA.W H'0C00 ; SB7

.DATA.W H'1000 ; LB0

.DATA.W H'2000 ; LB1

.DATA.W H'4000 ; LB2

.DATA.W H'6000 ; LB3

.DATA.W H'8000 ; FLASH END

EOWARI: Erase end

ABEND2: Erase error

Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings: The

setting of #a, #b, #c, #d, and #e values in the programs depends on the clock frequency. Tables

19.9 (1) and (2) indicate sample loop counter settings for typical clock frequencies. However, #e is

set according to table 19.10.

As a software loop is used, calculated values including percent errors may not be the same as

actual values. Therefore, the values are set so that the total programming time and total erase time

do not exceed 1 ms and 30 s, respectively.

The maximum number of writes in the program, N, is set to 50.

Programming and erasing in accordance with the flowcharts is achieved by setting #a, #b, #c, and

#d in the programs as shown in tables 19.9 (1) and (2). #e should be set as shown in table 19.10.

Wait state insertion is inhibited in these programs. If wait states are to be used, the setting should

be made after the program ends. The setting value for the watchdog timer (WDT) overflow time is

calculated based on the number of instructions between starting and stopping of the WDT,

including the write time and erase time. Therefore, no other instructions should be added between

starting and stopping of the WDT in this program example.

410

Table 19.9 (1) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with

Program Running in the On-Chip Memory (RAM)

Clock Frequency

f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz

Variable Time

Setting Counter

Setting Value Counter

Setting Value

a(f) Programming time 20 µs H'0028 H'0019 H'0014 H'0005

b(f) tvs1 4 µs H'0B H'07 H'06 H'02

c(f) tvs2 2 µs H'06 H'04 H'03 H'01

d(f) Erase time 10 ms H'2710 H'186A H'1388 H'04E2

Table 19.9 (2) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with

Program Running in the External Device

Clock Frequency

f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz

Variable Time

Setting Counter

Setting Value Counter

Setting Value

a(f) Programming time 20 µs H'000D H'0008 H'0006 H'0001

b(f) tvs1 4 µs H'04 H'03 H'02 H'01

c(f) tvs2 2 µs H'02 H'02 H'01 H'01

d(f) Erase time 10 ms H'0D05 H'0823 H'0682 H'01A0

411

Formula: When using a clock frequency not shown in tables 19.9 (1) and (2), follow the formula

below. The calculation is based on a clock frequency of 10 MHz.

After calculating a(f) and d(f) in the decimal system, omit the first decimal figures, and convert

them to the hexadecimal system, so that a(f) and d(f) are set to 20 µs or less and 10 ms or less,

respectively.

After calculating b(f) and c(f) in the decimal system, raise the first decimal figures, and convert

them to the hexadecimal system, so that b(f) and c(f) are set to 4 µs or more and 2 µs or more,

respectively.

Clock frequency f [MHz]

a (f) to d (f) = × a (f = 10) to d (f = 10)

Examples for a program running in on-chip memory (RAM) at a clock frequency of 12 MHz:

a (f) = ×25 = 30 ≈30 = H'001E

b (f) = ×7 = 8.4 ≈9 = H'09

c (f) = ×4 = 4.8 ≈5 = H'05

d (f) = ×6250 = 7500 ≈7500 = H'1D4C

Table 19.10 Watchdog Timer Overflow Interval Settings (#e Setting Value According to

Clock Frequency)

Variable

Clock Frequency [MHz] e (f)

10 MHz ≤ frequency ≤ 16 MHz H'A57F

2 MHz ≤ frequency < 10 MHz H'A57E

412

19.4.7 Prewrite Verify Mode

Prewrite-verify mode is a verify mode used when programming all bits to equalize their threshold

voltages before erasing them.

Program all flash memory to H'00 by writing H'00 using the prewrite algorithm shown in figure

19.10. H'00 should also be written when using RAM for flash memory emulation (when

prewriting a RAM area). (This also applies when using RAM to emulate flash memory erasing

with an emulator or other support tool.) After the necessary programming time has elapsed, exit

program mode (by clearing the P bit to 0) and select prewrite-verify mode (leave the P, E, PV, and

EV bits all cleared to 0). In prewrite-verify mode, a prewrite-verify voltage is applied to the

memory cells at the read address. If the flash memory is read in this state, the data at the read

address will be read. After selecting prewrite-verify mode, wait 4 µs or more before reading.

Note: For a sample prewriting program, see the prewrite subroutine in the sample erasing

program.

19.4.8 Protect Modes

Flash memory can be protected from programming and erasing by software or hardware methods.

These two protection modes are described below.

Software Protection: Prevents transitions to program mode and erase mode even if the P or E bit

is set in the flash memory control register (FLMCR). Details are as follows.

Function

Protection Description Program Erase Verify*1

Block

protect Individual blocks can be protected from erasing

and programming by the erase block registers

(EBR1 and EBR2). If H'F0 is set in EBR1 and

H'00 in EBR2, all blocks are protected from

erasing and programming.

Disabled Disabled Enabled

Emulation

protect*2When the RAMS or RAM0 bit, but not both, is

set in the wait-state control register (WSCR),

all blocks are protected from programming and

erasing.

Disabled Disabled*3Enabled

Notes: *1 Three modes: program-verify, erase-verify, and prewrite-verify.

*2 Except in RAM areas overlapped onto flash memory.

*3 All blocks are erase-disabled. It is not possible to specify individual blocks.

413

Hardware Protection: Suspends or disables the programming and erasing of flash memory, and

resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2).

Details of hardware protection are as follows.

Function

Protection Description Program Erase Verify*1

Programing

voltage (VPP)

protect

When 12 V is not applied to the FVPP pin,

FLMCR, EBR1, and EBR2 are initialized,

disabling programming and erasing. To obtain

this protection, VPP should not exceed VCC.*3

Disabled Disabled*2Disabled

Reset and

standby

protect

When a reset occurs (including a watchdog

timer reset) or standby mode is entered,

FLMCR, EBR1, and EBR2 are initialized,

disabling programming and erasing. Note that

RES input does not ensure a reset unless the

RES pin is held low for at least 20 ms at power-

up (to enable the oscillator to settle), or at least

ten system clock cycles (10ø) during operation.

Disabled Disabled*2Disabled

Interrupt

protect To prevent damage to the flash memory, if

interrupt input occurs while flash memory is

being programmed or erased, programming or

erasing is aborted immediately. The settings in

FLMCR, EBR1, and EBR2 are retained. This

type of protection can be cleared only by a

reset.

Disabled Disabled*2Enabled

Notes: *1 Three modes: program-verify, erase-verify, and prewrite-verify.

*2 All blocks are erase-disabled. It is not possible to specify individual blocks.

*3 For details, see section 19.7, Flash Memory Programming and Erasing Precautions.

19.4.9 Interrupt Handling during Flash Memory Programming and Erasing

If an interrupt occurs*1 while flash memory is being programmed or erased (while the P or E bit of

FLMCR is set), the following operating states can occur.

• If an interrupt is generated during programming or erasing, programming or erasing is aborted

to protect the flash memory. Since memory cell values after a forced interrupt are

indeterminate, the system will not operate correctly after such an interrupt.

• Program runaway may result because the vector table could not be read correctly in interrupt

exception handling during programming or erasure*2.

414

For NMI interrupts while flash memory is being programmed or erased, these malfunction and

runaway problems can be prevented by using the RAM overlap function with the settings

described below.

1. Do not store the NMI interrupt-handling routine*3 in the flash memory area (H'0000 to

H'7FFF). Store it elsewhere (in RAM, for example).

2. Set the NMI interrupt vector in address H'FC06 in RAM (corresponding to H'0006 in flash

memory).

3. After the above settings, set both the RAMS and RAM0 bits to 1 in WSCR. *4

Due to the setting of step 3, if an interrupt signal is input while 12 V is applied to the FVPP pin, the

RAM overlap function is enabled and part of the RAM (H'FC00 to H'FC7F) is overlapped onto the

small-block area of flash memory (H'0000 to H'007F). As a result, when an interrupt is input, the

vector is read from RAM, not flash memory, so the interrupt is handled normally even if flash

memory is being programmed or erased. This can prevent malfunction and runaway.

Notes: *1 When the interrupt mask bit (I) of the condition control register (CCR) is set to 1, all

interrupts except NMI are masked. For details see (2) in section 2.2.2, Control

Registers.

*2 The vector table might not be read correctly for one of the following reasons:

•If flash memory is read while it is being programmed or erased (while the P or E bit

of FLMCR is set), the correct value cannot be read.

•If no value has been written for the NMI entry in the vector table yet, NMI

exception handling will not be executed correctly.

*3 This routine should be programmed so as to prevent microcontroller runaway.

*4 For details on WSCR settings, see section 19.2.4, Wait-State Control Register.

Notes on Interrupt Handling in Boot Mode: In boot mode, the settings described above

concerning NMI interrupts are carried out, and NMI interrupt handling (but not other interrupt

handling) is enabled while the boot program is executing. Note the following points concerning

the user program.

• If interrupt handling is required

 Load the NMI vector (H'FB80) into address H'FC06 in RAM (the 38th byte of the

transferred user program should be H'FB80).

 The interrupt handling routine used by the boot program is stored in addresses H'FB80 to

H'FB8F in RAM. Make sure that the user program does not overwrite this area.

• If interrupt handling is not required

Since the RAMS and RAM0 bits remain set to 1 in WSCR, make sure that the user program

disables the RAM overlap by clearing the RAMS and RAM0 bits both to 0.

415

19.5 Flash Memory Emulation by RAM

Erasing and programming flash memory takes time, which can make it difficult to tune parameters

and other data in real time. If necessary, real-time updates of flash memory can be emulated by

overlapping the small-block flash-memory area with part of the RAM (H'FC00 to H'FD7F). This

RAM reassignment is performed using bits 7 and 6 of the wait-state control register (WSCR).

After a flash memory area has been overlapped by RAM, the RAM area can be accessed from two

address areas: the overlapped flash memory area, and the original RAM area (H'FC00 to H'FD7F).

Table 19.11 indicates how to reassign RAM.

Wait-State Control Register (WSCR)*2

Bit 76543210

RAMS RAM0 CKDBL —WMS1 WMS0 WC1 WC0

Initial value*100001000

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Notes: *1 WSCR is initialized by a reset and in hardware standby mode. It is not initialized in

software standby mode.

*2 For details of WSCR settings, see section 19.2.4, Wait-State Control Register (WSCR).

Table 19.11 RAM Area Selection

Bit 7: RAMS Bit 6: RAMO RAM Area ROM Area

0 0 None —

1 H'FC80 to H'FCFF H'0080 to H'00FF

1 0 H'FC80 to H'FD7F H'0080 to H'017F

1 H'FC00 to H'FC7F H'0000 to H'007F

416

Example of Emulation of Real-Time Flash-Memory Update

H'007F

H'0080

H'00FF

H'0100

H'0000

H'7FFF

H'FB80

H'FC80

H'FCFF

H'FF7F

Small-block

area (SB1)

Flash memory

address space

Overlapped

RAM

Overlapped RAM

On-chip

RAM area

Procedure

1. Overlap part of RAM (H'FC80 to H'FCFF) onto the area requiring real-time update (SB1).

(Set WSCR bits 7 and 6 to 01.)

2. Perform real-time updates in the overlapping RAM.

3. After finalization of the update data, clear the RAM overlap (by clearing the RAMS and

RAM0 bits).

4. Read the data written in RAM addresses H'FC80 to H'FCFF out externally, then program

the flash memory area, using this data as part of the program data.

Figure 19.12 Example of RAM Overlap

417

Notes on Use of RAM Emulation Function

• Notes on Applying, Releasing, and Shutting Off the Programming Voltage (VPP)

Care is necessary to avoid errors in programming and erasing when applying, releasing, and

shutting off VPP, just as in the on-board programming modes. In particular, even if the

emulation function is being used, make sure that the watchdog timer is set when the P or E bit

of the flash memory control register (FLMCR) has been set, to prevent errors in programming

and erasing due to program runaway while VPP is applied.

For details see section 19.7, Flash Memory Programming and Erasing Precautions (5).

418

19.6 Flash Memory Writer Mode (H8/3434F)

19.6.1 Writer Mode Setting

The on-chip flash memory of the H8/3434F can be programmed and erased not only in the on-

board programming modes but also in writer mode, using a PROM programmer.

19.6.2 Socket Adapter and Memory Map

Programs can be written and verified by attaching a special 100-pin/32-pin socket adapter to the

PROM programmer. Table 19.12 gives ordering information for the socket adapter. Figure 19.13

shows a memory map in writer mode. Figure 19.14 shows the socket adapter pin interconnections.

Table 19.12 Socket Adapter

Microcontroller Package Socket Adapter

HD64F3434F16 100-pin QFP HS3434ESHF1H

HD64F3434TF16 100-pin TQFP HS3434ESNF1H

H8/3434F H'0000

H'7FFF

H'0000

H'7FFF

On-chip ROM area

MCU mode Writer mode

1 output

H'1FFFF

Figure 19.13 Memory Map in Writer Mode

419

H8/3434F

Pin Name

FP-100B, TFP-100B

24, 25, 29,

32, 16

5, 6, 23,35

36, 37

4, 9, 59

15, 70, 71, 92

2, 3

Other pins

HN28F101 (32 Pins)

Pin No.

Pin Name

VPP

FA9

FA16

FA15

FO0

FO1

FO2

FO3

FO4

FO5

FO6

FO7

FA0

FA1

FA2

FA3

FA4

FA5

FA6

FA7

FA8

FA10

FA11

FA12

FA13

FA14

VCC

VSS

Socket Adapter Pin No.

STBY/FVPP

NMI

P95

P94

P93

P30

P31

P32

P33

P34

P35

P36

P37

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P91, P90, P63,

P64, P97

MD1, MD0, P92, P67

AVref, AVCC

VCCB, VCC

AVSS

VSS

RES

XTAL, EXTAL

NC (OPEN)

Power-on

reset circuit

Oscillator circuit

Legend:

VPP:

FO7 to FO0:

FA16 to FA0:

OE:

CE:

WE:

Programming power supply

Data input/output

Address input

Output enable

Chip enable

Write enable

Figure 19.14 Wiring of Socket Adapter

420

19.6.3 Operation in Writer Mode

The program/erase/verify specifications in writer mode are the same as for the standard

HN28F101 flash memory. However, since the H8/3434F does not support product name

recognition mode, the programmer cannot be automatically set with the device name. Table 19.13

indicates how to select the various operating modes.

Table 19.13 Operating Mode Selection in Writer Mode

Pins

Mode FVPP VCC CE OE WE D7 to D0A16 to A0

Read Read VCC VCC L L H Data output Address input

Output

disable VCC VCC L H H High impedance

Standby VCC VCC H X X High impedance

Command Read VPP VCC L L H Data output

write Output

disable VPP VCC L H H High impedance

Standby VPP VCC H X X High impedance

Write VPP VCC L H L Data input

Note: Be sure to set the FVPP pin to VCC in these states. If it is set to 0 V, hardware standby mode

will be entered, even when in writer mode, resulting in incorrect operation.

Legend:

L: Low level

H: High level

VPP:V

PP level

VCC:V

CC level

X: Don’t care

421

Table 19.14 Writer Mode Commands

1st Cycle 2nd Cycle

Command Cycles Mode Address Data Mode Address Data

Memory read 1 Write X H'00 Read RA Dout

Erase setup/erase 2 Write X H'20 Write X H'20

Erase-verify 2 Write EA H'A0 Read X EVD

Auto-erase setup/

auto-erase 2 Write X H'30 Write X H'30

Program setup/

program 2 Write X H'40 Write PA PD

Program-verify 2 Write X H'C0 Read X PVD

Reset 2 Write X H'FF Write X H'FF

PA: Program address

EA: Erase-verify address

RA: Read address

PD: Program data

PVD: Program-verify output data

EVD: Erase-verify output data

422

High-Speed, High-Reliability Programming: Unused areas of the H8/3434F flash memory

contain H'FF data (initial value). The H8/3434F flash memory uses a high-speed, high-reliability

programming procedure. This procedure provides enhanced programming speed without

subjecting the device to voltage stress and without sacrificing the reliability of programmed data.

Figure 19.15 shows the basic high-speed, high-reliability programming flowchart. Tables 19.15

and 19.16 list the electrical characteristics during programming.

Start

Set VPP = 12.0 V ±0.6 V

Address = 0

n = 0

Program command

Program setup command

n + 1 → n

Wait (25 µs)

Program-verify command

Wait (6 µs)

Address + 1 → address

Verification?

Last address?

Set VPP = VCC

End Fail

n = 20?

No go

Yes

Figure 19.15 High-Speed, High-Reliability Programming

423

High-Speed, High-Reliability Erasing: The H8/3434F flash memory uses a high-speed, high-

reliability erasing procedure. This procedure provides enhanced erasing speed without subjecting

the device to voltage stress and without sacrificing data reliability. Figure 19.16 shows the basic

high-speed, high-reliability erasing flowchart. Tables 19.15 and 19.16 list the electrical

characteristics during erasing.

Start

Program all bits to 0*

Address = 0

n = 0

Wait (10 ms)

Erase setup/erase command

n + 1 → n

Erase-verify command

Wait (6 µs)

Address + 1 → address

Verification?

Last address?

End Fail

n = 3000?

No go

Yes

Follow the high-speed, high-reliability programming flowchart in programming all bits. If some bits

are already programmed to 0, program only the bits that have not yet been programmed.

Note: *

Figure 19.16 High-Speed, High-Reliability Erasing

424

Table 19.15 DC Characteristics in Writer Mode

(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Typ Max Unit Test Conditions

Input high

voltage FO7 to FO0,

FA16 to FA0,

OE, CE, WE

VIH 2.2 —VCC + 0.3 V

Input low

voltage FO7 to FO0,

FA16 to FA0,

OE, CE, WE

VIL –0.3 —0.8 V

Output high

voltage FO7 to FO0VOH 2.4 —— VI

OH = –200 µA

Output low

voltage FO7 to FO0VOL ——0.45 V IOL = 1.6 mA

Input leakage

current FO7 to FO0,

FA16 to FA0,

OE, CE, WE

| ILI | ——2µA Vin = 0 to VCC

VCC current Read ICC —40 80 mA

Program ICC —40 80 mA

Erase ICC —40 80 mA

FVPP current Read IPP ——10 µAV

PP = 5.0 V

—10 20 mA VPP = 12.6 V

Program IPP —20 40 mA VPP = 12.6 V

Erase IPP —20 40 mA VPP = 12.6 V

425

Table 19.16 AC Characteristics in Writer Mode

(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Typ Max Unit Test Conditions

Command write cycle tCWC 120 ——ns Figure 19.17

Address setup time tAS 0——ns Figure 19.18*

Address hold time tAH 60 ——ns Figure 19.19

Data setup time tDS 50 ——ns

Data hold time tDH 10 ——ns

CE setup time tCES 0——ns

CE hold time tCEH 0——ns

VPP setup time tVPS 100 ——ns

VPP hold time tVPH 100 ——ns

WE programming pulse width tWEP 70 ——ns

WE programming pulse high time tWEH 40 ——ns

OE setup time before command write tOEWS 0——ns

OE setup time before verify tOERS 6——µs

Verify access time tVA ——500 ns

OE setup time before status polling tOEPS 120 ——ns

Status polling access time tSPA ——120 ns

Program wait time tPPW 25 ——ns

Erase wait time tET 9—11 ms

Output disable time tDF 0—40 ns

Total auto-erase time tAET 0.5 —30 s

Note: CE, OE, and WE should be high during transitions of VPP from 5 V to 12 V and from 12 V to

5 V.

*Input pulse level: 0.45 V to 2.4 V

Input rise time and fall time ≤ 10 ns

Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output

426

Auto-erase setup Auto-erase and status polling

Address

Command

input

Status polling

Command

input

Command

input Command

input

5.0 V

12 V

5.0 V

VCC

VPP

I/O7

I/O0 to I/O6

tVPS tVPH

tCEH tCES

tCES

tOEWS tWEP tCEH

tCES

tCWC

tWEP

tOEPS

tAET

tWEH

tDS tDH tDS tDH tSPA tDF

Figure 19.17 Auto-Erase Timing

427

tVPH

tVPS

tCEH

tCES

tOEWS tWEP tCEH

tCES

tCWC

tWEP

tDS tDH tDS tDH

tAS tAH

tPPW

tCES

tWEH

tCEH

tWEP tOERS

tDH

tDS

tVA tDF

Command

input

Command

input

Data

input Command

input

Command

input

Valid data

output

Data

input

Program setup Program Program-verify

Valid address

Address

5.0 V

12 V

5.0 V

VCC

VPP

I/O7

I/O0 to I/O6

Note: Program-verify data output values may be intermediate between 1 and 0 before programming has

been completed.

Valid data

output

Figure 19.18 High-Speed, High-Reliability Programming Timing

428

Address

5.0 V

12 V

5.0 V

VCC

VPP

I/O0 to I/O7

Erase setup Erase Erase-verify

Valid address

Command

input Command

input

Valid data

output

tVPS tVPH

tAS tAH

tOEWS tCWC

tCES tWEP

tCEH

tDH

tDS

tWEH

tDS tDH tDS tDH

tVA

tDF

tCES tWEP

tCEH tCES

tET tWEP

tCEH

tOERS

Note: Erase-verify data output values may be intermediate between 1 and 0 before erasing has been completed.

Figure 19.19 Erase Timing

19.7 Flash Memory Programming and Erasing Precautions

Read these precautions before using writer mode, on-board programming mode, or flash memory

emulation by RAM.

(1) Program with the specified voltages and timing.

The rated programming voltage (VPP) of the flash memory is 12.0 V.

If the PROM programmer is set to Hitachi HN28F101 specifications, VPP will be 12.0 V. Applying

voltages in excess of the rating can permanently damage the device. Take particular care to ensure

that the PROM programmer peak overshoot does not exceed the rated limit of 13 V.

(2) Before programming, check that the chip is correctly mounted in the PROM

programmer. Overcurrent damage to the device can result if the index marks on the PROM

programmer socket, socket adapter, and chip are not correctly aligned.

(3) Don’t touch the socket adapter or chip while programming. Touching either of these can

cause contact faults and write errors.

429

(4) Set H'FF as the PROM programmer buffer data for addresses H'8000 to H'1FFFF. The

H8/3434F PROM size is 32 kbytes. Addresses H'8000 to H'1FFFF always read H'FF, so if H'FF is

not specified as programmer data, a verify error will occur.

(5) Notes on applying, releasing, and shutting off the programming voltage (VPP)

Note: In this section, the application, release, and shutting-off of VPP are defined as follows.

Application: A rise in voltage from VCC to 12 V ± 0.6 V.

Release: A drop in voltage from 12 V ± 0.6 V to VCC.

Shut-off: No applied voltage (floating).

• Apply the programming voltage (VPP) after the rise of VCC, and release VPP before shutting off

VCC.

To prevent unintended programming or erasing of flash memory, in these power-on and

power-off timings, the application, release, and shutting-off of VPP must take place when the

microcontroller is in a stable operating condition as defined below.

Stable operating condition

 The VCC voltage must be stabilized within the rated voltage range (VCC = 2.7 V to 5.5 V)*

If VPP is applied, released, or shut off while the microcontroller’s VCC voltage is not within

the rated voltage range (VCC = 2.7 to 5.5 V)*, since microcontroller operation is unstable,

the flash memory may be programmed or erased by mistake. This can occur even if VCC =

0 V. To prevent changes in the VCC power supply when VPP is applied, be sure that the

power supply is adequately decoupled with inserting bypass capacitors.

Note: * In the LH version, VCC = 3.0 V to 5.5 V.

 Clock oscillation must be stabilized (the oscillation settling time must have elapsed), and

oscillation must not be stopped

When turning on VCC power, hold the RES pin low during the oscillation settling time

(tOSC1 = 20 ms), and do not apply VPP until after this time.

 The microcontroller must be in the reset state, or in a state in which a reset has ended

normally (reset has been released) and flash memory is not being accessed

Apply or release VPP either in the reset state, or when the CPU is not accessing flash

memory (when a program in on-chip RAM or external memory is executing). Flash

memory cannot be read normally at the instant when VPP is applied or released. Do not read

flash memory while VPP is being applied or released.

For a reset during operation, apply or release VPP only after the RES pin has been held low

for at least ten system clock cycles (10ø).

430

 The P and E bits must be cleared in the flash memory control register (FLMCR)

When applying or releasing VPP, make sure that the P or E bit is not set by mistake.

 No program runaway

When VPP is applied, program execution must be supervised, e.g. by the watchdog timer.

These power-on and power-off timing requirements should also be satisfied in the event of

a power failure and in recovery from a power failure. If these requirements are not

satisfied, overprogramming or overerasing may occur due to program runaway etc., which

could cause memory cells to malfunction.

• The VPP flag is set and cleared by a threshold decision on the voltage applied to the FVPP pin.

The threshold level is between approximately VCC + 2 V to 11.4 V.

When this flag is set, it becomes possible to write to the flash memory control register

(FLMCR) and the erase block registers (EBR1 and EBR2), even though the VPP voltage may

not yet have reached the programming voltage range of 12.0 ± 0.6 V.

Do not actually program or erase the flash memory until VPP has reached the programming

voltage range.

The programming voltage range for programming and erasing flash memory is 12.0 ± 0.6 V

(11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range.

When not programming or erasing the flash memory, ensure that the VPP voltage does not

exceed the VCC voltage. This will prevent unintended programming and erasing.

In this chip, the same pin is used for STBY and FVPP. When this pin is driven low, a transition

is made to hardware standby mode. This happens not only in the normal operating modes

(modes 1, 2, and 3), but also when programming the flash memory with a PROM programmer.

When programming with a PROM programmer, therefore, use a programmer which sets this

pin to the VCC level when not programming (FVPP=12 V).

431

tOSC1

2.7 to 5.5 V*

12 ± 0.6 V

VCC + 2 V to 11.4 V

VCCV

12 ± 0.6 V

VCCV

0 µs min

0 to VCCV

Min 10ø

(when RES is low)

VCC

VPP

RES

Boot mode

User program

mode

Timing at which boot

program branches

to RAM area

Periods during which the VPP flag is being set or

cleared and flash memory must not be accessed

Note: * In the LH version, VCC = 3.0 V to 5.5 V.

Figure 19.20 VPP Power-On and Power-Off Timing

(6) Do not apply 12 V to the FVPP pin during normal operation.

To prevent accidental programming or erasing due to microcontroller program runaway etc., apply

12 V to the VPP pin only when the flash memory is programmed or erased, or when flash memory

is emulated by RAM. Overprogramming or overerasing due to program runaway can cause

memory cells to malfunction. Avoid system configurations in which 12 V is always applied to the

FVPP pin.

While 12 V is applied, the watchdog timer should be running and enabled to halt runaway

program execution, so that program runaway will not lead to overprogramming or overerasing.

432

(7) Design a current margin into the programming voltage (VPP) power supply. Ensure that

VPP will not depart from 12.0 ±0.6 V (11.4 V to 12.6 V) during programming or erasing.

Programming and erasing may become impossible outside this range.

(8) Ensure that peak overshoot does not exceed the rated value at the FVPP and MD1 pins.

Connect decoupling capacitors as close to the FVPP and MD1 pins as possible.

Also connect decoupling capacitors to the MD1 pin in the same way when boot mode is used.

0.01 µF1.0 µF

12 V MD

0.01 µF1.0 µF

12 V FV

H8/3434F

Note: Also connect decoupling capacitors to the MD

pin in the same way when boot mode is used.

Figure 19.21 VPP Power Supply Circuit Design (Example)

(9) Use the recommended algorithms for programming and erasing flash memory. These

algorithms are designed to program and erase without subjecting the device to voltage stress and

without sacrificing the reliability of programmed data.

Before setting the program (P) or erase (E) bit in the flash memory control register (FLMCR), set

the watchdog timer to ensure that the P or E bit does not remain set for more than the specified

time.

(10) For details on interrupt handling while flash memory is being programmed or erased, see the

notes on NMI interrupt handling in section 19.4.9, Interrupt Handling during Flash Memory

Programming and Erasing.

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(11) Cautions on Accessing Flash Memory Control Registers

1. Flash memory control register access state in each operating mode

The H8/3434F has flash memory control registers located at addresses H'FF80 (FLMCR),

H'FF82 (EBR1), and H'FF83 (EBR2). These registers can only be accessed when 12 V is

applied to the flash memory program power supply pin, FVPP.

Table 19.17 shows the area accessed for the above addresses in each mode, when 12 V is and

is not applied to FVPP.

Table 19.17 Area Accessed in Each Mode with 12V Applied and Not Applied to FVPP

Mode 1 Mode 2 Mode 3

12 V applied

to FVPP

Reserved area

(always H'FF) Flash memory control

H'80)

12 V not applied

to FVPP

External address

space External address space Reserved area

(always H'FF)

2. When a flash memory control register is accessed in mode 2 (expanded mode with on-chip

ROM enabled)

When a flash memory control register is accessed in mode 2, it can be read or written to if 12

V is being applied to FVPP, but if not, external address space will be accessed. It is therefore

essential to confirm that 12 V is being applied to the FVPP pin before accessing these registers.

3. To check for 12 V application/non-application in mode 3 (single-chip mode)

When address H'FF80 is accessed in mode 3, if 12 V is being applied to FVPP, FLMCR is

read/written to, and its initial value after reset is H'80. When 12 V is not being applied to FVPP,

FLMCR is a reserved area that cannot be modified and always reads H'FF. Since bit 7

(corresponding to the VPP bit) is set to 1 at this time regardless of whether 12 V is applied to

FVPP, application or release of 12 V to FVPP cannot be determined simply from the 0 or 1 status

of this bit. A byte data comparison is necessary to check whether 12V is being applied. The

relevant coding is shown below.

LABEL1: MOV.B @H'FF80, R1L

CMP.B #H'FF, R1L

BEQ LABEL1

Sample program for detection of 12 V application to FVPP (mode 3)

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Table 19.18 DC Characteristics of Flash Memory

Conditions: VCC = 2.7 V to 5.5 V*2, AVCC = 2.7 V to 5.5 V*2, AVref = 2.7 V to AVCC*2,

VSS = AVSS = 0 V, VPP = 12.0 ± 0.6 V, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Typ Max Unit Test Conditions

High-voltage

(12 V) threshold

level*1

FVPP, MD1VHVCC + 2 —11.4 V

FVPP current During read IPP ——10 µAV

PP = 2.7 to 5.5 V

—10 20 mA VPP = 12.6 V

During

programming —20 40 mA

During

erasure —20 40 mA

Notes: *1 The listed voltages describe the threshold level at which high-voltage application is

recognized. In boot mode and while flash memory is being programmed or erased, the

applied voltage should be 12.0 V ± 0.6 V.

*2 In the LH version, VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC.

435

Table 19.19 AC Characteristics of Flash Memory

Conditions: VCC = 2.7 V to 5.5 V*5, AVCC = 2.7 V to 5.5 V*5, AVref = 2.7 V to AVCC*5,

VSS = AVSS = 0 V, VPP = 12.0 ± 0.6 V, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Typ Max Unit Test Conditions

Programming time*1, *2tP—50 1000 µs

Erase time*1, *3tE—130s

Number of writing/erasing count NWEC ——100 Times

Verify setup time 1*1tVS1 4——µs

Verify setup time 2*1tVS2 2——µs

Flash memory read setup tFRS 50 ——µsV

CC ≥ 4.5 V

time*4100 —— VCC < 4.5 V

Notes: *1 Set the times following the programming/erasing algorithm shown in section 19.

*2 The programming time is the time during which a byte is programmed or the P bit in the

flash memory control register (FLMCR) is set. It does not include the program-verify

time.

*3 The erase time is the time during which all 32-kbyte blocks are erased or the E bit in the

flash memory control register (FLMCR) is set . It does not include the prewrite time

before erasure or erase-verify time.

*4 After power-on when using an external colck source, after return from standby mode, or

after switching the programming voltage (VPP) from 12 V to VCC, make sure that this read

setup time has elapsed before reading flash memory.

When VPP is released, the flash memory read setup time is defined as the period from

when the FVPP pin has reached VCC + 2 V until flash memory can be read.

*5 In the LH version, VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC.

436

437

Section 20 ROM

(60-kbyte Dual-Power-Supply Flash Memory Version)

20.1 Flash Memory Overview

20.1.1 Flash Memory Operating Principle

Table 20.1 illustrates the principle of operation of the H8/3437F’s on-chip flash memory.