W71NW11GF1EW - Winbond - Datasheet.Directory

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 1 - Revision 2.0

MULTI-CHIP P ACKAGE (MCP) MEMORY

1.8V 1G-BIT x16-BIT SLC

NAND FLASH MEMORY

1.8V 1G-BIT (8M WORD x 8 BANK x 16-BIT)

LOW PO W ER DDR2 SDRAM

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 2 - Revision 2.0

Table of Contents

1 GENER AL D E SCRIPTIO N .............................................................................................................. 3

2 FEATURES...................................................................................................................................... 3

3 BALL CONFIGURATION ................................................................................................................. 4

3.1 121-Ball Description for W29N01GW NAND Flash Memory ................................................... 5

3.2 121-Ball Description for W97AH6KB Low Power DDR2 SDRAM ........................................... 6

4 Block Diagram ................................................................................................................................. 8

5 Package Specification ..................................................................................................................... 9

5.1 WFBGA121Ball (8X8mm^2, Ball pitch:0.5mm, Ø=0.3mm) ..................................................... 9

6 MCP ORDERING INFORMATION ................................................................................................ 10

7 Revision History ............................................................................................................................. 11

Table of Table

Table 3-1 W29N01GW WFBGA-121 Ball Description ............................................................................ 5

Table 3-2 W97AH6KB WFBGA-121 Ball Description ............................................................................. 7

Table 7-1 Revision History .................................................................................................................... 11

Table of Figure

Figure 3-1 W71NW11GF1EW, 121 Ball WFBGA Package (Balls facing down) ..................................... 4

Figure 4-1 W71NW11GF1EW MCP Flash & LPDDR2 SDRAM Block Diagram ..................................... 8

Figure 5-1 121 Ball WFBGA 8x8mm Package ........................................................................................ 9

Figure 6-1 MCP Ordering Information ................................................................................................... 10

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 3 - Revision 2.0

1 GENERAL DESCRIPTION

The W71NW series is a Multi-Chip Package (MCP) memory product family that consists of a 1.8V NAND

Flash Memory device and a 1.8V Low Power SDRAM device in one convenient Thin WFBGA package.

W71NW11GF1EW consists of:

• W29N01GW - 1.8V 1G-Bit x16-BIT NAND Flash Memory

• W97AH6KB - 1.8V 1G-Bit x16-BIT Low P ower DDR2 SDRAM

• 121 Ball WFBGA - Dimension 8x8x0.8mm, ball pitch 0.50-mm, ball diameter 0.3-mm

2 FEATURES

W29N01GW NAND Flash Memory W97AH6KB Low Power DDR2 SDRAM

• Basic Features

– Density : 1Gbit (Single chip solution)

– Vcc : 1.7V to 1.95V

– Bus width : x16

– Operating temperature

 Industrial: - 40°C to 85°C

• Single-Level Cell (SLC) technology.

• Organization

– Density: 1G-bit/128M-byte

– Page size:1,056 words( 1 024 +3 2 words)

– Block size:6 4 pages ( 64 K +2K words )

• Highest Performance

– Read performance (Max.)

 Random read: 25us

 Sequential read cycle: 35ns

– Write Erase performance

 Page program time: 300us(typ.)

 Block erase time: 2ms(typ.)

– Endurance 100K Erase/Program Cycles1

– 10-years data retention

• Command set

– Standard NAND command set

– Additional command support

 Sequential Cache Read

 Random Cache Read

 Cache Program

 Copy Back

 OTP Data Program, Data Lock by Page

and Data Rea d

– Contact Winbond for block Lock feature

• Lowest power consumption

– Read: 10mA(typ.)

– Program/Erase: 10mA(typ.)

– CMOS standby: 10uA(typ.)

• VDD1 = 1.7~1.95V

• VDD2/VDDCA/VDDQ = 1.14V ~ 1.30V

• Data width: x16

• Clock rate: up to 533MHz

• Four-bit prefetch DDR architecture

• Eight internal banks for concurrent operation

• Programmable READ and WRITE latencies

(RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per Bank Refresh

• Partial Array Self-Refresh(PASR)

• De ep Pow e r Dow n Mo de (DP D Mode )

• Programmable output buffer driver strength

• Data mask (DM) for write data

• Clock Stop capability during idle periods

• Double data rate for data output

• Differential clock inputs

• Bidirectional differential data strobe

• Interface: HSUL_12

• JEDEC LPDDR2-S4B compliance

• Support package:

• Operating Temperature Range

-40 ~ 85 °C

Note:

1. Endurance specification is based on 1bit/528 byte ECC (Erro r Correcti ng Code).

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 4 - Revision 2.0

3 BALL CONFIGURATION

Figure 3-1 W71NW11GF1EW, 121 Ball WFBGA Package (Balls facing down)

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 5 - Revision 2.0

3.1 121-Ball Description for W29N01GW NAND Flash Memory

Ball NO. BALL

NAME

I/O FUNCTION

WP#

Write Protect

F7 WE# I Write Enable

ALE

Address Latch Enable

C7 CLE I Command Latch Enable

CE#

Chip Enable

G6 RE# I Read Enable

R/B#

Ready/#Busy

C2 IO0 I/O Data Input Output 0

IO1

I/O

Data Input Output 1

A3 IO2 I/O Data Input Output 2

IO3

I/O

Data Input Output 3

C3 IO4 I/O Data Input Output 4

IO5

I/O

Data Input Output 5

B4 IO6 I/O Data Input Output 6

IO7

I/O

Data Input Output 7

J7 IO8 I/O Data Input Output 8

IO9

I/O

Data Input Output 9

J6 IO10 I/O Data Input Output 10

IO11

I/O

Data Input Output 11

G5 IO12 I/O Data Input Output 12

IO13

I/O

Data Input Output 13

J5 IO14 I/O Data Input Output 14

IO15

I/O

Data Input Output 15

A6,F5,K7 VCCn Po wer Su pply NAND

B2,B6,F6,K6

VSSn

Ground NAND

C5,N5 DNU Do Not Use

Multiple

No Connection

Table 3-1 W29N01GW WFBGA-121 Ball Description

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 6 - Revision 2.0

3.2 121-Ball Description for W97AH6KB Low Power DDR2 SDRAM

BALL NO. BALL

NAME I/O FUNCTION

L2 CS1_n I Chip Select

P5 CKE1 I Clock Enable

K2 CK_c I CK_t and CK_c are differential clock inputs

K1 CK_t I CK_t and CK_c are differential clock inputs

E3 CA9 I DDR Command/Address Input 9

F2 CA8 I DDR Command/Address Input

G2 CA7 I DDR Command/Address Input

G3 CA6 I DDR Command/Address Input

H2 CA5 I DDR Command/Address Input

M1 CA4 I DDR Command/Address Input

M2 CA3 I DDR Command/Address Input

N2 CA2 I DDR Command/Address Input

N3 CA1 I DDR Command/Address Input

P3 CA0 I DDR Command/Address Input

G10 DM1 I Input Data Mask

J10 DM0 I Input Data Mask

J9 DQS0_c I/O Data Strobe (Bi-directional, Differential)

K10 DQS0_t I/O Data Strobe (Bi-directional, Differential)

F10 DQS1_t I/O Data Strobe (Bi-directional, Differential)

G9 DQS1_c I/O Data Strobe (Bi-directional, Differential)

B8 DQ15 I/O Data Inputs/Output

B9 DQ14 I/O Data Inputs/Output

C11 DQ13 I/O Data Inputs/Output

C10 DQ12 I/O Data Inputs/Output

C9 DQ11 I/O Data Inputs/Output

D10 DQ10 I/O Data Inputs/Output

E10 DQ9 I/O Data Inputs/Output

E9 DQ8 I/O Data Inputs/Output

L9 DQ7 I/O Data Inputs/Output

L10 DQ6 I/O Data Inputs/Output

M10 DQ5 I/O Data Inputs/Output

P9 DQ4 I/O Data Inputs/Output

N9 DQ3 I/O Data Inputs/Output

N10 DQ2 I/O Data Inputs/Output

P8 DQ1 I/O Data Inputs/Output

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 7 - Revision 2.0

BALL NO. BALL

NAME I/O FUNCTION

P7 DQ0 I/O Data Inputs/Output

E2 ZQ I/O Reference Pin for Output Drive Strength

Calibration

B7, F1, J11, R5 VDD1 Core Power Supply 1

A7, D1, H11, J1, R4, R7 VDD2 Core Power Supply 2

A9, E11, G11, K11, M11, R9 VDDQ I/O Power Supply

H1, N1 VDDCA Input Receiver Power Supply

A8, E1, J3, R3, R6, R8 VSS Ground

B10, D11, F11, L11, N11, P10 VSSQ I/O Ground

G1, P2 VSSCA Ground for CA Input Receivers

J2 VREF(CA) Reference

Voltage for CA Command and

Control Input Receiver

H10 VREF(DQ) Reference Voltage for DQ Input Receiver

Table 3-2 W97AH6KB WFBGA-121 Ball Description

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 8 - Revision 2.0

4 Block Diagram

Figure 4-1 W71NW11GF1EW MCP F lash & LPD DR2 SDRAM Block Diag r am

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 9 - Revision 2.0

5 Package Specification

5.1 WFBGA121Ball (8X8mm^2, Ball pitch: 0.5mm, Ø=0.3mm)

Figure 5-1 121 Ball WFBGA 8x8mm Package

Note:

1. Ball land:0.35mm, Ball openi ng:0.28mm,

PCB Ball land suggested 0.28mm

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 10 - Revision 2.0

6 MCP ORDERING INFORMA TION

Figure 6-1 MCP Ordering Information

71 NW 1 1 G F 1 E W

Winbond Standard Product

W: Winbond

Product Family

71: MCP Product

Voltage

NW: 1.8V ONFI NAND Flash

Product Density

1: 1Gb

NAND I/O bits

1: 16 bit

Flash Generation

G= WEC 4X Tec hnolo g y Node

RAM Density

F= 1Gb LPDDR2

RAM Option Information

1: 4X Technology *16

Package Type

E: 121 Balls FBGA

Grade & Temperature

W: Industrial: -40°C to +85°C

W71NW11GF1EW

Publication Release Date: September 07, 2016

- 11 - Revision 2.0

7 Revisi on Histor y

VERSION DATE PAGE DESCRIPTION

A 11/08/13 New Create Preliminary

B 02/14/14 10 Temperature Change

C 04/21/14 NA Updated the LPDDR2 Document. (IDD values)

D 06/02/15 3 & 10 Temperature Change for both die.

E 02/18/16 NA Removed Preliminary annotations

2.0 09/07/2016 NA Preliminary annotations removed on attached

datasheets

Table 7-1 Revision History

Trademarks

Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.

All other marks are the property of their respective owner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in

systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products

are not i nte nde d f or ap pl ica t ions wher e in f ailure of Winbond pr o duc ts c ou ld r esu lt or le ad t o a s itu ati on

wherein personal injury, death or severe property or environmental damage could occur.

Winbond c ustom ers using or selling these produc ts f or use in s uch app lica tions d o so at t heir own risk

and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

W29N01GZ/W

Release Date: February 1st, 2016

1 – Revision G

W29N01GZ/W

1G-BIT 1.8V

NAND FL ASH MEMORY

W29N01GZ/W

Release Date: February 1st, 2016

2 – Revision G

Table of Contents

1. GEN ER AL D E SCR I PTION ............................................................................................................... 7

2. FEATURES ....................................................................................................................................... 7

3. PIN DESCRIPTIONS ........................................................................................................................ 8

3.1 Chip Enable (#CE) ................................................................................................................ 8

3.2 Write Enable (#WE) .............................................................................................................. 8

3.3 Read Enable (#RE) .............................................................................................................. 8

3.4 Address Latch Enable (ALE) ................................................................................................ 8

3.5 Command Latch Enable (CLE) ............................................................................................ 8

3.6 Write Protect (#WP) .............................................................................................................. 8

3.7 Ready/Busy (RY/#BY) .......................................................................................................... 8

3.8 Input and Output (I/Ox) ......................................................................................................... 8

4. BLOCK DIAGRAM ............................................................................................................................ 9

5. MEMORY ARRAY ORGANIZATION .............................................................................................. 10

5.1 X8 Array Organization ........................................................................................................ 10

5.2 X16 Array Organization ...................................................................................................... 11

6. MODE SELECTION TABLE ........................................................................................................... 12

7. COMMAND TABLE......................................................................................................................... 13

8. DEVICE OPERATIONS .................................................................................................................. 14

8.1 READ operation .................................................................................................................. 14

8.1.1 PAGE READ (00h-30h) ........................................................................................................ 14

8.1.2 CACHE READ OPERATIONS .............................................................................................. 15

8.1.3 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 19

8.1.4 READ ID (90h) ...................................................................................................................... 20

8.1.5 READ PARAMETER PAGE (ECh) ....................................................................................... 21

8.1.6 READ STATUS (70h) ........................................................................................................... 23

8.1.7 READ UNIQUE ID (EDh) ...................................................................................................... 25

8.2 PROGRAM operation ......................................................................................................... 26

8.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 26

8.2.2 SERIAL DATA INPUT (80h) ................................................................................................. 26

8.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 27

8.2.4 CACHE PROGRAM (80h-15h) ............................................................................................. 27

8.3 COP Y BACK oper ati on ....................................................................................................... 29

8.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 29

8.3.2 PROGRAM for COPY BACK (85h -10h) ................................................................................ 29

8.4 BLOCK ERASE operation .................................................................................................. 31

8.4.1 BLOCK ERASE (60h-D0h) ................................................................................................... 31

8.5 RESET operation ................................................................................................................ 32

8.5.1 RESET (FFh) ........................................................................................................................ 32

8.6 FEATURE OPERATION..................................................................................................... 33

8.6.1 GET FEATURES (EEh) ........................................................................................................ 36

8.6.2 SET FEATURES (EFh) ......................................................................................................... 37

8.7 ONE TIME PROGRAMMABLE (OTP) area ....................................................................... 38

W29N01GZ/W

Release Date: February 1st, 2016

3 – Revision G

8.7.1 OTP DATA PROGRAM (A0h-10h) ....................................................................................... 38

8.7.2 OTP DATA PROTECT (A5h-10h) ......................................................................................... 40

8.7.3 OTP DATA READ (AFh-30h) ................................................................................................ 41

8.8 WRITE PROTECT .............................................................................................................. 42

8.9 BLOCK LOCK ..................................................................................................................... 44

9. ELECTRICAL CHARACTERISTICS............................................................................................... 45

9.1 Absolute Maximum Ratings ................................................................................................ 45

9.2 Operating Ranges .............................................................................................................. 45

9.3 Device power-up timing ...................................................................................................... 46

9.4 DC Electrical Characteristics .............................................................................................. 47

9.5 AC Measurement Conditions ............................................................................................. 48

9.6 AC timing characteristics for Command, Address and Data Input ..................................... 48

9.7 AC timing characteristics for Operation .............................................................................. 49

9.8 Program and Erase Characteristics ................................................................................... 50

10. TIMING DIAGRAMS ....................................................................................................................... 51

11. INVALID BLOCK MANAGEMENT .................................................................................................. 60

11.1 Invalid blocks ...................................................................................................................... 60

11.2 Initial invalid blocks ............................................................................................................. 60

11.3 Error in operation ................................................................................................................ 61

11.4 Addressing in program operation ....................................................................................... 61

12. REV ISI ON HI ST O RY ...................................................................................................................... 62

W29N01GZ/W

Release Date: February 1st, 2016

4 – Revision G

List of Tables

Table 6-1 Addr es sing( X 8) ........................................................................................................................... 10

Table 6-2 Addr es sing( X 16) ......................................................................................................................... 11

Table 7-1 Mode Selection ........................................................................................................................... 12

Table 8-1 Command Table ......................................................................................................................... 13

Table 9-1 Device ID and configuration codes for Address 00h .................................................................. 20

Table 9-2 ONFI identifying codes for Address 20h ..................................................................................... 20

Table 9-3 Parameter Page Output Va lue .................................................................................................... 22

Table 9-4 Stat us Re gister Bit Def initi on ...................................................................................................... 24

Table 9-5 Features ...................................................................................................................................... 33

Table 9-6 Feature Address 01h .................................................................................................................. 33

Table 9-7 Feature Address 80h .................................................................................................................. 34

Table 9-8 Feature Address 81h .................................................................................................................. 35

Table 10-1 Absolute Maximum Ratings ...................................................................................................... 45

Table 10-2 Operating Ranges ..................................................................................................................... 45

Table 10-3 DC Elect ric al C harac ter ist ic s .................................................................................................... 47

Table 10-4 AC Measurement Conditions .................................................................................................... 48

Table 10-5 AC timing characteristics for Command, Address and Data Input ........................................... 48

Table 10-6 AC timing characteristics for Operation .................................................................................... 49

Table 10-7 Program and Erase Characteristics .......................................................................................... 50

Table 12-1 Valid Block Number .................................................................................................................. 60

Table 12-2 Block failure .............................................................................................................................. 61

Table 16-1 History Table ............................................................................................................................. 62

W29N01GZ/W

Release Date: February 1st, 2016

5 – Revision G

List of Figures

Figure 5-1 NAND Flash Memory Block Diagram .......................................................................................... 9

Figure 6-1 Array Organization(X8) .............................................................................................................. 10

Figure 6-2 Array Organization(X16) ............................................................................................................ 11

Figure 9-1 Page Read Operations .............................................................................................................. 14

Figure 9-2 Sequential Cache Read Operations .......................................................................................... 16

Figure 9-3 Random Cache Read Operation ............................................................................................... 17

Figure 9-4 Last Address Cache Read Operation ........................................................................................ 18

Figure 9-5 Random Data Output ................................................................................................................. 19

Figure 9-6 Read ID ...................................................................................................................................... 20

Figure 9-7 Read Parameter Page ............................................................................................................... 21

Figure 9-8 Read Status Operation .............................................................................................................. 23

Figure 9-9 Read Unique ID ......................................................................................................................... 25

Figure 9-10 Page Progr am.......................................................................................................................... 26

Figure 9-11 Random Data Input ................................................................................................................. 27

Figure 9-12 Cache Program Start ............................................................................................................... 28

Figure 9-13 Cache Program End ................................................................................................................ 28

Figure 9-14 Copy Back Program Operation ................................................................................................ 30

Figure 9-15 Cop y Back Operat ion w ith Ran dom Data Input ....................................................................... 30

Figure 9-16 Block Erase Operation ............................................................................................................. 31

Figure 9-17 Reset Operation....................................................................................................................... 32

Figure 9-18 Get Feature Operation ............................................................................................................. 36

Figure 9-19 Set Feature Operation ............................................................................................................. 37

Figure 9-20 OTP Data Program .................................................................................................................. 39

Figure 9-21 OTP Data Protect .................................................................................................................... 40

Figure 9-22 OTP Data Read ....................................................................................................................... 41

Figure 9-23 Erase Ena bl e ........................................................................................................................... 42

Figure 9-24 Erase Disable .......................................................................................................................... 42

Figure 9-25 Program Enable ....................................................................................................................... 42

Figure 9-26 Program Disable ...................................................................................................................... 43

Figure 9-27 Program for Copy Back Enable ............................................................................................... 43

Figure 9-28 Program for Copy Back Disable .............................................................................................. 43

Figure 10-1 RY/#B Y Beh av ior Dur ing Pow er-On ........................................................................................ 46

Figure 11-1 Command Latch Cycle ............................................................................................................ 51

Figure 11-2 Addres s Latch C ycle ................................................................................................................ 51

Figure 11-3 Data Latch Cycle ..................................................................................................................... 52

Figure 11-4 Serial Access Cycle after Read ............................................................................................... 52

Figure 11-5 Serial Access Cycle after Read (EDO) .................................................................................... 52

Figure 11-6 Read Status Operation ............................................................................................................ 53

Figure 11-7 Page Read Operation .............................................................................................................. 53

Figure 11-8 #CE Don't Care Read Operation ............................................................................................. 54

Figure 11-9 Random Data Output Operation .............................................................................................. 54

Figure 11-10 Cache Read Operation (1/2) ................................................................................................. 55

Figure 11-11 Cache Read Operation (2/2) ................................................................................................. 55

W29N01GZ/W

Release Date: February 1st, 2016

6 – Revision G

Figure 11-12 Read ID .................................................................................................................................. 56

Figure 11-13 Page Program........................................................................................................................ 56

Figure 11-14 #CE Don't Care Page Program Operation ............................................................................ 57

Figure 11-15 Page Program with Random Data Input ................................................................................ 57

Figure 11-16 Copy Back ............................................................................................................................. 58

Figure 11-17 Cache Program...................................................................................................................... 58

Figure 11-18 Block Erase ............................................................................................................................ 59

Figure 11-19 Reset ..................................................................................................................................... 59

Figure 12-1 flow chart of create initial invalid block table ........................................................................... 60

Figure 12-2 Bad block Replacement ........................................................................................................... 61

W29N01GZ/W

Release Date: February 1st, 2016

7 – Revision G

1. GENERAL DESCRIPTION

The W29N01GZ/W (1G-bit) NAND Flash m emor y provides a s torage sol ution f or embedded systems with

limited spac e, pins and pow er. It is ideal for code s hadowing to RAM, solid state applications and storing

media data s uch as, voice, video, tex t and photos. T he device oper ates on a sin gle 1.7V to 1.95V power

suppl y with active curr e nt consumption as low as 25mA and 10uA for CMOS standby current.

The m emory array to tals 138,412, 032 b ytes, and organized into 1,024 eras able block s of 135,168 bytes.

Each block consists of 64 programm able pages of 2, 112-bytes each. Each page consists of 2,048-bytes

for the m ain data storage ar ea and 64-bytes for the s pare data area (T he spare area is t ypica lly used for

error management functions).

The W29N01GZ/W supports the standard NAND flash memory interface using the multiplexed 8-bit bus to

transfer data, addresses, and command instructions. The five control signals, CLE, ALE, #CE, #RE and

#WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write Protect)

and the RY/#BY (Ready/Busy) for monitoring the device status.

2. FEATURES

• Basic Features

– Density : 1Gbit (Single chip solution)

– Vcc : 1.7V to 1.95V

– Bus width : X8 X16

– Operating temperature

 Industrial: - 40°C to 85°C

• Single-Level Cell (SLC) technology.

• Organization

– Density: 1G-bit/128M-byte

– Page size

 2,112 bytes (2048 + 64 bytes)

 1,056 words( 10 24 +32 wor ds )

– Block size

 64 pages (128K + 4K bytes)

 64 pages(64K +2K words)

• Highest Performance

– Read performance (Max.)

 Random read: 25us

 Sequential read cycle: 35ns

– Write Erase performance

 Page program time: 300us(typ.)

 Block erase time: 2ms(typ.)

– Endurance 100,000 Erase/Program

Cycles(1)

– 10-years data retention

• Command set

– Standard NAND command set

– Additional command support

 Sequential Cache Read

 Random Cache Read

 Cache Program

 Copy Back

 OTP Data Program

 OTP Data Lock by Page

 OTP Data Read

– Contact Winbond for block Lock feature

• Lowest power consumption

– Read: 10mA(typ.)

– Program/Erase: 10mA(typ.)

– CMOS standby: 10uA(typ.)

Note:

1. Endurance specification is based on 1bit/528 byte ECC (Erro r Correcti ng Code).

W29N01GZ/W

Release Date: February 1st, 2016

8 – Revision G

3. PIN DESCRIPTIONS

3.1 Chip Enable (#CE)

#CE pi n e nab les and disables de vice operati on. When #CE is hi gh the de v ice is disabled and t he I/O pins

are set t o high im pedance and enter s into sta ndby m ode if not busy. When #CE is set lo w th e dev ice wil l

be enabled, power co nsumption will increase t o active le vels and the d evice is re ady for Read an d W rite

operations.

3.2 Wri t e E nable (#WE)

#WE pin enables the device to control write operations to input pins of the device. Such as, command

instructions, addresses and data that are latched on the rising edge of #WE.

3.3 Read Enable (#RE)

#RE pin controls serial data output from the pre-loaded Data Register. Valid data is present on the I/O bus

after the tREA period from the falling edge of #RE. Column addresses are incremented for each #RE pulse.

3.4 Addres s Latch Enabl e (ALE)

ALE pin con trols addres s i nput to the address reg ister of the dev ice. When AL E is active high, addr esses

are latched via the I/O pins on the rising edge of #WE.

3.5 Comman d Latch Enable (CLE)

CLE pin controls command input to the command register of the device. When CLE is active high,

commands are latched into the command register via I/O pins on the rising edge of #WE.

3.6 Wri t e P rotect (#WP)

#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is active low,

all program/erase operations are disabled.

3.7 Ready/Busy (RY/#BY)

RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is

processing either a program, erase or read operations. When it returns to high, those operations have

completed. RY/#BY pin is an open drain.

3.8 Input and Output (I/Ox)

I/Ox bi-directional pins are used for the following; command, address and data operations.

W29N01GZ/W

Release Date: February 1st, 2016

9 – Revision G

4. BLOCK DIAGR AM

Logic

Control

Status

Command

Resister

Address

High Voltage

Generator

NAND Flash

Array

Row Decoder

Column Decoder

Cache Register

Data Register

I/O

Control

#CE

ALE

CLE

#RE

#WE

#WP

I/Ox

RY/#BY

Figure 5-1 NAND Flash Memory Block Diagram

W29N01GZ/W

Release Date: February 1st, 2016

10 – Revision G

5. ME M O R Y ARRAY ORGANIZATION

5.1 X8 Arra y Org anization

2048

1 block

2112 bytes

Cache register

Data register

Total

1024 blocks

1 page = 2048+64 bytes

1 block = 64 pages

= (128K+4K) bytes

1 device =1024 blocks

= (128M + 4M) bytes

IO0 ~ IO7

Figure 6-1 Array Organization(X8)

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

1st cycle A7 A6 A5 A4 A3 A2 A1 A0

2nd cycle L L L L A11 A10 A9 A8

3rd cycle A19 A18 A17 A16 A15 A14 A13 A12

4th cycle A27 A26 A25 A24 A23 A22 A21 A20

Table 6-1 Addressing(X8)

Notes:

1. “L” indicates a low conditio n, which mu st be held during the address cycle to insure correct processing.

2. A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A27 during the 3rd and 4th cycles are row

addresses.

3. The device ignor es an y additional address inputs that exceed the device’s requirem ent.

W29N01GZ/W

Release Date: February 1st, 2016

11 – Revision G

5.2 X16 Array Organizati on

Figure 6-2 Array Organization(X16)

I/O8~15

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1st cycle L A7 A6 A5 A4 A3 A2 A1 A0

2nd cycle L L L L L L A10 A9 A8

3rd cycle L A18 A17 A16 A15 A14 A13 A12 A11

4th cycle L A26 A25 A24 A23 A22 A21 A20 A19

Table 6-2 Addressing(X16)

NOTE:

1. “L” must to be held Low during the address cycle is inputted

2. A0 to A10 of 1st and 2nd cycle are column address, A11 to A26 of 3rd and 4th cycle are row address

3. The device ignores any additional address input than the device is required

1024

1 block

1056 words

Cache register

Data register

Total

1024 blocks

1 page = 1024+32 words

1 block = 64 pages

= (64K+2K) words

1 device =1024 blocks

= (64M + 2M) words

IO0 ~ IO15

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6. MODE SELECTION TABLE

MODE CLE ALE #CE #WE #RE #WP

Read

mode Command inpu t H L L H X

Address input L H L H X

Write

mode Command inpu t H L L H H

Address input L H L H H

Data input L L L H H

Sequential Read and Data output L L L H X

During read (busy) X X X X H X

During program (busy) X X X X X H

During erase (busy) X X X X X H

Write protect X X X X X L

Standby X X H X X 0V/Vcc

Table 7-1 Mode Selection

Notes:

1. “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” indicates a Don’t Care Level.

2. #WP should be biased to CMOS HIGH or LOW for standby.

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7. COMMAND TABLE

COMMAND 1st CYCLE 2nd CYCLE Acceptable during

busy

PAGE READ 00h 30h

READ for COPY BACK 00h 35h

SEQUENTIAL CACHE READ 31h

RANDOM CACHE READ 00h 31h

LAST ADDRESS CACHE READ 3Fh

READ ID 90h

READ STATUS 70h Yes

RESET FFh Yes

PAGE PROGRAM 80h 10h

PROGRAM for COPY BACK 85h 10h

CACHE PROGRAM 80h 15h

BLOCK ERASE 60h D0h

RANDOM DATA INPUT(1) 85h

RANDOM DATA OUTPUT(1) 05h E0h

READ PARAMETER PAGE ECh

READ UNIQUE ID EDh

GET FEATURES EEh

SET FEATURES EFh

OTP DATA PROTECT

A5h 10h

OTP DATA PROGRAM A0h 10h

OTP DATA READ AFh 30h

Table 8-1 Command Table

Notes:

4. RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page.

5. Any commands that are not in the above table are considered as undefined and are prohibited as inputs.

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8. DEVICE OPERATIONS

8.1 READ operation

8.1.1 PAG E READ (00h-30h)

When the device powers on, the default is READ mode. This operation can also be entered by writing 00h

command to the command register, and then write four address cycles, followed by writing 30h command.

After writing 30h command, the data is transferred from NAND array to Data Register during tR. Data

transfer progress can be done by monitoring the status of the RY/#BY signal output. RY/#BY signal will be

LOW during data transfer. Also, there is an alternate method by using the READ STATUS (70h) command.

If the READ STATUS command is issued during read operation, the Read (00h) command must be re-

issued to r ead out the data from Data Regis ter. When the d ata transf er is complete, RY/#BY signal goes

HIGH, and the data can be read from Data Register by toggling #RE. Read is sequential from initial column

address to the end of the page. (See Figure 9-1)

Figure 9-1 Page Read Operations

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8.1.2 CA CHE READ OPERATIONS

To obtain a higher degree of perf ormance r ead operations, the de vice’s Cache and Data Register can be

used independent of each other. Data can be read out from the Cache Register, while array data is

transferred from the NAND Array to the Data Register.

The CACHE READ mode starts with issuing a PAGE READ command (00h-30h) to transfer a page of data

from NAND array to the Cache Register. RY/#BY signal will go LOW during data transfer indicating a busy

status. Copying the next pa ge of data f rom the NAND array to the Data Register whi le making the Cac he

CACHE READ (00h-31h) command. The SEQUENTIAL CACHE READ mode will copy the next page of

data in sequence from the NAND array to the Data Register or use the RANDOM CACHE READ mode

(00h-31h) to copy a random page of data from NAND array to the Data Register. The RY/#BY signal goes

LOW f or a period of tRCBSY d uring the page data tr ansfer from NAND ar ray to t he Data Register. When

RY/#BY goes HIGH, this means that the Cache Register data is available and can be read out of the Cache

address, a RANDOM DATA OUTPUT (05h-E0h) com mand can be use d to change th e c ol umn address t o

read out the data.

At this po int in the proc edu re when com pleting th e r ead of the des ired num ber of b ytes, one of t wo things

can be chosen. Continue CACHE READ (31h or 00h-31h) operations or end the CACHE READ mode with

a LAST ADDRESS CACHE READ (3Fh) command.

To continue with the read operations, execute the CACHE READ (31h or 00h-31h) command. The RY/#BY

signal goes LOW f or the p e r iod of tRCBSY whi le dat a i s copie d f r om Data R e gister to the Cache Register

and the next page of data starts being copied from the NAND array to the Data Register. W hen RY/#BY

signal goes HIGH signifying that the Cache Register data is available, at this time #RE can start toggling to

output the d esired data star ting at column 0 addr ess or using the RAND OM DATA OUPUT command for

random column address access.

To terminate the C ACH E R EAD o perat ions a LAST A DDRE SS C ACH E R EAD (3F h) com m and is iss ued,

RY/#BY signal goes LOW and the Data Register contents is copied to the Cache Register. At the completion

of the Data Register to Cache Register transfer, RY/#BY goes HIGH indicating data is available at the

output of the Cac h e Reg is t er . At th is point Data can b e r ead by toggling #R E starting at c ol umn address 0

or using the RANDOM DATA OUPUT command for random column address access. The device NAND

array is ready for next command set.

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8.1.2.1. SEQUENTIAL CACHE READ (31h)

The SEQUENTIAL CACHE READ (31h) copies th e nex t page of data in sequence within block to the Data

issuing the command (31h), RY/#BY signal goes LOW and the STATUS REGISTER bits 6 and 5 = “00” for

the period of tRCBSY. When RY/#BY signal goes HIGH and STATUS REGISTER bits 6 and 5 = “10”, data

at the Cache Register is available. The data can be read out from the Cache Register by toggling #RE,

starting address is column 0 or by using the RANDOM DATA OUPUT command for random column address

access.

Figure 9-2 Sequential Cache Read Operations

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8.1.2.2. RANDOM CACHE READ (00h-31h)

The RANDOM CACHE READ (00h-31h) will copy a particular page from NAND array to the Data Register

while the previous page of data is available at the Cache Register output. Perform this function by first

issu ing the 00h comm and to the Command Register, then writing the f our addres s cycles for the desired

page of dat a to the Address Register. T hen write the 31h comm and to the Command Register. Note; the

column address bits are ignored.

After the RANDOM CACHE READ command is issued, RY/#BY signal goes LOW and STATUS REGISTER

bits 6 and 5 equal “00” for the period of tRCBSY. When RY/#BY signal goes HIGH and STATUS REGISTER

bits 6 an d 5 equal “10”, the page data in the Cache Register is a vailable. T he da ta can read out fr om the

Cache Register by toggling #RE, the starting column address will be 0 or use the RANDOM DATA OUTPUT

(05h-E0h) command change the column address to start reading out the data.

Figure 9-3 Random Cache Read Operation

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8.1.2.3. LAST ADDRESS C ACHE READ (3Fh)

The LAST ADDRESS CACHE READ (3Fh) copies a page of data from the Data Register to the Cache

and STATUS REGISTER bits 6 and 5 equals “00” for the period of tRCBSY. When RY/#BY signal goes

HIGH and STATUS REGISTER bits 6 and 5 equals “11”, the Cache Register data is available, and the

device NAND array is in ready state. The data can read out from the Cache Register by toggling #RE,

starting at address column 0 or RANDOM DATA OUTPUT (05h-E0h) command to change the column

address to read out the data.

Figure 9-4 Last Address Cache Read Operation

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8.1.3 RANDOM DA TA OUTPUT (05h-E0h)

The RANDO M DATA OUTPUT allo ws the selection of random colum n addresses to read ou t data fr om a

single or m ultiple of addresses. The us e of the RANDOM D AT A OUT PUT command is available after the

PAGE READ (00h-30h) sequence by writing the 05h command following by the 2 cycle column address

and then the E0h command. Toggling #RE will output data sequentially. The RANDOM DATA OUTPUT

command can be issued multiple times, but limited to the current loade d page.

Figure 9-5 Random Data Output

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8.1.4 REA D ID (90h)

READ ID command is comprised of two modes determined by the input address, device (00h) or ONFI

(20h) ident if ic atio n inf ormation. To ent er t he READ ID mode, write 90h to the C o m mand Register followed

by a 00h address cy cle, then toggle #RE for 5 single byte cycles, the W29N01GZ/W pre-programmed code

includes the Manufac turer ID , Device ID, and Product-Specific Information (see T able 9.1). If the REA D

ID command is f ollowed b y 20h a ddres s , th e output code includes 4 sin gl e byte cycles of O NFI iden tifying

information (see Table 9.2). The device remains in the READ ID mode until the next valid command is

issued.

Figure 9-6 R ead ID

# of

Byte/Cycles 1st

Byte/Cycle 2nd

Byte/Cycle 3rd

Byte/Cycle 4th

Byte/Cycle 5th

Byte/Cycle

X8 EFh A1h 80h 15h. 00h.

X16 EFh B1h 80h 55h 00h

Description MFR ID Device ID Cache

Programming

Supported

Page Size:2KB

Spare Area Size:64b

BLK Size w/o Spare:128KB

Organized:X8 X16

Serial Access:35ns

Table 9-1 Device ID and configuration codes for Address 00h

# of Byte/Cycles 1st

Byte/Cycle 2nd

Byte/Cycle 3rd

Byte/Cycle 4th

Byte/Cycle

Code 4Fh 4Eh 46h 49h

Table 9-2 ONFI identifying codes for Address 20h

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8.1.5 READ PARAMETER PAGE (ECh)

READ PARAMETER PAGE can read out the device’s parameter data structure, such as, manufacturer

information, device organization, timing parameters, key features , and other pertinent de vice parameters.

The data structure is stored with at least three copies in the device’s parameter page. Figure 9-7 sh ow s the

READ PARAMETER PAGE timing. The RANDOM DATA OUTPUT (05h-E0h) command is supported

during data output.

Figure 9-7 R ead Par ameter Page

Byte Description Value

0-3 Parameter page sig natur e 4Fh, 4Eh, 46h, 49h

4-5 Revision number 02h, 00h

6-7 Features

supported W29N01GZ (x8)

W29N01GW (x 16)

10h, 00h

11h, 00h

8-9 Optiona l command s supp orted 37h, 00h

10-31 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h

32-43 Device manufacturer 57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,

20h

44-63 Device model

W29N01GZ (x8) 57h, 32h, 39h, 4Eh, 30h, 31h, 47h, 5Ah, 20h, 20h, 20h,

20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h

W29N01GW( X16) 57h, 32h, 39h, 4Eh, 30h, 31h, 47h, 57h, 20h, 20h, 20h,

20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h

64 Manufacturer ID EFh

65-66 Date code 00h, 00h

67-79 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h

80-83 # of data bytes per page 00h, 08h, 00h, 00h

84-85 # of spare bytes per page 40h, 00h

86-89 # of data bytes per partial page 00h, 02h, 00h, 00h

90-91 # of spare bytes per parti al pa ge 10h, 00h

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Byte Description Value

92-95 # of pages per block 40h, 00h, 00h, 00h

96-99 # of blocks per unit 00h, 04h, 00h, 00h

100 # of logical units 01h

101 # of address cycles 22h

102 # of bits per cell 01h

103-104 Bad blocks maximum per unit 14h, 00h

105-106 Block endurance 01h, 05h

107 Guaranteed valid blocks at beginning of

target 01h

108-109 Block endurance for guaranteed valid

blocks 00h, 00h

110 # of programs per page 04h

111 Partial programming attributes 00h

112 # of ECC bits 01h

113 # of interleaved address bits 00h

114 Interl eav ed operation attribut e s 00h

115-127 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h

128 I/O pin capaci tan ce 0Ah

129-130 Timing mode support 07h, 00h

131-132 Program cache timing 07h, 00h

133-134 Maximum page program time BCh, 02h

135-136 Maximum block erase time 10h, 27h

137-138 Maximum random read time 19h, 00h

139-140 tCCS minimum 46h, 00h

141-163 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h

164-165 Vendor specific revision # 01h,00h

166-253 Vendor specific 00h

254-255 Integrity CRC Set at shipme nt

256-511 Value of bytes 0-255

512-767 Value of bytes 0-255

>767 Additional redundant parameter pages

Table 9-3 Par ameter Page Output Value

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8.1.6 REA D ST ATUS (70h)

The W29N01GZ/W has an 8-bit Status Register which can be read during device operation. Refer to Table

9.3 for specific Status Register definitions. After writing 70h command to the Command Register, read

cycles will only read from the Status Register. The status can be read from I/O[7:0] outputs, as long as #CE

and #RE are LOW. Note; #RE does not need to be toggled for Status Register read. The Command Register

rem ains in s tat us read mode until another command is issued. To c hang e to normal read mode, iss ue th e

PAGE READ (00h) command. After the PAGE READ command is issued, data output starts from the initial

column address.

Figure 9-8 Read Status Operation

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SR bit Page Read Cache Read Page Program Cache

Program Block Erase Definition

I/O 0 Not Use Not Use Pass/Fail Pass/Fail(N) Pass/Fail

0=Successful

Program/Erase

1=Error

in Program/Erase

I/O 1 Not Use Not Use Not Use Pass/Fail(N-1) Not Use 0=Successful

Program

1=Error in Program

I/O 2 Not Use Not Use Not Use Not Use Not Use 0

I/O 3 Not Use Not Use Not Use Not Use Not Use 0

I/O 4 Not Use Not Use Not Use Not Use Not Use 0

I/O 5 Ready/Busy Ready/Busy1 Ready/Busy Ready/Busy Ready/Busy Ready = 1

Busy = 0

I/O 6 Ready/Busy Cache

Ready/Busy2 Ready/Busy Cache

Ready/Busy Ready/Busy Ready = 1

Busy = 0

I/O 7 Write P rotect Write Protect W rite Protect Write P rotect Write Protect Unprotected = 1

Protected = 0

Table 9-4 Status Register Bit Def ini ti on

Notes:

1. SR bit 5 is 0 during the actual programming operation. If cache mode is used, this bit will be 1 when all internal

operation s are complete.

2. SR bit 6 is 1 when the Cache Register is ready to accept new data. RY/#BY follows bit 6.

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8.1.7 REA D UNIQUE ID (EDh)

The W29N01GZ/W NAND Flash device has a method to uniquely identify each NAND Flash device by

using the R EAD UN IQU E ID com m and. T he form at of th e ID is lim itles s, but the ID f or ever y NAND Flash

device manufactured, will be guaranteed to be unique.

Numerous NAND controllers typically use proprietary error correction code (ECC) schemes. In these cases

Winbond cannot protect unique ID data with factory programmed ECC. However, to ensure data reliability,

Winbond will program the NAND Fl ash de vices wit h 16 b ytes of unique ID code, starting at b yte 0 on the

page, immediately followed by 16 bytes of the complement of that unique ID. The combination of these two

actions is then r epeated 1 6 tim es. T his means the f inal cop y of the unique ID will resides a t location byte

511. At t his poin t an XOR or exc lusive op eration can be performed on the firs t copy of the uni que ID and

its complement. If the un ique ID is good, the r es ults s hou ld yield all the bits as 1s. In t he event th at any of

the bits are 0 after the XOR operation, the procedure can be repeated on a subsequent copy of the unique

ID data.

Figure 9-9 Read Unique ID

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8.2 PROGRAM operation

8.2.1 PAGE PROGRAM (80h-10h)

The W29N01GZ/W Page Program command will program pages sequentially within a block, from the lower

order pag e ad dres s to higher order page addres s . Program ming pages out of s equenc e is pr o hi bit ed. The

W29N01GX supports partial-page programming operations up to 4 times before an erase is required if

partitioning a page. Note; programming a single bit more than once without first erasing it is not supported.

8.2.2 SERIAL DA TA INPUT (8 0h)

Page Program operation starts with the execution of the Serial Data Input command (80h) to the Command

Register, f ollo wing next by i nputting f our ad dres s cycle s and t hen t h e d ata is l oad ed. Serial dat a is loaded

to Cache Register with each #WE cycle. The Program command (10h) is written to the Command Register

after the serial data inpu t is finished. At this time the inter nal write state controller autom atically executes

the algorithms for program and verifies operations. Once the programming starts, determining the

completion of the program process can be done by m onitoring the RY/#BY out put or the Status Register

Bit 6, which will follow the RY/#BY signal. RY/#BY will stay LOW during the internal array programming

operation during the period of (tPROG). During page program operation, only two commands are available,

READ STATU S (7 0h) and RESET (FFh). When the dev ice s tatus go es to the ready state, Status Register

Bit 0 (I/O0) indicates whether the progr am operati on passed (Bit0=0) or failed (Bit0=1), (s ee F igure 9-10).

The Command Register remains in read status mode until the next command is issued.

Figure 9-10 Pa ge Progr am

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8.2.3 RA NDO M DA TA INPUT ( 85h)

After the Pa ge Progr am (80h) ex ecut ion of the init ial dat a has been loaded into t he Cache Regist er, if the

need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command can

perform this func tion to a new colum n address prior to the Pro gram (10h) comm and. The RANDOM Data

INPUT command can be issued multiple times in the same page (See Figure 9-11).

Figure 9-11 Random Data Input

8.2.4 CACHE PRO GRAM (80h-15h)

CACHE PROGEAM (80h) command is started by writing the command to the Command Register. The next

writes sho uld be f our c ycles of address, and then eith er writing a full or partial page of input data into the

Cache Register. Issuing the CACHE PROGRAM (15h) command to the Command Register, starting

transferring data from the Cache Register to the Data Register on the rising edge of #WE and RY/#BY will

go LOW. Programming to the array starts after the data has been copied into the Data Register and RY/#BY

returns to HIGH.

When RY/#BY returns to HIGH, the next input data can be written to the Cache Register by issuing another

CACHE PROGRAM command series. The time RY/#BY goes LOW, is typical controlled by the actual

programming time. The time for the first programming pass equals the time it takes to transfer the data from

the Cache Register to the Data Register. On the second and subsequent programming passes, data

transfer from t he Cache Register to t he Data Regist er is held unti l Data Register content is program ming

into the NAND array.

The CACHE PROGRAM command can cross block address boundaries. RANDOM DATA INPUT (85h)

commands are permitted with CACHE PROGRAM operations. Status Register’s Cache RY/#BY Bit 6 (I/O6)

can be read after issui ng the REA D STATUS (70 h) comm and for conf irm ing when th e Cache Reg ister is

ready or busy. RY/#BY, alw ays fol lows Status Register Bit 6 (I/O6). Status Regis ter’s R Y/#BY Bit 5 ( I/O5)

can be polled to determine whether the array programming is in progress or completed for the current

programming cycle.

If only RY/#BY is used for detecting programming status, the last page of the program sequence must use

the PAGE PROGRA M (10 h) c omm and instead of the CACH E PROG RAM (1 5h) comm and. If the CACH E

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PROGRAM (15h) command is used every time, including the last page programming, Status Register’s Bit

5 (I/O5) must be used to determine when programming is complete.

Status Register’s Pass/Fail, Bit 0 (I/O0) returns the pass/fail status for the previous page when Status

is return ed with Status Reg ister’s Bit 0 (I/O0) when Bit 5 (I/O5) of the Status Register equals a “1” (ready

state) as shown in Fi gur e 9 -12 and 9-13.

Note: The CACHE PROGRAM command cannot be used on blocks 0-3 if used as boot blocks.

Figure 9-12 Cache Program Start

Figure 9-13 Cache Program End

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8.3 COPY B ACK operation

Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h) command

first, then the PROGRAM for COPY BACK (85h-10h) c ommand.

8.3.1 REA D for COPY BACK (00 h-35h)

The READ for COPY BACK command is used together with the PROGRAM for COPY BACK (85h-10h)

command. To start execution, READ for COPY BACK (00h) command is written to the Command Register,

followed by the four cycles of the source page address. To start the transfer of the selected page data from

the memory array to the Cache Register, write the 35h command to the Command Register.

After execution of the RE AD for COPY BACK comm and sequence and RY/#BY returns to HIGH m arking

the completion of the operation, the transferred data from the source page into the Cache Register may be

read out by toggling #RE. Data is output sequentially from the column address that was originally specified

with the READ for COPY BACK command. RANDOM DATA OUTPUT (05h-E0h) commands can be issued

multiple times without any limitation after READ for COPY BACK command has been executed (see Figures

9-14 and 9-15).

At this point the device is in ready state to accept the PROGRAM for COPY BACK command.

8.3.2 PROG RAM for COPY BACK (85h-10h)

After the READ for COPY BACK command operation has been completed and RY/#BY goes HIGH, the

PROGRAM for COPY BACK command can be written to the Command Register. The command results in

the transfer of data from the Cache Register to the Data Register, then internal operations start

programm ing of the new des tination page. T he sequenc e would be, writ e 85h to the Comm and Register,

followed by the four cycle destination page address to the NAND array . Next write the 10h command to the

Command Register; this will signal the int ernal control l er to automatically st art to program the data to new

destination page. During this programming time, RY/#BY will go LOW. The READ STATUS command can

be used inste ad of the R Y/#B Y signa l to det erm ine when the progr am is com plete. When Status Register

Bit 6 (I/O6) equals to “1”, Status Re gis ter Bit 0 (I/O0) w i ll indicate if the operation was successful or not.

The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for COPY BACK

command for modifying the original data. Once the data is copied into the Cache Register using the READ

for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h) command, along

with th e address of the data to be changed. The data to be ch anged is placed on the ex ternal data pins.

This operation copies the data into the Cache Register. Once the 10h command is written to the Command

the new page commences. The RANDOM DATA INPUT command can be issued numerous times without

limitation, as necessary before starting the programming sequence with 10h command.

Since COP Y BACK oper ations do not use external m emor y and the data of sour ce page m ight include a

bit errors, a competent ECC scheme should be developed to check the data before programming data to a

new destination page.

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Figure 9-14 Copy Back Program Operation

Figure 9-15 Copy Back Operation with Random Data Input

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8.4 BLOCK E RASE operation

8.4.1 BLOCK ERASE (60h -D0h)

Erase oper ations happe n at t he architectural block unit. T his W29N01GZ/W has 1024 erase block s. Eac h

block is organized into 64 pages (2112 bytes/page,1056words/page), 132K bytes (128K + 4K

bytes)/block,66Kwords(64K+2K words)/block The BLOCK ERASE command operates on a block by block

basis.

Erase Setup command (60h) is written to the Command Register. Next, the two cycle block address is

written to the device. The page address bits are loaded during address block address cycle, but are ignored.

The Erase Confirm command (D0h) is written to the Command Register at the rising edge of #WE, RY/#BY

goes LO W and the internal controller automatically handles the block erase sequence of operation. RY/#BY

goes LOW during Block Erase internal operations for a period of tBERS,

The READ STATUS (70h) command can be used for confirm block erase status. When Status Register

Bit6 (I/O6) becomes to “1”, block erase operation is finished. Status Register Bit0 (I/O0) will indicate a

pass/fail condition (see Figure 9-16).

Figure 9-16 Block Erase Operation

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8.5 RESET operation

8.5.1 RESET (FFh)

READ, PROGRAM, and ERASE commands can be aborted by the RESET (FFh) command during the time

the W29N01GZ/W is in the busy state. The Res et oper atio n puts the device into a k nown status . T he data

that is processed in either the programming or erasing operations are no longer valid. This means the data

can be partially programmed or erased and therefore data is invalid. The Command Register is cleared and

is ready to accept next command. The Data Register a nd Cache Register contents are marked invalid.

The Status R egister indicates a value of E0h when #WP is HIGH; oth erwise a value of 60h when #W P is

LOW. After R ESET command is written t o t he command reg ister , RY/#BY goes LOW for a period of tRST

(see Figure 9-17).

Figure 9-17 Reset Operation

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8.6 FEATURE OPERATION

The G ET FEAT UR ES ( E Eh ) a nd S ET FEAT UR E S (EFh) com mands are used to change the NA ND F lash

device b ehavior from the default po wer on settings. T hese comm ands use a one-byte featur e address to

determine which feature is to be read or modified. A range of 0 to 255 defines all features; e ach is described

in the features table (see Table 9.4 thru 9.7). The GET FEATURES (EEh) command reads 4-Byte

parameter in the features table (See GET FEATURES function). The SET FEATURES (EFh) command

places the 4-Byte parameter in the features table (See SET FEATURES function).When a feature set is

volatile, meaning it remains active by default until the device is powered of f. The set feature remains the

set even if a RESET (FFh) command is issued.

Feature address Description

00h N.A

01h Timing mo d e

02h-7Fh Reserved

80h Vendor specific par ameter : Programmable I/O drive strength

81h Vendor specific parameter : Programmable RY/#BY pull-down strength

82h-FFh Reserved

Table 9-5 Features

Feature Address 01h: Timing Mode

Sub feature

parameter

Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

Timing mode Mode 0 (default) Reserved (0) 0 0 0 00h 1

Mode 1 Reserved (0) 0 0 1 01h 1

Mode 2 Reserved (0) 0 1 0 02h 1

Mode 3 Reserved (0) 0 1 1 03h 2

Mode 4 Reserved (0) 1 0 0 04h 2

Mode 5 Reserved (0) 1 0 1 05h 2

Reserved (0) 00h

Table 9-6 Feature Address 01h

Notes:

1. Timing mode is set to mode 0 by default. The tim ing mode should be selected to indicate the maximum speed at

which the device will receive addresses, commands, and data cycles. The five supported settings for the timing

mode are shown. The device returns to mode 0 when a power cycle has occurred. Supported timing modes are

reported in the parameter page.

2. Not supported.

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Feature Address 80h: Programmable I/O Drive Strength

Sub feature

parameter

Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

I/O

drive strength

Full (default) Reserved (0) 0 0 00h 1

Three-quarters Reserved (0) 0 1 01h

One-half Reserved (0) 1 0 02h

One-quarter Reserved (0) 1 1 03h

Reserved (0) 00h

Table 9-7 Feature Address 80h

Note:

1. The default drive strength setting is Full st reng th. The P rog ram mab le I/O Drive Strength mode is used to change

from the default I/O drive strength. Drive strength should be selected based on expected loading of the memory

bus. This table shows the four supported output drive-strength settings. The device returns to the default drive

strength mode when a po wer cycle has occurred. AC timing parameters may need to be relaxed if I/O drive strength

is not set to full.

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Feature Address 81h: Programmable RY/#BY Pull-down Strength

Sub feature

parameter

Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

RY/#BY

pull-down

strength

Full (default) Reserved (0) 0 0 00h 1

Three-quarters Reserved (0) 0 1 01h

One-half Reserved (0) 1 0 02h

One-quarter Reserved (0) 1 1 03h

Reserved (0) 00h

Table 9-8 Feature Address 81h

Note:

1. The default programmable RY/#BY pull-down strength is set to Full strength. The pull-down strength is used to

change the RY/#BY pull-down stre ngth. RY/#BY pull-down strength should be se lected based o n expected l oading

of RY/#BY. The four suppor te d pull-down strength settings are shown. The device returns to the default pull-down

strength when a power cycle has occurred.

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8.6.1 GET FEATUR ES ( EEh)

The GET FEAT URES command returns the device feature settings including those previously set by the

SET FEATURES command. To use the Get Feature mode write the command (EEh) to the Command

If Read Status (70h) command is issued for monitoring the process completion status, Read Command

(00h) has to be executed to re-establish data ou tput m ode. Once, R Y/#BY goes HIG H, the device feature

settings can be read by toggling #RE. The device remains in Feature Mode until another valid command is

issued to Command Register. See Figure 9-18.

Figure 9-18 Get Feature Operation

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8.6.2 SET FEATURES (EFh)

The SET FEATURES command sets the behavior parameters by selecting a specified feature address. To

change device behavioral parameters, execute Set Feature command by writing EFh to the Command

rising edge of each #WE. The RY/#BY signal will go LOW during the period of tFEAT while the four feature

parameters are stored. The Read Status (70h) command can be issued for monitoring the progress status

of this operation. The parameters are stored in device until the device goes through a power on cycle. The

device remains in feature mode until another valid command is issued to Command Register.

Figure 9-19 Set Feature Operation

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8.7 ONE TIME PROGRAMMABLE (OTP) area

The device has One-Time Programmable (OTP) memory area comprised of ten pages (2112 bytes/page).

This entire range of pages is functionally guaranteed. Only the OTP commands can access the OTP area.

When the device ships from Winbond, the OTP area is in an erase state (all bits equal “1”). In the OTP

area, programming or partial-page programming is done only by programming “0” bits. The OTP area

cannot be erased, therefore protecting the area only prevent further programming.

OTP area progr amm ing an d prot ection h ave t wo se par ate commands. T he O TP D ATA PR OGR AM (A0h-

10h) com mand is used to program an OT P page. Programming an entire page as one o peration or up to

four partial-page programming sequences is available. Programming other OTP pages can be done in the

same way. The OTP DATA PROTECT (A5h-10h) command will permanently protected the OTP area from

further programming operations. The OTP DAT A RE A D c om mand (AFh-30 h) c an r ead th e O T P ar ea with

or without protection set. Note; there is no erase command for OTP area.

8.7.1 OTP DATA PROGRAM (A0h-10h)

Programming the OTP area can be done using the OTP DATA PROGRAM (A0h-10h) command. An entire

page can be programmed at once or up to four partial page programming sequences per page.

This command enables programming into the offset of an OTP page by using the two bytes of Column

Address [1 1:0]. If OT P area is protec ted by OTP DAT A PROTECT command, th e programm ing the OTP

area will not be executed, and RY/#BY goes LOW for a period of tOBSY.

To us e this com mand s equence, the A0h com mand is written t o Command Register. T hen iss ue the four

address cycles that are column address of first two cycles and range page address[0B:02] of the two

remaining cycles. Then wri t e 1 to 21 12 bytes of data, followed by pr ogram conf irm ation c ommand (10h) is

written to Command Register. At this point the internal controller automatically executes the algorithms for

program and verify. The RY/#BY will go LOW during the program execution for the period of (tPROG).

Program verification only detects 1’s that are not successfully programmed to 0’s.

If OTP area is not protected, RANDOM DATA INPUT commands can be used during OTP program

operations.

READ STATUS (70h) command is valid during the OTP program operation. For this operation, Status

protected, Status Register Bit7 (I/O7) will equal “0”; otherwise it is a “1”. After the device is in the ready

state, Status Register Bit0 (I/O0) indicates whether the operation passed or failed.

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Figure 9-20 OTP Data Program

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8.7.2 OTP DATA PROTECT (A5h-10h)

To protect the data in OTP area used the OTP DATA PROTECT (A5h-10h) command. After the OTP area

is protecte d, th e OTP area c annot be unprotected and no additio nal data c an be programmed to the O T P

area.

To us e this c omm and, A5h is wri tten to th e Com m and Register . T hen iss ues t he f our addres s c ycles with

the following address code: 00h-00h-01h-00h. Finalized by writing the protect confirmation command (10h)

to the Command Register. The RY/#BY signal w il l go LOW during this protection proc ess , a per iod similar

with page program time (tPROG).

READ STATUS (70h) command is valid during the OTP protect operation. For this operation, Status

go to the ready state, Status Register Bit0 (I/O0) indicates whether the operation passed or failed.

Figure 9-21 OTP Data Protect

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8.7.3 OTP DATA READ (AFh-30h)

This c ommand can r ead th e data from OTP pages. The read capability fr om OTP area is av ai la ble with or

without OTP area protection.

To use this command sequence, AFh command is written to Command Register. T hen issue four address

cycles comprised of the column address (first two cycles) and the range page address [0B:02] for the

remaining two cycles. Once the address is written, perform the read confirmation command (30h) to the

Comm and Register. The RY/#BY s ignal wil l go LOW while the OTP dat a is transferred f rom OT P area to

Data Register during the period of (tR). The RANDOM DATA OUTPUT command can use during OTP data

read operations. Read timing of OTP data read is the same as the typical PAGE READ timing.

READ STATUS and RESET command are valid during OTP data read operation. For this operation, Status

pages can be read by repeating OTP DATA READ command.

If OTP DATA READ command is followed by CACHE READ operation, the RESET command has to be

executed prior to issuing the CACHE READ commands. RESET time can be up to 5µs.

Figure 9-22 OTP Data Read

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8.8 WRITE PROTECT

#W P pin can e nable or disable pr ogram and erase com mands prev enting or allowing program and erase

operations. Figure 9-23 to 9-28 shows the enabling or disa bling tim ing with #WP setup tim e (tWW) that is

from rising or falling edge of #WP to latch the first commands. After first command is latched, #WP pin must

not toggle unt il the command operati on is complete and t he device is in the ready state. (Status Register

Bit5 (I/O5) equal 1.

Figure 9-23 Er ase Ena bl e

Figure 9-24 Erase Disable

Figure 9-25 Program Enable

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Figure 9-26 Program Disable

Figure 9-27 Program for Copy Back Enable

Figure 9-28 Program for Copy Back Disable

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8.9 BLOCK LO CK

The device has block lock feature that can protect the entire device or user can indicate a ranges of blocks

from program and erase operations. Using this feature offers increased functionality and flexibility data

protection to prevent unexpected program and erase operations. Contact to Winbond for using this feature.

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9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Rat ings

PARAMETERS SYMBOL CONDITIONS RANGE UNIT

Suppl y Voltage VCC –0.6 to +2.4 V

Voltage Applied to Any Pin VIN Relative to Ground –0.6 to +2.4 V

Storage Temperature TSTG –65 to +150 °C

Short circuit output current, I/Os 5 mA

Table 10-1 Absolute Maximum Ratings

Notes:

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, t his level may undershoot t o -2.0V for periods

<30ns.

2. Maximum DC voltage on input/output pins is Vcc+0.3V which, during transitions, may overshoot to Vcc+ 2.0V for

periods <20ns.

3. This device has been designed and tested for the specified operation ranges. Proper operation outside of these

levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond

absolute maximum rating s ma y cause permanent damage.

9.2 Op erat ing Ranges

PARAMETER SYMBOL CONDITIONS SPEC UNIT

MIN MAX

Suppl y Voltage VCC 1.7 1.95 V

Ambient Temperature,

Operating TA Industrial -40 +85 °C

Table 10-2 Operating Ranges

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9.3 Device p ower-up timing

The device is designed to avoid unexpected program/erase operations during power transitions. When the

device is powered on, the system has to wait until the ready state. #WP is recommended to VIL for

preventing unexpected Program and Erase operations during power-transition until Vcc is stable. The

RY/#BY will become val id afte r 50µs from the V cc ramp start, and at least 10µs after Vcc reaches minimum

Vcc level. The first command has to be a RESET command after the device is powered on. Before issuing

RESET command, the system has to wait until the RY/#BY goes HIGH, or wait at least 100µs after Vcc

reaches minimum Vcc. After issuing the RESET command, the busy time is 1ms maximum. RY /#B Y po lling

or READ STATUS command can monitor the reset busy period. After completing this procedure, the device

is initialized and ready for the operation (See Figure 10-1).

Figure 10-1 RY/#BY Beh avior Dur ing Power -On

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9.4 DC Electrical Characteristics

PARAMETER SYMBOL CONDITIONS SPEC UNIT

MIN TYP MAX

Sequential Read current Icc1

tRC= tRC MIN

#CE=VIL

IOUT=0mA - 10 25 mA

Program current Icc2 - - 10 25 mA

Erase current Icc3 - - 10 25 mA

Standby current (TTL) ISB1 #CE=VIH

#WP=0V/Vcc - - 1 mA

Standby current (CMOS) ISB2 #CE=Vcc – 0.2V

#WP=0V/Vcc - 10 50 µA

Input l eakage current ILI VIN= 0 V to Vcc - - ±10 µA

Output leakage cur rent ILO VOUT=0V to Vcc - - ±10 µA

Input hi gh voltage VIH I/O7~0, #CE,#WE,#RE,

#WP,CLE,ALE 0.8 x Vcc - Vcc + 0.3 V

Input l ow voltage VIL - -0.3 - 0.2 x Vcc V

Output high voltage(1) VOH IOH=--100µA Vcc-0.1 - - V

Output low voltag e(1) VOL IOL=100µA - - 0.1 V

Output low curr ent IOL(RY/#BY) VOL=0.2V 3 4 mA

Table 10-3 DC Electrical C har ac teris t ics

Note:

1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.

2. IOL (RY/#BY) may need to be relaxed if RY/#BY pull-down stre ngth is not se t to ful l

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9.5 AC Measurement Conditions

PARAMETER SYMBOL SPEC UNIT

MIN MAX

Input Capacitance(1), (2) CIN - 10 pF

Input/Output Capacitance(1), (2) CIO - 10 pF

Input Rise and Fall Times TR/TF - 5 ns

Input Pulse Voltages - 0 to VCC V

Input/Output timing Voltage - Vcc/2 V

Output load (1) CL 1TTL GATE and CL=30pF -

Table 10-4 AC Measurement Conditions

Notes:

1. Veri fi ed on device characterization , not 100% tested

2. Test conditi o ns TA=25’C, f=1M Hz, VIN=0V

9.6 AC timing characteri stics for Command, Address and Dat a Input

PARAMETER SYMBOL SPEC UNIT

MIN MAX

ALE to Data Loading Time tADL 100 - ns

ALE Hold Ti m e tALH 10 - ns

ALE setup T ime tALS 15 - ns

#CE Hold Time tCH 10 - ns

CLE Hold Ti m e tCLH 5 - ns

CLE set up Time tCLS 15 - ns

#CE setup Time tCS 25 - ns

Data Hold Time tDH 5 - ns

Data setup Time tDS 15 - ns

Write Cycle Time tWC 35 - ns

#WE Hi gh Hold Time tWH 15 - ns

#WE Pulse Width tWP 17 - ns

#WP s etup Time tWW 100 - ns

Table 10-5 AC timing characteristics for Command, Address and Data Input

Note:

1. tADL is the time from the #WE rising edge of final address cycle to the #WE rising edge of first data cycle.

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9.7 AC timing characteristics for Op eration

PARAMETER SYMBOL SPEC UNIT

MIN MAX

ALE to #RE Delay tAR 10 - ns

#CE Access Time tCEA - 30 ns

#CE HIGH to Output High-Z(1) tCHZ - 45 ns

CLE to #RE Delay tCLR 10 - ns

#CE HIGH to Output Hold tCOH 15 - ns

Cache Bus y in Cache Read mode tRCBSY 3 tR µs

Output High-Z to #RE LOW tIR 0 - ns

Data Transfer from Cell to Data Register tR - 25 µs

READ Cycle Time tRC 35 - ns

#RE Access Time tREA - 25 ns

#RE HIGH Hold Time tREH 15 - ns

#RE HIGH to Output Hold tRHOH 15 - ns

#RE HIGH to #WE LOW tRHW 100 - ns

#RE HIGH to Output High-Z(1) tRHZ - 100 ns

#RE LOW to output hold tRLOH 5 - ns

#RE Pulse Width tRP 17 - ns

Ready to #RE LOW tRR 20 - ns

Reset Time (READ/PROGRAM/ERASE)(2) tRST - 5/10/500 µs

#WE HIGH to Busy(3) tWB - 100 ns

#WE HIGH to #RE LOW tWHR 80 - ns

Table 10-6 AC timing characteristics for Operation

Notes: AC characteristics may need to be relaxed if I/O drive strength is not set to “full.”

1. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100 %

tested

2. The first time the RESE T (FFh ) command is issu ed while th e device is idle, the device will go busy for a maximum

of 1ms. Thereafter, the device goes busy for a maximum of 5μs.

3. Do not issue new command during tWB, even if RY/#BY is ready.

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9.8 Program and Erase Charact eristics

PARAMETER SYMBOL SPEC UNIT

TYP MAX

Number of partial page programs NoP - 4 cycles

Page Pro gram time tPROG 300 700 µs

Busy Tim e for Cache program (1) tCBSY 3 700 µs

Busy Time for SET FEATURES /GET FEATURES tFEAT - 1 µs

Busy Tim e for progr am /erase at locked bl ock tLBSY - 3 µs

Busy Tim e for OTP program when OTP is protected tOBSY - 30 µs

Block Erase Time tBERS 2 10 ms

Last Page Program time (2) tLPROG - - -

Table 10-7 Program and Erase Characteristics

Note:

1. tCBSY maximum time depends on timing between internal program complete and data-in.

2. tLPROG = Last Page program time (tPROG) + Last -1 Pag e prog ram tim e (tP ROG) – Last page Address, Command

and Data load time.

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10. TIMING DIAGRAMS

Figure 11-1 Command Latch Cycle

Figure 11-2 Address Latch Cycle

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Figure 11-3 Data Latch Cycle

Note:

1. Din Final = 2,111(x8)

Figure 11-4 Serial Access Cycle after Read

Figure 11-5 Serial Access Cycle after Read (EDO)

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Figure 11-6 Read Status Operation

Figure 11-7 Page Read Operation

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Figure 11-8 #CE Don't Care Read Operation

Figure 11-9 Random Data Output Operation

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Figure 11-10 Cache Read Operation (1/2)

Figure 11-11 Cache Read Operation (2/2)

Note:

1. See Table 9.1 for actual value.

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Figure 11-12 Read ID

Figure 11-13 Page Pro gr a m

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Figure 11-14 #CE Don't Care Page Program Operation

Figure 11-15 Page Program with Random Data Input

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Figure 11-16 Copy Back

Figure 11-17 Cache Program

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Figure 11-18 Block Erase

Figure 11-19 Reset

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11. INVALID BLOCK MANAGEMENT

11.1 Invalid blocks

The W29N01GZ/W may have initial invalid blocks when it ships from factory. Also, additional invalid blocks

may devel op dur ing t he use of the device. Nvb represents the minimum num ber of valid bl ocks in the total

number of available blocks (See Table 12.1). An invalid block is defined as blocks that contain one or more

bad bits. Block 0, block address 00h is guaranteed to be a valid block at the time of shipment.

Parameter Symbol Min Max Unit

Valid block number Nvb 1004 1024 blocks

Table 12-1 Valid Block Number

11.2 Initial invalid blocks

Initial invalid blocks are defined as blocks that contain one or more invalid bits when shipped from factory.

Although the device contains initial invalid blocks, a valid block of the device is of the same quality and

reliabili ty as all valid bl ocks in the device with referenc e to AC and D C specif ications. The W29N01GZ/W

has intern al circ uits to isolate eac h bl ock f rom other bl ocks and therefore, the in valid block s will not affect

the performance of the entire device.

Before the device is shipped from the factory, it will be erased and invalid blocks are marked. All initial

invalid blocks are marked with non-FFh at the first byte of spare area on the 1st or 2nd page. The initial

invalid block information cannot be recovered if inadvertently erased. Therefore, software should be created

to initially check for invalid blocks by reading the marked locations before performing any program or erase

operation, and create a table of initial invalid blocks as following flow chart

Figure 12-1 flow chart of create initial invalid block table

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11.3 Error in operation

Addition al inv al id b locks may develo p in t he de v ic e du ring its lif e cycle. Follo wing the procedures herein is

required to guarantee reliable data in the device.

After each program and erase operation, check the status read to determine if the operation failed. In case

of failure, a block replacement should be done with a bad-block management algorithm. The sy stem has to

use a minimum 1-bit ECC per 528 bytes of data to ensure data recovery.

Operation Detection and recommended procedure

Erase Status read after erase  Block Replacement

Program Status read after program  Block Replacement

Read Ver ify ECC  ECC correction

Table 12-2 Block failure

Figure 12-2 Bad block Replacement

Note:

1. An error happens in the nth page of block A during program or erase operation.

2. Cop y the data in block A to the same location of block B which is valid block.

3. Copy the nth page data of block A in the buffer memory to the nth page of block B

4. Creating or updating bad block table for preventing furth er program or erase to block A

11.4 Addressin g in pr ogr am operation

The pages withi n th e bl ock have to be pro gr am med sequentially from the lo wer or der pag e a ddr ess to th e

higher ord er pa ge addr ess w ith in the block. The lower or der pa ge is defined as th e s tar t p age to pr ogram,

does not need to be page 0 in the block. Random page programming is prohibited.

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12. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

A 10/22/2013 New Create Preliminary

B 10/25/2013 Correct typo

C 12/24/2013 52

tRCBSY : max 3us -> max tR

OTP : ONFI OTP

Remove commercial grade

D 08/07/2014 -

41 W29N01Gx  W29N01GZ/W

OTP : Legacy OTP

E 08/08/2014 65, 66 Update Ordering Part Number

F 11/07/2014 Remove “Advanced Information”, “Preliminary”

G 02/01/2016 23, 47 Update Parameter Page Output Value

Update Notes of Absolute Maximum Ratings

09/07/2016 Modified for MCP Combo Datasheet.

Table 16-1 History Table

Trademarks

Winbond is trademark of Winbond Electronics Corporation.

All other marks are the property of their respective owner.

Important Notice

W inbond pr oducts ar e not des ig ned, int end ed, a uth or i zed or war ranted for us e as c om ponents i n systems

or equipm ent intend ed for sur gical im plantation, atom ic energ y control instr uments, airplane or s paceship

instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for

other app licatio ns int ended to sup port or s ustain lif e. Further m ore, W inbond pro duc ts are not intend ed for

applications wherein failure of Winbond products could result or lead to a situation where in personal injury,

death or severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their own risk and

agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

W97AH6KK / W97AH2KK

LPDDR2-S4B 1Gb

Publication Release Date: May 22, 2014

Revision: A01-001

- 1 -

Table of Contents-

1. GENERAL DESCRIP TION ............................................................................................................................................ 6

2. FEATURES .................................................................................................................................................................... 6

3. PAD DESCRIPTION ...................................................................................................................................................... 7

3.1 Bas ic Functionality ......................................................................................................................................................... 7

3.2 Addressing Table ........................................................................................................................................................... 8

4. BLOCK DIAGRAM ......................................................................................................................................................... 9

5. FUNCTIONAL DESCRIPTION ..................................................................................................................................... 10

5.1 Simplified LPDDR2 State Diagram .............................................................................................................................. 10

5.1.1 Simpl ifi ed LPDDR2 Bus Interface St at e Diagram ......................................................................................................... 11

5.2 Power-up, Initialization, and Power-Off ........................................................................................................................ 12

5.2.1 Power Ramp and Device Initialization .......................................................................................................................... 12

5.2.2 Timing Parameters for Initialization .............................................................................................................................. 14

5.2.3 Power Ramp and Initialization Sequence .................................................................................................................... 14

5.2.4 Initi alizat i on aft er Reset (without Power ram p) ............................................................................................................. 15

5.2.5 Power-off Sequenc e .................................................................................................................................................... 15

5.2.6 Timing Parameters Power-Off ..................................................................................................................................... 15

5.2.7 Uncontrolled Power-Off Sequence .............................................................................................................................. 15

5.3 Mode Register Definition .............................................................................................................................................. 16

5.3.1 Mode Register Assignm ent and Definition ................................................................................................................... 16

5.3.1.1 Mode Regist er Assi gnm ent ............................................................................................................................... 16

5.3.2 MR0_Device Inform at i on (MA[7: 0] = 00H) ................................................................................................................... 17

5.3.3 MR1_Device Feature 1 (MA[7:0] = 01H) ...................................................................................................................... 17

5.3.3.1 Burs t Sequence by Burst Lengt h (BL), Burst T ype (BT), and Warp Control (WC) .............................................. 18

5.3.3.2 Non Wrap Restrictions ...................................................................................................................................... 18

5.3.4 MR2_Device Feature 2 (MA[7:0] = 02H) ...................................................................................................................... 19

5.3.5 MR3_I/O Configuration 1 (MA[7:0] = 03H) ................................................................................................................... 19

5.3.6 MR4_Device Tem perature (MA[ 7:0] = 04H) ................................................................................................................. 19

5.3.7 MR5_Basic Confi gurat i on 1 (MA[7:0] = 05H) ............................................................................................................... 20

5.3.8 MR6_Basic Confi gurat i on 2 (MA[7:0] = 06H) ............................................................................................................... 20

5.3.9 MR7_Basic Confi gurat i on 3 (MA[7:0] = 07H) ............................................................................................................... 20

5.3.10 MR8_Basic Confi gurat i on 4 (MA[7:0] = 08H) ............................................................................................................... 20

5.3.11 MR9_Test Mode (MA[7: 0] = 09H) ................................................................................................................................ 20

5.3.12 MR10_Calibration (MA[7:0] = 0AH) ............................................................................................................................. 21

5.3.13 MR16_PASR_Bank Mask (MA[ 7:0] = 10H) .................................................................................................................. 21

5.3.14 MR17_PASR_Segm ent Mask (MA[7:0] = 11H) ............................................................................................................ 22

5.3.15 MR32_DQ Calibration Patt ern A (MA[7:0] = 20H) ........................................................................................................ 22

5.3.16 MR40_DQ Calibration Patt ern B (MA[7:0] = 28H) ........................................................................................................ 22

5.3.17 MR63_Reset (MA[7: 0] = 3FH): MRW only ................................................................................................................... 22

5.4 Command Definitions and Timing Diagrams ................................................................................................................ 23

5.4.1 Activat e Command ...................................................................................................................................................... 23

5.4.1.1 Act ivate Command Cycle: tRCD = 3, tRP = 3, tRRD = 2 ................................................................................... 23

5.4.1.2 tFAW Timing ..................................................................................................................................................... 24

5.4.1.3 Command I nput Setup and Hold Timing............................................................................................................ 24

5.4.1.4 CKE Input Setup and Hold Timing .................................................................................................................... 25

5.4.2 Read and Write Access Modes.................................................................................................................................... 25

5.4.3 Burst Read Command ................................................................................................................................................. 25

5.4.3.1 Data Out put (Read) Timing (tDQSCKmax) ........................................................................................................ 26

5.4.3.2 Data Out put (Read) Timing (tDQSCKmin) ......................................................................................................... 27

5.4.3.3 Burs t Read: RL = 5, BL = 4, tDQSCK > tCK ...................................................................................................... 27

5.4.3.4 Burs t Read: RL = 3, BL = 8, tDQSCK < tCK ...................................................................................................... 28

5.4.3.5 LPDDR2: tDQSCKDL Timing ............................................................................................................................ 28

5.4.3.6 LPDDR2: tDQSCKDM Timing ........................................................................................................................... 29

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.3.7 LPDDR2: tDQSCKDS Timin g............................................................................................................................ 29

5.4.3.8 Burs t Read Followed by Burst Write: RL = 3, WL = 1, BL = 4 ............................................................................ 30

5.4.3.9 Seamless B urst Read: RL = 3, BL= 4, tCCD = 2 ............................................................................................... 30

5.4.4 Reads Interrupted by a Read ....................................................................................................................................... 31

5.4.4.1 Read Burs t Interrupt Example: RL = 3, BL= 8, tCCD = 2 ................................................................................... 31

5.4.5 Burst Write Operation .................................................................................................................................................. 31

5.4.5.1 Data I nput (Writ e) Timi ng .................................................................................................................................. 32

5.4.5.2 Burst Write: WL = 1, B L= 4 ............................................................................................................................... 32

5.4.5.3 Burs t Wirte Followed by Burst Read: RL = 3, WL= 1, BL= 4 .............................................................................. 33

5.4.5.4 Seaml ess B urst W rite: WL= 1, BL = 4, tCCD = 2............................................................................................... 33

5.4.6 W rites Interrupted by a Write ....................................................................................................................................... 34

5.4.6.1 Write Burst Interrupt Timing: W L = 1, BL = 8, tCCD = 2 .................................................................................... 34

5.4.7 Burst Terminate ........................................................................................................................................................... 34

5.4.7.1 Burs t Write Truncated by BST: WL = 1, BL = 16 ............................................................................................... 35

5.4.7.2 Burs t Read Truncated by BST: RL = 3, BL = 16 ................................................................................................ 35

5.4.8 W rite Data Mask .......................................................................................................................................................... 36

5.4.8.1 Write Data Mask Timing .................................................................................................................................... 36

5.4.9 Precharge Operat i on ................................................................................................................................................... 37

5.4.9.1 Bank Selection for Precharge by Address Bits .................................................................................................. 37

5.4.10 Burst Read Operati on Followed by Precharge ............................................................................................................. 37

5.4.10.1 Burs t Read Followed by Precharge: RL = 3, BL = 8, RU(tRTP(m in)/tCK) = 2 .................................................... 38

5.4.10.2 Burs t Read Followed by Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 3 .................................................... 38

5.4.11 Burst Writ e Followed by Precharge ............................................................................................................................. 39

5.4.11.1 Burs t Write Follwed by Precharge: WL = 1, BL = 4............................................................................................ 39

5.4.12 Auto Precharge Operation ........................................................................................................................................... 40

5.4.13 Burst Read with Auto-Precharge ................................................................................................................................. 40

5.4.13.1 Burs t Read with Auto-Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 2 ........................................................ 40

5.4.14 Burst Write with Auto-Precharge .................................................................................................................................. 41

5.4.14.1 Burst Write with Auto-Precharge: W L = 1, BL = 4 .............................................................................................. 41

5.4.14.2 Prec harge & Auto Precharge Cl arifi cation ......................................................................................................... 42

5.4.15 Refresh Command ...................................................................................................................................................... 43

5.4.15.1 Command Sc hedul i ng Separati ons Related to Refresh ..................................................................................... 44

5.4.16 LPDDR2 SDRAM Refresh Requirements .................................................................................................................... 44

5.4.16.1 Definition of tSRF .............................................................................................................................................. 45

5.4.16.2 Regular, Di st ri but ed Refres h Pattern ................................................................................................................. 47

5.4.16.3 All owable Trans i tion from Repetitive Burst Refresh ........................................................................................... 47

5.4.16.4 NOT-Al l owable Trans i tion from Re petitive Burst Refresh .................................................................................. 48

5.4.16.5 Recommended Self-Refresh Entry and Exit ...................................................................................................... 48

5.4.16.6 All Bank Refresh Operat i on ............................................................................................................................... 49

5.4.16.7 Per B ank Ref resh Operation ............................................................................................................................. 49

5.4.17 Self Refres h Operation ................................................................................................................................................ 50

5.4.18 Partial Array Self-Refresh: Bank Masking .................................................................................................................... 51

5.4.19 Partial Array Self-Refresh: Segment Masking .............................................................................................................. 51

5.4.20 Mode Register Read Command .................................................................................................................................. 52

5.4.20.1 Mode Regist er Read Timi ng Example: RL = 3, tMRR = 2 .................................................................................. 53

5.4.20.2 Read to MRR Timing Example: RL = 3, tMRR = 2 ............................................................................................ 54

5.4.20.3 Burs t Write Followed by MRR: RL = 3, WL = 1, BL = 4 ..................................................................................... 54

5.4.21 Temperature S ensor.................................................................................................................................................... 55

5.4.21.1 Temperat ure Sensor Timing ............................................................................................................................. 56

5.4.21.2 DQ Calibrat i on .................................................................................................................................................. 56

5.4.21.3 MR32 and MR40 DQ Calibration Timing Exampl e: RL = 3, tMRR = 2 ............................................................... 57

5.4.22 Mode Register Writ e Command................................................................................................................................... 58

5.4.22.1 Mode Regist er Write Timing Example: RL = 3, tMRW = 5 ................................................................................. 58

5.4.22.2 Truth T abl e for Mode Register Read (MRR) and Mode Register Write (MRW) .................................................. 58

5.4.23 Mode Register Wri t e Reset (MRW Reset) ................................................................................................................... 59

5.4.24 Mode Register Writ e ZQ Calibrati on Command ........................................................................................................... 59

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Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.24.1 ZQ Cali brat i on Initial i zat i on Timing Example ..................................................................................................... 60

5.4.24.2 ZQ Cali brat i on Short Timing Example ............................................................................................................... 60

5.4.24.3 ZQ Cali brat i on Long Timing Example ................................................................................................................ 61

5.4.24.4 ZQ Cali brat i on Reset Timing Example .............................................................................................................. 61

5.4.24.5 ZQ External Res istor V al ue, Toleranc e, and Capacitive Loadi ng ...................................................................... 62

5.4.25 Power-Down ................................................................................................................................................................ 62

5.4.25.1 Bas ic Power Down Entry and Exit Timing ......................................................................................................... 62

5.4.25.2 CKE Intensive Environment .............................................................................................................................. 63

5.4.25.3 Refres h to Refresh T iming with CKE Int ensive Environment ............................................................................. 63

5.4.25.4 Read to P ower-Down Entry ............................................................................................................................... 64

5.4.25.5 Read with Auto Precharge to Power-Down Entry .............................................................................................. 64

5.4.25.6 Write to Power-Down Entry ............................................................................................................................... 65

5.4.25.7 Write with Auto Precharge to P ower-Down Entry .............................................................................................. 65

5.4.25.8 Refres h Command t o Power-Down E ntry .......................................................................................................... 66

5.4.25.9 Activate Command to Power-Down E ntry ......................................................................................................... 66

5.4.25.10 Precharge/Precharge-All Command to Power-Down Entry ............................................................................... 66

5.4.25.11 Mode Regist er Read t o Power-Down Entry ....................................................................................................... 67

5.4.25.12 MRW Comm and to Power-Down Entry ............................................................................................................. 67

5.4.26 Deep Power-Down ...................................................................................................................................................... 67

5.4.26.1 Deep Power Down Entry and Exit Timing .......................................................................................................... 68

5.4.27 Input Clock Stop and Frequency Change .................................................................................................................... 68

5.4.28 No Operation Command .............................................................................................................................................. 69

5.5 Truth Tables ................................................................................................................................................................. 69

5.5.1 Command Truth Table ................................................................................................................................................. 70

5.5.2 CKE Truth Table.......................................................................................................................................................... 71

5.5.3 Current State B ank n - Command to Bank n Truth Table ............................................................................................. 72

5.5.4 Current State B ank n - Command to Bank m Truth Table ............................................................................................ 74

5.5.5 Data Mask Truth Table ................................................................................................................................................ 75

6. ELECTRICAL CHARACTERISTIC .............................................................................................................................. 76

6.1 Absolute Maximum DC Ratings ................................................................................................................................... 76

6.2 AC & DC Operating Conditions .................................................................................................................................... 76

6.2.1 Recommended DC Operating Conditi ons .................................................................................................................... 76

6.2.1.1 Recommended DC Operating Conditions ......................................................................................................... 76

6.2.2 Input Leakage Current ................................................................................................................................................. 77

6.2.3 Operating Tem perat ure Conditi ons .............................................................................................................................. 77

6.2.4 AC and DC Input Measurement Levels ........................................................................................................................ 77

6.2.4.1 AC and DC Logic Input Levels for Single-Ended Signals................................................................................... 77

6.2.4.1.1 Single-Ended AC and DC Input Levels for CA and CS_n Inputs ....................................................................... 77

6.2.4.1.2 Single-Ended AC and DC Input Levels for CKE ................................................................................................ 78

6.2.4.1.3 Single-Ended AC and DC Input Levels for DQ and DM ..................................................................................... 78

6.2.4.2 Vref T olerances ................................................................................................................................................ 78

6.2.4.2.1 VRef(DC) Toleranc e and VRef AC-Noise Limits ................................................................................................ 79

6.2.4.3 Input Signal ....................................................................................................................................................... 80

6.2.4.3.1 LPDDR2-800/1066 Input Signal ........................................................................................................................ 80

6.2.4.4 AC and DC Logic Input Levels for Different i al Signals ....................................................................................... 81

6.2.4.4.1 Differenti al Signal Def i niti on .............................................................................................................................. 81

6.2.4.4.2 Differenti al Swing Requirements for Clock (CK_t - CK_c) and Strobe (DQS_t - DQS_c) ................................... 81

6.2.4.5 Single-Ended Requirements for Differential Si gnals .......................................................................................... 82

6.2.4.6 Differential Input Cross Point Voltage ................................................................................................................ 83

6.2.4.7 Slew Rate Defi niti ons f or Singl e-Ended Input Signals ....................................................................................... 84

6.2.4.8 Slew Rate Defi niti ons f or Diff erential Input S i gnals ............................................................................................ 84

6.2.5 AC and DC Output Measurement Levels ..................................................................................................................... 85

6.2.5.1 Single Ended AC and DC Output Levels ........................................................................................................... 85

6.2.5.2 Differential AC and DC Output Levels ............................................................................................................... 85

6.2.5.3 Single Ended Output Slew Rate ........................................................................................................................ 85

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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6.2.5.4 Differential Output Slew Rate ............................................................................................................................ 87

6.2.5.5 Overshoot and Unders hoot S pecifications ........................................................................................................ 88

6.2.6 Output buffer Charact eri st ics ....................................................................................................................................... 89

6.2.6.1 HSUL_12 Driver Out put Timing Reference Load ............................................................................................... 89

6.2.6.2 RONPU and RONPD Resistor Definition .............................................................................................................. 89

6.2.6.3 RONPU and RONPD Characteristics with ZQ Cal i bration ..................................................................................... 90

6.2.6.4 Output Dri ver Temperature and Voltage S ensitivity ........................................................................................... 90

6.2.6.5 RONPU and RONPD Characteristics without ZQ Calibrat i on ................................................................................ 91

6.2.6.6 RZQ I-V Curve .................................................................................................................................................. 92

6.2.6.7 Input/Output Capacitance ................................................................................................................................. 94

6.3 IDD Specification Parameters and Test Conditions ..................................................................................................... 95

6.3.1 IDD Measurement Conditi ons ...................................................................................................................................... 95

6.3.1.1 Defini tion of Switc hi ng for CA Input Signals ...................................................................................................... 95

6.3.1.2 Definition of Switching for IDD4R ...................................................................................................................... 96

6.3.1.3 Definition of Switching for IDD4W ..................................................................................................................... 96

6.3.2 IDD Specific ations ....................................................................................................................................................... 97

6.3.2.1 LPDDR2 IDD Specific at i on Parameters and Operating Condi tions, -40°C~85°C (x16, x32) .............................. 97

6.3.2.2 IDD6 Partial Array Self-Refresh Current, 85°C (x16, x32) ................................................................................. 99

6.4 Clock Specification ....................................................................................................................................................... 99

6.4.1 Definit i on for tCK(avg) and nCK................................................................................................................................... 99

6.4.2 Definition for tCK(abs) ................................................................................................................................................. 99

6.4.3 Definit i on for tCH(avg) and tCL(avg) .......................................................................................................................... 100

6.4.4 Definition for tJIT(per) ................................................................................................................................................ 100

6.4.5 Defini tio n for tJ IT (cc) ................................................................................................................................................. 100

6.4.6 Definition for tERR(nper) ........................................................................................................................................... 100

6.4.7 Definit i on for Duty Cycle Jitter tJIT(duty) .................................................................................................................... 101

6.4.8 Definit i on for tCK(abs ), tCH(abs) and tCL(abs) .......................................................................................................... 101

6.5 Period Clock Jitter ...................................................................................................................................................... 101

6.5.1 Clock Peri od Jitt er Effects on Core Timing Param eters ............................................................................................. 101

6.5.1.1 Cycl e Time De-rating for Core Timing Parameters .......................................................................................... 101

6.5.1.2 Clock Cycle De-rating for Core Timing Parameters ......................................................................................... 102

6.5.2 Clock Jitter Eff ects on Command/Address Timing Parameters .................................................................................. 102

6.5.3 Clock Jitter Eff ects on Read Timing Parameters ........................................................................................................ 102

6.5.3.1 tRPRE ............................................................................................................................................................ 102

6.5.3.2 tLZ(DQ), tHZ(DQ), tD QS CK, tLZ(DQ S) , tH Z ( D Q S) ......................................................................................... 102

6.5.3.3 tQ SH, tQSL ..................................................................................................................................................... 102

6.5.3.4 tRPST ............................................................................................................................................................. 103

6.5.4 Clock Jitter Eff ects on Write Timing Parameters ........................................................................................................ 103

6.5.4.1 tDS , tDH ......................................................................................................................................................... 103

6.5.4.2 tDSS, tDSH ..................................................................................................................................................... 103

6.5.4.3 tDQSS ............................................................................................................................................................ 103

6.6 Refresh Requirements ............................................................................................................................................... 104

6.6.1 Refresh Requirem ent P aram eters ............................................................................................................................. 104

6.7 AC Timings ................................................................................................................................................................ 105

6.7.1 LPDDR2 AC Timing .................................................................................................................................................. 105

6.7.2 CA and CS_n Setup, Hold and Derating .................................................................................................................... 110

6.7.2.1 CA and CS_n Setup and Hold Base-Values for 1V/nS .................................................................................... 110

6.7.2.2 Derating V al ues LPDDR2 tIS/t I H - AC/DC Based AC220 ................................................................................ 111

6.7.2.3 Required Tim e tVAC above VIH(ac ) {bel ow VIL(ac)} for Valid Transition......................................................... 111

6.7.2.4 Nom i nal Slew Rate and tVAC for Setup Time tIS for CA and CS_n with Respect to Clock .............................. 112

6.7.2.5 Nom i nal Slew Rate for Hold Time tIH for CA and CS_n with Respect to Clock ................................................ 113

6.7.2.6 Tangent Li ne for S etup Time tIS for CA and CS_n with Respect to Clock ....................................................... 114

6.7.2.7 Tangent Li ne for Hold Time tIH for CA and CS_n with Respect to Clock ......................................................... 115

6.7.3 Data Setup, Hold and Slew Rate Derating ................................................................................................................. 116

6.7.3.1 Data Setup and Hold Base-Values .................................................................................................................. 116

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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6.7.3.2 Derating V al ues LPDDR2 tDS/tDH - AC/DC Based AC220 ............................................................................. 117

6.7.3.3 Required Tim e tVAC above VIH(ac ) {bel ow VIL(ac)} for Valid Transition......................................................... 117

6.7.3.4 Nom i nal Slew Rate and tVAC for Setup Time tDS for DQ with Respect to Strobe ........................................... 118

6.7.3.5 Nom i nal Slew Rate for Hold time tDH for DQ with Respect to Strobe .............................................................. 119

6.7.3.6 Tangent Li ne for S etup Time tDS for DQ with Respect to Strobe .................................................................... 120

6.7.3.7 Tangent Li ne for Hold Time tDH for DQ with Respect to Strobe ...................................................................... 121

7. REVISION HISTORY ................................................................................................................................................. 122

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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1. GENERAL DESCRIPTION

LPDDR2 is a high-speed SDRAM device internally configured as an 8-Bank m emory. These devices contains 1 Gb

has 1,073,741,824 bits.

All LPDDR2 devices use a double data rat e architecture on the Command/Address (CA) bus to reduce the number

of input pads in th e s ystem. T he 10-bit C A bus contain s c omm and, address , and Bank /Row Buf fer inform ation. Each

comm and uses one clock cycle, during which com mand inform ation is transfer red on both the pos itive and n egative

edge of the clock.

For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a

Read or Write command. The address and BA bits registered coincident with the Activate command are used to

select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command

are used to select the Bank and the starting column location for the burst access.

2. FEATURES

• VDD1 = 1.7~1.95V

• VDD2/VDDCA/VDDQ = 1.14V~1.30V

• Data width: x16 / x32

• Clock rate: up to 533 MHz

• Data rate: up to 1066 Mb/s/pad

• Four-bit prefetch DDR architecture

• Eight internal banks for concurrent operation

• Programmable READ and WRITE latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per Bank Refresh

• Partial Array Self-Refresh(PASR)

• Deep Power Down Mode (DPD Mode)

• Programmable output buffer driver strength

• Data mask (DM) for write data

• Clock Stop capability during idle periods

• Double data rate for data output

• Differential clock inputs

• Bidirectional differential data strobe

• Interface: HSUL_12

• JEDEC LPDDR2-S4B compliance

• Support KGD (Known Good Die) form

• Operating Temperature Range:

-25°C ≤ Tj ≤ 85°C

-40°C ≤ Tj ≤ 85°C

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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3. PAD DESCRIPTION

3.1 Basic F unctionali ty

Name

Type

Description

CK_t, CK_c Input

Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both

positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive

Clock edge.

Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the crosspoint of a

rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint of a falling CK_t and a rising

CK_c.

CKE Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input

buffers and output drivers. Power savings modes are entered and exited through CKE transitions.

CKE is considered part of the command code. See 6.5.1 “Comman d Truth Ta ble” for command code

descriptions.

CKE is sampled at the positive Clock edge.

CS_n Input Chip Select: CS_n is considered part of the command code. See 6.5.1 “Command Truth Table” for

command code descripti ons.

CS_n is sampled at the positive Clock edge.

CA[n:0] Input DDR Command/Address Inputs:

Uni-directional command/address bus inputs.

CA is considered part of the command code. See 6.5.1 “Command Truth Table” for command code

descriptions.

DQ[n:0] I/O Data Inputs/Output: Bi-directional data bus. n=15 for 16 bits DQ; n=31 for 32 bits DQ.

DQSn_t,

DQSn_c I/O

Data Strobe (Bi-directional, Differential):

The data strobe is bi-directional (used for read and write data) and differential (DQS_t and DQS_c). It is output

with read data and input with write data. DQS_t is edge-aligned to read data and centered with write data.

For x16, DQS0_t and DQS0_c correspond to the data on DQ0-7; DQS1_t and DQS1_c to the data on DQ8-15.

For x32 DQS0_t and DQS0_c correspond to the data on DQ0-7; DQS1_t and DQS1_c to the data on DQ8-15;

DQS2_t and DQS2_c to the data on DQ16-23; DQS3_t and DQS3_c to the data on DQ24-31.

DMn Input

Input Data Mask:

DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that

input data during a Write access. DM is sampled on both edges of DQS_t. Although DM is for input only, the DM

loading shall match the DQ and DQS (or DQS_c).

DM0 is the input data mask signal for the data on DQ0-7.

For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.

For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask

signal for the data on DQ24-31.

VDD1 Supply Core Power Supply 1: Power supply for core.

VDD2 Supply Core Power Supply 2: Power supply for core.

VDDCA Supply Input Receiver Power Supply: Power supply for CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers.

VDDQ Supply I/O Power Supply: Power supply for Data input/output buffers.

VREF(CA) Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all

CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers.

VREF(DQ) Supply R efer ence Vo ltage f or DQ Input Receiver: Reference voltage for all Data input buffers.

VSS Supply Ground

VSSCA Supply Ground for CA Input Receivers

VSSQ Supply I/O Ground

ZQ I/O Reference Pad for Output Drive Strength Calibration

Note: Dat a includes DQ and DM.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 8 -

3.2 Addressing Table

Density 1Gb

Number of Banks 8

Bank Addresses BA0-BA2

tREFI(µS)*2 7.8

x16 Row Addresses R0-R12

Column Addresses*1 C0-C9

x32 Row Addresses R0-R12

Column Addresses*1 C0-C8

Notes:

1. The least-s i gnificant c ol umn address C0 is not transmitted on the CA bus, and is implied to be zero.

2. tREFI values for all bank refresh is Tj = -40~85°C.

3. Row and Column Address values on the CA bus that are not used are “don’t care”.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 9 -

4. BLOCK DIAGR AM

CK_

CKE

CA0

CLOCK

BUFFER

COMMAND

DECODER

ADDRESS

BUFFER

REFRESH

COUNTER COLUMN

COUNTER

CONTROL

SIGNAL

GENERATOR

MODE

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #0

DATA CONTROL

CIRCUIT DQ

BUFFER

DQ , DQS_t ,

DQS_c

CK_t

CA9

BANK #7

Power

GND

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5. FUNCTIONAL DESCRIPTION

LPDDR2-S4 devices use a double data rate architecture on the DQ pads to achieve high speed operation. The

double d ata rate architec ture is essent ially a 4n prefet ch archit ecture with an inter face desig ned to tr ansf er two data

bits per DQ every clock cycle at the I/O pads. A single read or write access for the LPDDR2-S4 effectively consists of

a single 4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four corresponding n-bit-wide,

one-half-clock-cycle data transfers at the I/O pads.

Read and write accesses are burst oriented; accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence.

Prior to n or mal operatio n, t he L PDDR2 device must b e init ia li zed. The follo w ing sec tion pr o vides d eta il ed inf ormation

covering de vice in iti ali zati o n, reg ister defin it ion, command des c ript ion and device oper at io n.

5.1 Simplified LPDDR2 S tate Diagram

LPDDR2-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related

commands to control them. For a complete definition of the device behavior, the information provided by the state

diagram should be integrated with the truth tables and timing specification.

The truth tables provide complementary information to the state diagram, they clarify the device behavior and the

applied restrictions when considering the actual state of all the banks.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 11 -

5.1.1 Simplified LPDDR2 Bus Interface State Diagram

Precharging

Writing

With

Autoprecharge

Reading

With

Autoprecharge

ReadingWriting

Active*1

Active

Power

Down

Active

Reading

Writing

Idle

Power

Down

Idle

Reading

Resetting

Refreshing

Self

Refreshing

Deep

Power

Down

Power

Resetting

Reading

Resetting

Power

Down

Automatic Sequence

Command Sequence

Power

Applied

Reset

MRR

PDX

BST

WRA

PDX

Reset

DPDX

MRR

MRW

MRR

PDX

RD RD

BST

DPD

SREF

SREFX

REF

ACT

RDA

PR,PRA

PR(A)=Precharge (All)

ACT=Activate

WR(A)=Write(with Autoprecharge)

RD(A)=Read (with Autoprecharge)

BST=Burst Terminate

Reset=Reset is achieved through MRW command

MRW=Mode Register Write

MRR=Mode Register Read

PD=Enter Power Down

PDX=Exit Power Down

SREF=Enter Self Refresh

SREFX=Exit Self Refresh

DPD=Enter Deep Power Down

DPDX=Exit Deep Power Down

REF=Refresh

PR,PRA

Note: F or LPDDR2 -SDRA M in the Idle state, all banks are precharged.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 12 -

5.2 Power-up, Initi a lization, and Power-Off

The LPDDR2 Devices must be powered up and initialized in a predefined manner. Operational procedures other

than those specified may result in undefined operation.

5.2.1 Power Ramp and Device Initialization

The following sequence shall be used to power up an LPDDR2 device. Un less specified other wise, these steps are

mandatory.

1. Power Ramp

While applying power (after Ta), CKE shall be held at a logic low level (≤ 0.2 x VDDCA), all other inputs shall be

between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state

while CKE is held low.

On or before the completion of the power ramp (Tb) CKE must be held low.

DQ, DM, DQS_t and DQS_c vo ltage levels m ust be bet ween VSSQ and VDDQ during volt age ram p to avoid latch up.

CK_t, CK_c, CS_n, and CA input levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up.

The following conditions apply:

Ta is the point where any power supply first reaches 300mV.

After Ta is reached, VDD1 must be greater than VDD2 - 200mV.

After Ta is reached, VDD1 and VDD2 must be greater than VDDCA - 200mV.

After Ta is reached, VDD1 and VDD2 must be greater than VDDQ - 200mV.

After Ta is reached, VREF must always be less than all other supply voltages.

The voltage difference between any of VSS, VSSQ, and VSSCA pads m a y not exceed 100mV.

The above conditions apply between Ta and power-off (controlled or uncontrolled).

Tb is the point when all supply voltag es are with in their res pec tive min/m ax operati ng c o ndi ti ons . Reference voltages

shall be within their respective min/max operating conditions a minimum of 5 clocks before CKE goes high.

For supply and reference voltage operating conditions, see 7.2.1.1 “Recommended DC Operating Conditions”

table.

Power ramp duration tINIT0 (Tb - Ta) must be no greater than 20 mS.

2. CKE and clock

Beginning at Tb, CKE m ust remain low for at least tINIT1 = 100 nS, after which it may be asserted high. C loc k m us t

be stabl e at leas t tINIT2 = 5 x tCK prior t o the f irst low t o high tr ansition of CKE (Tc). CKE, CS_ n and C A inputs m ust

observe setup and hold time (tIS, tIH) requirements with respect to the first rising clock edge (as well as to the

subsequent falling and rising edges).

The clock period shall be within the range defined for tCKb (18 nS to 100 nS), if any Mode Register Reads are

performed. Mode Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are

met. Furthermor e, some AC param eters (e.g. tDQSCK) m ay have rel axed timings (e.g. tDQSCKb) bef ore the system is

appropriately configured.

While keeping CKE high, issue NOP commands for at least tINIT3 = 200 µS. (Td).

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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3. Reset command

After tINIT3 is s atisf ied, a M RW( Reset) comm and shall be issued (Td). T he mem ory contro ller m ay optionall y issue a

Precharge-All command prior to the MRW Reset command. Wait for at least tINIT4 = 1 µS while keeping CKE

asserted and issuing NOP commands.

4. Mode Registers Reads and Device Auto-Initialization (DAI) polling:

After tINIT4 is satisf ied (Te) onl y MRR c om mands and po wer-do wn entr y/exit c om mands are al lo wed. Therefor e, af ter

Te, CKE may go low in accordance to Power-Down entry and exit specification (see section 6.4.25 “Power-Down”).

The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is com plete or

the memory controller shall wait a minimum of tINIT5 before proceeding.

As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings before

the system is appropriately configured.

After the DAI-bit (MR#0, “DAI”) is set to zero “DAI complete” by the memory device, the device is in idle state (Tf).

The state of the DAI status bit can be determined by an MRR command to MR#0.

The LPDDR2 SDRAM device wil l set the DAI -bit no later than tINIT5 (10 µS) af ter the Reset com mand. T he m em ory

controller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding.

After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issuing

MRR commands (MR0 “Device Information” etc.).

5. ZQ Calibration:

After tINIT5 (Tf), an MRW ZQ Initialization Calibration command may be issued to the memory (MR10). This

comm and is used to ca libra te th e LPDDR 2 outp ut dr ivers (RON ) over pr ocess , vo ltage, and tem per ature. Optionally,

the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pad connection. In systems in

which more than one LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration

commands. The device is ready for normal operation after tZQINIT.

6. Normal Operation:

After tZQINIT (Tg), MRW commands may be used to properly configure the memory, for example the output buffer

driver strength, latencies etc. Specifically, MR1, MR2, and MR3 shall be set to configure the memory for the target

frequency and memory configuration.

The LPDDR2 device will now be in IDLE state and ready for any valid command.

After Tg, the clock frequency may be changed according to the clock frequency change procedure described in

section 6.4.27 “Input Clock Stop and Frequency Change”.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 14 -

5.2.2 Timing Parameters for Initialization

Symbol Value Unit Comment

min max

tINIT0 20 mS Maximum Power Ramp Time

tINIT1 100 nS Minimum CKE low time after completion of power ramp

tINIT2 5 tCK Minimum stable clock before first CKE high

tINIT3 200 µS Minimum Idle time after first CKE assertion

tINIT4 1 µS Minimum Idle time after Reset command

tINIT5 10 µS Maximum duration of Device Auto-Initialization

tZQINIT 1 µS ZQ Initial Calibration for LPDDR2-S4

tCKb 18 100 nS Clock cycle time during boot

5.2.3 Power Ramp and Initializati on Sequence

*Midlevel on CA bus means : valid NOP

INIT2

(min)

INIT3

200 μs

(min)

INIT1

100 ns

(min)

INIT0

20 ms

(max)

INIT4

1 μs

(min)

ISCKE

INIT5

Ta Tb Tc Tg

TeTd

RESET

ZQC Valid

CK_t / CK_c

Supplies

CKE

CA*

MRR

ZQINIT

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 15 -

5.2.4 Initialization after Reset (without Power ramp)

If the RESET command is issued outside the power up initialization sequence, the reinitialization procedure shall

begin with step 3 (Td).

5.2.5 Power-off Sequence

The following sequence shall be used to power off the LPDDR2 device.

While removing power, CKE shall be held at a logic low level (≤ 0.2 x VDDCA), all other inputs shall be between

VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is

held low.

DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during power off sequence to avoid

latch-up. CK_t, CK_c, CS_n and CA input levels must be between VSSCA and VDDCA during power off sequence t o

avoid latch-up.

Tx is the point wher e a n y p o wer supply decreas es u nder its m inimum value spec if ied in 7.2.1.1 “Recomm en d ed DC

Operating Conditions” table.

Tz is the point where all power supplies are below 300 mV. After Tz, the device is powered off.

The time between Tx and Tz (tPOFF) shall be less than 2s.

The following conditions apply:

Between Tx and Tz, VDD1 must be greater than VDD2 - 200 mV.

Between Tx and Tz, VDD1 and VDD2 must be greater than VDDCA - 200 mV.

Between Tx and Tz, VDD1 and VDD2 must be greater than VDDQ - 200 mV.

Between Tx and Tz, VREF must always be less than all other supply voltages.

The voltage difference between any of VSS, VSSQ, and VSSCA pads m a y not exceed 100 mV.

For supply and reference voltage operating conditions, see 7.2.1.1 “Recommended DC Operating Conditions”

table.

5.2.6 Timing Parameters Power-Off

Symbol

Value

Unit Comment

min

max

POFF

Maximum Power-Off Ramp Time

5.2.7 Uncontrolled Power-Off Sequence

The following sequence shall be used to power off the LPDDR2 device under uncontrolled condition.

Tx is the point where an y power supply decreases under its minim um value specified in the DC operating condition

table. After turning off all power supplies, any power supply current capacity must be zero, except for any static

charge remaining in the system.

Tz is the point where all power supply first reaches 300 mV. After Tz, the device is powered off.

The time between Tx and Tz (tPOFF) shall be less than 2s. The relative levels between supply voltages are

uncontrolled during this period.

VDD1 and VDD2 shall decrease with a slope lower than 0.5 V/µS between Tx and Tz.

Uncontrolled power off sequence can be applied only up to 400 times in the life of the device.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 16 -

5.3 Mode Reg ister Definition

5.3.1 Mode Register A ssignment and Definition

Each register is denoted as “R” if it can be read but not written, “W” if it can be written but not read, and “R/W” if it

can be read and written.

Mode Register Read command shall be used to read a register. Mode Register Write command shall be used to

write a register.

5.3.1.1 Mode Register Assignment

MR#

MA[7:0]

Function

Access

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

0 00

Device Info. R (RFU) RZQI

DNVI

DI DAI

Device Feature 1

nWR (for AP)

Device Feature 2 W (RFU) RL & WL

3 03

I/O Config-1 W (RFU) DS

4 04

Refresh Rate R TUF (RFU) Refresh Rate

Basic Config-1

LPDDR2 Manufacturer ID

Basic Config-2 R Revision ID1

7 07

Basic Config-3 R Revision ID2

8 08

Basic Config-4 R I/O width Density Type

Test Mode

Vendor-Specific Test Mode

I/O Calibration W Calibration Code

11-15 0B

~0F

(reserved) - (RFU)

16 10

PASR_Bank W Bank Mask

PASR_Seg

Segment Mask

18-19 12H

~13

(Reserved) - (RFU)

20-31 14h–1Fh Reserved for NVM

20H

DQ Calibration Pattern A

See 6.4.21.2 “DQ Calibration”

33-39 21H

~27

(Do Not Use) -

28H

DQ Calibration Pattern B

See 6.4.21.2 “DQ Calibration”

41-47

29H

~2F

(Do Not Use) -

48-62

30H~3EH

(Reserved)

(RFU)

3FH

Reset

64-126

40H

~7E

(Reserved) - (RFU)

127

7FH

(Do Not Use)

128-190

80H~BEH

(Reserved for Vendor Use)

(RFU)

191

BFH

(Do Not Use)

192-254

C0H

~FE

(Reserved for Vendor Use) - (RFU)

255

FFH

(Do Not Use)

Notes:

1. RFU bits shall be set to ‘0’ during Mode Register writes .

2. RFU bits shall be read as ‘0’ during Mode Regist er reads.

3. All Mode Regist ers t hat are specified as RFU or write-only shall return undef i ned dat a when read and DQS shall be toggled.

4. All Mode Regist ers t hat are specified as RFU shall not be written.

5. Writes to read-only regist ers s hall have no impact on the functionality of t he device.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 17 -

5.3.2 MR0_Device Information (MA[7:0] = 00H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

(RFU) RZQI

DNVI

DI DAI

DAI (Device Auto-Initialization Status) Read-only OP0 0b: DAI complete

1b: DA I still in progress

DI (Device Information) Read-only OP1 0b: S4 SDRAM

DNVI (Data Not Valid Information) Read-only OP2 0b: LPDDR2 SDRAM will not implement DNV functionalit

RZQI (Built in Self Test for RZQ Information) Read-only OP[4:3]

00b: RZQ self test not executed.

01b: ZQ-pad may connect to VDDCA or float

10b: ZQ-pad may short to GND

11b: ZQ-pad self test completed, no error condition detected

(ZQ-pad may not connect to VDDCA or float nor short to GND)

Notes:

1. RZQI will be set upon completion of the MR W ZQ Initialization Calibration command.

2. If ZQ is connected to VDDCA to set default calibration by user, OP[4:3] shall be read as 01. If user does not want to connect ZQ pad to

VDDCA, but OP[4:3] is read as 01 or 10, it might indicate a ZQ-pad assembly error. It is recommended that the assembly error being

correct ed first.

3. In the case of possible assembly error (either OP [ 4:3] = 01 or OP[4:3]=10 as defined above), the LPDDR2 device will default to factory t rim

settings for RON, and will ignore ZQ calibration commands. In either case, the syst em may not function as intended.

4. In the case of the ZQ self-test returning a value of 11b, this result indic at es that the device has detect ed a resistor c onnect i on to the ZQ pad.

However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e., 240

Ohm ± 1%).

5.3.3 MR1_Device Feature 1 (MA [7:0] = 01H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

nWR (for AP) WC BT BL

BL Write-only OP[2:0]

010b: BL4 (default)

011b: BL8

100b: BL16

All others: reserved

BT Write-only OP3 0b: Sequential (default)

1b: Interleaved

WC Write-only OP4 0b: Wrap (default)

1 b: No wrap (allowed for SDRAM BL4 only)

nWR Write-only OP[7:5]

001b: nWR=3 (default)

010b: nWR=4

011b: nWR=5

100b: nWR=6

101b: nWR=7

110b: nWR=8

All o ther s: reserved

Note:

1. Programmed val ue i n nWR register is the number of clock cycles which det ermines when to start internal precharge operat i on for a write

burst with AP enabled. It is determined by RU(tWR/tCK).

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 18 -

5.3.3.1 Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC)

C3 C2 C1 C0 WC BT BL Burst Cycle Number and Burst Address Sequence

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

X X 0b 0b wrap any 4

0 1 2 3

X X 1b 0b 2 3 0 1

X X X 0b nw any y y+1 y+2 y+3

X 0b 0b 0b

wrap

seq

0 1 2 3 4 5 6 7

X 0b 1b 0b 2 3 4 5 6 7 0 1

X 1b 0b 0b 4 5 6 7 0 1 2 3

X 1b 1b 0b 6 7 0 1 2 3 4 5

X 0b 0b 0b

int

0 1 2 3 4 5 6 7

X 0b 1b 0b 2 3 0 1 6 7 4 5

X 1b 0b 0b 4 5 6 7 0 1 2 3

X 1b 1b 0b 6 7 4 5 2 3 0 1

X X X 0b nw any illegal (not allowed)

0b 0b 0b 0b

wrap seq

0 1 2 3 4 5 6 7 8 9 A B C D E F

0b 0b 1b 0b 2 3 4 5 6 7 8 9 A B C D E F 0 1

0b 1b 0b 0b 4 5 6 7 8 9 A B C D E F 0 1 2 3

0b 1b 1b 0b 6 7 8 9 A B C D E F 0 1 2 3 4 5

1b 0b 0b 0b 8 9 A B C D E F 0 1 2 3 4 5 6 7

1b 0b 1b 0b A B C D E F 0 1 2 3 4 5 6 7 8 9

1b 1b 0b 0b C D E F 0 1 2 3 4 5 6 7 8 9 A B

1b 1b 1b 0b E F 0 1 2 3 4 5 6 7 8 9 A B C D

X X X 0b int illegal (not allowed)

X X X 0b nw any illegal (not allowed)

Notes:

1. C0 input is not present on CA bus. It is implied zero.

2. For BL=4, the burst address represents C[1: 0].

3. For BL=8, the burst address represents C[2:0].

4. For BL=16, the burst address represents C[3:0].

5. For no-wrap (nw), BL4, the burst shall not cross the page boundary and shall not cross sub-page boundary. The variable y m ay start at

any address with C0 equal to 0 and may not start at any address shown in table below.

5.3.3.2 Non Wrap Restrictions

Bus Width 1Gb

Not across full page boundary

x16 3FE, 3FF, 000, 001

x32 1FE, 1FF, 000, 001

Not across sub page boundary

x16 1FE, 1FF, 200, 201

x32 None

Note: Non-wrap BL=4 data-orders shown above are prohibited.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 19 -

5.3.4 MR2_Device Feature 2 (MA [7:0] = 02H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

(RFU)

RL & WL

RL & WL Write-only OP[3:0]

0001b: RL = 3 / WL = 1 (default)

0010b: RL = 4 / WL = 2

0011b: RL = 5 / WL = 2

0100b: RL = 6 / WL = 3

0101b: RL = 7 / WL = 4

0110b: RL = 8 / WL = 4

All others: reserved

5.3.5 MR3_I/O Configuration 1 (MA[7:0] = 03H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

(RFU)

DS Write-only OP[3:0]

0000

reserved

0001b: 3

4.3

-ohm typical

0010b: 40-ohm typical (default)

0011b: 4

-ohm typical

0100b:

-ohm typical

0101b: reserved

0110b:

-ohm typical

0111b:

120

-ohm typical

All others: reserved

5.3.6 MR4_Device Temperature (MA[ 7:0] = 04H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

TUF

(RFU)

SDRAM Refresh Rate

SDRAM

Refresh Rate Read-only OP[2:0]

000

: SDRAM Low temperature operating limit exceeded

001b: 4x tREFI, 4x tREFIpb, 4x tREFW

010b: 2x tREFI, 2x tREFIpb, 2x tREFW

011b: 1x tREFI, 1x tREFIpb, 1x tREFW (≤ 85°C)

100b: Reserved

101b: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, do not de-rate

SDRAM AC timing

110b: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, de-rat e SDRAM

AC timing

111b:

SDRAM High temperature operating limit exceeded

Temperature

Update Flag (TUF) Read-only OP7

: OP[2:0] value has not changed since last read of MR4.

: OP[2:0] value has changed since last read of MR4.

Notes:

1. A Mode Register Read from MR4 will reset OP7 to ‘0’.

2. OP7 is reset to ‘0’ at power-up.

3. If OP2 equals ‘1’, the device temperature is great er t han 85°C.

4. OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last read of MR4.

5. LPDDR2 might not operate properly when OP[2:0] = 000b or 111b.

6. For specified operating temperature range and maximum operating temperature, refer to “Operating Temperature Conditions” table.

7. LPDDR2 devices must be derated by adding 1.875 nS to the following core timing parameters: tRCD, tRC, tRAS, tRP, and tRRD. tDQSCK

shall be de-rated according to the tDQSCK de-rating value in “LPDDR2 AC Timing” table. Prevaili ng clock f requency spec and related

setup and hold timings shall remain unchanged.

8. The recommended f requency for reading MR4 is provided in “Temperature Sensor” section.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 20 -

5.3.7 MR5_Basic Configuration 1 (MA[7:0] = 05H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

LPDDR2 Manufacturer ID

LPDDR2 Manufacturer ID Read-only OP[7:0] 0000 1000b: Winbond

5.3.8 MR6_Basic Configuration 2 (MA[7:0] = 06H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Revision ID1

Revision ID1 Read-only OP[7:0] 00000000b: A-version

Note: MR6 is Vendor Specific.

5.3.9 MR7_Basic Configuration 3 (MA[7:0] = 07H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Revision ID2

Revision ID2 Read-only OP[7:0] 00000000b: A-version

Note: MR 7 is Vendor Specific.

5.3.10 MR8_Basic Configuration 4 (MA[7:0] = 08H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

I/O width Density Type

Type Read-only OP[1:0] 00b: S4 SDRAM

Density Read-only OP[5:2] 0100b: 1Gb

I/O width Read-only OP[7:6] 00b: x32

01b: x16

5.3.11 MR9_Test Mode (MA [7:0] = 09H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Vendor-specific Test Mode

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 21 -

5.3.12 MR10_Cali bration (MA[7:0] = 0AH)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Calibration Code

Calibration Code Write-only OP[7:0]

0xFF: Calibration command after initialization

0xAB: Long calibration

0x56: Short cal ibr at ion

0xC3: ZQ Reset

others: Reserved

Notes:

1. Host process or shall not write MR10 with “Reserved” values.

2. LPDDR2 devices s hall i gnore cali bration command when a “Reserved” value is written i nto MR10.

3. See AC timing table for the calibrati on l atenc y.

4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see section 6.4.24 “Mode Register Write ZQ

Calibration Command”) or default calibration (through the ZQreset command) is supported. If ZQ is connected to VDDCA, the

device operates with default cali bration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not

change after power is applied to the device.

5. Optionally, the MRW ZQ Initialization Calibrati on command will update MR0 to indicat e RZQ pad connection.

5.3.13 MR16_PA SR_Bank Mask (MA [7:0] = 10H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

S4 SDRAM Bank Mask (8-bank)

Bank [7:0] Mask Write-only OP[7:0] 0b: refresh enable to the bank (=unmasked, default)

1b: refresh blocked (=masked)

OP Bank Mask 8-Bank S 4 SDRAM

0 XXXXXXX1 Bank 0

1 XXXXXX1X Bank 1

2 XXXXX1XX Bank 2

3 XXXX1XXX Bank 3

4 XXX1XXXX Bank 4

5 XX1XXXXX Bank 5

6 X1XXXXXX Bank 6

7 1XXXXXXX Bank 7

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 22 -

5.3.14 MR17_PASR_Segment Mask (MA[7:0] = 11H)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Segment Mask

Segment [7:0] Mask Write-only OP[7:0] 0b: refresh enable to the segment (=unmasked, default)

1b: refresh blocked (=masked)

Segment OP Segmen t Mas k R[12:10]

0 0 XXXXXXX1 000b

1 1 XXXXXX1X 001b

2 2 XXXXX1XX 010b

3 3 XXXX1XXX 011b

4 4 XXX1XXXX 100b

5 5 XX1XXXXX 101b

6 6 X1XXXXXX 110b

7 7 1XXXXXXX 111b

5.3.15 MR32_DQ Calibration Pattern A (MA[7:0] = 20H)

Reads to MR32 return DQ Calibration Pattern “A”. See section 6.4.21.2 “DQ Calibration”.

5.3.16 MR40_DQ Calibration Pattern B (MA[7:0] = 28H)

Reads to MR40 return DQ Calibration Pattern “B”. See section 6.4.21.2 “DQ Calibration”.

5.3.17 MR63_Reset (MA[7:0] = 3FH): MRW only

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

For additonal information on MRW RESET see section 6.4.22 “Mode Register Write Command”.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4 Comman d Definiti ons and Timing Diagrams

5.4.1 Activate Command

The SDRA M Ac ti vate c om mand is iss ued b y ho ldin g C S_n LOW, CA0 LOW, and CA1 H IGH at the ris in g e dge of th e

clock . T he bank addresses ar e used t o s el ec t th e desired bank. The row a ddres ses ar e used t o determ ine whic h ro w

to activa te in the selected bank. T he Activate comm and must be a pplied b efore an y Read or W rite opera tion can be

executed. The LPDDR2 SDRAM can accept a read or write command at time tRCD after the activate command is

sent. Onc e a ba nk has been ac ti vate d it must be prechar ged b ef or e anot her Act iv ate c om mand can be appli ed to the

same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time

interval between successive Activate commands to the same bank is determined by the RAS cycle time of the device

(tRC). The minimum time interval between Activate commands to different banks is tRRD.

Certain r estr icti ons o n op eration of the 8-ba nk devices must be obs erve d. There are two rules. O ne f or r estr i c ting t he

number of sequential Act ivate comm ands that can be issued an d another f or allowing m ore time for RAS pr echarge

for a Precharge All command. The rules are as follows:

8-bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated (or refreshed, in the

case of REFpb) i n a ro l lin g tF AW windo w . Con v er ting to clock s is done by dividin g tFAW[nS] by t CK[nS], and r ound in g

up to next integer value. As an example of the rolling window, if RU{ (tFAW / tCK) } is 10 clocks, and an activate

command is issued in clock N, no more than three further activate commands may be issued at or between clock

N+1 and N+9. REFpb also counts as bank-activation for the purposes of tFAW.

8-bank device Precharge All Allowance: tRP for a Precharge All command for an 8-bank device shall equal tRPab,

which is greater than tRPpb.

5.4.1.1 Activate Command Cycle: tRCD = 3, tRP = 3, tRRD = 2

T0 T1 T2 T3 Tn Tn+3Tn+2Tn+1

CK_t / CK_c

CA0-9

[Cmd]

Activate Nop Activate Read

RAS-CAS delay=tRCD

RAS-RAS delay time=tRRD Bank Precharge time=tRP

Bank Active=tRAS

Row Cycle time=tRC

Read Begins

Precharge Nop Nop Activate

Bank A

Row Addr Row Addr Bank B

Row Addr Row Addr Bank A

Col Addr Col Addr Bank A Bank A

Row Addr Row Addr

Note:

A Precharge-A l l command uses tRPab timing, while a Single Bank Precharge command uses tRPpb timing. I n this figure, tRP is used to denote

either an All-bank Precharge or a Single Bank Precharge

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 24 -

5.4.1.2 tFAW Timing

CA0-9

[Cmd]

CK_t / CK_c T

z+2

z+1

tRRD

tFAW

tRRD

y+2

y+1

Bank E Bank E

tRRD

Bank A Bank A Bank B Bank B Bank C Bank C Bank D Bank D

ACT NopNopNop NopACT

ACT

ACTACT

Note: tFAW is for 8-bank devices only.

5.4.1.3 Command Input Setup and Hold Timing

Nop

CK_t / CK_c

CA0-9

[Cmd]

T1 T2 T3

CS_n

Command

Nop

Command

tIS tIH

tIHtIH tIStIS

Rise CA

Rise

Fall CA

Fall

VIL(AC) VIL(DC)

VIH(AC) VIH(DC)

HIGH or LOW (but a defined logic level)

Note: Setup and hold conditions also appl y to the CKE pad. See section related to power down for timing diagrams relat ed to the CKE pad.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.1.4 CKE Input Setup and Hold Timing

HIGH or LOW (but a defined logic level)

T0 T1 Tx Tx+1

CK_t / CK_c

CKE

tISCKE tISCKE

tIHCKE tIHCKE

VIHCKE

VILCKE VIHCKE

VILCKE

Notes:

1. After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE specif ication (LOW pulse width).

2. After CKE is registered HIGH, CKE signal level shall be maint ai ned above VIHCKE for tCKE specif ic at ion (HIGH pulse width).

5.4.2 Read and Write Access Modes

After a bank has bee n act ivated, a r ead or write c ycle c an be exec uted. T his is accom plishe d b y setting CS_ n LOW,

CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine

whether the access cycle is a READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW).

The LPDDR2 SD R AM pr ov ides a f ast column acces s operatio n. A s i ngle R e ad or Write Command will initiate a burst

read or write operation on successive clock cycles.

A new bur st access m ust not interrupt the pre vious 4-bit burst oper ation in case of BL = 4 setting. In cas e of BL = 8

and BL = 16 settings, Reads may be interrupted by Reads and Writes may be interrupted by Writes provided that this

occurs on even clock cycles after the Read or Write command and tCCD is met.

5.4.3 Burst Read Command

The Burs t Read c om mand is initiat ed by having C S_n LOW, CA0 HIG H, C A1 LOW and CA2 HIGH at th e r is ing edg e

of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address

for the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is

issued to th e rising edge of the clock from which the t DQSCK dela y is measur ed. The first vali d datum is available RL

* tCK + tDQSCK + tDQSQ after the rising edg e of the c loc k where the Read C om mand is issued. T he data strob e out p ut

is driven LOW tRPRE before the first rising valid strobe edge. The first bit of the burst is synchronized with the first

rising edge of the data strobe. Each subsequent data-out appears on each DQ pad edge aligned with the data

strobe. The RL is programmed in the mode registers.

Timings for the data strobe are measured relative to the crosspoint of DQS_t and its complement, DQS_c.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 26 -

5.4.3.1 Data Output (Read) Timing (tDQSCKmax)

DQS_c

CK_t

CK_c

RL-1 RL

DQS_t

DQS_c

RL+BL/2

QQ Q Q

tQH

tHZ(DQ)

tDQSQmax

tDQSCKmax

tLZ(DQ)

tLZ(DQS)

tRPRE

tHZ(DQs)

tRPST

tQH

tCH tCL

DQS_t

tQSH tQSL

Notes:

1. tDQSCK may span multiple clock periods.

2. An effecti ve Burst Lengt h of 4 is shown.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.3.2 Data Output (Read) Timing (tDQSCKmin)

QQQQ

tDQSQmax

tDQSCKmin

RL+BL/2

tHZ(DQs)

tRPST

tQH

tHZ(DQ)

tQH

tLZ(DQ)

tDQSQmax

tRPRE

tLZ(DQS)

CK_t

CK_c RL-1 RL

tCH tCL

DQS_t

DQS_c

DQS_t

tQSL

tQSH

Note: An effective Burst Length of 4 is shown.

5.4.3.3 Burst Read: RL = 5, BL = 4, tDQSCK > tCK

CK_t / CK_c

CA0-9

[Cmd]

Nop Nop Nop Nop Nop Nop Nop Nop

Read

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQS_c

DQSCK

RL = 5

Bank A

Col Addr Col Addr

DOUT A0 DOUT A1 DOUT A2 DOUT A3

DQS_t

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.3.4 Burst Read: RL = 3, BL = 8, tDQSCK < tCK

CK_t / CK_c

CA0-9

[Cmd]

Nop Nop Nop Nop Nop Nop Nop NopRead

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQS_c

tDQSCK

RL = 3

Bank A

Col Addr Col Addr

DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7

DQS_t

5.4.3.5 LPDDR2: tDQSCKDL Timing

CA0-9

[Cmd]

DQS

Tm+8

32mS maximum

RL = 5

CK_t / CK_c

DQS_c

DQS_t

DOUT A3

Tm+7

Tm+6Tm+5

Tm+4Tm+3Tm+2Tm+1Tm

DQSCKm

DOUT A2DOUT A1DOUT A0

Tn+8

RL = 5

DOUT A3

Tn+7

Tn+6

Tn+5

Tn+4

Tn+3Tn+2Tn+1

DQSCKn

DOUT A2DOUT A1DOUT A0

DQSCKDL

= l t

DQSCKn

– t

DQSCKm

Col

Addr

Read Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop

Read

Col

Addr

Col

Addr

Col

Addr

Nop

Note: tDQSCKDLmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn ,tDQSCKm} pair withi n any 32mS rolling window.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.3.6 LPDDR2: tDQSCKDM Timing

CA0-9

[Cmd]

DQS

Tm+8

1.6µS maximum

RL = 5

CK_t / CK_c

DQS_c

DQS_t

Tm+7

Tm+6Tm+5

Tm+4Tm+3Tm+2Tm+1Tm

DQSCKm

Tn+8

RL = 5

Tn+7

Tn+6

Tn+5

Tn+4

Tn+3Tn+2Tn+1

DQSCKn

DOUT

tDQSCKDM = l tDQSCKn – tDQSCKm l

Nop

Col

Addr

Read Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop

Read

Col

Addr

Col

Addr

Col

Addr

Nop

DOUT

A3 DOUT

DOUT

Note: tDQSCKDMmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn,tDQSCKm} pair within any 1.6µS rolling window.

5.4.3.7 LPDDR2: tDQSCKDS Timing

CA0-9

[Cmd]

DQS

Tm+8

160nS maximum

RL = 5

CK_t / CK_c

DQS_c

DQS_t

Tm+7

Tm+6Tm+5

Tm+4Tm+3Tm+2Tm+1Tm

DQSCKm

Tn+8

RL = 5

Tn+7

Tn+6

Tn+5

Tn+4

Tn+3Tn+2Tn+1

DQSCKn

DOUT A0

DQSCKDS

= l t

DQSCKn

– t

DQSCKm

Nop

Col

Addr

Read Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop

Read

Col

Addr

Col

Addr

Col

Addr

Nop

DOUT A1 DOUT A2 DOUT A3 DOUT A0 A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2

Nop

Note:

tDQSCKDSmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn ,tDQSCKm} pair for reads within a consecutive burst

within any 160nS rolling window

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 30 -

5.4.3.8 Burst Read Followed by Burst Write: RL = 3, WL = 1, BL = 4

CK_t / CK_c

CA0-9

[Cmd]

Nop Nop Nop Nop Nop Write Nop NopRead

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQS_c

DQSCK

RL = 3

Bank A

Col Addr Col Addr

DOUT A0 DOUT A1 DOUT A2 DOUT A3 DIN A0 DIN A1 DIN A2

WL=1

DQSSmin

BL / 2

Bank A

Col Addr Col Addr

DQS_t

The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL)

and the Burst Length (BL). Minim um read to write latency is RL + RU(tDQSCKmax/tCK) + BL/2 + 1 - W L clock cycles.

Note that if a read burst is truncated with a Burst Terminate (BST) command, the effective burst length of the

truncated read burst should be used as “BL” to calculate the minimum read to write delay

5.4.3.9 Seamless Burst Read: RL = 3, BL= 4, tCCD = 2

CK_t / CK_c

CA0-9

[Cmd]

Nop Read Nop Nop Nop Nop Nop Nop

Read

DQS_c

RL = 3

Bank N

Col Addr A Col Addr A

DOUT A0

T0 T1 T2 T3T4 T5T6 T7 T8

tCCD = 2

Bank N

Col Addr B Col Addr B

DQS_t

DOUT A1 DOUT A2 DOUT A3DOUT B0 DOUT B1 DOUT B2 DOUT B3

The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4

operation, every 4 clocks for BL = 8 operation, and every 8 clocks for BL=16 operation.

For LPDDR 2-SD RA M, this operatio n is a llow ed re gar d l ess of whet her the access es read the s ame or different bank s

as long as the banks are activated.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.4 Reads Interrupt ed by a Read

For LPDDR2-S4 device, burst read can be interrupted by another read on even clock cycles after the Read

command, provided that tCCD is met.

5.4.4.1 Read Burst Interrupt Example: RL = 3, BL= 8, tCCD = 2

RL = 3

CCD=2

Nop Read Nop Nop Nop Nop Nop Nop

Col Addr A

DOUT A0

T7T6

T5T4T3T2T1

Bank N

Col Addr A

Read

Bank N

Col Addr B Col Addr B

CA0-9

[Cmd]

CK_t / CK_c

DQS_c

DQS_t

DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B4 DOUT B5

Notes:

1. For LP DDR2-S 4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16.

2. For LP DDR2-S 4 devices, read burst interrupt may occur on any clock cycle after the intial read command, provided that tCCD is met.

3. Reads c an only be interrupted by other reads or the BST command.

4. Read burst interrupt i on is allowed to any bank inside DRAM.

5. Read burst with Auto-P recharge is not allowed to be interrupt ed.

6. The eff ective burst l engt h of the first read equals two times the number of clock cycles between the first read and the interrupti ng read.

5.4.5 Burst Write Operation

The Burs t W rite com mand i s initiat ed b y hav ing CS _n LOW , CA0 H IGH, C A1 LO W and CA2 LOW at the rising edge

of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address

for the burst. The Write Latency (WL) is defined from the rising edge of the clock on which the Write Command is

issued to the r is ing ed ge of the c lock from wh ich the t DQSS delay is m eas ur ed. T he f irs t valid d ata must be driven WL

* tCK + tDQSS from the rising edge of the clock from which the Write command is issued. The data strobe signal

(DQS) should be driven LOW tWPRE prior to the data input. The data bits of the burst cycle must be applied to the

DQ pads tDS prior to the respective edge of the DQS_t, DQS_c and held valid until tDH after that edge. The burst

data are s am pled on succ essive edges of the DQS_t, DQS_c u ntil t he burs t leng th is c ompleted, which is 4, 8, or 16

bit burst.

For LPDD R2-SDRA M dev ices , tWR must be satisf ied befor e a prech arge com m and to the s am e bank m a y be issued

after a burst write operation.

Input timings are measured relative to the crosspoint of DQS_t and its complement, DQS_c.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 32 -

5.4.5.1 Data Input (Write) Timing

DQS_c

DQS_t

DQS_c

D D D D

DMin

DMin DMin DMin

tDQSH tDQSL

tWPRE tWPST

tDH

tDS

(dc)

(ac)

tDH

5.4.5.2 Burst Write: WL = 1, BL= 4

CA0-9

[Cmd]

DQS_c

CK_t / CK_c

DQS

DQS_c

T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1

tRP

tWR

tDSH

tDSS tDSS

tWR

Bank A

Col Addr Col Addr Bank A

Row Addr

Bank A Row Addr

Nop

NopNop

NopWrite Precharge Activate

DIN A0 DIN A1 DIN A2 DIN A3

tDQSSmax

tDQSSmin

Completion of Burst Write

Case 1:with t

DQSS

(max)

Case 2:with t

DQSS

(min)

WL = 1

DQS_t

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.5.3 Burst Wirte Followed by Burst Read: RL = 3, WL= 1, BL= 4

CK_t / CK_c

CA0-9

[Cmd] Nop Read

Nop Nop Nop

Write

DQS_c

tWTR

Bank M

Col Addr A Col Addr A

DIN A0 DIN A1 DIN A2 DIN A3

T0 T1 T2 T3 T4 T5 T6 T7 T8

WL = 1

Bank N

Col Addr B Col Addr B

RL = 3

DQS_t

Notes:

1. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 +

RU( tWTR/tCK)].

2. tWTR starts at the rising edge of the clock after the last valid input datum.

3. If a write burst is truncat ed with a Burst Terminate (BST) command, the effecti ve burst l ength of the truncated write burst shoul d be

used as “BL” to calculate the minimum write to read delay.

5.4.5.4 Seamless Burst Write: WL= 1, BL = 4, tCCD = 2

CK_t / CK_c

CA0-9

[Cmd]

Nop Write Nop Nop Nop Nop Nop Nop

Write

DQS_c

WL=1

Bank M

Col Addr A Col Addr A

DIN A0 DIN A1 DIN A2 DIN A3

T0 T1 T2 T3 T4 T5 T6 T7 T8

tCCD = 2

Bank N

Col Addr B Col Addr B

DIN B0 DIN B1 DIN B2 DIN B3

DQS_t

Note:

The seamless burst write operation i s s upport ed by enabling a write comm and every other clock for BL = 4 operation, every four clocks for

BL = 8 operation, or every eight clocks for BL = 16 operation. This operation is all owed regardless of same or different banks as long as the

banks are activated

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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5.4.6 Writes Interrupted by a Write

For LPDDR2-S4 devices, burst writes can only be interrupted by another write on even clock cycles after the write

command, provided that tCCD(min) is met.

5.4.6.1 Write Burst Interrupt Timing: WL = 1, BL = 8, tCCD = 2

CK_t / CK_c

CA0-9

[Cmd] Nop Write Nop Nop Nop Nop Nop Nop

Write

DQS_c

WL=1

Bank M

Col Addr A Col Addr A

DIN A0 DIN A1

T0 T1T2 T3 T4 T5 T6 T7 T8

tCCD = 2

Bank N

Col Addr B Col Addr B

DIN B2 DIN B3 DIN B5

DIN B4

DIN B1

DIN B0 DIN B6 DIN B7DIN A2 DIN A3

DQS_t

Notes:

1. For LP DDR2-S 4 devices, write burs t interrupt function is only allowed on burst of 8 and burst of 16.

2. For LP DDR2-S 4 devices, write burs t interrupt may only occur on even clock cycles after the previous write commands, provided that

tCCD(min) is met.

3. Writes can only be interrupted by other writes or the BST command.

4. Write burst interrupt i on is allowed to any bank i nside DRAM.

5. Write burst with Auto-Precharge is not allowed to be int errupted.

6. The eff ective burst l engt h of the first write equals two times the number of clock cycles between the first write and the interrupti ng write.

5.4.7 Burst Terminate

The Burs t T erminate ( BST) c omm and is initia ted b y having C S_n LOW, CA0 HIG H, CA1 HI GH, C A2 LOW , and CA3

LOW at the rising edge of clock. A Burst Teminate command may only be issued to terminate an active Read or

Write burst. Therefore, a Burst Terminate command may only be issued up to and including BL/2 - 1 clock cycles

after a Read or Write command. The effective burst length of a Read or Write command truncated by a BST

command is as follows:

Effective burst length = 2 x {Number of clock cycles from the Read or Write Command to the BST command}

Note that if a read or wr ite bur st is trunc at ed w ith a B u rs t T erm inate ( B ST ) command, the eff ective burst len gth of the

truncated burst should be used as “BL” to calculate the minimum read to write or write to read delay.

The BST command only affects the most recent read or write command. The BST command truncates an ongoing

read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is

issued. The BST command truncates an on going write burst WL * tCK + tDQSS after the rising edge of the clock

where the Burst Terminate command is issued.

For LPDDR2-S4 devices, the 4-bit prefetch architecture allows the BST command to be issued on an even number

of clock cycles after a Write or Read command. Therefore, the effective burst length of a Read or Write command

truncated by a BST command is an integer multiple of 4.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 35 -

5.4.7.1 Burst Write Truncated by BST: WL = 1, BL = 16

CA0-9

[Cmd]

Nop BST

Nop

Nop Nop Nop Nop Nop

Write

WL=1

Bank M

Col Addr A Col Addr A

DIN A0 DIN A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

WL*tCK+tDQSS

CK_t / CK_c

DQS_c

DQS_t

DIN A2 DIN A3 DIN A4 DIN A5 DIN A6 DIN A7

BST not allowed

Notes:

1. The BST command truncat es an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command

is issued.

2. For LP DDR2-S 4 devices, BST can only be issued at even number of clock cycles after the Write command.

3. Addit i onal BST commands are not allowed after T 4 and may not be issued until after the next Read or Write command.

5.4.7.2 Burst Read Truncated by BST: RL = 3, BL = 16

CA0-9

[Cmd]

Nop BST

Nop

Nop Nop Nop Nop Nop

Read

RL = 3

Bank N

Col Addr A Col Addr A

T0 T1 T2 T3 T4 T5 T6 T7 T8

RL*t

DQSCK+

DQSQ

CK_t / CK_c

DQS_c

DQS_t

DOUT A2DOUT A1DOUT A0 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7

BST not allowed

Notes:

1. The BST command truncat es an ongoing read burst RL * tCK + tDQSCK + tDQSQ aft er the rising edge of t he clock where the Burst Terminate

command is issued.

2. For LP DDR2-S 4 devices, BST can only be issued at even number of clock cycles after the Read command.

3. Addit i onal BST commands are not allowed after T 4 and may not be issued until after the next Read or Write command.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 36 -

5.4.8 Write Data Mask

One write data mask (DM) pad for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the

implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given

cycle of the bur st. Da ta m ask has ident ical tim ings on write operat ions as the data b its, th ough us ed as inpu t on l y, is

internally loaded identically to data bits to insure matched system timing.

See 6.4.14.2 “Precharge & Auto Precharge Clarification” table for Write to Precharge timings.

5.4.8.1 Write Data Mask Timing

Data Mask Timing

DHtDS

tDS tDH

(ac)

(ac) V

(dc)

(dc) V

(ac)

(ac) V

(dc)

[Cmd]

WL = 2

Wirte t

DQSSmin

tDQSSmax

tWR

tWTR

01 2 3

0123

Case 2: max tDQSS

Case 1: min tDQSS

Data Mask Function,WL= 2, BL=4 shown,second DQ masked

DQS_c

DQS_t

CK_c

CK_t

DQS_c

DQS_t

DQS_c

DQS_t

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 37 -

5.4.9 Precharge Operation

The Prec harge comm and is used to pr echarge or close a ba nk that has been activat ed. The Prec harge com mand is

initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock.

The Precharge Command can be used to precharge each bank independently or all banks simultaneously. For 8-

bank devices, the AB flag, and the bank address bits, BA0, BA1, and BA2 are used to determine which bank(s) to

precharge. The bank ( s ) will be a va ilabl e f or a s ubsequent ro w ac c ess t RPab after an All-Bank Pr echar ge c om mand is

issued and tRPpb after a Single-Bank Precharge command is issued.

In order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank

devices, the Row Precharge time (tRP) for an All-Bank Precharge for 8-bank devices (tRPab) will be longer than the

Row Precharge time for a Single-Bank Precharge (tRPpb).

5.4.9.1 Bank Selection for Precharge by Address Bits

AB (CA4r) BA2 (CA9r) BA1 (CA8r) BA0 (CA7r) Precharged Bank(s)

8-bank device

0 0 0 0 Bank 0 only

0 0 0 1 Bank 1 only

0 0 1 0 Bank 2 only

0 0 1 1 Bank 3 only

0 1 0 0 Bank 4 only

0 1 0 1 Bank 5 only

0 1 1 0 Bank 6 only

0 1 1 1 Bank 7 only

1 DON’T CARE DON’T CARE DON’T CARE All Banks

5.4.10 Burst Read Operation Followed by Precharge

For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a Read

command. For an untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the

eff ective burs t lengt h. A new ba nk active ( com m and) m ay be is sued t o th e sam e ba nk af ter the Ro w Prec har ge tim e

(tRP). A precharge command cannot be issued until after tRAS is satisfied.

For LPDDR2-S4 devices, the minimum Read to Precharge spacing has also to satisfy a minim um analog time from

the rising clock edge that initiates the last 4-bit prefetch of a Read command. This time is called tRTP (Read to

Precharge).

For LPDDR2-S4 devices, tRTP begins BL/2 - 2 clock cycles after the Read command. If the burst is truncated by a

BST command or a Read command to a different bank, the effective “BL” shall be used to calculate when tRTP

begins.

See 6.4.14.2 “Precharge & Auto Precharge Clarification” table for Read to Precharge timings.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 38 -

5.4.10.1 Burst Read Followed by Precharge: RL = 3, B L = 8, RU(tRTP(min)/tCK) = 2

CA0-9

[Cmd]

Nop

Nop Nop Precharge Nop Nop Activate Nop

Read

RL = 3

Bank M

Col Addr A Col Addr A

DOUT A0 DOUT A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7

Bank M Bank M

Row Addr Row Addr

BL / 2 tRTP

tRP

CK_t / CK_c

DQS_c

DQS_t

5.4.10.2 Burst Read Followed by Precharge: RL = 3, B L = 4, RU(tRTP(min)/tCK) = 3

CA0-9

[Cmd]Nop

Nop NopPrecharge Nop NopActivate Nop

Read

DQS

RL = 3

Bank M

Col Addr A Col Addr A

DOUT A0 DOUT A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

DOUT A2 DOUT A3

Bank M Bank M

Row Addr Row Addr

BL / 2

tRTP=3 tRP

CK_t / CK_c

DQS_c

DQS_t

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 39 -

5.4.11 Burst Write Foll owed by Precharge

For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge

comm and m a y be is sued. This delay is kno wn as the write r ec o very time (tWR) referenced f r om the completion of the

burst write to t he precharg e command. No Prec harge comm and to the sam e bank should be is sued prior to the tWR

delay.

LPDDR2-S4 devices wr ite data to the ar ray in prefetc h quadruples (prefetch = 4). The beginning of an internal write

operation may only begin after a prefetch group has been latched completely. Therefore, the write recovery time (tWR)

starts at different boundaries.

The m inimum W rite to Precharge c omm and spacing to the s ame bank is WL + BL /2 + 1 + R U(tWR/tCK) clock cycles.

For an untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the effective burst

length.

See 6.4.14.2 “Precharge & Auto Precharge Clarification” table for Write to Precharge timings.

5.4.11.1 Burst Write Follwed by Precharge: WL = 1, BL = 4

CA0-9

[Cmd]

DQS

T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1

>=tRP

tWR

Bank A

Col Addr Col Addr Bank A

Row Addr

Bank A Row Addr

Nop

NopNop

Nop

Nop Precharge Activate

DIN A0 DIN A1 DIN A2 DIN A3

tDQSSmax

tDQSSmin

Completion of Burst Write

Case 1:with tDQSS(max)

Case 2:with tDQSS(min)

WL = 1

Write

CK_t / CK_c

DQS_c

DQS_t

DQS_c

DQS_t

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 40 -

5.4.12 Auto Precharge Operation

Before a new r ow in an active b ank c an be op ened, th e active bank m ust be pr echarge d using e ither th e Prec harge

command or the auto-precharge function. W hen a Read or a Write command is given to the LPDDR2 SDRAM, the

AP bit (C A0f) may be set to allow the active bank to automatically begin precharge at the earliest possible moment

during the burst read or write cycle.

If AP is LOW when the Read or Write command is issued, then normal Read or Write burst operation is executed

and the bank remains active at the completion of the burst.

If AP is HIG H when the R ead or W rite c ommand is issued, then the auto-prec h arge function is eng age d. T hi s f eatur e

allows the precharge op eration to be partially or com pletely hidden during burst read cycles (dependent upon Read

or Write latency) thus improving system performance for random data access.

5.4.13 Burst Read with A uto-Precharge

If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged.

LPDDR2-S4 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 - 2 +

RU(tRTP/tCK) clock cycles later than the Read with AP command, whichever is greater. Refer to section 6.4.14.2

“Precharge & Auto Precharge Clarification” table for equations related to Auto-Precharge for LPDDR2-S4.

A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied

simultaneously.

■ The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

■ The RAS cycle time (tRC) from the previous bank activation has been satisfied.

5.4.13.1 Burst Read with Auto-Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 2

CA0-9

[Cmd] NopNop Nop

Nop Nop Nop

Activate Nop

Read

RL = 3

Bank M

Col Addr A Col Addr A

DOUT A0 DOUT A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

DOUT A2 DOUT A3

Bank M

Row Addr Row Addr

BL / 2

tRTP >=tRPpb

CK_t / CK_c

DQS_c

DQS_t

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 41 -

5.4.14 Burst Write with Auto-Precharge

If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The

LPDDR2 SDRAM starts an Auto Prechar ge operation on the rising edge which is tWR cycles af ter the completion of

the burst write.

A new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied.

■ The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

■ The RAS cycle time (tRC) from the previous bank activation has been satisfied.

5.4.14.1 Burst Write w ith Auto-Precharge: WL = 1, BL = 4

CA0-9

[Cmd]

T0 T1 T2 T3 T4

tRPpb

tWR

Bank A

Col Addr Col Addr Bank A

Row Addr Row Addr

Nop

Nop Nop Activate

DIN A0 DIN A1 DIN A2 DIN A3

WL = 1

Write

T5 T6 T7 T8

Nop Nop

CK_t / CK_c

DQS_c

DQS_t

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 42 -

5.4.14.2 Precharge & Auto Precharge Clarification

From

Command

To Command

Minimum Delay between

“From Command” to “To Command”

Unit Notes

Read Precharge (to same Bank as Read)

BL/2 + max (2, RU( tRTP/tCK)) - 2 CLK 1

Precharge All

BL/2 + max (2, RU( tRTP/tCK)) - 2 CLK 1

BST

(for Reads)

Precharge (to same Ban k as R ead) 1 CLK 1

Precharge All 1 CLK 1

Read w/AP

Precharge (to same Bank as Read w/AP)

BL/2 + max (2, RU( tRTP/tCK)) - 2 CLK 1, 2

Precharge All

BL/2 + max (2, RU( tRTP/tCK)) - 2 CLK 1

Activate (to same Bank as Read w/AP)

BL/2 + max (2, RU( tRTP/tCK)) - 2 + RU(tRPpb/tCK) CLK 1

Write or Write w/ AP ( same ban k) lllegal CLK 3

Write or Write w/ AP ( differ ent bank) R L + BL/2 + RU(tDQSCKmax/tCK) - WL + 1 CLK 3

Read or Read w /AP (same bank) lllegal CLK 3

Read or Read w /AP (dif ferent bank) BL/2 CLK 3

Write Precharge (to same Bank as Write)

WL + BL/2 + RU(tWR/tCK) + 1 CLK 1

Precharge All

WL + BL/2 + RU(tWR/tCK) + 1 CLK 1

BST

(for Writes)

Precharge (to same Ban k as Write) WL + RU(tWR/tCK) + 1 CLK 1

Precharge All WL + RU(tWR/tCK) + 1 CLK 1

Write w/AP

Precharge (to same Bank as Write w/AP)

WL + BL/2+ RU(tWR/tCK) + 1 CLK 1

Precharge All

WL + BL/2 + RU(tWR/tCK) + 1 CLK 1

Activate (to same Bank as Write w/AP)

WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK) CLK 1

Write or Write w/ AP ( same ban k) lllegal CLK 3

Write or Write w/ AP ( differ ent bank) BL/2 CLK 3

Read or Read w /AP (same bank) lllegal CLK 3

Read or Read w /AP (dif ferent bank) WL + BL/2 + RU(t WTR/tCK) + 1 CLK 3

Precharge

Precharge (to same Bank as Precharge)

1 CLK 1

Precharge All

1 CLK 1

Precharge All

Precharge

1 CLK 1

Precharge All

1 CLK 1

Notes:

1. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all,

issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank.

2. Any command issued during the specified minimum delay time is illegal.

3. After Read with AP, seamless read operations to different banks are supported. After Write with AP, seamless write operations to different banks

are supported. Read w/AP and Write w/AP may not be interrupted or truncated.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 43 -

5.4.15 Refresh Command

The Ref resh c omm and is initiate d b y hav ing CS _n L OW , CA0 LOW, CA1 LOW, and C A2 HIGH at the risin g edge of

clock. Per Bank Ref resh is initiated b y havin g CA3 LOW at the rising edge of clo ck and All Bank Refresh is initia ted

by having CA3 HIGH at the rising edge of clock. Per Bank Refresh is only allowed in devices with 8 banks.

A Per Bank Refresh command, REFpb performs a refresh operation to the bank which is scheduled by the bank

counter in the memory device. The bank sequence of Per Bank Refresh is fixed to be a sequential round-robin:

“0-1-2-3-4-5-6-7-0-1-...”. The bank count is synchronized between the controller and the SDRAM upon issuing a

RESET com mand or at ev e r y exi t f rom self refresh, b y resettin g bank count to zero. T he b ank addres s ing f or t he Per

Bank Refresh count is the same as established in the single-bank Precharge command (See 6.4.9.1 “Bank

Selection for Precharge by Address Bits” table).

A bank must be idle before it can be refreshed. It is the responsibility of the controller to track the bank being

refr eshed by the Per Bank Refresh comm and.

As shown in 6.4.15.1 “Command Scheduling Separations Related to Refresh” table, the REFpb command may

not be issued to the memory until the following conditions have been met:

a) The tRFCab has been satisified after the prior REFab command

b) The tRFCpb has been satisified after the prior REFpb command

c) The tRP has been satisified after prior Precharge commands to that given bank

The tRRD has be en s at is f ie d af ter t h e pri or A CT IVATE command (if applica bl e, f or example after act ivat ing a r o w in a

different bank than affected by the REFpb command).

The target bank is inaccessable during the Per Bank Refresh cycle time (tRFCpb), however other banks within the

device are accessable and m ay be addr essed during the Per Bank Refresh cycle. Duri ng the REFpb oper ation, an y

of the banks other than the one being refreshed can be maintained in active state or accessed by a read or a write

command.

When the Per Bank refresh cycle has completed, the affected bank will be in the Idle state.

As shown in 6.4.15.1 “Command Sc heduling Separations Related to Refresh” table, after issuing REFpb:

a) The tRFCpb must be satisified before issuing a REFab command

b) The tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank

c) The tRRD must be satisified before issuing an ACTIVATE command to a different bank

d) The tRFCpb must be satisified before issuing another REFpb command

An All Bank Refresh command, REFab performs a refresh operation to all banks. All bank s have to be in Idle state

when REFab is issued (for instance, by Precharge all-bank command). REFab also synchronizes the bank count

between the co ntrol ler and the SD R AM to zero.

As shown in 6.4.15.1 “Command Scheduling Separations Related to Refresh” table, the REFab command m ay

not be issued to the memory until the following conditions have been met:

a) The tRFCab has been satisified after the prior REFab command

b) The tRFCpb has been satisified after the prior REFpb command

c) The tRP has been satisified after prior Precharge commands

When the All Bank refresh cycle has completed, all banks will be in the Idle state.

As shown in 6.4.15.1 “Command Sc heduling Separations Related to Refresh” table, after issuing REFab:

a) The tRFCab latency must be satisfied before issuing an ACTIVATE command

b) The tRFCab latency must be satisfied before issuing a REFab or REFpb command

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 44 -

5.4.15.1 Command Scheduling Separations Related to Refresh

Symbol minimum delay from to Note

tRFCab REFab REFab

Activate cmd to any bank

REFpb

tRFCpb REFpb REFab

Activate cmd to same bank as REFpb

REFpb

tRRD REFpb Activate cmd to different bank than REFpb

Activate REFpb affecting an idle bank (different bank than Activate) 1

Activate cmd to different bank than prior Activate

Note:

1. A bank must be in the Idle state before it is refreshed. Therefore, after Activate, REFab is not allowed and REFpb is allowed

only if it affects a bank which is in the Idle state.

5.4.16 LPDDR2 SDRAM Refresh Requirements

(1) Minimum number of Refresh commands:

The LPDDR2 SDRAM requires a minimum number of R Refresh (REFab) commands within any rolling Refresh

Window (tREFW = 32 mS @ MR4[2:0] = “011” or Tj ≤ 85°C). The required minimum number of Refresh commands

and resulting average refresh interval (tREFI) are give n in 7.6.1 “Refresh Requirement Parameters” table.

See Mode Register 4 for tREFW and tREFI refresh multipliers at different MR4 settings.

(2) Burst Refresh limitation:

To limit maximum current consumption, a maximum of 8 REFab commands may be issued in any rolling tREFBW

(tREFBW = 4 x 8 x tRFCab). This cond it ion does not app ly if REFpb com mands are used.

(3) Refresh Requirements and Self-Refresh:

If an y time within a ref resh windo w is s pent in Self -Refresh Mo de, the num ber of requ ired Ref res h comm ands in th is

particular window is reduced to:

R* = R - RU{tSRF / tREFI} = R - RU{R * tSRF / tREFW}; where RU stands for the round-up function.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 45 -

5.4.16.1 Definition of tSRF

CKE

tREFW

tSRF

Enter Self-Refresh

Exit Self-Refresh

Exit Self-Refresh Enter Self-Refresh

Enter Self-Refresh

Exit Self-Refresh

tREFW tSRF

tSRF

tSRF1 tSRF2

tREFW

tSRF=tSRF1+tSRF2

Several examples on how tSRF is caclulated:

A: with the time spent in Self-Refresh Mode fully enclosed in the Refresh Window (tREFW).

B: at Self-Refresh entry.

C: at Self-Refresh exit.

D: with several different invervals spent in Self Refresh during one tREFW interval.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 46 -

In contrast to JESD79 and JESD79-2 and JESD79-3 compliant SDRAM devices, LPDDR2-S4 devices allow

significant flexibiliy in scheduling REFRESH commands, as long as the boundary conditions above are met. In the

most straight forward case a REFRESH command should be scheduled every tREFI. In this case Self-Refresh may

be entered at any time.

The users may choose to deviate from this regular refresh pattern e.g., to enable a period where no refreshes are

required. As an example, using a 1Gb LPDDR2-S4 device, the user can choose to issue a refresh burst of 4096

REFRESH commands with the maximum allowable rate (limited by tREFBW) followed by a long time without any

REFRESH commands, until the refresh window is complete, then repeating this sequence. The achieveable time

without R EFRESH com mands is given b y tREFW - (R / 8) * tREFBW = tREFW - R * 4 * tRFCab.@ Tj ≤ 85°C this c an be

up to 32 mS - 4096 * 4 * 130 nS ≈ 30 mS.

While both - the regular and the burst/pause - patterns can satisfy the refresh requirements per rolling refresh

interval, if they are repeated in every subsequent 32 mS window, extreme care must be taken when transitioning

from one pattern to another to satisfy the refresh requirement in every rolling refresh window during the transition.

Figure of 6.4.16.3 shows an example of an allowable transition from a burst pattern to a regular, distributed pattern. If

this transition happens directly after the burst refresh phase, all rolling tREFW interval will have at least the required

number of refreshes.

Figure of 6.4.16.4 shows an example of a non-al lo wab le transition. I n t his c as e th e regular refr esh pat tern s t ar ts af ter

the completion of the pause-phase of the burst/pause refresh pattern. For several rolling tREFW intervals the

minimmun number of REFRESH commands is not satisfied.

The understanding of the pattern transition is extremly relevant (even if in normal operation only one pattern is

employed), as in Self-Refresh-Mode a regular, distributed refresh pattern has to be assumed, which is reflected in

the equation for R* above. Therefore it is recommended to enter Self-Refresh-Mode ONLY directly after the burst-

phase of a burst/pause refresh pattern as indicated in figure of 6.4.16.5 and begin with the burst phase upon exit

from Self-Refresh.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 47 -

5.4.16.2 Regular, Distributed Refresh Pattern

REFI

REFBW

0 mS

32 mS 64 mS 96 mS

Notes:

1. Compared to repetitive burst Refresh with subs equent Ref res h pause.

2. For an exampl e, in a 1Gb LPDDR2 device at Tj ≤ 85°C, the distributed refresh pattern would have one REFRESH command per 7.8 µS; the

burst refresh pattern would have an average of one refresh command per 0.52 µS followed by ≈30 mS without any REF RESH command.

5.4.16.3 Allowable Transition from Repetitive Bur st Refresh

tREFI tREFI

tREFBW tREFBW

0 mS 32 mS 64 mS 96 mS

Notes:

1. Shown with subsequent Refres h pause t o regular distri but ed Refres h patt ern.

2. For an exampl e, in a 1Gb LPDDR2 device at Tj ≤ 85°C, the distributed refresh pattern would have one REFRESH command per 7.8 µS; the

burst refresh pattern would have an average of one refresh command per 0.52 µS followed by ≈30 mS without any REF RESH command.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 48 -

5.4.16.4 NOT-Allowable Transition from Repetitive Burs t Refresh

tREFI tREFI

tREFBW tREFBW

0 mS 32 mS 64 mS 96 mS

tREFW=32mS

Not enough Refresh commands

In this refresh window!!

Notes:

1. Shown with subsequent Refres h pause t o regular distri but ed Refres h patt ern.

2. Only ≈2048 REFRESH commands (< R which is 4096) in the indicated tREFW window.

5.4.16.5 Recommended Self-Refresh Entry and Exit

REFBW

0 mS32 mS

Self-Refresh

Note:

1. In conjuncti on with a Burst/Pause Refresh patterns.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 49 -

5.4.16.6 All Bank Refresh Operation

>=t

RPab

Precharge Nop Nop REFab ANY

CA0-9

[Cmd]

CK_t / CK_c

T1 T2 T3 T4 Tx Tx+1 Ty Ty+1

Nop Nop

REFab

>=t

RFCab

>=t

RFCab

5.4.16.7 Per Bank Refresh Operation

CA0-9

[Cmd]

CK_t / CK_c

T0 T1 Tx Tx+1 Tx+2 Ty Ty+1 Tz Tz+1

>=tRPab >=tRFCpb >=tRFCpb

Activate command to Bank 1

Refresh to Bank 1

Refresh to Bank 0

ACT

AB Row A

Bank 1

Row A

REFpb

NOPNOP

Precharge

Notes:

1. In the beginning of this example, the REFpb bank is pointi ng to Bank 0.

2. Operations to other banks than the bank being refreshed are allowed during the tRFCpb period.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 50 -

5.4.17 Self Refresh Operation

The Self Refresh command can be used to retain data in the LPDDR2 SDRAM, even if the rest of the system is

powered down. When in the Self Refresh mode, the LPDDR2 SDRAM retains data without external clocking. The

LPDDR2 SDRAM dev ice has a bui lt-in t im er to acc omm odate Se lf Ref res h opera tion. T he Self R efres h Command is

defined b y hav in g CK E LO W, CS_n LOW, CA0 LOW , CA1 LOW, and CA2 HIGH at the r isi ng e dge of the c l o ck . CKE

must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following the

power-dow n com mand. On c e the c om mand is reg ister ed, C KE must be hel d LO W to keep the de vice in Se l f Refresh

mode.

LPDDR2-S4 devices can operate in S elf Refresh in b oth the Standard or Extended T em perature Ranges. L PDDR2-

S4 devices wil l also manage Self Ref r esh po wer c onsumpt ion when t he op erat in g t emperature changes , l o wer at lo w

temperatures and higher temperatures.

Once th e LPDDR2 SDRA M has ent ered Self Refresh m ode, a ll of the ex terna l signals except C KE, are “don’t c are”.

For proper s elf r efres h operation, power s uppl y pads (VDD1, VDD2, an d VDDCA) must be at val id levels. VDDQ may be

turned off during Self-Refresh. Prior to exiting Self-Refresh, VDDQ must be within specified limits. VrefDQ and VrefCA

may be at any level within minimum and maximum levels (see section 7.1 “Absolute Maximum DC Ratings” table).

However prior to exit Self-Refresh, VrefDQ and VrefCA must be within specified limits (see section 7.2.1.1

“Recommended DC Operating Conditions” table). The SDRAM initiates a minimum of one all-bank refresh

command internally within tCKESR period once it enters Self Refresh mode. The clock is internally disabled during

Self Refresh Operation to save power. The minimum time that the LPDDR2 SDRAM must remain in Self Refresh

mode is tCKESR. The user may change the external clock frequency or halt the external clock one clock after Self

Refres h entry is registered; however, the cloc k must be restarted an d stable befo re the device can ex it Self Refresh

operation.

The proc edure for exiting Self Refresh requires a sequence of c omm ands. First, the clock shall be stable and w ithi n

specif ied limits for a m inm um of 2 clock cycles pri or to CKE goi ng b ac k H IGH . O nce Self R ef res h Ex it is reg is ter ed, a

delay of at leas t tXSR m ust be sat isfied bef ore a v alid comm and can be issued to the device to a llow for an y interna l

refresh in progress. CKE must remain HIGH for the entire Self Ref resh exit per iod tXSR for proper operation except

for s elf ref r es h re-entry. NOP com mands m ust be r e gistered on eac h pos it ive c loc k edge durin g th e Self Ref r es h exit

interval tXSR.

The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when

CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh

command (8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 51 -

For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements

outlined i n section 6.4.16 “LPDD R2 SDR AM Refr esh Requirem ents”, since no ref resh oper ations ar e perf orm ed in

power-down mode.

2 tCK(min)

tIHCKE

tCKESR(min)

tISCKE

tIHCKE

Valid Enter SR NOP NOP NOP Valid

Exit SR

Input clock frequency may be changed

or stopped during Self-Refresh

Enter Self-Refresh Exit Self-Refresh

tXSR(min)

tISCKE

CKE

[Cmd]

CK_c

CK_t

CS_n

Figure of Self Refresh Operation

Notes:

1. Input cl ock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a minimum of 2 clocks of stable

clock are provided and the clock frequency is between the minim um and maximum frequency for the particul ar speed grad

2. Device must be in the “All banks idle” state pri or to entering S elf Refresh m ode.

3. tXSR begi ns at the rising edge of the clock after CKE is driven HIGH.

4. A valid command may be issued only after tXSR is satisfied. NOPs shall be issued during tXSR.

5.4.18 Par tial Arr ay Sel f-Refresh: Bank Masking

Each bank of LPDDR2 SDRAM can be independently configured whether a self refresh operation is taking place.

One mode register unit of 8 bits accessible via MRW command is assigned to program the bank masking status of

each bank up to 8 banks. For bank masking bit assignments, see section 6.3.13 Mode Register 16

“MR16_PASR_Bank Mask (MA [7:0] = 10H)”.

The mask bit to the bank controls a refresh operation of entire memory within the bank. If a bank is masked via MRW,

a refr esh op er ati on to the entire ba nk is block ed a nd d ata r e tent io n by a bank is n ot g uar an tee d in s e lf ref r esh mode.

To enable a refresh operation to a bank, a coupled mask bit has to be programmed, “unmasked”. When a bank mask

bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask bits.

5.4.19 Par tial Arr ay Sel f-Refresh: Segment Masking

Segment masking scheme may be used in place of or in combination with bank masking scheme in LPDDR2-S4

SDRAM. The number of segments differ by the density and the setting of each segment mask bit is applied across

all the bank s. For segm ent masking bit assignm ents , see section 6.3.14 Mode Re gister 1 7 “MR17_PASR_Segment

Mask (MA[7:0] = 11H)”.

For those refresh-enabled banks, a refresh operation to the address range which is represented by a segment is

blocked w hen the mask bit to this segment is pr ogramm ed, “masked” . Programm ing of segment mask bits is similar

to the one of bank mask bits.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 52 -

Table of Exa mple of Bank and Segment Masking use in LPDDR2-S4 devices

Segment Mask(MR 1 7) Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

BankMask (MR16) 0 1 0 0 0 0 0 1

Segment 0 0 - M - - - - - M

Segment 1 0 - M - - - - - M

Segment 2 1 M M M M M M M M

Segment 3 0 - M - - - - - M

Segment 4 0 - M - - - - - M

Segment 5 0 - M - - - - - M

Segment 6 0 - M - - - - - M

Segment 7 1 M M M M M M M M

Note:

This table illust rat es an example of an 8-bank LPDDR2-S4 device, when a refresh operation to bank 1 and bank 7, as well as segment 2 and

segment 7 are masked

5.4.20 Mode Register Read Command

The Mode Register Read command is used to read configuration and status data from mode registers. The Mode

at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r- CA4r}. The mode register

contents are availab le on t he first data b eat of DQ[0:7], RL * tCK + t DQSCK + tDQSQ after the ris ing edge of the clock

where the Mode Register Read Command is issued. Subsequent data beats contain valid, but undefined content,

except in the case of the DQ Calibration function DQC, where subsequent data beats contain valid content as

described in section 6.4.21.2 “DQ Calibration”. All DQS_t, DQS_c shall be toggled for the duration of the Mode

The MRR c om mand has a burs t le ngth of four. The Mode Register Re ad o per at io n (c ons isti ng of th e MR R c om mand

and the corresponding data traffic) shall not be interrupted. The MRR command period (tMRR) is 2 clock cycles.

Mode Re gister Reads t o reserved and write-only regis ters shall r eturn valid, but undefined c ontent on all dat a beats

and DQS_t, DQS_c shall be toggled.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 53 -

5.4.20.1 Mode Register Read Timing Example: RL = 3, tMRR = 2

CMD not allowed

T0 T1 T2 T3 T4 T5 T6 T7 T8

CA0-9

[Cmd]

[0-7]

[8-max]

tMRR = 2 tMRR = 2

RL = 3

Reg A Reg A Reg B Reg B

MRR MRR

DOUT A UNDEF DOUT B

UNDEF UNDEF UNDEF UNDEF UNDEF

UNDEFUNDEF

UNDEF

CK_t / CK_c

DQS_t

DQS_c

Notes:

1. Mode Register Read has a burst length of four.

2. Mode Register Read operat i on shall not be int errupt ed.

3. Mode Register dat a is valid onl y on DQ[0-7] on the first beat. Subsequent beats contain vali d, but undefined data. DQ[ 8-max] contai n valid, but

undefined data for the duration of the MRR burst.

4. The Mode Regist er Command period is tMRR. No c ommand (other than Nop) is allowed during this period.

5. Mode Register Reads t o DQ Calibration regist ers MR32 and MR40 are described in the section on DQ Calibration.

6. Minim um Mode Register Read to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycle s.

7. Minim um Mode Register Read to Mode Register Write late ncy is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles.

The MRR command shall not be issued earlier than BL/2 clock cycles after a prior Read command and WL + 1 +

BL/2 + RU( tWTR/tCK) clock cycles after a prior Write command, because read-bursts and write-bursts shall not be

truncated by MRR. Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the

effective burst length of the truncated burst should be used as “BL

”.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 54 -

5.4.20.2 Read to MRR Timing Example: RL = 3, tMRR = 2

CMD not allowed

T0 T1 T2 T3 T4 T5 T6 T7 T8

CA0-9

[Cmd]

[0-7]

[8-max]

BL / 2 tMRR = 2

RL = 3

BA M

Col Addr A Reg B Reg B

Read MRR

DOUT A0 DOUT B UNDEF UNDEF UNDEF

UNDEFUNDEF

Col Addr A

DOUT A1 DOUT A2 DOUT A3

DOUT A0 DOUT A1 DOUT A2 DOUT A3

CK_t / CK_c

DQS_c

DQS_t

Notes:

1. The minimum number of clocks from t he burst read command to the Mode Register Read command is BL/2.

2. The Mode Regist er Read Command period is tMRR. No c ommand (other than Nop) is allowed during this peri od.

5.4.20.3 Burs t Write Followed by MRR: RL = 3, WL = 1, BL = 4

T0 T1 T2 T3 T4 T5 T6 T7 T8

CA0-9

[Cmd]

BA N

Col Addr A Reg B Reg B

Write MRR

Col Addr A

DIN A0 DIN A1 DIN A2 DIN A3

CMD not allowed

WL = 1 tWTR

RL = 3

tMRR = 2

CK_t / CK_c

DQS_c

DQS_t

Notes:

1. The minimum number of clock cycles from the burst write command to the Mode Register Read command is [WL + 1 + BL/2 + RU( tWTR/tCK)].

2. The Mode Regist er Read Command period is tMRR. No command (other than Nop) is allowed during this period.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 55 -

5.4.21 Temperature Sensor

LPDDR2 SDRAM features a temperature sensor whose status can be read from MR4. This sensor can be used to

determine an appropriate refresh rate, determine whether AC timing derating is required in the Extended

Temperature Range and/or monitor the operating temperature. Either the temperature sensor or the device operating

temperature (See 7.2.3 “Operating Temperature Conditions” table) may be used to determ ine whether operating

temperature requirements are being met.

LPDDR2 devices shall monitor device temperature and update MR4 according to tTSI. Upon exiting self-refresh or

power-down, the device temperature status bits shall be no older than tTSI.

When using the temperature sensor, the actual device junction temperature may be higher than the operating

temperature specification (See 7.2.3 “Operating Temperature Conditions” table) that applies for the Standard or

Extended Temperature Ranges. For example, Tj may be above 85°C when MR4[2:0] equals 011b.

To assure proper operation using the temperature sensor, applications should consider the following factors:

TempGradient is the maximum temperature gradient experienced by the memory device at the temperature of

interest over a range of 2°C.

ReadInterval is the time period between MR4 reads from the system.

TempSensorInterval (tTSI) is maxim um delay betwee n intern al up dates of MR4.

SysRespDelay is the maximum time between a read of MR4 and the response by the system.

LPDDR2 de vices sha ll all ow for a 2°C tem perature m argin b etween th e point at which th e device t em peratur e enters

the Extended Temperature Range and point at which the controller re-configures the system accordingly.

In order to determine the required f requency of polling MR4, the s ystem shall use the maximum Tem pGradient and

the maximum response time of the system using the following equation:

TempGradient x (ReadInterval + tTSI + SysRespDelay) ≤ 2°C

Table of Temperature Sensor

Symbol Parameter Max/Min Value Unit

TempGradient System Temperature Gradient Max System Dependent °C/S

ReadInterval MR4 Read Interval Max System Dependent mS

tTSI Temperature Sensor Interval Max 32 mS

SysRespDelay System Response Delay Max System Dependent mS

TempMargin Device Temperature Margin Max 2 ºC

For example, if TempGradient is 10°C/s and the SysRespDelay is 1 mS:

10°C/s x (ReadInterval + 32mS + 1mS) ≤ 2°C

In this case, ReadInterval shall be no greater than 167 mS.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 56 -

5.4.21.1 Temperature Sensor Timing

Temp

Device

Temp

Margin

MR4

Trip Level

Temperature

Sensor

Update

Host

MR4 Read MRR MR4=0x03

MR4=0x03 MR4=0x86 MR4=0x86 MR4=0x86 MR4=0x86 MR4=0x06

Readlnterval

MRR MR4=0x86

tTSI

Time

SysRespDelay

2°C

< (tTSI + Readlnterval + SysRespDelay)

TempGradient

5.4.21.2 DQ Calibration

LPDDR2 device features a DQ Calibration function that outputs one of two predefined system timing calibration

patterns. A Mode Register Read to MR32 (Pattern “A”) or MR40 (Pattern “B”) will return the specified pattern on

DQ[0] and DQ[8] for x16 devices, and DQ[0], DQ[8], DQ[16], and DQ[24] for x32 devices.

For x16 devices, DQ[7:1] and DQ[15:9] may optionally drive the sam e information as DQ[0] or may drive 0b during

the MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same

information as DQ[0] or may drive 0b during the MRR burst.

For LPDDR2-S4 devices, MRR DQ Calibration commands may only occur in the Idle state.

Table of Data Calibration Patte rn Description

Pattern MR#

Bit Time 0

Bit Time 1

Bit Time 2

Bit Time 3

Description

Pattern A MR32 1 0 1 0 Read to MR32 return DQ calibr at ion patt ern A

Pattern B MR40 0 0 1 1 Read to MR40 return DQ calibr at ion patt ern B

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 57 -

5.4.21.3 MR32 and MR40 DQ Calibration Timing Example: RL = 3, tMRR = 2

CK_t / CK_c

CA0-9

[Cmd]

DQS_t

DQS_c

DQ[0]

DQ[7:1]

DQ[8]

DQ[16]

DQ[24]

DQ[15:9]

DQ[23:17]

DQ[31:25]

T0 T1 T2 T3 T4 T5 T6 T7 T8

x16

x32

Pattern “A” Pattern “B”

RL = 3

MRR

= 2

CMD not allowed Optionally driven the same as DQ0 or to 0b

Reg 32 Reg 32 Reg 40 Reg 40

MRR40

MRR32

11 1 1

1 1 11

1 1

0 0 0 0

0000

0 0 0 0

MRR

= 2

Notes:

1. Mode Regist er Read has a burst length of four.

2. Mode Register Read operat i on shall not be int errupt ed.

3. Mode Register Reads t o MR32 and MR40 drive valid data on DQ[0] during the entire burst. For x16 devices, DQ[8] shall drive the same

informat i on as DQ[0] during the burst. For x32 devices, DQ[8], DQ[16], and DQ[24] shall dri ve the same information as DQ[0] during t he burst.

4. For x16 devices, DQ[7: 1] and DQ[15:9] may optional l y drive the same information as DQ[0] or they may drive 0b during the burst.

For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0] or they may drive 0b

during the burst.

5. The Mode Regist er Command period is tMRR. No command (other than Nop) is allowed during this period.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 58 -

5.4.22 Mode Register Write Command

The Mode Register Write comm and is used to write configuration data to m ode registers. The Mode Register W rite

(MRW) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising

edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The data to be written to the mode

only registers shall have no impact on the functionality of the device.

For LPDDR2-S4 de vices, t he MRW may onl y be issu ed when all bank s are i n the i dle prec harge stat e. One method

of ensuring that the banks are in the idle precharge state is to issue a Precharge-All command.

5.4.22.1 Mode Register Write Timing Example: RL = 3, tMRW = 5

CMD not allowed

CA0-9

[Cmd]

CK_t / CK_c

T0 Tx Tx + 1 Tx + 2 Ty + 1 Ty + 2

MRW MRW ANY

MR Addr MR Data MR Data

MR Addr

tMRW

Notes:

1. The Mode Regist er Write Command period is tMRW. No command (other than Nop) is allowed during this period.

2. At time Ty, the device is in the idle state.

5.4.22.2 Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW)

Current State Command Intermediate State Next State

All Banks Idle MRR Mode Register Reading (All Banks Idle) All Banks Idle

MRW Mode Register Writing (All Banks Idle) All Banks Idle

MRW (RESET) Resetting (Device Auto-Initialization) All Banks Idle

Bank(s) Active MRR Mode Register Reading (Bank(s) Active) Bank(s) Active

MRW Not Allowed Not Allowed

MRW (RESET) Not Allowed Not Allowed

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 59 -

5.4.23 Mode Register Write Reset (MRW Reset)

Any MRW c omm and issued to MRW 63 init iates an M RW Reset. The MRW R eset com m and brings t he d evice to the

Device Auto-Initialization (Resetting) State in the Power-On Initialization sequence (see step 3 in sections 6.2.1

“Power Ramp and Device Initialization”). The MRW Reset command may be issued from the Idle state for

LPDDR2-S4 devices. This command resets all Mode Registers to their default values. No commands other than

NOP may be issued to the LPDDR2 device during the MRW Reset period (tINIT4). After MRW Reset, boot timings

must be observed until the device initialization sequence is complete and the device is in the Idle state. Array data

for LPDDR2-S4 devices are undefined after the MRW Reset command.

For the timing diagram related to MRW Reset, refer to 6.2.3 “Power Ramp and Initialization Sequence” figure.

5.4.24 Mode Register Write ZQ Calibration Command

The MRW command is also used to initiate the ZQ Calibration command. The ZQ Calibration command is used to

calibrate t he L PD D R2 o upu t dr i vers (R ON ) ov er pr oc ess, tem per atur e, an d volt age . LPD DR2-S 4 d ev ices s upp or t ZQ

Calibration.

There are four ZQ Calibration commands and related timings times, tZQINIT, tZQRESET, tZQCL, and tZQCS. tZQINIT

corresponds to the initialization calibration, tZQRESET for resetting ZQ setting to default, tZQCL is for long calibration,

and tZQCS is for short calibration. See Mode Register 10 (MR10) for description on the command codes for the

different ZQ Calibration commands.

The Initialization ZQ Calibration (ZQINIT) shall be performed for LPDDR2-S4 devices. This Initialization Calibration

achieves a RON accuracy of ±15%. After initialization, the ZQ Long Calibration may be used to re-calibrate the

system to a RON accuracy of ±15%. A ZQ Short Calibration may be used periodically to compensate for temperature

and voltage drift in the system.

The ZQReset Command resets the RON calibration to a default accuracy of ±30% across process, voltage, and

temperature. This command is used to ensure RON accuracy to ±30% when ZQCS and ZQCL are not used.

One ZQCS command can effectively correct a minimum of 1.5% (ZQCorrection) of RON impedance error within

tZQCS f or all s peed b ins as suming the maxim um sens itivities spec if ie d i n th e ‘Out put Driver V olt age and Temperature

Sensitivity’. The appropriate interval between ZQCS commands can be determined from these tables and other

application-specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage

(Vdriftr ate) drift rates that t he LPDDR2 is s ubject to in the applic ation, is illustr ated. The interval c ould be defined b y

the following formula:

) × ( + ) ×

(VdriftrateVSensTdriftrateTSens onZQCorrecti

where TSens = max(dRONdT) and VSens = max(dRONdV) define the LPDDR2 temperature and voltage

sensitivities.

For exam ple, if TSens = 0.75% / °C, VSens = 0.2 0% / mV, T driftrate = 1°C / s ec and Vdr iftrate = 15 m V / sec, the n

the interval between ZQCS commands is calculated as:

15) × (0.20 + 1) × (0.75 1.5

= 0.4s

For LPDDR2-S4 devices, a ZQ Calibration command may only be issued when the device is in Idle state with all

banks precharged.

No other activities can be performed on the LPDDR2 data bus during the calibration period (tZQINIT, tZQCL, tZQCS).

The qui et tim e on the LPD DR2 data bus helps to acc urately cal ibrate RO N. Ther e is no re quired qui et tim e after the

ZQ Reset c ommand. If multiple dev ices share a s ingle ZQ R esistor, onl y one devi ce ma y be calibrat ing at any give n

time. After calibration is achieved, the LPDDR2 device shall disable the ZQ pad’s current consumption path to

reduce power.

In systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQINIT, tZQCS, or

tZQCL between the devices. ZQ Reset overlap is allowed. If the ZQ resistor is absent from the system, ZQ shall be

connecte d to VDDCA. In this cas e, the L PDDR 2 devic e s hall ignore ZQ calibrat ion comm ands and the device will use

the default calibration settings (See section 7.2.6.5 “RONPU and RONPD Characteristics without ZQ Calibration”

Output Driver DC Elec tric al Charac ter ist ic s without ZQ Cal ibrat ion table).

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 60 -

5.4.24.1 ZQ Calibration Initialization Timing Example

CK_t / CK_c

CA0-9

[Cmd]

T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2

tZQINIT

CMD not allowed

MRW ANY

MR Addr MR Data

Notes:

1. The ZQ Calibrati on Init i alizat i on period is tZQINIT. No command (other than Nop) is allowed during this period.

2. CKE must be continuous l y registered HIGH duri ng the calibrat i on period.

3. All devices connected to the DQ bus should be high impedance during the calibrati on process.

5.4.24.2 ZQ Calibration Short Timing Example

CK_t / CK_c

CA0-9

[Cmd]

T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2

tZQCS

CMD not allowed

MRW ANY

MR Addr MR Data

Notes:

1. The ZQ Calibrati on Short peri od is tZQCS. No command (other than Nop) is allowed during this period.

2. CKE must be continuous l y registered HIGH duri ng the calibrat i on period.

3. All devices connected to the DQ bus should be high impedance during the calibrati on process.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 61 -

5.4.24.3 ZQ Calibration Long Timing Example

CK_t / CK_c

CA0-9

[Cmd]

T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2

tZQCL

CMD not allowed

MRW ANY

MR Addr MR Data

Notes:

1. The ZQ Calibrati on Long peri od is tZQCL. No c ommand (other than Nop) is allowed during this period.

2. CKE must be continuous l y registered HIGH duri ng the calibrat i on period.

3. All devices connect ed to the DQ bus should be high impedance during the calibration process.

5.4.24.4 ZQ Calibration Reset Timing Example

CK_t / CK_c

CA0-9

[Cmd]

T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2

ZQRESET

CMD not allowed

MRW ANY

MR Addr MR Data

Notes:

1. The ZQ Calibrati on Reset period is tZQRESET. No command (other than Nop) is allowed during this period.

2. CKE must be continuous l y registered HIGH duri ng the calibrat i on period.

3. All devices connected to the DQ bus should be high impedance during the calibrati on process.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 62 -

5.4.24.5 ZQ External Resistor Value, Tolerance, and Capacitive Loading

To us e the ZQ Ca librati on f unctio n, a 240 O hm ± 1% t oleranc e ex terna l res istor m ust be conn ected bet ween th e ZQ

pad and ground. A single resistor can be used for each LPDDR2 device or one resistor can be shared between

multiple LPDDR2 devices if the ZQ calibration timings for each LPDDR2 device do not overlap. The total capacitive

loading on the ZQ pad must be limited (See section 7.2.6.7 “Input/Output Capacitance” table).

5.4.25 Power-Down

For LPDDR2 SDRAM, power-down is s ynchronously entered when CKE is registered LOW and CS_n HIGH at the

rising edge of clock. CKE must be registered HIGH in the previous clock cycle. A NOP com mand must be driven in

the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register, read, or

write operations are in progress. CKE is allowed to go LOW while any of other operations such as row activation,

precharge, autopr ech arge, or ref resh is in pr ogres s, b ut power -dow n IDD spec w ill not be applied until fin ishing th ose

operations. Timing diagrams are shown in the following pages with details for entry into power down.

For LPDDR 2 SDRAM, if power-do wn occurs when all bank s are idle, this mode i s ref erred to as idle power- do wn; if

power-down occurs when there is a row active in any bank, this mode is referred to as active power-down.

Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c, and CKE. In power-down

mode, CKE must be maintained LOW while all other input signals are “Don’t Care”. CKE LOW must be maintained

until tCKE has been satisfied. VREF must be maintained at a valid level during power down.

VDDQ may be turned off during power down. If VDDQ is turned off, then VREFDQ must also be turned off. Prior to

exiting power down, both VDDQ and VREFDQ m ust be within their respective min/m ax operating ranges (See 7.2.1.1

“Recommended DC Operating Conditions” table).

For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements

outlined in section 6.4.16 “LPDDR2 SDRAM Refresh Requirements”, as no refresh operations are performed in

power-down mode.

The power-down state is exited when CKE is registered HIGH. The controller shall drive CS_n HIGH in conjunction

with CKE H IGH when exiting the power-down s tate. CKE HIG H must be m aintained u ntil tCKE has been satisfied. A

valid, executable command can be applied with power-down exit latency, tXP after CKE goes HI GH . Power-down ex it

latency is defined in section 7.7.1 “LPDDR2 A C Timing” table.

5.4.25.1 Basic Power Down Entry and Exit Timing

CK (min)

IHCKE

CKE(min)

ISCKE

IHCKE

Valid Enter

PD NOP Valid

Exit

Input clock frequency may be changed

or the input clock stopped during Power-Down

Enter Power-Down mode Exit Power-Down mode

XP(min)

ISCKE

CKE

[CMD]

CK_c

CK_t

CS_n

KE(min)

Valid

NOP

Note:

Input clock frequenc y may be changed or the input clock stopped during power-down, provided that upon exiting power-down, the clock is stabl e

and within specifi ed limits for a minmum of 2 clock cycles prior to power-down exit and the clock frequency is between the minimum and maximum

frequency for the particular speed grade.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 63 -

5.4.25.2 CKE Intensive Environment

CKE

tCKE

CK_c

CK_t

5.4.25.3 Refr esh to Refresh Timing with CKE Intensive Environment

CKE t

CKE

[Cmd]

REFI

REF

CK_c

CK_t

Note:

The pattern shown above can repeat over a long period of time. With this pattern, LPDDR2 SDRAM guarantees al l AC and DC timing & voltage

specificat i ons with temperat ure and voltage dri ft.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 64 -

5.4.25.4 Read to Power-Down Entry

T0 T1 T2 Tx Tx+1 Tx+2Tx+9

Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8

Tx+9Tx+8Tx+7Tx+6Tx+5Tx+4Tx+3Tx+2Tx+1

TxT2T1T0

RL t

ISCKE

Q Q Q Q

Read operation starts with a read command and

CKE should be kept HIGH until the end of burst operation.

CKE

[Cmd]

CKE

[Cmd]

CK_c

CK_t

DQS_t

DQS_c

DQS_t

DQS_c

Note:

CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Read command is Registered.

5.4.25.5 Read with Auto Precharge to Power-Down Entry

T0T1 T2 Tx Tx+1 Tx+2 Tx+9Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8

QQQQ

QQQQ Q Q Q Q

RDA

RDA PRE

PRE

Tx+9Tx+8Tx+7Tx+6Tx+4 Tx+5Tx+3Tx+2Tx+1

TxT2T1

[Cmd]

CKE

[Cmd]

CKE should be kept HIGH

until the end of burst operation.

CKE should be kept HIGH

until the end of burst operation.

BL = 4

BL = 8

Start internal precharge

BL/2

With tRTP = 7.5ns

& tRAS min satisfied

BL/2

With tRTP = 7.5ns

& tRAS min satisfied

ISCKE

CK_c

CK_t

DQS_t

DQS_c

DQS_t

DQS_c

Note:

CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Read command is registered.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 65 -

5.4.25.6 Write to Power-Down Entry

BL = 4

D D D D

DDD

ISCKE

[Cmd]

CKE

[Cmd]

CKE

T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx+6Tx Tx+1 Tx+2 Tx+4 Tx+5

Tx+2 Tx+3 Tx+4Tx+1TxTm+5Tm+4Tm+3Tm+2

Tm+1

T1T0

CK_c

CK_t

DQS_t

DQS_c

DQS_t

DQS_c

Tx+3

ISCKE

BL = 8

Note:

CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK) clock cycles after the clock on which the Write command is registered.

5.4.25.7 Write with Auto Precharge to Power-Down Entry

WRA

BL = 4

D D D D

DDD

WRA

[Cmd]

CKE

[Cmd]

CKE

T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2

Tx+2 Tx+3 Tx+4

Tx+1Tx

Tm+5Tm+4

Tm+3

Tm+2

Tm+1

TmT1

Tx+3 Tx+4 Tx+5 Tx+6

PRE

Start Internal Precharge

CK_c

CK_t

CK_c

CK_t

DQS_t

DQS_c

DQS_t

DQS_c

ISCKE

BL = 8

Note:

CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK) + 1 clock cycles after the Write command is registered.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 66 -

5.4.25.8 Refresh Command to Power-Down Entry

T0 T1T2 T3 T4 T5 T6 T7T8T9T10 T11

REF

IHCKE

ISCKE

CKE

[Cmd]

CK_c

CK_t

Note:

CKE may go LOW tIHCKE after the clock on which the Refresh command is registered.

5.4.25.9 Activate Command to Power-Down Entry

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9T10 T11

ACT

tIHCKE tISCKE

CKE

[Cmd]

CK_c

CK_t

Note:

CKE may go LOW tIHCKE after the clock on which the Activate command is registered.

5.4.25.10 Precharge/Precharge-All Command to Power-Down Entry

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

PRE

tIHCKE tISCKE

CKE

[Cmd]

CK_c

CK_t

Note:

CKE may go LOW tIHCKE after the clock on which the Precharge/Precharge-Al l command is registered.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 67 -

5.4.25.11 Mode Register Read to Power-Down Entry

T0 T1 T2 Tx Tx+1 Tx+2 Tx+9

Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8

tISCKE

MRR

Q Q Q Q

Mode Register Read operation starts with a MRR command and

CKE should be kept HIGH until the end of burst operation.

CK_c

CK_t

DQS_t

DQS_c

[Cmd]

CKE

Note:

CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Mode Register Read command is

registered.

5.4.25.12 MRW Command to Power-Down Entry

T0T1T2T3 T4 T5 T6 T7 T8 T9 T10 T11

MRW

ISCKE

CKE can go to LOW tMRW after a Mode Register Write command

CKE

[Cmd]

MRW

CK_c

CK_t

Note:

CKE may be registered LOW tMRW after the clock on which the Mode Register Write command is registered.

5.4.26 Deep Power-Down

Deep Power-D own is e nter ed when CK E is regis ter ed LOW with CS _n LOW, CA0 HIG H, CA1 H IGH, and C A2 LOW

at the risin g edge of clock . A NOP comm and mus t be driven in the cloc k cycle fol lowing the power-down command.

CKE is not allowed to go LOW while mode register, read, or write operations are in progress. All banks must be in

idle sta te with no activity on th e data bus prior to e ntering the De ep Power D own m ode. During De ep Power-Down,

CKE must be held LOW.

In Deep Po wer -Do wn mode, all input buf f er s ex c ept CKE, al l out put b uf f er s , and the po wer supply to interna l circuitry

may be disabled within the SDRAM. All power supplies must be within specified limits prior to exiting Deep Power-

Down. VrefDQ and VrefCA may be at any level within minimum and maximum levels (See 7.1 “Absolute Maximum

DC Ratings”). However prior to exiting Deep Power-Down, Vref must be within specified limits (See 7.2.1.1

“Recommended DC Operating Conditions”).

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 68 -

The contents of the SDRAM may be lost upon entry into Deep Power-Down mode.

The Deep Po wer-Do wn sta te is ex ited when C KE a nd CS_n ar e re gister ed HIGH, whil e m eeting tISCKE with a stable

clock input. The SDRAM must be fully re-initialized by controller as described in the Power up initialization

Sequence. The SDRAM is ready for normal operation after the initialization sequence.

5.4.26.1 Deep Power Down Entry and Exit Timing

2 tCK (min)

tDPD

tISCKE

tIHCKE

NOP Enter

DPD NOP Reset

Exit

DPD

Input clock frequency may be changed

or the input clock stopped during Deep Power-Down

Enter Deep Power-Down mode Exit Deep Power-Down mode

tISCKE

CKE

[Cmd]

CS_n

NOP

tINIT3 = 200 μs (min)

NOP

CK_c

CK_t

tRP

Notes:

1. Init i alizat i on sequenc e may start at any time after TC.

2. tINIT3 and TC refer to timings in the LPDDR2 initiali zat i on sequence. For more detail, see section 6.2 “Power-up, Init ia lization, and Power-

Off”.

3. Input cl ock frequency may be changed or the input clock stopped during deep power-down, provided that upon exiting deep power-down, t he

clock is stable and within specified limits for a minmum of 2 clock cycles prior to deep power-down exit and the clock frequency is between the

minimum and maximum frequency for the particul ar speed grade.

5.4.27 Input Clock Stop and Frequency Change

LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions:

• tCK(abs)min is met for each clock cycle;

• Refresh Requirements apply during clock frequency change;

• During clock frequency change, only REFab or REFpb commands may be executing;

• Any Activate, or Precharge commands have executed to completion prior to changing the frequency;

• The related timing conditions (tRCD, tRP) have been met prior to changing the frequency;

• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH.

After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to

set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target

clock frequency.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 69 -

LPDDR2 devices support clock stop during CKE LOW under the following conditions:

• CK_t is held LOW and CK_c is held HIGH during clock stop;

• Refresh Requirements apply during clock stop;

• During clock stop, only REFab or REFpb commands may be executing;

• Any Activate, or Precharge commands have executed to completion prior to stopping the clock;

• The related timing conditions (tRCD, tRP) have been met prior to stopping the clock;

• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH.

LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions:

• tCK(abs)min is met for each clock cycle;

• Refresh Requirements apply during clock frequency change;

• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have

executed to completion, including any associated data bursts prior to changing the frequency;

• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to changing the

frequency;

• CS_n shall be held HIGH during clock frequency change;

• During clock frequency change, only REFab or REFpb commands may be executing;

• The LPDDR2 device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of

2tCK + tXP.

After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc.

These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.

LPDDR2 devices support clock stop during CKE HIGH under the following conditions:

• CK_t is held LOW and CK_c is held HIGH during clock stop;

• CS_n shall be held HIGH during clock clock stop;

• Refresh Requirements apply during clock stop;

• During clock stop, only REFab or REFpb commands may be executing;

• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have

executed to completion, including any associated data bursts prior to stopping the clock;

• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to stopping the clock;

• The LPD DR 2 de vice is r e ad y for normal operat ion after the c lock is restar ted an d s atis f ies t CH(abs) and tCL(abs) for a

minimum of 2tCK + tXP.

5.4.28 No Operation Command

The purpos e of the No O peration com mand (NOP) is to prevent the L PDDR2 de vice fr om registering any un wanted

command between operations. Only when the CKE level is constant for clock cycle N-1 and clock cycle N, a NOP

command may be issued at clock cycle N. A NOP command has two possible encodings:

1. CS_n HIGH at the clock rising edge N.

2. CS_n LOW and CA0, CA1, CA2 HIGH at the clock rising edge N.

The No Operation command will not terminate a previous operation that is still executing, such as a burst read or

write cycle.

5.5 Truth Tabl es

The truth tables provide complementary information to the state diagram, they clarify the device behavior and the

applied restrictions when considering the actual state of all the Banks.

Operation or timing that is not s pec if ied is ille gal , and af t er s uc h an event, i n or de r to guaran tee pr o per op eration, the

LPDDR2 device must be powered down and then restarted through the specified initialization sequence before

normal operation can continue.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 70 -

5.5.1 Command Truth Table

Command Command Pads DDR CA Pads (10)

CK_t

EDGE

CKE CS_N

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CK_t(n-1)

CK_t(n)

MRW H H L L L L L MA0 MA1 MA2 MA3 MA4 MA5

X MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7

MRR H H L L L L H MA0 MA1 MA2 MA3 MA4 MA5

X MA6 MA7 X

Refresh

(per bank)11 H H L L L H L X

X X

Refresh

(all bank) H H L L L H H X

X X

Enter

Self Refresh

H L L L L H X

X X X

Activate

(bank) H H L L H R8 R9 R10 R11 R12 BA0 BA1 BA2

X R0 R1 R2 R3 R4 R5 R6 R7 R13 R14

Write

(bank) H H L H L L RFU RFU C1 C2 BA0 BA1 BA2

X AP*3,4 C3 C4 C5 C6 C7 C8 C9 C10 C11

Read

(bank) H H L H L H RFU RFU C1 C2 BA0 BA1 BA2

X AP*3,4 C3 C4 C5 C6 C7 C8 C8 C10 C11

Precharge

(per bank, all bank) H H L H H L H AB X X BA0 BA1 BA2

X X

BST H H L H H L L X

X X

Enter Deep

Power Down

H L L H H L X

X X X

NOP H H L H H H X

X X

Maintain

PD,SREF,DPD

(NOP) L L L H H H X

X X

NOP H H H X

X X

Maintain

PD,SREF,DPD

(NOP) L L H X

X X

Enter

Power Down

H L H X

X X X

Exit PD,

SREF,DPD

L H H X

X X X

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 71 -

Notes:

1. All LPDDR2 c ommands are defined by states of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock.

2. For LPDDR2 SDRAM, Bank addresses BA0, BA1 , BA2 (BA) determine which bank is to be operated upon.

3. AP is signif icant only to SDRAM.

4. AP “high” during a READ or WRITE command indicates that an auto-precharge will occur to the bank associat ed with the READ or WRITE

command.

5. “X” means “H or L (but a defined logic level)”.

6. Self refresh exit and Deep Power Down exit are asynchronous.

7. VREF must be between 0 and VDDQ during Self Refresh and Deep Power Down operation.

8. CAxr refers to command/ address bit “x” on the rising edge of clock.

9. CAxf refers to comm and/addres s bit “x” on the falling edge of clock.

10. CS_n and CKE are sampled at the rising edge of clock.

11. Per Bank Ref resh is only allowed in devices with 8 banks.

12. The least-s i gnificant c ol umn address C0 is not transmitted on the CA bus, and is implied to be zero.

13. AB “high”during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is do-not-care.

5.5.2 CKE Truth Table

Notes:

1. “CKEn” is the logic state of CKE at clock rising edge n; “CKEn-1” was the state of CKE at the previous clock edge.

2. “CS_n” is the logic stat e of CS_n at the clock rising edge n;

3. “Current state” is the state of the LPDDR2 device immediately prior to clock edge n.

4. “Comm and n” is the command regist ered at clock edge N, and “Operation n” is a result of “Command n”.

5. All states and sequenc es not shown are illegal or reserved unless explicit l y desc ri bed elsewhere in this docum ent.

6. Power Down exit tim e (tXP) should el apse before a command other than NOP is issued.

7. Self-Refresh exit t ime (t XSR) should elapse before a command other than NOP is issued.

8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Func tional Descripti on.

9. The cl ock must toggle at least once during the tXP period.

10. The cl ock must toggle at least once during the tXSR time.

11. X’ means ‘Don’t care’.

12. Upon exiting Resetting Power Down, the device will ret urn to the Idle state if tINIT5 has expired.

Device C urrent S tate*3

CKEn-1*1

CKEn*1

CS_n*2

Command n*4

Operation n*4

Device N ext St ate

Notes

Active Power Down L L X X Maintain Active Power Down Active Power Down

L H H NOP Exit Active Power Down Active 6, 9

Idle Power Down L L X X Maintain Idle Power Down Idle Power Down

L H H NOP Exit Idle Power Down Idle 6, 9

Resetting Power Down L L X X Maintain

Resetting Power Down Resetting

Power Down

L H H NOP Exit Resetting Power Down Idle or Resetting 6, 9, 12

Deep Power Down L L X X Maintain

Deep Power Down Deep Power Down

L H H NOP Exi t D eep Power Down Power On 8

Self Refresh

Maintain Self Refresh

Self Refresh

L H H NOP Exit Self Refresh Idle 7, 10

Bank(s) A ctive H L H NOP Enter

Active Power Down Active Power Down

All Banks Idle

H L H NOP Enter

Idle Power Down Idle Power Dow

H L L Enter

Self Refresh Enter

Self Refresh Self Refresh

H L L Deep Power Down

Enter

Deep Power Down Deep Power Down

Resetting H L H NOP Enter

Resetting Power Down Resetting Power Down

Others states H H Refer to the Command Truth Table

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 72 -

5.5.3 Current State Bank n - Command to Bank n Truth Table

Current

State Command Operation Next State Notes

Any NOP Continue prev ious operation Current S tate

Idle

ACTIVATE Select and activate row Active

Refresh (Per Bank) Begin to refresh Refreshing(Per Bank) 6

Refresh (All Bank) B egin to ref resh R efreshing( All Bank) 7

MRW Load value to Mode R egister M R Writing 7

MRR Read value from Mode R egister Idle M R R eading

Reset Begin Dev ice Auto-Initialization Resetting 7, 8

Precharge Deactivate row in ba nk or ban ks Precharging 9, 15

Row Active

Read Select column, and st ar t read b ur st Reading

Write Select column, and st ar t write burst Writing

MRR Read value from Mode R egister Active MR Reading

Precharge Deactiv ate row in bank or banks Precharging 9

Reading

Read Select column, and st ar t new read burst Reading 10, 11

Write Select column, and st ar t write burst Writing 10, 11, 12

BST Read burst terminate Active 13

Writing

Write Select column, and st ar t new write burst Writing 10, 11

Read Select column, and st ar t read b ur st Reading 10, 11, 1 4

BST Wr ite burst terminate Active 13

Power On Reset Begin Device Auto-Initialization Resetting 7, 9

Resetting MRR Read value from Mode Register Resetting MR Reading

Notes:

1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Power Down.

2. All states and sequenc es not shown are illegal or reserved.

3. Current St ate Def i niti ons:

Idle: The bank or banks have been precharged, and tRP has been met.

Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accessesare in progress.

Reading: A Read burst has been initiated, with A uto Precharge disabled, and has not yet terminated or been termi nated.

Writing: A Write burst has been initiat ed, with Auto Precharge disabled, and has not yet termi nated or been terminated.

4. The foll owing stat es must not be interrupted by a command issued to the same bank. NOP commands or allowable commands to the other

bank should be issued on any clock edge occurring during these states. Allowable commands to the other banks are determi ned by its current

state and 6.5.3 “Current State Bank n - Command to Ban k n Truth Table”, and according to 6.5.4 “Current State Bank n - Command to

Bank m Truth Table”.

Precharging: starts with the registration of a Precharge command and ends when tRP is m et. Once tRP is met, the bank will be in the idle

state.

Row Activating: starts with registration of an Activate command and ends when tRCD is met. Once tRCD is met, the bank will be in the

‘Active’ state .

Read with AP Enabled: starts with the regist ration of the Read comm and with Auto Precharge enabled and ends when t RP has been met.

Once tRP has been met, the bank will be in t he idle st ate.

Write with AP Enabled: starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once

tRP is met, the bank will be in the idle state.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 73 -

5. The foll owing stat es must not be interrupted by any executable command; NOP commands must be applied to each positive clock edge

during these states.

Refreshing (Per Bank): starts with registration of a Refresh (Per Bank) command and ends when tRFCpb is m et. Onc e tRFCpb is met, the

bank will be in an ‘idle’ state.

Refreshing (All Bank): starts with registration of a Refresh (All Bank) command and ends when tRFCab is met. Once tRFCab is met, the

device will be in an ‘all banks idle’ state.

Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once t MRR has been met, the bank

will be in the Idle state.

Resetti ng MR Reading: starts with the registrati on of a MRR command and ends when tMRR has been met. Once tMRR has been m et, the

bank will be in the Resetting state.

Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the

bank will be in the Active state.

MR Writing: starts with the registrat ion of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will

be in the Idle state.

Precharging A l l : s t arts with the regist ration of a Precharge-All command and ends when tRP is met. Once t RP is met, the bank will be in the

idle state.

6. Bank-specific; requires that the bank is idle and no bursts are in progress.

7. Not bank-spec ific; requires that all banks are idle and no bursts are in progress.

8. Not bank-spec ific reset command is achieved through Mode Register W rite command.

9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid stat e for pre- charging.

10. A command other than NOP should not be issued to the same bank while a Read or Write burst with Auto Precharge is enabled.

11. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled.

12. A Write command may be applied after the completion of the Read burst; otherwise, a BST must be used to end the Read prior to asserting a

Write command.

13. Not bank-specific. Burst Termi nat e (BST) command affects t he most recent read/write burst started by the most recent Read/Write command,

regardless of bank.

14. A Read command may be applied after the completion of the Write burst; ot herwise, a BST must be used to end the Write prior to asserting a

Read command.

15. If a Precharge command is issued to a bank in the Idle state, tRP shall still apply.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 74 -

5.5.4 Current State Bank n - Command to Bank m Truth Table

Current State of

Bank n

Command

for

Bank m Operation Next State for

Bank m Notes

Any NOP Continue prev ious operation Current S tate of B ank m

Idle Any Any command allowed to Bank m - 18

Row Activ ating,

Active, or

Precharging

Activate Select and activ ate row in Bank m Active 7

Read Select column, and st ar t read b ur st from Bank m Reading 8

Write Select column, and st ar t write burst to Bank m Writing 8

Precharge Deactiv ate row in bank or banks Precharging 9

MRR Read value from Mode R egister Idle MR Reading or

Active MR Readin 10, 11,

BST Read or Write burst terminate an ongoing

Read/ Write from/to Bank m Active 18

Reading

(Autoprecharge

disabled)

Read Select column, and st ar t read b ur st from Bank m Reading 8

Write Select column, and st ar t write burst to Bank m Writing 8, 14

Activate Select and activ ate row in Bank m Active

Precharge Deactiv ate row in bank or banks Precharging 9

Writing

(Autoprecharge

disabled)

Read Select column, and st ar t read b ur st from Bank m Reading 8, 16

Write Select column, and st ar t write burst to Bank m Writing 8

Activate Select and activ ate row in Bank m Active

Precharge Deactiv ate row in bank or banks Precharging 9

Reading wit h

Autoprecharge

Read Select column, and st ar t read b ur st from Bank m Reading 8, 15

Write Select column, and st ar t write burst to Bank m Writing 8, 14, 15

Activate Select and activ ate row in Bank m Active

Precharge Deactiv ate row in bank or banks Precharging 9

Writing with

Autoprecharge

Read Select column, and st ar t read b ur st from Bank m Reading 8, 15, 16

Write Select column, and st ar t write burst to Bank m Writing 8, 15

Activate Select and activ ate row in Bank m Active

Precharge Deactiv ate row in bank or banks Precharging 9

Power On Reset Begin Device Auto-Initialization Resetting 12, 17

Resetting MRR Read value from Mode Register Resetting MR Reading

Notes:

1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power

Down.

2. All states and sequenc es not shown are illegal or reserved.

3. Current St ate Def i niti ons:

Idle: the bank has been precharged, and tRP has been met.

Active: a row in the bank has been activated, and tRCD has been met. No data bursts/acc esses and no register accesses are in progress .

Reading: a Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Writing: a Writ e burst has been initiated, with Auto Precharge dis abl ed, and has not yet terminated or been terminated.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 75 -

4. Refresh, S elf-Refresh, and Mode Register Write commands may only be issued when all bank are idle.

5. A Burst Terminate (BST ) command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. The foll owing stat es must not be interrupted by any executable command; NOP commands must be applied during each clock cycle while in

these states:

Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once t MRR has been met, the bank

will be in the Idle state.

Resetti ng MR Reading: starts with the registrati on of a MRR command and ends when tMRR has been met. Once tMRR has been m et, the

bank will be in the Resetting state.

Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the

bank will be in the Active state.

MR Writing: starts with the regist ration of a MRW command and ends when tMRW has been met. Once t MRW has been met, the bank will

be in the Idle state.

7. tRRD must be met between Activate command to Bank n and a subsequent Activate command to Bank m.

8. Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and Writes with Auto

Precharge disabled.

9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre- charging.

10. MRR is allowed during the Row Activating state (Row Activati ng st arts with regis t ration of an Activat e command and ends when tRCD is met).

11. MRR is allowed during the Precharging s t ate. (Precharging starts with registration of a Precharge command and ends when tRP is met.

12. Not bank-spec ific; requires that all banks are idle and no bursts are in progress.

13. The next state f or Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The reader shall note that

the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating st ate and Precharging, the next state may

be Active and Precharge dependent upon tRCD and tRP respectively.

14. A Write command may be applied after the compl etion of the Read burst; otherwise a BST must be issued to end the Read prior to asserting a

Write command.

15. Read with auto precharge enabl ed or a Write with auto precharge enabled may be followed by any valid command to other banks provided

that the timing restrictions in 6.4.14.2 “Precharge & Auto Precharge Clarification” table are followed.

16. A Read command may be applied after the completion of the Write burst; ot herwise, a BST must be issued to end the Write prior to asserting

a Read command.

17. Reset command is achieved through Mode Register Write command.

18. BST is all owed only if a Read or Write burst is ongoing.

5.5.5 Data Mask Trut h Tabl e

Name (Functional) DM DQs Note

Write enable L Valid 1

Write inhibit H X 1

Note:

1. Used to mask write data, provided coi nci dent with the corres pondi ng data.

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6. ELECTRICAL CHARACTERISTIC

6.1 Absolute Maximum DC Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and

functional operation of the device at these or any other conditions above those indicated in the operational sections

of this s pecification is not implied. Exp osure to abso lute max imum rating conditio ns for extende d periods m ay af fect

reliability.

Parameter Symbol Min Max Units Notes

VDD1 supply voltage relative to VSS VDD1 -0.4 +2.3 V 2

VDD2 supply voltage relative to VSS VDD2 -0.4 +1.6 V 2

VDDCA supply voltage relative to VSSCA VDDCA -0.4 +1.6 V 2, 4

VDDQ supply voltage relative to VSSQ VDDQ -0.4 +1.6 V 2, 3

Voltage on any ball relative to VSS VIN, VOUT -0.4 +1.6 V

Storage Temperature TSTG -55 +125 °C 5

Notes:

1. Stress es great er than those list ed under “Absol ute Maximum Ratings” may c ause permanent damage to the device. This is a stress rat ing

only and functional operation of t he device at t hese or any other conditions above those indicated in the operational sections of this

specificat i on is not implied. Exposure to absolute maxim um rati ng conditions f or extended periods may affect reliabil i ty.

2. See “Power Ramp” in section 6.2.1 “Pow er Ramp and Device Initialization” for rel ationships between power supplies.

3. VREFDQ ≤ 0.6 x VDDQ; however, V REFDQ may be ≥ VDDQ provided that VREFDQ ≤ 300mV.

4. VREFCA ≤ 0. 6 x VDDCA; however, VREFCA may be ≥ VDDCA provided that VREFCA ≤ 300mV.

5. Storage T emperature is the junction temperat ure of the LPDDR2 device.

6.2 AC & DC Operating Conditions

Operation or timing that is not s pec if ied is ille gal , and after s uc h an event, in or de r to guaran tee pr o per op eration, the

LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence before

normal operation can continue.

6.2.1 Recommended DC Operating Conditions

6.2.1.1 Recommended DC Operating Conditions

Symbol LPDDR2-S4B DRAM Unit

Min Typ Max

VDD1 1.70 1.80 1.95 Core Power 1 V

VDD2 1.14 1.20 1.30 Core Power 2 V

VDDCA 1.14 1.20 1.30

Input Buffer Power V

VDDQ 1.14 1.20 1.30 I/O Buffer Power V

Note: VDD1 uses significan tly less power than VDD2.

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6.2.2 Input Leakage Current

Parameter/Condition Symbol Min Max Unit Notes

Input Leakage current

For CA, CKE, CS _n, CK_t, CK_c

Any input 0V ≤ VIN ≤ VDDCA

(All other pads not under test = 0V)

IL -2 2 µA 2

VREF supply leakage current

VREFDQ = VDDQ/2 or VREFCA = VDDCA/2

(All other pads not under test = 0V) IVREF -1 1 µA 1

Notes:

1. The minimum limit requirem ent is for testi ng purposes. The leakage current on VREFCA and VREFDQ pads should be minimal.

2. Alt hough DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification.

6.2.3 Operating Temperature Conditions

Parameter/Condition Symbol Min Max Unit

Standard Tj -40 85 °C

Extended 85 105 °C

Notes:

1. Operating Temperature is the junction temperature of the LPDDR2 device.

2. Some appl ications require operation of LPDDR2 in the maximum temperature conditons in the Extended Temperature Range between 85°C

and 105°C. For LPDDR2 devices, some derating is necc essary to operate in this range. See the MR4 Device Temperature (MA[7: 0] = 04h)

table.

3. Either the device operating temperature or the temperature sensor (See section 6.4.21 “T emperature Sensor”) may be used to set an

appropriate refres h rat e, determi ne the need for AC timing derating and/or monitor the operating temperature. When using the temperature

sensor, the actual device junction temperat ure may be higher than the Tj rating that applies for the Standard or Extended Temperature Ranges.

For example, Tj may be above 85ºC when the tem perat ure sens or indicat es a temperature of less than 85°C.

4. All parts list in sect i on 3 ordering informat i on table will not guarantee to meet AC specification in the range of extended temperature range.

6.2.4 AC and DC Input Measurement Levels

6.2.4.1 AC and DC Logic Input Levels for Single-Ended Signal s

6.2.4.1.1 Single-Ended AC and DC Input Levels for CA and CS_n Inputs

Symbol Parameter LPDDR2-800/1066 Unit Notes

Min Max

VIHCA(AC) AC input logic high Vref + 0.220 N ote 2 V 1, 2

VILCA(AC) AC input logic low Note 2 Vref - 0.220 V 1, 2

VIHCA(DC) DC input logic high Vref + 0.130 VDDCA V 1

VILCA(DC) DC input logic low VSSCA Vref - 0.130 V 1

VRefCA(DC) Reference Voltage for CA and CS_n inputs 0.49 * VDDCA 0.51 * VDDCA V 3, 4

Notes:

1. For CA and CS_n input only pads. Vref = VrefCA(DC).

2. See section 7.2.5.5 “Overshoot and Undershoot Specifications”.

3. The ac peak noise on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than ± 1% VDDCA (for reference: approx.

± 12 mV).

4. For referenc e: approx. VDDCA/2 ± 12 mV.

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6.2.4.1.2 Single-Ended AC and DC Input Levels for CKE

Symbol

Parameter

Min

Max

Unit

Note

VIHCKE CKE Input High Lev el 0.8 * V DDCA Note 1 V 1

VILCKE CKE Input Low Level Note 1 0.2 * VDDCA V 1

Note 1: See section 7.2.5.5 “Overshoot and Undershoot Specifications”.

6.2.4.1.3 Single-Ended AC and DC Input Levels for DQ and DM

Symbol Parameter LPDDR2-1066/LPDDR2-800 Unit Notes

Min Max

VIHDQ(AC) AC input logic high Vref + 0.220 N ote 2 V 1, 2

VILDQ(AC) AC input logic low Note 2 Vref - 0.220 V 1, 2

VIHDQ(DC) DC input logic high Vref + 0.130 VDDQ V 1

VILDQ(DC) DC input logic low VSSQ Vref - 0.130 V 1

VRefDQ(DC) Reference Voltage for DQ , DM inputs 0.49 * VDDQ 0.51 * VDDQ V 3, 4

Notes:

1. For DQ input only pads. Vref = VrefDQ(DC).

2. See section 7.2.5.5 “Overshoot and Undershoot Specifications”.

3. The ac peak noise on VRefDQ may not allow VRefDQ to deviate from VRefDQ(DC) by more than ± 1% VDDQ (for reference: approx.

±12 mV).

4. For referenc e: approx. VDDQ/2 ± 12 mV.

6.2.4.2 Vref Tolerances

The DC tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in below

“VRef(DC) Tolerance an d VRef AC-Noise Limits” figure. It shows a valid refere nce voltage VRef(t) as a function of

time. (VRef stands for VRefCA and VRefDQ likewise). VDD stands for VDDCA for VRefCA and VDDQ for VRefDQ.

VRef(DC) is the linear a verage of VRef(t) over a very long period of time (e.g. 1 sec) and is specified as a frac tion of

the linear avera ge of VDDQ or VDDCA a ls o over a very long per iod of time ( e.g. 1 s ec ). This average h as to meet the

min/max requirements in 7.2.4.1.1 “Single-Ended AC and DC Input Levels for CA and CS_n Inputs” table.

Furtherm or e VRef(t) ma y tem poraril y deviate f rom VRef(DC) b y no m ore than ± 1 % VDD. Vref(t) cann ot track noise on

VDDQ or VDDCA if this would s end Vref outside these specifications.

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6.2.4.2.1 VRef(DC) Tolerance and VRef AC-Noise Limits

VRef ac-noise VRef (DC)max

VRef (DC)min

VRef (t)

VDD

VSS

VRef (DC)

voltage

time

VDD/2

The voltage le ve ls for setup and h old t ime measur em ents VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are depe ndent on VRef.

“VRef” s hall be underst ood as VRef(DC), as defined in above “VRef(DC) Toler ance an d VRef AC-Noise Limits” figure.

This c larifies that dc-vari ations of VRef aff ect t he absolute v oltage a signal h as to reac h to achi eve a val id high or lo w

level and therefore the time to which setup and hold is measured. Devices will function correctly with appropriate

timing deratings with VREF outside these specified levels so long as VREF is maintained between 0.44 x VDDQ (or

VDDCA) and 0.56 x VDDQ (or VDDCA) and so long as the controller achieves the required single-ended AC and DC

input levels from instantaneous VRef (see 7.2.4.1.1 “Single-Ended AC and DC Input Levels for CA and CS_n

Inputs” table and 7.2.4.1.3 “Single-Ended AC and DC Input Levels for DQ and DM” table) Therefore, system

timing and voltage budgets need to account for VREF deviations outside of this range.

This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage

associated with VRef ac-noise. Tim ing and voltage effects due to ac-noise on VRef up to the specified lim it (± 1% of

VDD) are included in LPDDR2 timings and their associated deratings.

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6.2.4.3 Input Signal

6.2.4.3.1 LPDDR2-800/1066 Input Signal

VIL and VIH Levels With Ringback

1.550V

1.200V

0.820V

0.730V

0.624V

0.612V

0.600V

0.588V

0.576V

0.470V

0.380V

0.000V

-0.350V VSS – 0.35V

VSS

VIL(AC)

VIL(DC)

VREF – AC noise

VREF – DC error

VREF + DC error

VREF + AC noise

VIH(DC)

VIH(AC)

VDD

VDD + 0.35V

Minimum VIL and VIH Levels

VIH(AC)

0.820V

0.730V VIH(DC)

0.624V

0.612V

0.600V

0.588V

0.576V

0.470V

0.380V

VIL(DC)

VIL(AC)

Notes:

1. Numbers ref l ect nomi nal values.

2. For CA 0-9, CK_t, CK_c, and CS_n, VDD stands for VDDCA. For DQ , D M, DQS_t, an d DQS _c, VDD stands for VDDQ.

3. For CA 0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ.

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6.2.4.4 AC and DC Logic Input Levels for Differential Signals

6.2.4.4.1 Differential Signal Definition

IHDIFF(AC)

MIN

Half cycle

Differntial

voltage

ILDIFF(DC)

MAX

ILDIFF(AC)

MAX

IHDIFF(DC)

MIN

DVAC time

CK_t-CK_c

DQS_t-DQS_c

DVAC

0.0

Figure of Definition of Differential AC-Swing and “Time above AC-Level” tDVAC

6.2.4.4.2 Differential Swing Requirements for Clock (CK_t - CK_c) and Strobe (DQS_t - DQS_c)

Table of Differential AC and DC Input Levels

Symbol Parameter LPDDR2-800/1066 Unit Notes

Min Max

VIHdiff(dc) Differential input high 2 x (VIH(dc) - Vref) Note 3 V 1

VILdiff(dc) Differential input logic low Note 3 2 x (VIL(dc) - Vref) V 1

VIHdiff(ac) Differential input high ac 2 x (VIH(ac) - Vref) Note 3 V 2

VILdiff(ac) Differential input low ac Note 3 2 x (VIL(ac) - Vref) V 2

Notes:

1. Used to define a differential signal slew-rate. For C K_t - CK_c use VIH/VIL(dc) of CA and VREFCA; for DQS_t - DQ S_c , us e VIH/VIL(dc) of DQs

and VREFDQ; if a reduced dc-high or dc-low level is us ed for a signal group, then the reduced level applies also here.

2. For CK_t - CK_c use VIH/VIL(ac) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low

level is used for a signal group, then the reduced level applies also here.

3. These values are not defi ned, however the singl e-ended s i gnals CK_t, CK_c, DQS_t, and DQS_c need to be within the respective limi ts

(VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to section 7.2.5.5 “Overshoot

and Undershoot Spec ifications”.

4. For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC).

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Table of Allowed Time before Ringback (tDVAC) for CK_t - CK_c and DQS_t - DQS_c

Slew Rate [V/nS]

DVAC

[pS]

@ |VIHdiff(ac) or VILdiff( ac)| = 440mV

> 4.0 175

4.0 170

3.0 167

2.0 163

1.8 162

1.6 161

1.4 159

1.2 155

1.0 150

< 1.0 150

6.2.4.5 Single-Ended Requirements for Differential Signals

Each individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain

requirements for single-ended signals.

CK_t and CK_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle.

DQS_t, DQS_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle preceeding and following a valid transition.

Note that the applicable ac-levels for CA and DQ’s are different per speed-bin.

VSEL(ac) time

CK_t,CK_

DQS_t, or DQS_c

VSEH(ac)

VDDCA or VDDQ

VSEH(ac)min

VDDCA/2 or VDDQ/2

VSSCA or VSSQ

VSEL(ac)max

Figure of Single-Ended Requirement for Differential Signals

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Note that while CA and DQ signal requirements are with respect to Vref, the single-ended components of differential

signals have a requirement with respect to VDDQ/2 for DQS_t, DQS_c and VDDCA/2 for CK_t, CK_c; this is nominally

the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

ended components of differential signals the requirement to reach VSEL(ac)max, VSEH(ac)min has no bearing on

timing, but adds a restriction on the common mode characteristics of these signals.

The signal ended requirements for CK_t, CK_c, DQS_t and DQS_c are found in 7.2.4.1.1 “Single-Ended AC and

DC Input Levels for CA and CS_n Inputs” table and 7.2.4.1.3 “Single-Ended AC and DC Input Levels for DQ

and DM” table, respectively.

Table of Single-Ended Levels for CK_t, DQS_t, CK_c, DQS_c

Symbol Parameter LPDDR2-800/1066 Unit Notes

Min Max

VSEH(AC) Single-ended high-level for strobes (VDDQ/2) + 0.220 Note 3 V 1, 2

Single-ended high-level for CK_t, CK_c (VDDCA/2) + 0.220 Note 3 V 1, 2

VSEL(AC) Single-ended low-level for strobes Note 3 (VDDQ/2) - 0.220 V 1, 2

Single-ended low-level for CK_t, CK_c Note 3 (VDDCA/2) - 0.220 V 1, 2

Notes:

1. For CK_t, CK_c use VSEH/VSEL(ac) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c) use

VIH/VIL(ac) of DQs.

2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VSEH(ac)/VSEL(ac) for CA is based on VREFCA; if a reduced ac-high or ac-low level is used for

a signal group, then the reduced level applies also here.

3. These values are not defi ned, however the singl e-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c,

DQS3_t, DQS3_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for

overshoot and undershoot. Ref er to section 7.2.5.5 “Overshoot and Undershoot Specifications”.

6.2.4.6 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each

cross point voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements of

above Single-ended levels for CK_t, DQS_t, CK_c, DQS_c table. The differential input cross point voltage VIX is

measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS.

VDDCA/2 or VDDQ/2

VSSCA or VSSQ

VDDCA or VDDQ

CK_c, DQS_c

CK_t, DQS_t

VIX

Figure of Vix Definition

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Table of Cross Point Voltage for Differential Input Signals (CK, DQS)

Symbol Parameter LPDDR2-800/1066 Unit Notes

Min Max

VIXCA Differential Input Cross Point Voltage relative to

VDDCA/2 for CK_t, CK_c - 120 120 mV 1, 2

VIXDQ Differential Input Cross Point Voltage relative to

VDDQ/2 for DQS_t, DQS_c - 120 120 mV 1, 2

Notes:

1. The typical val ue of VIX(AC) is expec ted to be about 0.5 × VDD of the transmitting device, and VIX(AC) i s expected to track variations in VDD.

VIX(AC) indicat es the voltage at which differential input signals must cross.

2. For CK_t and CK_c, Vref = VrefCA(DC). F or DQS _t and DQS_c, Vref = VrefDQ(DC).

6.2.4.7 Slew Rate Definitions for Single-Ended Input Signals

See section 7.7.2 “C A and CS_n Setup, Hold and Derating” for sing le-ende d s lew ra te def initi ons f or addr ess and

command signals.

See section 7.7.3 “Data Setup, Hold and Slew Rate Derating” for single-ended slew rate definitions for data

signals.

6.2.4.8 Slew Rate Definitions for Differential Input Signals

Input slew rate for differential signals (CK_t, CK_c and DQS_t, DQS_c) are defined and measured as shown in

below table and figure.

Table of Differential Inpu t Sl ew Rate Definition

Description Measured Defined by

from to

Differential input slew rate for rising edge

(CK_t - CK_c and DQS_t - DQS_c). VILdiffmax VIHdiffmin [VIHdiffmin - VILdiffmax] / DeltaTRdiff

Differential input slew rate for falling edge

(CK_t - CK_c and DQS_t - DQS_c). VIHdiffmin VILdiffmax [VIHdiffmin - VILdiffmax] / DeltaTFdiff

Note: The differential signal (i.e. CK_t - CK_c and DQS_t - DQS_c) must be linear between these thresholds.

Delta TFdiff

Delta TRdiff

ILdiffmax

IHdiffmin

Differential Input Voltage (i.e.DQS_t-DQS_c;CK_t-CK_c)

Figure of Differential Inp ut Slew Rate Definition for DQS_t, DQS_c and CK_t, CK_c

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6.2.5 AC and DC Output Measurement Levels

6.2.5.1 Single Ended AC and DC Output Levels

Table of Single-Ended AC and DC Output Levels

Symbol Parameter LPDDR2-800/1066 Unit Notes

VOH(DC) DC output high measurement level (for IV curve linearity) 0.9 x VDDQ V 1

VOL(DC) DC output low measurement level (for IV curve linear ity ) 0.1 x VDDQ V 2

VOH(AC) AC output high measurement level (for output slew rate) VREFDQ + 0.12 V

VOL(AC) AC output low measurement level (for output slew rate) VREFDQ - 0.12 V

IOZ Output Leakage current (DQ, DM, DQS_t, DQS_c)

(DQ, DQS_t, DQS_c are disabled;0V ≤ Vout ≤ VDDQ) Min -5 µ

Max +5

MMPUPD Delta RON between pull-up and pull-down for DQ/DM Miin -15

Max +15

Notes:

1. IOH = -0.1mA.

2. IOL = +0.1mA.

6.2.5.2 Differential A C and DC Output Levels

Table of Differential AC and DC Output Levels of (DQS_t, DQS_c)

Symbol Parameter LPDDR2-800/1066 Unit Notes

VOHdiff(AC)

AC differential output high measurement level (for output SR)

+ 0.20 x VDDQ

VOLdiff(AC)

AC differential output low measurement level (for output SR)

- 0.20 x VDDQ

Notes:

1. IOH = -0.1mA.

2. IOL = +0.1mA.

6.2.5.3 Single Ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and

measured between VOL(AC) and VOH(AC) for single ended signals as shown in below table and figure.

Table of Single-Ended Output Slew Rate Definition

Description Measured Defined by

from to

Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)] / DeltaTRse

Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)] / DeltaTFse

Note: Output slew rate is verified by design and characteri zat i on, and may not be subject to producti on test.

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Delta TFse

Delta TRse

VREF

VOL(AC)

Single Ended Output Vollage (i.e.DQ)

VOH(AC)

Figure of Single Ended Output Slew Rate Definiton

Table of Output Slew Rate (Single-Ended)

Symbol Parameter LPDDR2-800/1066 Units

Min Max

SRQse Single-ended Output Slew Rate (RON = 40Ω ± 30%)

1.5 3.5 V/nS

SRQse

Single-ended Output Slew Rate (RON = 60Ω ± 30%)

1.0 2.5 V/nS

Output slew-rate matching Ratio (Pull-up to Pull-down)

0.7 1.4

Description:

SR: Slew R ate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

se: Single-ended Signals

Notes:

1. Measured with output reference load.

2. The ratio of pull -up to pull-down slew rate is specifi ed for the same temperature and voltage, over the entire tem perature and volt age range.

For a given output, it represents the maximum difference between pull-up and pulldown drivers due t o process variation.

3. The output slew rate for falli ng and risi ng edges is defi ned and measured between VOL(AC) and VOH(AC).

4. Slew rates are measured under norm al SSO conditions, with 1/2 of DQ signals per data byte driving logic high and 1/2 of DQ signals per data

byte driving logic low.

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6.2.5.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and

measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below table and figure.

Table of Differential Output Slew Rate Definition

Description Measured Defined by

from

Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTRdiff

Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTFdiff

Note: Output slew rate is verified by design and characteri zat i on, and may not be subject to producti on test.

Delta TFdiff

Delta TRdiff

VOLdiff(AC)

Differential Output VoltAge (i.e. DQS_t – DQS_c)

VOHdiff(AC)

Figure of Differential Output Slew Rate Definition

Table of Differential Output Slew Rate

Symbol Parameter LPDDR2-800/1066 Units

Min Max

SRQdiff Differential Output Slew Rate (RON = 40Ω ± 30%)

3.0 7.0 V/nS

SRQdiff

Differential Output Slew Rate (RON = 60Ω ± 30%)

2.0 5.0 V/nS

Description:

SR: Slew R ate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

diff: differential Signals

Notes:

1. Measured with output reference load.

2. The output slew rate for falli ng and risi ng edges is defined and measured between VOLdiff(AC) and VOHdiff(AC).

3. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals per data

byte driving logic-low.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 88 -

6.2.5.5 Overshoot and Undershoot Specifications

Table of AC Overshoot/Undershoot Specification

Parameter

LPDDR2

Unit

1066

933

800

667

533

400

333

Maximum peak amplitude

allowed for overshoot area.

(See figure below)

Max 0.35 V

Maximum peak amplitude

allowed for undershoot area.

(See figure below) Max 0.35 V

Maximum area above VDD.

(See figure below)

Max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 V-nS

Maximum area below V

(See figure below) Max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 V-nS

(CA0-9, CS_n, CKE, CK _t, CK _c, DQ, DQS_t, DQS_c, DM)

Notes:

1. For CA 0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM, DQS_t, an d DQS_c, VDD stands for VDDQ.

2. For CA 0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS st ands f or VSSQ.

3. Maximum peak amplitude values are referenced from actual VDD and VSS values.

4. Maximum area values are referenced from maximum operating VDD and V SS values.

VDD

VSS

Overshoot Area

Undershoot Area

Maximum Amplitude

Time (ns)

Volts

(V)

Figure of Over shoot and Undershoot Definition

Notes:

1. For CA 0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM, DQS_t, a nd DQS_c, VDD stands for VDDQ.

2. For CA 0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ.

3. Maximum peak amplitude values are referenc ed f rom actual VDD and VSS values.

4. Maximum area values are referenced from maxi mum operating VDD and V SS values.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 89 -

6.2.6 Output buffer Characteristics

6.2.6.1 HSUL_12 Driver Output Timing R eference Load

These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment

or a depiction of the actual load presented by a production tester. System designers should use IBIS or other

simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their

production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

0.5 x VDDQ

Cload = 5pF

VREF

Output

LPDDR2

SDRAM

VTT = 0.5 x VDDQ

RTT = 50 Ω

Figure of HSUL_12 Driver Output Reference Load for Timing and Slew Rate

Note:

All output timing parameter values (like tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported with respect to this

reference load. This reference load is also used to report slew rate.

6.2.6.2 RONPU and RONPD Resis tor Definition

RONPU =

)( )( –

IoutABS VoutVDDQ

Note: This is under the condition that RONPD is turned off

RONPD =

)(IoutABS

Vout

Note: This is under the condition that RONPU is turned off

Chip in Drive Mode

VDDQ

VSSQ

Output Driver

IPU

IPD

RONPU

RONPD IOut

VOut

Other

Circuityrt

RCV,

...

Figure of Output Driver Definition of Voltages and Currents

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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6.2.6.3 RONPU and RONPD Characteristics with ZQ Calibration

Output driver impedance RON is defined by the value of the external reference resistor RZQ. Nominal RZQ is 240Ω.

Table of Output Driver DC Electr ical Characteristics with ZQ Calibration

RON

NOM

Resistor Vout Min Nom Max Unit Note

34.3Ω RON34PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1, 2, 3, 4

RON34PU 0. 5 x VDDQ 0.85 1.00 1.15 RZQ/7 1, 2, 3, 4

40.0Ω RON40PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1, 2, 3, 4

RON40PU 0. 5 x VDDQ 0.85 1.00 1.15 RZQ/6 1, 2, 3, 4

48.0Ω RON48PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1, 2, 3, 4

RON48PU 0. 5 x VDDQ 0.85 1.00 1.15 RZQ/5 1, 2, 3, 4

60.0Ω RON60PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1, 2, 3, 4

RON60PU 0. 5 x VDDQ 0.85 1.00 1.15 RZQ/4 1, 2, 3, 4

80.0Ω RON80PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1, 2, 3, 4

RON80PU 0. 5 x VDDQ 0.85 1.00 1.15 RZQ/3 1, 2, 3, 4

120.0Ω RON120PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1, 2, 3, 4

RON120PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1, 2, 3, 4

Mismatch between pull-up and pull-down

MMPUPD -15.00 +15.00 % 1, 2, 3, 4, 5

Notes:

1. Across ent i re operating t emperature range, af t er calibrat i on.

2. RZQ = 240Ω.

3. The tolerance limits are specified after calibration with fixed voltage and temperature. For behavior of the tolerance limits if temperature or

voltage changes after cali brat i on, see following sect i on on voltage and temperat ure sensit i vity.

4. Pull-down and pull-up output dri ver impedanc es are recommended to be calibrated at 0. 5 x VDDQ.

5. Mesaurem ent def i niti on for mismatch bet ween pull-up and pull-down: MMPUPD: Measure RONPU and RONPD, both at 0.5 x VDDQ:

MMPUPD =

RONNOM

RONPD RONPU –

x 100

For example, with MMPUPD(max) = 15% and RONPD = 0.85, RONPU must be less than 1.0.

6.2.6.4 Output Driver Temperature and Voltage Sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen according to the tables shown below.

Table of Output Driver Sensitivity Definition

Resistor Vout Min Max Unit Notes

RONPD 0.5 x VDDQ

85 – (dR ONdT ×|ΔT| ) – (dRON d V × |ΔV| ) 115 + (dRONdT ×| ΔT| )+(dRONdV × |ΔV|) % 1, 2

RONPU

Notes:

1. ΔT = T–T (@calibration), ΔV=V–V(@ calibration).

2. dRONdT and dRONdV are not subject to production test but are verified by design and characteri zat i on.

Table of Output Driver Temper ature and Voltage Sensitivity

Symbol Parameter Min Max Unit Note

dRONdT RON Temperature Sensitivity 0.00 0.75 % / °C

dRONdV RON Voltage Sensitivity 0.00 0.20 % / mV

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 91 -

6.2.6.5 RONPU and RONPD Characteristics without ZQ Calibration

Output driver impedance RON is defined by design and characterization as default setting.

Table of Output Driver DC Electrical Character istics without ZQ Calibration

RON

NOM

Resistor Vout Min Nom Max Unit Note

34.3Ω RON34PD 0.5 x VDDQ 24 34.3 44.6 Ω 1

RON34PU 0.5 x VDDQ 24 34.3 44.6 Ω 1

40.0Ω RON40PD 0.5 x VDDQ 28 40 52 Ω 1

RON40PU 0.5 x VDDQ 28 40 52 Ω 1

48.0Ω RON48PD 0.5 x VDDQ 33.6 48 62.4 Ω 1

RON48PU 0.5 x VDDQ 33.6 48 62.4 Ω 1

60.0Ω RON60PD 0.5 x VDDQ 42 60 78 Ω 1

RON60PU 0.5 x VDDQ 42 60 78 Ω 1

80.0Ω RON80PD 0.5 x VDDQ 56 80 104 Ω 1

RON80PU 0.5 x VDDQ 56 80 104 Ω 1

120.0Ω RON120PD 0.5 x VDDQ 84 120 156 Ω 1

RON120PU 0.5 x VDDQ 84 120 156 Ω 1

Note: Across entire operating temperature range, without calibrati on.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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6.2.6.6 RZQ I-V Curve Table of RZQ I-V Curve

Voltage[V]

RON = 240Ω (RZQ)

Pull-Down

Pull-Up

Current [mA] / RON [Ohms]

default value after

ZQReset

With Calibration default value after

ZQReset

With Calibration

Min Max

[mA] [mA]

0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00

0.05 0.19 0.32 0.21 0.26 -0.19 -0.32 -0.21 -0.26

0.10 0.38 0.64 0.40 0.53 -0.38 -0.64 -0.40 -0.53

0.15 0.56 0.94 0.60 0.78 -0.56 -0.94 -0.60 -0.78

0.20 0.74 1.26 0.79 1.04 -0.74 -1.26 -0.79 -1.04

0.25 0.92 1.57 0.98 1.29 -0.92 -1.57 -0.98 -1.29

0.30 1.08 1.86 1.17 1.53 -1.08 -1.86 -1.17 -1.53

0.35 1.25 2.17 1.35 1.79 -1.25 -2.17 -1.35 -1.79

0.40 1.40 2.46 1.52 2.03 -1.40 -2.46 -1.52 -2.03

0.45 1.54 2.74 1.69 2.26 -1.54 -2.74 -1.69 -2.26

0.50 1.68 3.02 1.86 2.49 -1.68 -3.02 -1.86 -2.49

0.55 1.81 3.30 2.02 2.72 -1.81 -3.30 -2.02 -2.72

0.60 1.92 3.57 2.17 2.94 -1.92 -3.57 -2.17 -2.94

0.65 2.02 3.83 2.32 3.15 -2.02 -3.83 -2.32 -3.15

0.70 2.11 4.08 2.46 3.36 -2.11 -4.08 -2.46 -3.36

0.75 2.19 4.31 2.58 3.55 -2.19 -4.31 -2.58 -3.55

0.80 2.25 4.54 2.70 3.74 -2.25 -4.54 -2.70 -3.74

0.85 2.30 4.74 2.81 3.91 -2.30 -4.74 -2.81 -3.91

0.90 2.34 4.92 2.89 4.05 -2.34 -4.92 -2.89 -4.05

0.95 2.37 5.08 2.97 4.23 -2.37 -5.08 -2.97 -4.23

1.00 2.41 5.20 3.04 4.33 -2.41 -5.20 -3.04 -4.33

1.05 2.43 5.31 3.09 4.44 -2.43 -5.31 -3.09 -4.44

1.10 2.46 5.41 3.14 4.52 -2.46 -5.41 -3.14 -4.52

1.15 2.48 5.48 3.19 4.59 -2.48 -5.48 -3.19 -4.59

1.20 2.50 5.55 3.23 4.65 -2.50 -5.55 -3.23 -4.65

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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PD Min

PD Max

PU Min

PU Max

-2

-4

-6

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

Voltage

Figure of RON = 240 Ohms IV Curve after ZQReset

PD Min

PD Max

PU Min

PU Max

-2

-4

-6

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

Voltage

Figure of RON = 240 Ohms IV Curve after Calibration

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 94 -

6.2.6.7 Input/Output Capacitance

Table of Input/Output Capacitance

Parameter Symbol Min Max Units Note

Input capacitance, CK_t and CK_c CCK 1 2 pF 1, 2

Input capacitance delta, CK_t and CK_c CDCK 0 0.2 pF 1, 2, 3

Input capacitance, all other inp ut-only pads CI 1 2 pF 1, 2, 4

Input capacitance delta, all other input-only pads CDI -0.4 0.4 pF 1, 2, 5

Input/output capacitance, DQ, DM, DQS_t, DQS_c CIO 1.25 2.5 pF 1, 2, 6, 7

Input/output capacitance delta, DQS_t, DQS_c CDDQS 0 0.25 pF 1, 2, 7, 8

Input/output capacitance delta, DQ, DM CDIO -0.5 0.5 pF 1, 2, 7, 9

Input/output capacitance, ZQ Pad CZQ 0 2.5 pF 1, 2

(-40°C ≤ Tj ≤ 85°C; VDDQ = 1.14- 1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V , LP DDR2-S4 VDD2 = 1.14-1.3V)

Notes:

1. This paramet er appl i es to die device only (does not include pack age capacitance).

2. This paramet er is not subject to producti on test. It is verified by design and characterizati on. The capacitance is measured according to

JEP147 (Procedure for measuring input capaci tance using a vector network analyzer (VNA) with VDD1, VDD2, VDDQ, VSS, VSSCA, VSSQ

applied and all other pads floating.

3. Absol ute value of CCK_t - CCK_c.

4. CI appl ies to CS_n, CKE, CA0-CA9

5. CDI = CI - 0.5 * (CCK_t + CCK_c).

6. DM loadi ng m atc hes DQ and DQS.

7. MR3 I/O confi guration DS OP3-OP0 = 0001B (34.3 Ohm typical).

8. Absol ute value of CDQS_t and CDQS_c.

9. CDIO = CIO - 0.5 * (CDQS_t + CDQS_c) in byte lane.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 95 -

6.3 IDD Sp ecification P arameters and Test Condition s

6.3.1 IDD Measurement Conditions

The following definitions are used within the IDD measurement tables:

LOW: VIN ≤ VIL(DC) MAX

HIGH: VIN ≥ VIH(DC) MIN

STABLE: Inputs are stable at a HIGH or LOW level

SWITCHING: See tables below.

6.3.1.1 Definition of Switching for CA Input Signals

Switching for CA

CK_t

(RISING) /

Ck_C

(FALLING)

CK_t

(FALLING) /

Ck_C

(RISING)

CK_t

(RISING) /

Ck_C

(FALLING)

CK_t

(FALLING) /

Ck_C

(RISING)

CK_t

(RISING) /

Ck_C

(FALLING)

CK_t

(FALLING) /

Ck_C

(RISING)

CK_t

(RISING) /

Ck_C

(FALLING)

CK_t

(FALLING) /

Ck_C

(RISING)

Cycle N N+1 N+2 N+3

CS_n HIGH HIGH HIGH HIGH

CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

CA6 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA7 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

CA8 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA9 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

Notes:

1. CS_n must always be driven HIGH.

2. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.

3. The above pattern (N, N+1, N+2, N+3...) is used continuous l y during IDD measurement for IDD values that require SW ITCHI NG on the CA bus.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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6.3.1.2 Definition of Switching for IDD4R

Clock CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ

Rising HIGH LOW N Read_Rising HLH LHLHLHL L

Falling HIGH LOW N Read_Falling LLL LLLLLLL L

Rising HIGH HIGH N + 1 NOP LLL LLLLLLL H

Falling HIGH HIGH N + 1 NOP HLH HLHLLHL L

Rising HIGH LOW N + 2 Read_Rising HLH HLHLLHL H

Falling HIGH LOW N + 2 Read_Falling LLL HHHHHHH H

Rising HIGH HIGH N + 3 NOP LLL HHHHHHH H

Falling HIGH HIGH N + 3 NOP HLH LHLHLHL L

Notes:

1. Data strobe (DQS ) is changing between HIGH and LOW every clock cycle.

2. The above pattern (N, N+1... ) is used continuously during IDD measurement for IDD4R.

6.3.1.3 Definition of Switching for IDD4W

Clock CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ

Rising HIGH LOW N Write_Rising HLL LHLHLHL L

Falling HIGH LOW N Write_Falling LLL LLLLLLL L

Rising HIGH HIGH N + 1 NOP LLL LLLLLLL H

Falling HIGH HIGH N + 1 NOP HLH HLHLLHL L

Rising HIGH LOW N + 2 Write_Rising HLL HLHLLHL H

Falling HIGH LOW N + 2 Write_Falling LLL HHHHHHH H

Rising HIGH HIGH N + 3 NOP LLL HHHHHHH H

Falling HIGH HIGH N + 3 NOP HLH LHLHLHL L

Notes:

1. Data strobe (DQS ) is changing between HIGH and LOW every clock cycle.

2. Data masking (DM) must always be driven LOW.

3. The above pattern (N, N+1... ) is used continuously during IDD measurement for IDD4W.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 97 -

6.3.2 IDD Specifications

6.3.2.1 LPDDR2 IDD Specification Parameters and Operating Conditions, -40°C~85°C (x16, x32)

Parameter/Condition

Symbol

Power Supply

400 MHz

533 MHz

Unit

Notes

Operating one bank active-precharge current:

tCK = tCK(avg)min; tRC = tRCmin;

CKE is HIGH;

CS_n is HIGH between valid commands;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD01

VDD1

IDD02

VDD2

IDD0IN VDDCA 3.5 3.5 mA 1, 2

VDDQ 0.8 0.8 mA

Idle power-down s t andby current:

tCK = tCK(avg)min;

CKE is LOW; CS_n is HIGH;

All banks/RBs idle;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD2P1 VDD1 0.6 0.6 mA 1

IDD2P2

VDD2

0.8

IDD2PIN VDDCA 0.015 0.015 mA 1, 2

VDDQ 0.025 0.025 mA

Idle power-down s ta ndby current with clock st op:

CK_t =LOW, CK_c =HIGH;

CKE is L OW; CS_n is HIGH;

All banks/RBs idle;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD2PS1

VDD1

0.6

IDD2PS2

VDD2

0.8

IDD2PSIN VDDCA 0.015 0.015 mA 1, 2

VDDQ 0.025 0.025 mA

Idle non power-down standby current:

tCK = tCK(avg)min;

CKE is HIGH; CS_n is HIGH;

All banks/RBs idle;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD2N1

VDD1

IDD2N2

VDD2

IDD2NIN VDDCA 3.5 3.5 mA 1, 2

VDDQ 0.025 0.025 mA

Idle non power-down standby current with clock stop:

CK_t =LOW, CK_c =HIGH;

CKE is HIGH; CS_n is HIGH;

All banks/RBs idle;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD2NS1

VDD1

IDD2NS2 VDD2 9 12 mA 1

IDD2NSIN VDDCA 3.5 3.5 mA 1, 2

VDDQ 0.025 0.025 mA

Active power-down standby current:

tCK = tCK(avg)min;

CKE is L OW; CS_n is HIGH;

One bank/RB active;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD3P1

VDD1

IDD3P2

VDD2

IDD3PIN VDDCA 0.02 0.02 mA 1, 2

VDDQ 0.025 0.025 mA

Active power-down standby current with clock stop:

CK_t=LOW, CK_c=HIGH;

CKE is L OW; CS_n is HIGH;

One bank/RB active;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD3PS1 VDD1 2 2 mA 1

IDD3PS2

VDD2

IDD3PSIN VDDCA 0.02 0.02 mA 1, 2

VDDQ 0.025 0.025 mA

Active non power-down standby current:

tCK = tCK(avg)min;

CKE is HIGH; CS_n is HIGH;

One bank/RB active;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD3N1

VDD1

IDD3N2 VDD2 14 18 mA 1

IDD3NIN VDDCA 4 4 mA 1, 2

VDDQ 0.025 0.025 mA

Active non power-down standby current with clock stop:

CK_t=LOW, CK_c=HIGH;

CKE is HIGH; CS_n is HIGH;

One bank/RB active;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD3NS1

VDD1

IDD3NS2

VDD2

IDD3NSIN VDDCA 4 4 mA 1, 2

VDDQ 0.025 0.025 mA

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 98 -

Parameter/Condition Symbol

Power Supply

400 MHz 533 MHz Unit Notes

Operating burst read current:

tCK = tCK(avg)min;

CS_n is HIGH between valid commands;

One bank/RB active;

BL = 4; RL = RLmin;

bus inputs are SWITCHING;

50% data change each burst transfer

IDD4R1 VDD1 4 4 mA 1

IDD4R2 VDD2 160 190 mA 1

IDD4RIN VDDCA 4 4 mA 1

Operating burst write current:

tCK = tCK(avg)min;

CS_n is HIGH between valid commands;

One bank/RB active;

BL = 4; WL = WLmin;

CA bus inputs are SWITCHING;

50% data change each burst transfer

IDD4W1 VDD1 4 4 mA 1

IDD4W2 VDD2 200 200 mA 1

IDD4WIN

VDDCA 4 4 mA

1, 2

VDDQ 11 11 mA

All Bank Refresh Burst current:

tCK = tCK(avg)min;

CKE is HIGH between valid commands;

tRC = tRFCabmin;

Burst refresh;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

IDD51 VDD1 38 38 mA 1

IDD52 VDD2 120 120 mA 1

IDD5IN

VDDCA 4 4 mA

1, 2

VDDQ 0.025 0.025 mA

All Bank Refresh Average current:

tCK = tCK(avg)min;

CKE is HIGH between valid commands;

tRC = tREFI;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

IDD5AB1 VDD1 4 4 mA 1

IDD5AB2 VDD2 14 17 mA 1

IDD5ABIN VDDCA 4 4 mA 1, 2

VDDQ 0.025 0.025 mA

Per Bank Refresh Average current:

tCK = tCK(avg)min;

CKE is HIGH between valid commands;

tRC = tREFI/8;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

IDD5PB1 VDD1 3 3 mA 1

IDD5PB2 VDD2 13 16 mA 1

IDD5PBIN VDDCA 4 4 mA 1, 2

VDDQ 0.025 0.025 mA

Deep Power-Down current:

CK_t=LOW, CK_c=HIGH;

CKE is LOW;

CA bus inputs are STABLE;

Data bus inputs are STABLE;

IDD81 VDD1 15 15 µA 1

IDD82 VDD2 100 100 µA 1

IDD8IN VDDCA 15 15 µA 1, 2

VDDQ 25 25 µA

Notes:

1. IDD values published are the maximum of the distribution of the arithm etic mean.

2. Measured current s are t he summation of VDDQ and VDDCA.

3. IDD current specific ati ons are tested after the device is properly initialized.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

- 99 -

6.3.2.2 IDD6 Partial Array Self-Refresh Current, 85°C (x16, x32)

Parameter Symbol Power Supply

400 MHz 533 MHz Condition Unit

IDD6 Partial Array

Self-Refresh

Current

Full Array

IDD61

VDD1 900 900

Self refresh current

CK_t=LOW, CK_c=HIGH;

CKE is LOW;

CA bus inputs are STABLE;

Data bus inputs are STABLE;

µA

IDD62

VDD2 2000 2000

IDD6IN

VDDCA

VDDQ

1/2 Array

IDD61

VDD1 800 800

µA

IDD62

VDD2 1500 1500

IDD6IN

VDDCA

VDDQ

1/4 Array

IDD61

VDD1 700 700

µA

IDD62

VDD2 1200 1200

IDD6IN

VDDCA

VDDQ

1/8 Array

IDD61

VDD1 650 650

µA

IDD62

VDD2 1000 1000

IDD6IN

VDDCA

VDDQ

Notes:

1. LPDDR2-S4 SDR AM us es t he same PASR scheme & IDD6 current value categorizati on as LPDDR (JESD209).

2. LPDDR2-S4 SDRAM devices support both bank-mas king & s egment-masking. The IDD6 currents are measured using bank-masking only.

3. IDD values publis hed are the maximum of the distribution of the arithm etic mean.

6.4 Clo ck S pecification

The j itter spec ified is a ran dom jitter m eeting a Gaus sian distribut ion. Input c locks violating th e min/m ax values m ay

result in malfunction of the LPDDR2 device.

6.4.1 Definition for tCK(avg) and nCK

tCK(avg) is calcul ate d as the avera ge c lock period acros s an y consec ut ive 200 cycle wind o w, where eac h c l ock period

is calculated from rising edge to rising edge.

tCK(avg) =













∑

tCK

/ N

where N = 200

Unit ‘tCK(avg)’ represents the actual clock average tCK(avg) of the input clock under operation. Unit ‘nCK’ represents

one clock cycle of the input clock, counting the actual clock edges.

tCK(avg) may change by up to ± 1% within a 100 clock cycle window, provided that all jitter and timing specs are met.

6.4.2 Definition for tCK(abs)

tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising

edge.

tCK(abs) is not subject to production test.

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6.4.3 Definition for tCH(avg) and tCL(avg)

tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses.

tCH(avg) =











∑

tCH

/ (N × tCK(avg))

where N = 200

tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.

tCL(avg) =











∑

tCL

/ (N × tCK(avg))

where N = 200

6.4.4 Definition for tJIT(per)

tJIT(per) is the single period jitter defined as the largest deviation of any signal tCK from tCK(avg).

tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.

tJIT(per),act is the actual clock jitter for a given system.

tJIT(per),allowed is the specified allowed clock period jitter.

tJIT(per) is not subject to production test.

6.4.5 Definition for tJIT(cc)

tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles.

tJIT(cc) = Max of |{tCKi +1 - tCKi}|.

tJIT(cc) defines the cy cle to cycle jitter.

tJIT(cc) is not subject to production test.

6.4.6 Definition for tERR(nper)

tERR(nper) is defined as the cumulative error across n multiple consecutive cycles from tCK(avg).

tERR(nper),act is the actual clock jitter over n cycles for a given system.

tERR(nper),allowed is the specified allowed clock period jitter over n cycles.

tERR(nper) is not subject to production test.

tERR(nper) =













∑

−+

1ni

ij j

tCK

– n × tCK(avg)

tERR(nper),min can be calculated by the formula shown below:

tERR(nper), min = (1 + 0.68LN(n)) × tJIT(per), min

tERR(nper),max can be calculated by the formula shown below:

tERR(nper), max = (1 + 0.68LN(n)) × tJIT(per), max

Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.

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6.4.7 Definition for Duty Cycle Jitter tJIT(duty)

tJIT(duty) is defined with absolute and average specification of tCH / tCL.

tJIT(duty),min = MIN((tCH(abs),min – tCH(avg),min),(tCL(abs),min – tCL(avg),min)) x tCK(avg)

tJIT(duty),max = MAX((tCH(abs),max – tCH(avg),max),(tCL(abs),max – tCL(avg),max)) x tCK(avg)

6.4.8 Definition for tCK(abs), tCH(abs) and tCL(abs)

These parameters are specified per their average values, however it is understood that the following relationship

between the average timing and the absolute instantaneous timing holds at all times.

Table of Definition for tCK(abs), tCH(abs), and tCL(abs)

Parameter Symbol Min Unit

Absolute Clock Period tCK(abs) tCK(avg),min + tJIT(per),min pS

Absolute Clock HIGH Pulse Width tCH(abs) tCH(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg)

Absolute Clock LOW Pulse W idth tCL(abs) tCL(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg)

Notes:

1. tCK(avg),min is expressed is pS for this table.

2. tJIT(duty),min is a negative value.

6.5 Period Clock Jitter

LPDDR2 devices can tolerate some clock period jitter without core timing parameter de-rating. This section

describes device t iming requirem ents in t he presence of clock period jitter (tJIT(per)) in excess of the values found in

section 7.7.1 “LPDDR2 AC Timing” table and how to determine cycle time de-rating and clock cycle de-rating.

6.5.1 Clock Period Jitter Effects on Core Timing Parameters

(tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW)

Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these parameters when

meas ured in number s of clock c ycles. W hen the dev ice is operated with clock jitter within the sp ecificatio n limits , the

LPDDR2 device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}.

W hen the dev ic e is oper a te d with c lock jitter outside spec if icatio n l imits, the number of c lock s or t CK(avg) m a y need to

be increased based on the values for each core timing parameter.

6.5.1.1 Cycle Time De-rating for Core Timing Parameters

For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual

cumulati ve peri od error ( tERR(tnPARAM),act) in exces s of the al lowed cum ulati ve p eriod er ror (tERR(tnPARAM),allowed),

the equ ation belo w calcu lates the am ount of cycle time d e-rating ( in nS) requ ired if the equation results in a positive

value for a core timing parameter (tCORE).

CycleTimeDerating = MAX





















−

−+ 0,)(

),(),(

avgtCK

tnPARAM allowedtnPARAMtERRacttnPARAMtERRtPARAM

A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time

derating required is the maximum of the cycle time de-ratings determined for each individual core timing parameter.

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6.5.1.2 Clock Cycle De-rating for Core Timing Parameters

For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be specified

with amount of period jitter (tJIT(per)).

For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual

cumulati ve peri od error ( tERR(tnPARAM),act) in exces s of the al lowed cum ulati ve p eriod er ror (tERR(tnPARAM),allowed),

the equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value

for a core timing parameter (tCORE).

ClockCycleDerating = RU

tnPARAM

avg

tCK allowed

tnPARAMtERRacttnPARAMtERRtPARAM

−











−+

)( ),(),(

A clock cycle de-rating analysis should be conducted for each core timing parameter.

6.5.2 Clock Jitter Effects on Command/Address Timing Parameters

(tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb)

These parameters are measured from a command/address signal (CKE, CS, CA0 - CA9) transition edge to its

respectiv e clock s ignal (CK_t/CK_c ) crossing. T he spec values are not aff ected by the am ount of clock jitter app lied

(i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address.

Regardless of clock jitter values, these values shall be met.

6.5.3 Clock Jitter Effects on Read Timing Parameters

6.5.3.1 tRPRE

When the device is operated with input clock jitter, tRPRE needs to be de-rated by the actual period jitter

(tJIT(per),act,max) of the input clock in excess of the allowed period jitter (tJIT(per),allowed,max). Output de-ratings are

relative to the input clock.

tRPRE(min, derated) =











−

−)( ,),(,,

9.0 avgtCK maxallowedpertJIT maxact tJIT(per)

For example,

if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500 pS, tJIT(per),act,min = -172 pS and

tJIT(per),act,max = + 193 pS, then

tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500= .8628 tCK(avg)

6.5.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)

These parameters are measured from a specific clock edge to a data signal (DMn, DQm.: n=0,1,2,3. m=0–31)

transition and will be met with respect to that clock edge. Therefore, they are not affected by the amount of clock

jitter applied (i.e. tJIT(per).

6.5.3.3 tQSH, tQSL

These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and tCL(abs)min.

tQSH(abs)min = tCH(abs)min – 0.05

tQSL(abs)min = tCL(abs)min – 0.05

These parameters determi ne absolute Data-Valid window at t he LPDDR2 d evice pad.

Absolute min data-valid window @ LPDDR2 device pad =

min { ( tQSH(abs)min * tCK(avg)min – tDQSQmax – tQHSmax ) , ( tQSL(abs)min * tCK(avg)min – tDQSQmax – tQHSmax ) }

This minimum data-valid window shall be met at the target frequency regardless of clock jitter.

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6.5.3.4 tRPST

tRPST is affected by duty cycle jitter which is represented by tCL(abs). Therefore tRPST(abs)min can be specified by

tCL(abs)min.

tRPST(abs)min = tCL(abs)min – 0.05 = tQSL(abs)min

6.5.4 Clock Jitter Effects on Write Timing Parameters

6.5.4.1 tDS, tDH

These parameters are measured from a data signal (DMn, DQm.: n=0,1,2,3. m=0–31) transition edge to its

respective data strobe signal (DQSn_t, DQSn_c: n=0,1,2,3) crossing. The spec values are not affected by the

amount of clock jitter ap plied (i. e. tJIT(per), as the s etup an d hold ar e relat ive to t he clock signal cr ossing t hat latc hes

the command/address. Regardless of clock jitter values, these values shall be met.

6.5.4.2 tDSS, tDSH

Thes e parameter s are measured f rom a data s trobe signal (D QSx_t, DQSx_c ) cross ing to its res pective clock signal

(CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the

setup an d hold are rel ative to the c lock signa l cros sing that latches the c omm and/address. R egardl ess of c lock j itter

values, these values shall be met.

6.5.4.3 tDQSS

This parameter is measured from a data strobe signal (DQSx_t, DQSx_c) crossing to the subsequent clock signal

(CK_t/CK_c ) c r os sing. When the de vice is o perated with in put clock j itter, t his p ar a meter needs to b e d e-r ated b y the

actual period jitter tJIT(per),act of the input clock in excess of the allowed period jitter tJIT(per),allowed.

tDQSS(min, derated) =

)( ,),(,),(

75.0 avg

tCK minallowed

pertJIT minact pertJIT −

−

tDQSS(max, derated) =

)

(,),

(

1avg

tCK maxallowed

pertJIT

max

act

pertJIT −

−

For example,

if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500 pS, tJIT(per),act,min = -172 pS and

tJIT(per),act,max = + 193 pS, then

tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-172 + 100)/2500 = .7788 tCK(avg)

and

tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 - 100)/2500 = 1.2128 tCK(avg)

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6.6 Refresh Requirement s

6.6.1 Refresh Requirement Parameters

Parameter Symbol 1 Gb Unit

Number of Banks 8

Refresh Window Tj ≤ 85°C tREFW 32 mS

Required number of REFRESH commands (min) R 4,096

Average time between REFRESH commands

(for reference only) Tj ≤ 85°C REFab tREFI 7.8 µS

REFpb tREFIpb 0.975 µS

Refresh Cycle time tRFCab 130 nS

Per Bank Refresh Cycle time tRFCpb 60 nS

Burst Refresh Window = 4 x 8 x tRFCab tREFBW 4.16 µS

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6.7 AC Timings

6.7.1 LPDDR2 AC Timing

(Note 6 apply to the entire table)

Parameter Symbol min /

max min

tCK

Data Rate

Unit

1066

933

800

667

533

400

333

Max. Frequency*4

533

466

400

333

266

200

166

MHz

Clock Timing

Average Clock Period tCK(avg)

MIN

1.875

2.15

2.5

3.75

MAX

100

Average high pulse width tCH(avg)

MIN

0.45

tCK(avg)

MAX

0.55

Average low pulse width tCL(avg)

MIN

0.45

tCK(avg)

MAX

0.55

Absolute Clock Peri od

CK(abs)

MIN

CK(avg)min

+ t

JIT(per)min

Absolute clock HIGH pulse width

(with allowed jitter) tCH(abs),

allowed

MIN

0.43

tCK(avg)

MAX

0.57

Absolute clock LOW pulse width

(with allowed jitter) tCL(abs),

(allowed)

MIN

0.43

tCK(avg)

MAX

0.57

Clock Period Jitt er

(with allowed jitter) tJIT(per),

(allowed)

MIN

-90

-95

-100

-110

-120

-140

-150

MAX

100

110

120

140

150

Maximum Clock Jitter between

two consecutive clock cycles

(with allowed jitter)

tJIT(cc),

allowed MAX 180 190 200 220 240 280 300 pS

Duty cycle Jitter

(with allowed jitter) tJIT(duty),

allowed

MIN

MIN ((t

CH(abs),min

- t

CH(avg),min)

(tCL(abs),min - tCL(avg),min)) * tCK(avg) pS

MAX MAX ((tCH(abs),max - tCH(avg),max),

(tCL(abs),max - tCL(avg),max)) * tCK(avg) pS

Cumulative error ac ross 2 cycles tERR(2per),

(allowed) MIN -132 -140 -147 -162 -177 -206 -221 pS

MAX

132

140

147

162

177

206

221

Cumulative error acros s 3 cycle s tERR(3per),

(allowed) MIN -157 -166 -175 -192 -210 -245 -262 pS

MAX

157

166

175

192

210

245

262

Cumulative error ac ross 4 cycles tERR(4per),

(allowed) MIN -175 -185 -194 -214 -233 -272 -291 pS

MAX

175

185

194

214

233

272

291

Cumulative error ac ross 5 cycles tERR(5per),

(allowed) MIN -188 -199 -209 -230 -251 -293 -314 pS

MAX 188 199 209 230 251 293 314

Cumulative error ac ross 6 cycles tERR(6per),

(allowed) MIN -200 -211 -222 -244 -266 -311 -333 pS

MAX

200

211

222

244

266

311

333

Cumulative error ac ross 7 cycles tERR(7per),

(allowed) MIN -209 -221 -232 -256 -279 -325 -348 pS

MAX

209

221

232

256

279

325

348

Cumulative error ac ross 8 cycles tERR(8per),

(allowed) MIN -217 -229 -241 -266 -290 -338 -362 pS

MAX

217

229

241

266

290

338

362

Cumulative error ac ross 9 cycles tERR(9per),

(allowed) MIN -224 -237 -249 -274 -299 -349 -374 pS

MAX

224

237

249

274

299

349

374

Cumulative error ac ross 10

cycles tERR(10per),

(allowed) MIN -231 -244 -257 -282 -308 -359 -385 pS

MAX

231

244

257

282

308

359

385

Cumulative error ac ross 11

cycles tERR(11per),

(allowed) MIN -237 -250 -263 -289 -316 -368 -395 pS

MAX

237

250

263

289

316

368

395

Cumulative error ac ross 12

cycles tERR(12per),

(allowed) MIN -242 -256 -269 -296 -323 -377 -403 pS

MAX

242

256

269

296

323

377

403

Cumulative error ac ross n = 13,

14 . . . 49, 50 cycles tERR(nper),

(allowed) MIN tERR(nper),allowed,min = (1 + 0.68ln(n)) * tJIT(per),allowed,min pS

MAX

ERR(nper),allowed,max

= (1 + 0.68ln(n)) * t

JIT(per),allowed,max

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Parameter Symbol min /

max min

tCK Data Rate Unit

1066 933 800 667 533 400 333

ZQ Calibration Parameters

Initializat i on Cal i bration Time tZQINIT MIN 1 µS

Full Calibrat i on Time tZQCL MIN 6 360 nS

Short Calibration T ime tZQCS MIN 6 90 nS

Calbration Reset Time tZQRESET MIN 3 50 nS

Read Parameters*11

DQS output ac cess time from CK_t/CK_c tDQSCK MIN 2500 pS

MAX 5500

DQSCK Delta Short*15 tDQSCKDS MAX 330 380 450 540 670 900 1080 pS

DQSCK Delta Medium*16 tDQSCKDM MAX 680 780 900 1050 1350 1800 1900 pS

DQSCK Delta Long*17 tDQSCKDL MAX 920 1050 1200 1400 1800 2400 - pS

DQS - D Q s kew tDQSQ MAX 200 220 240 280 340 400 500 pS

Data hold skew factor tQHS MAX 230 260 280 340 400 480 600 pS

DQS Output High Pulse Width tQSH MIN tCH(abs) - 0.05 tCK(avg)

DQS Output Low Pulse Width tQSL MIN tCL(abs) - 0.05 tCK(avg)

Data Half Period tQHP MIN min(tQSH, tQSL) tCK(avg)

DQ / DQS output hold time from DQS tQH MIN tQHP - tQHS pS

Read preamble*12,*13 tRPRE MIN 0.9 tCK(avg)

Read postamble*12,*14 tRPST MIN tCL(abs) - 0.05 tCK(avg)

DQS low-Z from clock*12 tLZ(DQS) MIN tDQSCK(MIN) - 300 pS

DQ low-Z from clock*12 tLZ(DQ) MIN tDQSCK(MIN) - (1.4 * tQHS(MAX)) pS

DQS high-Z from clock*12 tHZ(DQS) MAX tDQSCK(MAX) - 100 pS

DQ high-Z from clock*12 tHZ(DQ) MAX tDQSCK(MAX) + (1.4 * tDQSQ(MAX)) pS

Write Parameters*11

DQ and DM input hold time (Vref based) tDH MIN 210 235 270 350 430 480 600 pS

DQ and DM input setup time (Vref based) tDS MIN 210 235 270 350 430 480 600 pS

DQ and DM input pulse width tDIPW MIN 0.35 tCK(avg)

Write command to 1st DQS latching

transition tDQSS MIN 0.75 tCK(avg)

MAX 1.25

DQS input high-level width tDQSH MIN 0.4 tCK(avg)

DQS input low-level width tDQSL MIN 0.4 tCK(avg)

DQS falling edge to CK setup time tDSS MIN 0.2 tCK(avg)

DQS falling edge hold time from CK tDSH MIN 0.2 tCK(avg)

Write postambl e tWPST MIN 0.4 tCK(avg)

Write preamble tWPRE MIN 0.35 tCK(avg)

CKE Input Parameters

CKE min. pulse width (high and low pulse

width) tCKE MIN 3 3 tCK(avg)

CKE input setup time tISCKE*2 MIN 0.25 tCK(avg)

CKE input hold time tIHCKE*3 MIN 0.25 tCK(avg)

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Parameter Symbol min /

max min

tCK Data Rate Unit

1066 933 800 667 533 400 333

Command Address Input Parameters*11

Address and control input setup time

(Vref based) tIS*1 MIN 220 250 290 370 460 600 740 pS

Address and control input hol d time

(Vref based) tIH*1 MIN 220 250 290 370 460 600 740 pS

Address and control input pulse width tIPW MIN 0.40 tCK(avg)

Boot Parameters (10 MHz - 55 MHz)*5, 7, 8

Clock Cycle Time tCKb MAX 100 nS

MIN 18

CKE Input Setup Time tISCKEb MIN 2.5 nS

CKE Input Hold Time tIHCKEb MIN 2.5 nS

Address & Control Input Setup Time tISb MIN 1150 pS

Address & Control Input Hold Time tIHb MIN 1150 pS

DQS Output Data Access Time

from CK_t/CK_c tDQSCKb MIN 2.0 nS

MAX 10.0

Data Strobe Edge to

Ouput Data Edge tDQSQb - 1.2 tDQSQb MAX 1.2 nS

Data Hold Skew Factor tQHSb MAX 1.2 nS

Mode Register Parameters

MODE REGISTER Write command period tMRW MIN 5 5 tCK(avg)

Mode Register Read command period tMRR MIN 2 2 tCK(avg)

LPDDR2 SDRAM Core Parameters*9

Read Latency RL MIN 3 8 7 6 5 4 3 3 tCK(avg)

Write Latency WL MIN 1 4 4 3 2 2 1 1 tCK(avg)

ACTIVE to ACTIVE command period tRC MIN tRAS + tRPab (with all-bank Prechar ge)

tRAS + tRPpb (with per-bank Precharge) nS

CKE min. pulse width during Self-Refresh

(low pulse width during Self -Refresh) tCKESR MIN 3 15 nS

Self refresh exit to next valid command

delay tXSR MIN 2 tRFCab + 10 nS

Exit power down to next valid command

delay tXP MIN 2 7.5 nS

CAS to CAS delay tCCD MIN 2 2 tCK(avg)

Internal Read to Precharge command delay tRTP MIN 2 7.5 nS

RAS to CAS Delay tRCD Fast 3 15 nS

Row Precharge Time (single bank) tRPpb Fast 3 15 nS

Row Precharge Time (all banks) tRPab

8-bank Fast 3 18 nS

Row Active Time tRAS MIN 3 42 nS

MAX - 70 µS

Write Recovery Time tWR MIN 3 15 nS

Internal Write to Read Command Delay tWTR MIN 2 7.5 10 nS

Active bank A to Active bank B tRRD MIN 2 10 nS

Four Bank Activate Window tFAW MIN 8 50 60 nS

Minimum Deep Power Down Time tDPD MIN 500 µS

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Parameter Symbol min /

max min

tCK Data Rate Unit

1066 933 800 667 533 400 333

LPDDR2 Temperature De-Rating

tDQSCK De-Rating tDQSCK

(Derated) MAX 5620 6000 pS

Core Timings Temperature De-Rating

tRCD

(Derated) MIN tRCD + 1.875 nS

tRC

(Derated) MIN tRC + 1.875 nS

tRAS

(Derated) MIN tRAS + 1.875 nS

tRP

(Derated) MIN tRP + 1.875 nS

tRRD

(Derated) MIN tRRD + 1.875 nS

Notes:

1. Input set-up/hold time for signal (CA[0:n], CS_n).

2. CKE input set up time is measured from CKE reaching high/l ow voltage level to CK_t/CK_c crossi ng.

3. CKE input hold time is measured from CK _t/CK _c crossi ng to CKE reaching high/low voltage level.

4. Frequency values are for ref erence only. Cl ock cycle tim e (tCK) shal l be used to determine device capabilities.

5. To guarantee device operation before the LPDDR2 device is configured a number of AC boot timing parameters are defined in this table.

Boot parameter symbols have the letter b appended, e.g. tCK during boot is tCKb.

6. Frequency values are for ref erence only. Cl ock cycle tim e (tCK or tCKb) shall be used to determine device capabilities.

7. The SDRAM will set some Mode register default values upon receiving a RESET (MRW) command as specifi ed in “Mode Regist er

Definition”.

8. The output skew param eters are measured with Ron default setti ngs into the referenc e load.

9. The min tCK column applies only when tCK is greater than 6nS for LPDDR2-S4 devices.

10. All AC timings assum e an input slew rate of 1V/nS.

11. Read, W rite, and Input Setup and Hold values are referenced to Vref.

12. For low-to-high and high-to-low transi t i ons, the timing referenc e will be at the point when the signal cro sses VTT. tHZ and tLZ transitions

occur in the same access time (with respect to clock) as valid data transiti ons. These parameters are not referenced to a specific vol t age

level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins dri ving (for tRPRE, tLZ(DQS),

tLZ(DQ) ). Below “HSUL_12 Driver Output Reference Load for Timing and Slew Rate” figure shows a method to calculate the point when

device is no longer driving tHZ(DQS) and tHZ(DQ), or begins dri vi ng tLZ(DQS), tLZ(DQ) by measuri ng the signal at two different voltages. The

actual voltage measurem ent points are not crit ical as long as the calculati on is consist ent.

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VTT + 2x Y mV

VTT + Y mV

VTT - Y mV

VTT - 2x Y mV

VTT

Actual waveform

tLZ(DQS), tLZ(DQ)

tHZ(DQS), tHZ(DQ)

VOH - X mV

VOH - 2x X mV

VOL + 2x X mV

VOL + X mV

VTT

VOH

VOL

2x Y

2x X X

T1T2

Stop driving point = 2 x T1 – T2

begin driving point = 2 x T1 – T2

Figure of HSUL_12 Driver Output Reference Load for Timing and Slew Rate

The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defin ed as sin gle-end ed. T he tim ing param eter s tRPRE

and tRPST are determined from the differential signal DQS_t-DQS_c.

13. Measured from the start driving of DQS_t - DQS_c to the start driving the first rising strobe edge.

14. Measured from the f rom start driving the last falling st robe edge to the stop driving DQS_t , DQS_c.

15. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence

of bursts within a 160nS rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drif t in the system is < 10°C/s.

Values do not include clock jitter.

16. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 1. 6µS rolling window.

tDQSCKDM is not tested and is guaranteed by desi gn. Tem perature drift in the system is < 10°C/s. Values do not include clock jitter.

17. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 32mS rolling window.

tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10°C/s. Values do not include clock jitter.

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Publication Release Date: May 22, 2014

Revision: A01-001

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6.7.2 CA and CS_n Setup, Hold and Derating

For all input signals ( CA and CS_n) t he total tIS (s etup time) and tIH (h old tim e) required is ca lculated b y addi ng the

data sheet tIS(base) and tIH(base) value (see 7.7.2.1 “CA and CS_n Setup and Hold Base-Values f or 1V/nS” table)

to the ΔtIS and ΔtIH derating value (see 7.7.2.2 “Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220” table).

Example: tIS (total setup time) = tIS(base) + ΔtIS.

Setup (tIS) nom inal s lew rat e for a rising signal is defin ed as the s lew r ate bet ween the last c rossing of VREF(dc) and

the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the

last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew

rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value (see 7.7.2.4 “Nominal

Slew Rate and tVAC for Setup Time tIS for CA and CS_n with Respect to Clock” figure). If the actual signal is

later tha n t he nominal sle w r ate l in e a n ywhere betwee n s hade d ‘VREF(dc) to ac r eg i on’, th e sle w rat e of a tangent line

to the actual signal from the ac level to dc level is used for derating value (see 7.7.2.6 “Tangent Line for Setup

Time tIS for CA and CS_n with Respect to Clock” figure).

Hold ( tIH) nominal slew rat e for a r ising sign al is def ined as the sle w rate bet ween the l ast cros sing of V IL(dc)max and

the first crossing of VREF(dc). Hold (tIH) nomina l slew rate f or a fallin g signal is defined as th e slew r ate between the

last cros sing of VIH(dc)min and the firs t crossing of VREF(dc). If the actual sign al is alwa ys later than the nom inal slew

rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value (see 7.7.2.5 “Nominal

Slew Rate for Hold Time tIH for CA and CS_n with Respect to Clock” figure). If the actual signal is earlier than

the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the

actual s ignal fr om the dc leve l to VREF(dc) level is us ed for derating v alue (see 7.7.2.7 “Tangent Line for Hold Time

tIH for CA and CS_n with Respect to Clock” figure).

For a va li d transition th e in put signal has to remain ab ove /be lo w VIH/IL(ac) for some time tVAC (see 7.7.2.3 “Required

Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition” table).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached

VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and

reach VIH/IL(ac).

For slew rates in between the values listed in 7.7.2.2 “Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220”

table, the derating values may obtained by linear interpolation. These values are typically not subject to production

test. They are verified by design and characterization.

6.7.2.1 C A and CS_n Set up and Hold Base-Values for 1V/nS

Unit [pS] LPDDR2-1066 LPDDR2-800 reference

tIS(base)

0 70 VIH/L(ac) = VREF(dc) ± 220mV

tIH(base) 90 160 VIH/L(dc) = VREF(dc) ± 130mV

Note: ac/dc referenced for 1V/nS CA and CS_n slew rate and 2V/nS differential CK_t-CK_c slew rate.

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6.7.2.2 Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220

ΔtIS, ΔtIH derat i ng i n [pS] AC /DC based

AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV

DC130 Threshold -> VIH(dc)=VREF(dc)+130mV, V IL(dc)=VREF(dc)-130mV

CA, CS_n

Slew Rate

V/nS

CK_t,CK_c Differential Slew Rate

4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/ nS 1. 6 V/nS 1. 4 V/nS 1. 2 V/nS 1. 0 V/ nS

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

2.0 110 65 110 65 110 65 - - - - - - - - - -

1.5 74 43 73 43 73 43 89 59 - - - - - - - -

1.0 0 0 0 0 0 0 16 16 32 32 - - - - - -

0.9 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - -

0.8 - - - - -8 -13 8 3 24 19 40 35 56 55 - -

0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78

0.6 - - - - - - - - 10 -3 26 13 42 33 58 65

0.5 - - - - - - - - - - 4 -4 20 16 36 48

0.4 - - - - - - - - - - - - -7 2 17 34

Note: Cel l contents ‘ -’ are defined as not supported.

6.7.2.3 Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition

Slew Rate [V/nS] tVAC @ 220mV [pS]

min max

> 2.0 175 -

2.0 170 -

1.5 167 -

1.0 163 -

0.9 162 -

0.8 161 -

0.7 159 -

0.6 155 -

0.5 150 -

<0.5 150 -

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6.7.2.4 Nominal Slew Rate and tVAC for Setup Time tIS for CA and CS_n with Respect to Clock

CK_c

CK_t

VDDCA

VIH(ac) min

VIH(dc) min

VREF(dc)

VIL(dc) max

VIL(ac) max

VREF to ac

region

nominal

Slew rate

nominal

Slew rate

VREF to ac

region

tIHtIH

tIS tIS

tVAC

VssCA

Setup Slew Rate = VREF(dc) - VIL(ac)max

Falling Signal Δ TF Setup Slew Rate = VIH(ac) min - VREF(dc)

Rising Signal Δ TR

Δ TF Δ TR

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6.7.2.5 Nominal Slew Rate for Hold Time tIH for CA and CS_n with Respect to Clock

CK_t

CK_c

DDCA

IH(AC)

min

IH(DC)

min

REF(DC)

IL(DC)

max

IL(AC)

max

DC to V

REF

region nominal

Slew rate

nominal

Slew rate DC to V

REF

region

Hold Slew Rate = V

REF(DC)

- V

IL(DC)

max

Rising Signal Δ TR Hold Slew Rate = V

IH(DC)

min - V

REF(DC)

Falling Signal Δ TF

Δ TF

Δ TR

SSCA

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6.7.2.6 Tangent Line for Setup Time tIS for CA and CS_n wi th Respect to Clock

CK_c

CK_t

VDDCA

tIH

tIS tIS

VIH(AC) min

VIH(DC) min

VREF(DC)

VIL(DC) max

VIL(AC) max

nominal

line

tangent

line

tangent

line

nominal

line

VREF to AC

region

VREF to AC

region

Δ TR

Δ TF

tVAC

Setup Slew Rate = tangent line[V

REF(DC)

- V

IL(AC)

max]

Falling Signal Δ TF

Setup Slew Rate = tangent line[VIH(AC)min - VREF(DC)]

Rising Signal Δ TR

VSSCA

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6.7.2.7 Tangent Line for Hold Time tIH for CA and CS_n with Respect to Clock

CK_t

CK_c

DDCA

IH(AC)

min

IH(DC)

min

REF(DC)

IL(DC)

max

IL(AC)

max

DC to V

REF

region

DC to V

REF

region

nominal

line

nominal

line

tangent

line

tangent

line

Δ TR Δ TF

Hold Slew Rate = tangent line [V

REF(DC)

- V

IL(DC)

max

Rising Signal Δ TR

Hold Slew Rate = tangent line [V

IH(DC)

min - V

REF(DC)

]

Falling Signal Δ TF

SSCA

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Publication Release Date: May 22, 2014

Revision: A01-001

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6.7.3 Data Setup, Hold and Slew Rate Derating

For all input signa ls (D Q, D M) th e t otal tDS (s etup t im e) and tDH (hold t im e) requir ed is ca lculated b y addi ng the data

sheet tDS(base) and tDH(base) value (see 7.7.3.1 “Data Setup and Hold Base-Values” table) to the ΔtDS and ΔtDH

(see 7.7.3.2 “Derating Values LPDDR2 tDS/tDH - AC/DC Based AC220” table) derating value respectively.

Example: tDS (total setup time) = tDS(base) + ΔtDS.

Setup (tDS) nominal slew r ate f or a ris ing si gnal is defin ed as t he sl ew rat e bet ween the last cr ossin g of V REF(dc) and

the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between

the last crossing of VREF(dc) and the first crossing of VIL(ac)max (see 7.7.3.4 “Nominal Slew Rate and tVAC for

Setup Time tDS for DQ with Respect to Strobe” figure). If the actual si gnal is a lwa ys earli er than t he nom inal sl ew

rate line b etween shad ed ‘VREF(dc) to ac region’, use nom inal slew rate f or derating va lue. If the actua l signal is later

than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to

the actua l signa l from the ac le vel to dc level is used f or deratin g value (see 7.7.3.6 “Tangent Line for Setup Time

tDS for DQ with Respect to Strobe” figure).

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and

the firs t cr os sing of VREF(dc). Hold ( tDH) nominal sle w r ate f or a f alling s ig 5na l is defined as th e s lew ra te between t he

last cros sing of VIH(dc)min and the firs t crossing of VREF(dc) (see 7.7.3.5 “Nominal Slew Rate for Hold time tDH for

DQ with Respect to Strobe” figure). If the actual signal is always later than the nominal slew rate line between

shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the

nominal s lew rate lin e anywhere b etween s haded ‘dc to VREF(dc) region’, the s lew rate of a tangen t line to the ac tual

signal from the dc level to VREF(dc) level is used for derating value (see 7.7.3.7 “Tangent Line for Hold Time tDH

for DQ with Respect to Strobe” figure).

For a va li d tra ns it ion th e in put signal has to r emain above /be lo w V IH/IL(ac) for some time tVAC (see 7.7.3.3 “Required

Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition” table).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached

VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and

reach VIH/IL(ac).

For sle w rates in b etween the values list ed in 7.7.3.2 “Derating Valu es LPDDR 2 tDS/tDH - AC/DC Based AC220”

table, the derating values may obtained by linear interpolation. These values are typically not subject to production

test. They are verified by design and characterization.

6.7.3.1 Data Setup and Hold Base-Values

Unit [pS] LPDDR2-1066 LPDDR2-800 reference

tDS(base) -10 50 VIH/L(ac) = VREF(dc) ± 220mV

tDH(base)

80 140 VIH/L(dc) = VREF(dc) ± 130mV

Note: ac/dc referenced for 1V/nS DQ,DM slew rate and 2V/nS differential DQS_t-DQS_c slew rate.

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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6.7.3.2 Derating Values LPDDR2 tDS/tDH - AC/DC Based AC220

ΔtDS, ΔDH derating in [pS] AC/DC based a

AC220 Threshold -> VIH(ac) = VREF(dc) + 220mV, VIL(ac) = VREF(dc) - 220mV

DC130 Threshold -> VIH(dc) = VREF(dc) + 130mV, VIL(dc) = VREF(dc) - 130mV

DQ, DM Slew

Rate V/nS

DQS_t, DQS_c Differential Slew Rate

4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/ nS 1. 6 V/nS 1. 4 V/nS 1. 2 V/nS 1. 0 V/ nS

ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH

2.0 110 65 110 65 110 65 - - - - - - - - - -

1.5 74 43 73 43 73 43 89 59 - - - - - - - -

1.0 0 0 0 0 0 0 16 16 32 32 - - - - - -

0.9 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - -

0.8 - - - - -8 -13 8 3 24 19 40 35 56 55 - -

0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78

0.6 - - - - - - - - 10 -3 26 13 42 33 58 65

0.5 - - - - - - - - - - 4 -4 20 16 36 48

0.4 - - - - - - - - - - - - -7 2 17 34

Note: Cel l contents ‘ -’ are defined as not supported.

6.7.3.3 Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition

Slew Rate [V/nS] tVAC @ 220mV [pS]

min max

> 2.0 175 -

2.0 170 -

1.5 167 -

1.0 163 -

0.9 162 -

0.8 161 -

0.7 159 -

0.6 155 -

0.5 150 -

<0.5 150 -

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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6.7.3.4 Nominal Slew Rate and tVAC for Setup Time tDS for DQ with Respect to Strobe

DQS_t

DQS_c

tDH

tDS tDS

VDDQ

nominal

Slew rate

VIH(AC) min

VIH(DC) min

VREF(DC)

VIL(DC) max

VIL(AC) max

Vss

nominal

Slew rate

VREF to AC

region

VREF to AC

region

tVAC

Δ TR

Δ TF

Setup Slew Rate = V

REF(DC)

- V

IL(AC)

max

Falling Signal Δ TF Setup Slew Rate = VIH(AC)

min

- VREF(DC)

Rising Signal Δ TR

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Publication Release Date: May 22, 2014

Revision: A01-001

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6.7.3.5 Nominal Slew Rate for Hold time tDH for DQ with Respect to Strobe

DQS_t

DQS_c

IH(AC)

min

IH(DC)

min

REF(DC)

IL(DC)

max

IL(AC)

max

VssQ

DDQ

Hold Slew Rate = [VREF(DC) - VIL(DC)max

Rising Signal Δ TR

DC to V

REF

region

nominal

Slew rate

nominal

Slew rate

DC to V

REF

region

Hold Slew Rate = [VIH(DC)min - VREF(DC)

Falling Signal Δ TF

Δ TFΔ TR

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Publication Release Date: May 22, 2014

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6.7.3.6 Tangent Line for Setup Time tDS for DQ with Respect to Strobe

DQS_c

DQS_t t

IH(ac)

min

DDQ

Setup Slew Rate = tangent line[VIH(ac)min - VREF(dc)

Rising Signal Δ TR

VAC Δ TR

tangent

line

REF to ac

region

nominal

line

IH(dc)

min

REF(dc)

IL(dc)

max

IL(ac)

max

VssQ

tangent

line

nominal

line

REF to ac

region

Δ TF

VAC

Setup Slew Rate = tangent line[VREF(dc) - VIL(ac)max]

Falling Signal Δ TF

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

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6.7.3.7 Tangent Line for Hold Time tDH for DQ with Respect to Strobe

DQS_c

DQS_t t

DDQ

IH(AC)

min

IH(DC)

min

REF(DC)

IL(DC)

max

IL(AC)

max

Vss

tangent

line

nominal

line

DC to V

REF

region

Δ TR Δ TF

Hold Slew Rate = tangent line [VREF(DC) - VIL(DC)max

Rising Signal Δ TR

DC to V

REF

region

tangent

line

nominal

line

Hold Slew Rate = tangent line [VIH(DC)min - VREF(DC)]

Falling Signal Δ TF

W97AH6KK / W97AH2KK

Publication Release Date: May 22, 2014

Revision: A01-001

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7. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

A01-001 May 22, 2014 All Initial formally datasheet

Sep 07, 2016 Modified for MCP Combo Datasheet

Important Notice

Winbond products are not designed , intended, authorized or warranted for use as components in systems or

equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship

instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for

other applications intended to support or sustain life. Further more, Winbond products are not intended for

applications wherein failure of Winbond products could result or lead to a situation wherein personal injury,

death or severe property or enviro nmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their own risk and

agree to fully indemnify Winbond for any damages resulting from such improper use or sales.