B25 -144 t we 4 HEWLETT PACKARD Uz Four Character 5.0mm (0.2 in.) Smart 5 x 7 Alphanumeric Displays Technical Data Features Enhanced Drop-in Replace- ment to HPDL-2416 Smart Alphanumeric Display Built-in RAM, ASCII Decoder, and LED Drive Circuitry * CMOS IC for Low Power Consumption * Software Controlled _ Dimming Levels and Blank * 128 ASCII Character Set * End-Stackable * Categorized for Luminous Intensity; YELLOW and GREEN Categorized for Color * Low Power and Sunlight Viewable AlGaAs Versions * Wide Operating Temperature Range -40C to +85C HDLR-2416 HDLO-2416 HDLA-2416 HDLY-2416 HDLG-2416 HDLS-2416 HDLU-2416 Description These are 5.0 mm (0.2 inch) four character 5 x 7 dot matrix displays driven by an on-board CMOS IC. These displays are pin for pin compatible with the HPDL-2416. The IC stores and decodes 7 bit ASCII data and displays it using a 5 x 7 font. Multiplexing circuitry, and drivers are also part of the IC. The IC has fast setup and hold times which makes it easy to interface to a microprocessor. Absolute Maximum Ratings Supply Voltage, Vop to Ground!) ooo. esacsesesesescesseces -0.5 V to 7.0 V Input Voltage, Any Pin to Ground ...eeec............. -0.5 V to Vop + 0.5 V Free Air Operating Temperature Range, Ty veseeeseeeee -40C to +85C Relative Humidity (non-condensing) at 65C ooooeeccececcecsecccccc 85% Storage Temperature, T Maximum Solder Temperature, 1.59 mm * Excellent ESD Protection (0.063 in.) below Seating Plane, t <5 SC. cooccecsscccsssssseeesecs..... 260C * Wave Solderable ESD Protection, R = 1.5 kQ, C = 100 PP eee. V, = 2kV (each pin) * Wide Viewing Angle Note: (50 typ) 1. Maximum Voltage is with no LEDs illuminated. Devices: Standard Red | AlGaAs Red | High Efficiency Red Orange Yellow Green HDLR-2416 HDLS-2416 HDLO-2416 HDLA-2416 | HDLY-2416 HDLG-2416 HDLU-2416 WITH THE HDLX-2416 EE WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVEDThe address and data inputs can be disabled which allows operates at the 100% brightness can be directly connected to the the HDLX-2416 to operate level, while the HDLU-2416 microprocessor address and exactly like an HPDL-2416 by operates at the 27% brightness data buses. disabling all of the enhance- level. Power on sets the internal ments except the expanded brightness control (bits 3-5) in The HDLX-2416 has several character set. the control register to binary enhancements over the HPDL- code (000). For the HDLS-2416 2416. These features include an The difference between the binary code (000) corresponds to expanded character set, internal sunlight viewable HDLS-2416 a 100% brightness level, and for 8 level dimming control, exter- and the low power HDLU-2416 the HDLU-2416 binary code nal dimming capability, and occurs at power-on or at the (000) corresponds to a 27% individual digit blanking. default brightness level. Follow- _ brightness level. The other Finally, the extended functions ing power up, the HDLS-2416 seven brightness levels are identical for both parts. Package Dimensions a 0.990 3 0.126 t 0.38 0.25 to.13 6.35 0.38 peF 025 70.13 yp 250 YP 0.018 a.oto.c0s Y i | . i t | | 10.18 peel | 15.24 ! 0.600 i [ | 1 IMAGE mI t 1.52 241 | 0.135 d.o69 AEF a.cgs 7YP PIN 1 IDENTIFIER DATE CODE (YEAR, WEEK) VA PART NUMBER - LUMINOUS INTENSITY a n o a COLOR BIN (3) HDLX-2416 YYWW Xzet SS TTT Ta oF 0.096 _| Le 2.84 Typ 0.514013 , 0.020 =.005 me iy 8 { no [ a a Pin Pin No. Function No. Function 1 | CE, Chip Enable 10 | GND 2 CE, Chip Enable 11 D, Data Input Notes: 3 CLR Clear 12 D, Data Input 1. Unless otherwise specified the tolerance 4 CUE Cursor Enable 13 | D, Data Input on all dimensions is +0.254 mm (+0.010"} 5 CU Cursor Select 14 D, Data Input 2. All dimensions are in mumy/inches. 6 WR Write 15 D, Data Input 3. For yellow and green displays only. 7 A, Address Input 16 D, Data Input 1 8 A, Address Input 17 D, Data Input : 9 Von 18 | BL Display BlankCharacter Set | bo 0 1 0 1 0 1 1 a 1 0 ASCII D1 0 0 1 1 Q 0 0 1 1 0 CODE D2 0 0 0 0 1 1 Q 0 0 1 D3 {a 0 0 0 0 0 1 1 1 1 D6;05/D4} Hex 0 1 2 3 4 5 9 A B c e ole ., asee ata 0 0 e 6. e ols - seus s s ane ous ae eo. ae ae ee ae ae aa e e aae ee oe e a) ee o es eo] een |e e aae coo | sae aasan 0 0 1 1 ry ej e|s ale s a a e es e/* e108 ole eo! @ een; s e| @ es s/o @#/ sien a a ean oan ose eee ons Gee e e s ee es s s e ae ae e . a se . e s s o/1 0 2 s a 8 ee neues . . @ oe . s s * ae eau a eas esene i es a see e se] s se an essse .. e 8 Oof14]4 3 [ues : son e oe a e a ae og e s 7 a8 o peeaa e e a s e e ae a e ass ese eenen . e es e e sae e a aos eee ls e sp @)i8 @ e sis e@ ae scenes : 3 ae 1 o}0 4 : e|s" a 2 e jee eo ]/s @ eo sise aee ie e ase on e e 2 seaea ese . aap e se a . Ad , ti oj;14] 5 *e 1g *. : e * e s a e e . ea asses aoe asa sseea oe s . 2 se a. s iJ e ene ae te aoe ene ie se tsa Tirjoye) % : 2] sy he] ge 3 e . 8 eu es e es eae aes aa oe ae8 e ese e e e e a an 8 a e s eeelsaa eases seen |p ae onue aesa |e ele eis ela ele @ | seean e . e 1 1 1 7 eo sle oe s e B8is ela a ssifje os a e eoue acca enes | 2 ann a e os ejaas a 8 s e a 2 ele a a o ne es ae@e oes s s a a a eee e e . ease oe ana * ea * s esdee e cd e aes Notes: 1. High = 1 tevel. 2. Low = 0 levet4 Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Supply Voltage Vop 4.5 5.0 5.5 Vv Electrical Characteristics Over Operating Temperature Range 4.5 Dominant Wavelength"! ry 585 nmHDLG-2416 Parameter Symbol | Min. | Typ. | Units Test Conditions Average Luminous I, 1.2 5.6 med *" i]luminated in all four digits. Intensity per digit, 19 dots ON Character Average Peak Wavelength rppaK 568 nm Dominant Wavelength?! a 574 nm Notes: 1. Refers to the initial case temperature of the device immediately prior to the light measurement. 2. Dominant wavelength, X 4: 18 derived from the CIE chromaticity diagram, and represents the single wavelength which defines the color of the device. AC Timing Characteristics Over Operating Temperature Range at V,,, = 4.5 V Parameter Symbol Min Units Address Setup tas 10 ns Address Hold tay 40 ns Data Setup tos 50 ns Data Hold tou 40 ns Chip Enable Setup tors 0 ns Chip Enable Hold CEH 0 ns Write Time ty 75 ns Clear tour 10 us Clear Disable . torrp 1 Ls Timing Diagram cE, 2.0V cE, 0.8V x 'ces>] t "cen Ag-A,,cU 20v 0.8 V as m| rSan | wR \ Los tw D9 -Ds 2.0V \08 Vv tose eeton tcLa 'ciro*1 2.0V oO} rl 2 08 V Enlarged Character Font oaoioosy a M 7 / a Bn i | , # a a 68 ozsrooot ly | | TYP _ NOTES: 1, UNLESS OTHERWISE SPECIFIED THE TOLERANCE i L 0.80 (0.031) TYP ON ALL DIMENSIONS 1S 20.254 mm (0.010!N.) 2. DIMENSIONS ARE IN MILLIMETRES (INCHES).Electrical Description Pin Function Description Chip Enable (CE, and CE,, pins 1 and 2) CE, and CE, must be a logic 0 to write to the display. Clear (CLR, pin 3) When CLR is a logic 0 the ASCII RAM is reset to 20hex (space) and the Control Register/ Attribute RAM is reset to OOhex. Cursor Enable (CUE pin 4) CUE determines whether the IC displays the ASCII or the Cursor memory. (1 = Cursor, 0 = ASCID. Cursor Select CU determines whether data is stored in the pins 8 and 7) (CU, pin 5) ASCII RAM or the Attribute RAM/Control Register. (1 = ASCII, 0 = Attribute RAM/Control Register). Write WR must be a logic 0 to store data in the CWR, pin 6) display. Address AA, selects a specific location in the display Inputs memory. Address 00 accesses the far right (A, and A,, display location. Address 11 accesses the far left location. Data Inputs D,-D, are used to specify the input data for the (D,-D,, display. pins 11-17) Von Vop is the positive power supply input. (pin 9) GND GND is the display ground. (pin 10) Blanking BL is used to flash the display, blank the Input display or to dim the display. (BL, pin 18) Display Internal Block Diagram Figure 1 shows the HDLX-2416 display internal block diagram. The CMOS IC consists ofa 4x7 Character RAM, a 2 x 4 Attrib- ute RAM, a 5 bit Control Regis- ter, a 128 character ASCII decoder and the refresh circuitry necessary to synchronize the decoding and driving of four 5 x 7 dot matrix displays. Four 7 bit ASCII words are stored in the Character RAM. The IC reads the ASCII data and decodes it via the 128 character ASCII decoder. The ASCII decoder includes the 64 character set of the HPDL-2416, 32 lower case ASCII symbols, and 32 foreign language sym- bols. A 5 bit word is stored in the Control Register. Three fields within the Control Register provide an 8 level brightness control, master blank, and extended functions disable. For each display digit location, two bits are stored in the Attrib- ute RAM. One bit is used to enable a cursor character at each digit location. A second bit is used to individually disable the blanking features at each digit location. The display is blanked and dimmed through an internal blanking input on the row drivers. Logic within the IC allows the user todim the __ display either through the BL input or through the brightness control in the control register. Similarly the display can be blanked through the BL input, the Master Blank in the Control Register, or the Digit Blank Disable in the Attribute RAM.| {mle a Cc Oy, a Q| S| a al CHARACTER/CURSOR MULTIPLEXER MULTIPLEXER CHARACTER/ CURSOR SELECT CHARACTER RAM ASCII DECODER . 2 | WRITE DATA Zi CHARACTER Ao- Ary ADDRESS ouT 7 SELECT COLUMN 13 a 7 DATA 7 d Dg - Dg J DATAIN 4 | >} WRITE (4x 7) 22} READ 3] Row CURSOR _ 75 7 ADORESS 7 | SELECT CHARACTER f~! CLR xa_____] RI M ATTRIBUTE RA cue oc, Do DIGIT CURSOR D DIGIT BLANK 1 DISABLE Ao-Ai WRITE ADDRESS {2x 4) WRITE 2 7 READ ADDRESS CLR ctr _ CONTROL REGISTER Dy MASTER BLANK 3_}| BRIGHTNESS -D ; Da-Os-7 LEVELS - EXTENDED De FUNCTIONS DISPLAY 1x5 ) 4 }- WRITE 3 4 Ls -q CLR eLR 13 et 4 DIGITAL DUTY ; CONTROL 4 (LSB"s) osc . +32 7 2(MSB"s) f Figure 1. Internal Block Diagram COLUMN DRIVERS ROW DRIVERS | ROW SELECT DISPLAY BLANKDisplay Clear Data stored in the Character RAM, Control Register, and Attribute RAM will be cleared if the clear (CLR) is held low fora minimum of 10 ps. Note that the display will be cleared regardless of the state of the chip enables (CE,, CE ): After the display is cleared, the ASCII code for a space (20hex) i is loaded into all character RAM locations and 00hex is loaded into all Attribute RAM/Control Register memory locations. Data Entry Figure 2 shows a truth table for the HDLX-2416 display. Setting the chip enables (CE,, CE 2) to logic 0 and the cursor select (CU) to logic 1 will enable ASCII data loading. When cursor select (CU) is set to logic 0, data will be loaded into the Control Register and Attribute RAM. Address inputs A,-A, are used to select the digit location in the display. Data inputs D,-D, are used to load information into the dis- play. Data will be latched into the display on the rising edge of the WR VR signal. D,-D, ,A-A,, CE, _CE,, and cu must be held stable during the write cycle to ensure that correct data is stored into the display. Data can be loaded into the display in any order. Note that when and A, are logic 0, data is stored in the right most display loca- tion. Cursor When cursor enable (CUE) is a logic 1, a cursor will be displayed in all digit locations where a logic 1 has been stored in the Digit Cursor memory in the Attribute RAM. The cursor consists of all 35 dots ON at half brightness. A flashing cursor can be displayed by pulsing CUE. When CUE is a logic 0, the ASCII data stored in the Character RAM will be dis- played regardless of the Digit Cursor bits. Blanking Blanking of the display is controlled through the BL input, the Control Register and Attrib- ute RAM. The user can achieve a variety of functions by using these controls in different combinations, such as full hardware display blank, soft- ware blank, blanking of individ- CUE {BL} CLR | Ce,| CE, | WRI CU] a | a, D, D, | D, | D, D, D, D, Function 0 1 Display ASCIL 1 1 1 Display Stored Cursor x x x x x x x x x x x Xx x xX Go Reset RAMs Blank Display but do not reset x 0 1 RAMS and Control Register Extended Intensity Master Digit Digit Write to Attribute RAM 0 o Functions Control Blank Blank Cursor and Control Register Disable Disable 0 0 On 000 = 100%* o-= Digit Digit DBD, ~ 0, Allows Digit n to be 0 1 Enable 001 = 60% Display Blank Cursor blanked DD, 010 40% ON Disable 1 1 O11 = 27% DBD, = 1 Prevents Digit n x x 1 0 0 Qo ls 100 = 17% l= Digit Digit from being blanked. 0 Disable 101 = 10% Display Blank Cursor D,-D, 110 = 7% Blanked | Disable 2 2 DC, = 0 Removes cursor from 111 =3% Digit n D, Digiit Digit 0 I Always Blank Cursor DC, = 1 Stores cursor at Enabled Disable 3 3 Digit n 1 0 Digit 0 ASCH Data (Right Most Character) 1 1 Digit 1 ASCTI Data x x { 9 0 0 Write to Character RAM 1 0 > Digit 2 ASCII Data 1 1 Digit 3 ASCII Data (Left Most Character) 1 x Xx x x 1 xX] 1 x | Xx x x x] x | x x x x No Change ) x x 1 0 = Logic 0; 1 = Logic 1; X = Do Not Care; * 000 = 27% for HDLU-2416 Figure 2. Display Truth Tableual characters, and synchronized flashing of individual characters or entire display (by strobing the blank input). All of these blanking modes affect only the output drivers, maintaining the contents and write capability of the internal RAMs and Control Register, so that normal loading of RAMs and Control Register can take place even with the display blanked. Figure 3 shows how the Ex- tended Function Disable (bit D, of the Control Register), Master Blank (bit D, of the Control Register), Digit Blank Disable (bit D, of the Attribute RAM), and BL input can be used to blank the display. When the Extended Function Disable is a logic 1, the display can be blanked only with the BL input. When the Extended Function Disable is a logic 0, the display can be blanked through the BL input, the Master Blank, and the Digit Blank Disable. The entire display will be blanked if either the BL input is logic 0 or the Master Blank is logic 1, providing all Digit Blank Disable bits are logic 0. Those digits with Digit Blank Disable bits a logic 1 will ignore Table 1. Current Requirements at Different Brightness Levels EFD MB DBD, BL 10 0 0 0 0 Display Blanked by BL 0 0 X 1 Display ON 0 x 1 0 Display Blanked by BL. Individual characters "ON" based on "1" being stored in DBD, 0 1 0 x Display Blanked by MB 0 1 1 1 Display Blanked by MB. Individual characters "ON" based on "1" being stored in DBD, 1 X Xx 0 Display Blanked by BL 1 x xX 1 Display ON Figure 3. Display Blanking Truth Table both blank signals and remain ON. The Digit Blank Disable bits allow individual characters to be blanked or flashed in __ synchronization with the BL input. Dimming Dimming of the display is controlled through either the BL input or the Control Register. A pulse width modulated signal can be applied to the BL input to dim the display. A three bit word in the Control Register generates an internal pulse width modulated signal to dim the display. The internal dimming feature is enabled only if the Extended Function Disable is a logic 0. Bits 3-5 in the Control Register provide internal brightness control. These bits are inter- preted as a three bit binary code, with code (000) corresponding to the maximum brightness and code (111) to the minimum brightness. In addition to varying the display brightness, bits 3-5 also vary the average value of I,,. Ip, can be specified at any brightness level as shown in Table 1: Symbol | D,/; D, D, | Brightness | 25C Typ. | 25C Max. Max.over Temp. | Units Inp#) =| 0} 0 | 0 100% 110 130 160 mA Oo}o]1 60% ' .66 79 98 mA ol1iio 40% 45 53 66 mA Oo; 1 1 27% 30 37 46 mA 1] 0 0 17% 20 24 31 mA 1/o] 1 10% 12 15 20 mA 1/1] 0 1% 9 11 15 mA 1;i1ii1 3% 44 6 9 mA+ Voo 1k zt 13 BU {PIN 1a 10 kHz INSTA 1k ouTPuT 250k 2 1 LOG 400 pF T Figure 4. Intensity Modulation Control Using an Astable Multivi- brator (reprinted with permission from Electronics magazine, Sept. 19, 1974, VNU Business pub. Inc.) Figure 4 shows a circuit de- signed to dim the display from 98% to 2% by pulse width modulating the BL input. A logarithmic or a linear potenti- ometer may be used to adjust the display intensity. However, a logarithmic potentiometer matches the response of the human eye and therefore pro- vides better resolution at low intensities. The circuit fre- quency should be designed to operate at 10 kHz or higher. Lower frequencies may cause the display to flicker. Extended Function Disable Extended Function Disable (bit D, of the Control Register) disables the extended blanking _ and dimming functions in the HDLX-2416. If the Extended Function Disable is a logic 1, the internal brightness control, Master Blank, and Digit Blank Disable bits are ignored. How- ever the BL input and Cursor control are still active. This allows downward compatibility to the HPDL-2416. Mechanical and Electri- cal Considerations The HDLX-2416 ts an 18 pin DIP package that can be stacked horizontally and vertically to create arrays of any size. The HDLX-2416 is designed to operate continuously from -40C to + 8S for all possible input conditions, ~ The HDLX-2416 is assembled by die attaching and wire bonding 140 LEDs and a CMOS IC toa high temperature printed circuit board. A polycarbonate lens is placed over the PC board creat- ing an air gap environment for the LED wire bonds. Backfill epoxy environmentally seals the display package. This package construction makes the display highly tolerant to temperature cycling and allows wave solder- ing. ~ The inputs to the CMOS IC are protected against static dis- charge and input current latchup. However, for best results standard CMOS han- dling precautions should be used. Prior to use, the HDLX- 2416 should be stored in anti- static tubes or conductive material. During assembly a grounded conductive work area should be used, and assembly personnel should wear conduc- tive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static charge build-up. Input current latchup is caused when the CMOS inputs are subjected either to a voltage below ground (V,_ < ground) or to a voltage higher than V,, (V._ > Vpp) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should be connected either to ground or to Vip: Voltages should not be applied to the inputs until Vop has been applied to the display. Transient input voltages should be eliminated. Soldering and Post Solder Cleaning Instructions for the HDLX-2416 The HDLX-2416 may be hand soldered or wave soldered with SN63 solder. When hand soldering it is recommended that an electronically temperature controlled and securely grounded soldering iron be used. For best results, the iron tip temperature should be set at 315C (600F). For wave solder- ing, a rosin-based RMA flux can be used. The solder wave temperature should be set at 245C +5C (473F +9F), and dwell in the wave should be set between 1 1/2 to 3 seconds for optimum soldering. The preheat temperature should not exceed 110C (230F) as measured on the solder side of the PC board. Post solder cleaning may be performed with a solvent or aqueous process. For solvent cleaning, Allied Chemicals Genesolv DES, or DuPonts Freon TE may be used. These solvents are azeotropes of trichlorotrifluroethane FC-113 with low concentrations of ethanol (5%). The maximum exposure time in the solvent vapors at boiling temperature should not exceed 2 minutes. Parts should not be handled until dry and cool. Solvents containing high concentrations of alcohols such as methanol, ketones such as acetone or chlorinated solvent should notbe used as they will chemically attack the polycarbonate lens. Solvents containing trichlo- roethane FC-111 or FC-112 and trichloroethylene (TCE) are also not recommended. An aqueous cleaning process may be used. A saponifier, such as Kester bio-kleen Formula 5799 or its equivalent, may be added to the wash cycle of an aqueous process to remove rosin flux residues. Organic acid flux residues must be thoroughly removed by an aqueous cleaning process to prevent corrosion of the leads and solder connections. The optimum water temperature is 60C (140F). The maximum cumulative exposure of the HDLX-2416 to wash and rinse cycles should not exceed 15 minutes. For additional infor- mation on soldering and post readability in the end users ambient lighting conditions. The concept is to employ both luminance and chrominance contrast techniques. These enhance readability by having the OFF-dots blend into the display background and the ON- HDLR-2416/ HDLU-2416/ HDLS-2416: HDLO-2416: HDLA-2416: -HDLY-2416: solder cleaning, see Application - Note 1027. Contrast Enhancement The objective of contrast en- hancement is to provide good HDLG-2416: HEWLETT PACKARD CA) dots vividly stand out against the same background. Contrast enhancement may be achieved by using one of the following filters listed below. For addi- tional information on contrast enhancement, see Application Note 1015. Panelgraphic RUBY RED 60 SGL Homalite H100-1605 RED 3M Louvered Filter R6610 RED or N0210 GRAY Panelgraphic SCARLET RED 65 or GRAY 10 SGL Homalite H100-1670 RED or -1266 GRAY 3M Louvered Filter R6310 RED or N0210 GRAY Panelgraphic AMBER 23, AMBER 26 or GRAY 10 SGL Homalite H100-1709 AMBER or -1266 GRAY 3M Louvered Filter A6010 or N02 10 GRAY Panelgraphic YELLOW 27 or GRAY 10 SGL Homalite H100-1720 AMBER or -1266 GRAY 3M Louvered Filter A5910 AMBER or N0210 GRAY Panelgraphic GREEN 48 SGL Homalite H100-1440 GREEN 3M Louvered Filter G5610 GREEN or NO210 GRAY For more information call: United States: 1-800-752-0900* Or write: Hewlett-Packard Components Customer Information Center Building 49 AV 19310 Pruneridge Avenue Cupertino, California 95014 Canada: (416) 678-9430* Europe: (49) 7031/14-0* Far East/Australia: (65) 271-9444* Japan: (81) 3-331-6111* *Or call your local HP sales office listed in your telephone directory. Ask for a Components representative, Data Subject to Change Copyright 1991 Hewlett-Packard Co. Obsoletes 5091-0680E Printed in U.S.A. 509 1-2676E (8/91)