D−8 DGN−8 D−16
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FEATURES APPLICATIONS
TPS2062/TPS2066
D AND DGN PACKAGE
(TOP VIEW)
†All Enable Inputs Are Active High For TPS2065, TPS2066, and TPS2067
1
GND
TPS2063/TPS2067
D PACKAGE
(TOP VIEW)
TPS2061/TPS2065
D AND DGN PACKAGE
(TOP VIEW)
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
EN1†
EN2†
GND
IN2
EN3†
NC
OC1
OUT1
OUT2
OUT3
NC
NC
GND
IN
IN
EN†
OUT
OUT
OUT
GND
IN
EN2†
OC1
OUT1
OUT2
EN1†
OC2
OC3
OC2OC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DESCRIPTION
TPS201xA
TPS202x
TPS203x
33 mΩ, single 0.2 A − 2 A
0.2 A − 2 A
0.2 A − 2 A
TPS2014
TPS2015
TPS2041B
TPS2051B
TPS2045
TPS2055
TPS2061
TPS2065
80 mΩ, single
600 mA
1 A
500 mA
500 mA
250 mA
250 mA
1 A
1 A
GENERAL SWITCH CATALOG
TPS2042B
TPS2052B
TPS2046
TPS2056
TPS2062
TPS2066
TPS2060
TPS2064
80 mΩ, dual 500 mA
500 mA
250 mA
250 mA
1 A
1 A
1.5 A
1.5 A
TPS2100/1
260 mΩIN1 500 mA
IN2 10 mA
OUT
IN1
IN2 TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
1.3 Ω
TPS2043
TPS2053B
TPS2047
TPS2057
TPS2063
TPS2067
80 mΩ, triple
500 mA
500 mA
250 mA
250 mA
1 A
1 A
TPS2044B
TPS2054B
TPS2048
TPS2058
80 mΩ, quad
500 mA
500 mA
250 mA
250 mA
80 mΩ, dual
TPS2080
TPS2081
TPS2082
TPS2090
500 mA
500 mA
500 mA
250 mA
TPS2091
TPS2092 250 mA
250 mA
80 mΩ, quad
TPS2085
TPS2086
TPS2087
TPS2095
500 mA
500 mA
500 mA
250 mA
TPS2096
TPS2097 250 mA
250 mA
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES
•Heavy Capacitive Loads•70-m ΩHigh-Side MOSFET
•Short-Circuit Protections•1-A Continuous Current•Thermal and Short-Circuit Protection•Accurate Current Limit(1.1 A min, 1.9 A max)•Operating Range: 2.7 V to 5.5 V•0.6-ms Typical Rise Time•Undervoltage Lockout•Deglitched Fault Report ( OC)•No OC Glitch During Power Up•1- µA Maximum Standby Supply Current•Bidirectional Switch•Ambient Temperature Range: -40 °C to 85 °C•ESD Protection
•UL Listed - File No. E169910
The TPS206x power-distribution switches are intended for applications where heavy capacitive loads andshort-circuits are likely to be encountered. This device incorporates 70-m ΩN-channel MOSFET power switchesfor power-distribution systems that require multiple power switches in a single package. Each switch is controlledby a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switchrise times and fall times to minimize current surges during switching. The charge pump requires no externalcomponents and allows operation from supplies as low as 2.7 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
When the output load exceeds the current-limit threshold or a short is present, the device limits the outputcurrent to a safe level by switching into a constant-current mode, pulling the overcurrent ( OCx) logic output low.When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing thejunction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from athermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switchremains off until valid input voltage is present. This power-distribution switch is designed to set current limit at1.5 A typically.
AVAILABLE OPTION AND ORDERING INFORMATION
RECOMMENDED TYPICAL PACKAGEDMAXIMUM SHORT-CIRCUIT NUMBER OF DEVICES
(1)T
A
ENABLE
CONTINUOUS CURRENT LIMIT SWITCHES
MSOP (DGN) SOIC(D)LOAD CURRENT AT 25 °C
Active low TPS2061DGN TPS2061DSingleActive high TPS2065DGN TPS2065DActive low TPS2062DGN TPS2062D-40 °C to 85 °C 1 A 1.5 A DualActive high TPS2066DGN TPS2066DActive low - TPS2063DTripleActive high - TPS2067D
(1) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2062DR).
ORDERING INFORMATION
T
A
SOIC(D)
(1)
STATUS MSOP (DGN)
(1)
STATUS
TPS2061DG4 Active TPS2061DGNG4 ActiveTPS2062DG4 Active TPS2062DGNG4 Active-40 °C to 85 °C
TPS2065DG4 Active TPS2065DGNG4 ActiveTPS2066DG4 Active TPS2066DGNG4 Active
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .
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ABSOLUTE MAXIMUM RATINGS
DISSIPATING RATING TABLE
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Input voltage range, V
I(IN)
(2)
-0.3 V to 6 VOutput voltage range, V
O(OUT)
(2)
, V
O(OUTx)
-0.3 V to 6 VInput voltage range, V
I( EN)
, V
I(EN)
, V
I( ENx)
, V
I(ENx)
-0.3 V to 6 VVoltage range, V
I( OC)
, V
I( OCx)
-0.3 V to 6 VContinuous output current, I
O(OUT)
, I
O(OUTx)
Internally limitedContinuous total power dissipation See Dissipation Rating TableOperating virtual junction temperature range, T
J
-40 °C to 125 °CStorage temperature range, T
stg
-65 °C to 150 °CHuman body model MIL-STD-883C 2 kVElectrostatic discharge (ESD) protection
Charge device model (CDM) 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND.
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING
D-8 585.82 mW 5.8582 mW/ °C 322.20 mW 234.32 mWDGN-8 1712.3 mW 17.123 mW/ °C 941.78 mW 684.33 mWD-16 898.47 mW 8.9847 mW/ °C 494.15 mW 359.38 mW
MIN MAX UNIT
Input voltage, V
I(IN)
2.7 5.5 VInput voltage, V
I( EN)
, V
I(EN)
, V
I( ENx)
, V
I(ENx)
0 5.5 VContinuous output current, I
O(OUT)
, I
O(OUTx)
0 1 AOperating virtual junction temperature, T
J
-40 125 °C
over recommended operating junction temperature range, V
I(IN)
= 5.5 V, I
O
= 1 A, V
I( ENx)
= 0 V, or V
I(ENx)
= 5.5 V (unlessotherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
POWER SWITCH
Static drain-source on-stateresistance, 5-V operation V
I(IN)
= 5 V or 3.3 V, I
O
= 1 A, -40 °C≤T
J
≤125 °C 70 135 m Ωand 3.3-V operationr
DS(on)
Static drain-source on-stateresistance, 2.7-V V
I(IN)
= 2.7 V, I
O
= 1 A, -40 °C≤T
J
≤125 °C 75 150 m Ωoperation
(2)
V
I(IN)
= 5.5 V 0.6 1.5t
r
(2)
Rise time, output
V
I(IN)
= 2.7 V 0.4 1C
L
= 1 µF, R
L
= 5 Ω, T
J
= 25 °C msV
I(IN)
= 5.5 V 0.05 0.5t
f
(2)
Fall time, output
V
I(IN)
= 2.7 V 0.05 0.5
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
(2) Not tested in production, specified by design.
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TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)over recommended operating junction temperature range, V
I(IN)
= 5.5 V, I
O
= 1 A, V
I( ENx)
= 0 V, or V
I(ENx)
= 5.5 V (unlessotherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
ENABLE INPUT EN OR EN
V
IH
High-level input voltage 2.7 V ≤V
I(IN)
≤5.5 V 2
VV
IL
Low-level input voltage 2.7 V ≤V
I(IN)
≤5.5 V 0.8
I
I
Input current V
I( ENx)
= 0 V or 5.5 V, V
I(ENx)
= 0 V or 5.5 V -0.5 0.5 µA
t
on
Turnon time C
L
= 100 µF, R
L
= 5 Ω3
mst
off
Turnoff time C
L
= 100 µF, R
L
= 5 Ω10
CURRENT LIMIT
T
J
= 25 °C 1.1 1.5 1.9V
I(IN)
= 5 V, OUT connected to GND,I
OS
Short-circuit output current Adevice enabled into short-circuit
-40 °C≤T
J
≤125 °C 1.1 1.5 2.1
I
OC_TRIP
Overcurrent trip threshold V
I(IN)
= 5 V, current ramp ( ≤100 A/s) on OUT 2.4 3 A
T
J
= 25 °C 2.2 3 3.8V
I(IN)
= 5 V, OUT1, OUT2 connected to GND,I
OS
(3)
Short-circuit output current Adevice enabled into short-circuit
-40 °C≤T
J
≤125 °C 2.2 3 4.2
I
OC_TRIP
(3)
Overcurrent trip threshold V
I(IN)
= 5 V, current ramp ( ≤100 A/s) on OUT1, OUT2 tied together 4.8 6 A
SUPPLY CURRENT (TPS2061, TPS2065)
T
J
= 25 °C 0.5 1No load on OUT, V
I( ENx)
= 5.5 V,Supply current, low-level output µAor V
I(ENx)
= 0 V
-40 °C≤T
J
≤125 °C 0.5 5
T
J
= 25 °C 43 60No load on OUT, V
I( ENx)
= 0 V,Supply current, high-level output µAor V
I(ENx)
= 5.5 V
-40 °C≤T
J
≤125 °C 43 70
OUT connected to ground, V
I( EN)
= 5.5 V,Leakage current -40 °C≤T
J
≤125 °C 1 µAor V
I(EN)
= 0 V
Reverse leakage current V
I(OUTx)
= 5.5 V, IN = ground T
J
= 25 °C 0 µA
SUPPLY CURRENT (TPS2062, TPS2066)
T
J
= 25 °C 0.5 1No load on OUT, V
I( ENx)
= 5.5 V,Supply current, low-level output µAor V
I(ENx)
= 0 V
-40 °C≤T
J
≤125 °C 0.5 5
T
J
= 25 °C 50 70No load on OUT, V
I( ENx)
= 0 V,Supply current, high-level output µAor V
I(ENx)
= 5.5 V
-40 °C≤T
J
≤125 °C 50 90
OUT connected to ground, V
I(/ENx)
= 5.5 V,Leakage current -40 °C≤T
J
≤125 °C 1 µAor V
I(ENx)
= 0 V
Reverse leakage current V
I(OUTx)
= 5.5 V, IN = ground T
J
= 25 °C 0.2 µA
SUPPLY CURRENT (TPS2063, TPS2067)
T
J
= 25 °C 0.5 2Supply current, low-level output No load on OUT, V
I( ENx)
= 0 V µA-40 °C≤T
J
≤125 °C 0.5 10
T
J
= 25 °C 65 90Supply current, high-level output No load on OUT, V
I( ENx)
= 5.5 V µA-40 °C≤T
J
≤125 °C 65 110
OUT connected to ground, V
I( ENx)
= 5.5 V,Leakage current -40 °C≤T
J
≤125 °C 1 µAor V
I(ENx)
= 0 V
Reverse leakage current V
I(OUTx)
= 5.5 V, INx = ground T
J
= 25 °C 0.2 µA
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN 2 2.5 V
Hysteresis, IN T
J
= 25 °C 75 mV
OVERCURRENT OC1 and OC2
Output low voltage, V
OL(OCx)
I
O( OCx)
= 5 mA 0.4 V
Off-state current V
O( OCx)
= 5 V or 3.3 V 1 µA
OC deglitch OCx assertion or deassertion 4 8 15 ms
THERMAL SHUTDOWN
(4)
Thermal shutdown threshold 135 °C
Recovery from thermal shutdown 125 °C
Hysteresis 10 °C
(3) This configuration has not been tested for UL certification.(4) The thermal shutdown only reacts under overcurrent conditions.
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DEVICE INFORMATION
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense Deglitch
Note A: Current sense
Note B: Active low (EN) for TPS2061. Active high (EN) for TPS2065.
(See Note A)
(See Note B)
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
Terminal Functions (TPS2061 and TPS2065)
TERMINAL
I/O DESCRIPTIONNAME TPS2061 TPS2065
EN 4 - I Enable input, logic low turns on power switchEN - 4 I Enable input, logic high turns on power switchGND 1 1 GroundIN 2, 3 2,3 I Input voltageOC 5 5 O Overcurrent, open-drain output, active-lowOUT 6, 7, 8 6, 7, 8 O Power-switch output
Functional Block Diagram
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Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO
CS
Driver Current
Limit
CS
Thermal
Sense
Charge
Pump
GND
EN1
IN
EN2
OC1
OUT1
OUT2
OC2
Deglitch
Deglitch
(See Note A)
(See Note A)
(See Note B)
(See Note B)
Note A: Current sense
Note B: Active low (ENx) for TPS2062. Active high (ENx) for TPS2066.
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
Terminal Functions (TPS2062 and TPS2066)
TERMINAL
I/O DESCRIPTIONNAME NO.
TPS2062 TPS2066
EN1 3 - I Enable input, logic low turns on power switch IN-OUT1EN2 4 - I Enable input, logic low turns on power switch IN-OUT2EN1 - 3 I Enable input, logic high turns on power switch IN-OUT1EN2 - 4 I Enable input, logic high turns on power switch IN-OUT2GND 1 1 GroundIN 2 2 I Input voltageOC1 8 8 O Overcurrent, open-drain output, active low, IN-OUT1OC2 5 5 O Overcurrent, open-drain output, active low, IN-OUT2OUT1 7 7 O Power-switch output, IN-OUT1OUT2 6 6 O Power-switch output, IN-OUT2
Functional Block Diagram
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TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
Terminal Functions (TPS2063 and TPS2067)
TERMINAL
I/O DESCRIPTIONNAME TPS2063 TPS2067
EN1 3 -- I Enable input, logic low turns on power switch IN1-OUT1EN2 4 -- I Enable input, logic low turns on power switch IN1-OUT2EN3 7 -- I Enable input, logic low turns on power switch IN2-OUT3EN1 -- 3 I Enable input, logic high turns on power switch IN1-OUT1EN2 -- 4 I Enable input, logic high turns on power switch IN1-OUT2EN3 -- 7 I Enable input, logic high turns on power switch IN2-OUT3GND 1, 5 1, 5 GroundIN1 2 2 I Input voltage for OUT1 and OUT2IN2 6 6 I Input voltage for OUT3NC 8, 9, 10 8, 9, 10 No connectionOC1 16 16 O Overcurrent, open-drain output, active low, IN1-OUT1OC2 13 13 O Overcurrent, open-drain output, active low, IN1-OUT2OC3 12 12 O Overcurrent, open-drain output, active low, IN2-OUT3OUT1 15 15 O Power-switch output, IN1-OUT1OUT2 14 14 O Power-switch output, IN1-OUT2OUT3 11 11 O Power-switch output, IN2-OUT3
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Thermal
Sense
Driver Current
Limit
UVLO CS
Driver Current
Limit
CS
Thermal
Sense
GND
EN1
IN1
EN2
OC1
OUT1
OUT2
OC2
Deglitch
Deglitch
Driver Current
Limit
CS
Thermal
Sense
Charge
Pump
GND
IN2
EN3
OUT3
OC3
Deglitch
VCC
Selector
UVLO
(See Note A)
Note A: Current sense
Note B: Active low (ENx) for TPS2063; Active high (ENx) for TPS2067
(See Note A)
(See Note A)
(See Note B)
(See Note B)
(See Note B)
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
Functional Block Diagram
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PARAMETER MEASUREMENT INFORMATION
VI(EN)
5 V/div
VO(OUT)
2 V/div
RL = 5 W,
CL = 1 mF
TA = 255C
t − Time − 500 ms/div
VI(EN)
5 V/div
VO(OUT)
2 V/div
RL = 5 W,
CL = 1 mF
TA = 255C
t − Time − 500 ms/div
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time With 1- µF Load Figure 3. Turnoff Delay and Fall Time With 1- µF Load
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VI(EN)
5 V/div
VO(OUT)
2 V/div
RL = 5 W,
CL = 100 mF
TA = 255C
t − Time − 500 ms/div
VO(OUT)
2 V/div
VI(EN)
5 V/div
RL = 5 W,
CL = 100 mF
TA = 255C
t − Time − 500 ms/div
VI(EN)
5 V/div
IO(OUT)
500 mA/div
t − Time − 500 ms/div
VI(EN)
5 V/div
IO(OUT)
500 mA/div
470 mF
100 mF
220 mF
VIN = 5 V
RL = 5 W,
TA = 255C
t − Time − 1 ms/div
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Turnon Delay and Rise Time With 100- µF Load Figure 5. Turnoff Delay and Fall Time With 100- µF Load
Figure 6. Short-Circuit Current, Figure 7. Inrush Current With DifferentDevice Enabled Into Short Load Capacitance
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VO(OC)
2 V/div
IO(OUT)
1 A/div
t − Time − 2 ms/div
VO(OC)
2 V/div
IO(OUT)
1 A/div
t − Time − 2 ms/div
TYPICAL CHARACTERISTICS
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
23456
Turnon Time − ms
VI − Input Voltage − V
CL = 100 mF,
RL = 5 W,
TA = 255C
1.5
1.6
1.7
1.8
1.9
2
23456
CL = 100 mF,
RL = 5 W,
TA = 255C
Turnoff Time − mS
VI − Input Voltage − V
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. 2- ΩLoad Connected to Enabled Device Figure 9. 1- ΩLoad Connected to Enabled Device
TURNON TIME TURNOFF TIMEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 10. Figure 11.
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0
0.1
0.2
0.3
0.4
0.5
0.6
2 3 4 5 6
Rise Time − ms
VI − Input Voltage − V
CL = 1 mF,
RL = 5 W,
TA = 255C
0
0.05
0.1
0.15
0.2
0.25
2 3 4 5 6
CL = 1 mF,
RL = 5 W,
TA = 255C
Fall Time − ms
VI − Input Voltage − V
0
10
20
30
40
50
60
−50 0 50 100 150
VI = 5.5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Enabled −
II (IN) Aµ
VI = 5 V
0
10
20
30
40
50
60
70
−50 0 50 100 150
VI = 5.5 V
VI = 5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Enabled −
II (IN) Aµ
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
RISE TIME FALL TIMEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 12. Figure 13.
TPS2061, TPS2065 TPS2062, TPS2066SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT ENABLEDvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 14. Figure 15.
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0
10
20
30
40
50
60
70
80
90
−50 0 50 100 150
VI = 5.5 V
VI = 5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Enabled −
II (IN) Aµ
TJ − Junction Temperature − 5C
− Supply Current, Output Disabled −II (IN) Aµ
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−50 0 50 100 150
VI = 2.7 V VI = 3.3 V
VI = 5.5 V
VI = 5 V
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−50 0 50 100 150
VI = 5.5 V VI = 5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Disabled −
II (IN) Aµ
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−50 0 50 100 150
VI = 5.5 V
VI = 5 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Disabled −
II (IN) Aµ
VI = 3.3 V
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
TPS2063, TPS2067 TPS2061, TPS2065SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLEDvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 16. Figure 17.
TPS2062, TPS2066 TPS2063, TPS2067SUPPLY CURRENT, OUTPUT DISABLED SUPPLY CURRENT, OUTPUT DISABLEDvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 18. Figure 19.
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1.34
1.36
1.38
1.4
1.42
1.44
1.48
1.5
1.52
1.54
1.56
−50 0 50 100 150
1.46
VI = 3.3 V
VI = 5 V
VI = 3.3 V
VI = 5.5 V
TJ − Junction Temperature − 5C
− Short-Circuit Output Current − A
IOS
VI = 2.7 V
0
20
40
60
80
100
120
−50 0 50 100 150
Out1 = 5 V
Out1 = 3.3 V
Out1 = 2.7 V
IO = 0.5 A
TJ − Junction Temperature − 5C
rDS(on) − Static Drain-Source
On-State Resistance − mΩ
2.1
2.14
2.18
2.22
2.26
2.3
−50 0 50 100 150
UVLO Rising
UVLO Falling
UVOL − Undervoltage Lockout − V
TJ − Junction Temperature − 5C
1.5
1.7
1.9
2.1
2.3
2.5
2.5 3 3.5 4 4.5 5 5.5 6
TA = 255C
Load Ramp = 1A/10 ms
Threshold Trip Current − A
VI − Input Voltage − V
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
STATIC DRAIN-SOURCE ON-STATE RESISTANCE SHORT-CIRCUIT OUTPUT CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 20. Figure 21.
THRESHOLD TRIP CURRENT UNDERVOLTAGE LOCKOUTvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 22. Figure 23.
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0
50
100
150
200
0 2.5 5 7.5 10 12.5
Current-Limit Response − sµ
Peak Current − A
VI = 5 V,
TA = 255C
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
CURRENT-LIMIT RESPONSE
vsPEAK CURRENT
Figure 24.
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APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
IN
OC1
EN1
OC2
2
8
5
7
0.1 µF22 µF
0.1 µF22 µF
Load
Load
OUT1
OUT2
Power Supply
2.7 V to 5.5 V
6
EN2
3
4
GND
0.1 µF
TPS2062
1
OVERCURRENT
OC RESPONSE
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
Figure 25. Typical Application
A 0.01- µF to 0.1- µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing theoutput with a 0.01- µF to 0.1- µF ceramic capacitor improves the immunity of the device to short-circuit transients.
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do notincrease the series resistance of the current path. When an overcurrent condition is detected, the devicemaintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs onlyif the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before thedevice is enabled or before V
I(IN)
has been applied (see Figure 15 ). The TPS206x senses the short andimmediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overloadoccurs, high currents may flow for a short period of time before the current-limit circuit can react. After thecurrent-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-currentmode.
In the third condition, the load has been gradually increased beyond the recommended operating current. Thecurrent is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device isexceeded (see Figure 18 ). The TPS206x is capable of delivering current up to the current-limit threshold withoutdamaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown conditionis encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent orovertemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause amomentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.The TPS206x is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminatesthe need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turnedoff due to an overtemperature shutdown.
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GND
IN
EN1
EN2
OC1
OC2
OUT1
OUT2
TPS2062 Rpullup
V+
POWER DISSIPATION AND JUNCTION TEMPERATURE
THERMAL PROTECTION
UNDERVOLTAGE LOCKOUT (UVLO)
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
APPLICATION INFORMATION (continued)
Figure 26. Typical Circuit for the OC Pin
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass largecurrents. The thermal resistances of these packages are high compared to those of power packages; it is gooddesign practice to check power dissipation and junction temperature. Begin by determining the r
DS(on)
of theN-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use thehighest operating ambient temperature of interest and read r
DS(on)
from Figure 20 . Using this value, the powerdissipation per switch can be calculated by:•P
D
= r
DS(on)
×I
2
Multiply this number by the number of switches being used. This step renders the total power dissipation fromthe N-channel MOSFETs.
Finally, calculate the junction temperature:•T
J
= P
D
x R
ΘJA
+ T
A
Where:
•T
A
= Ambient temperature °C•R
ΘJA
= Thermal resistance•P
D
= Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generallysufficient to get a reasonable answer.
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present forextended periods of time. The TPS206x implements a thermal sensing to monitor the operating junctiontemperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperaturerises due to excessive power dissipation. Once the die temperature rises to approximately 140 °C due toovercurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the powerswitch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooledapproximately 10 °C, the switch turns back on. The switch continues to cycle in this manner until the load fault orinput power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdownor overcurrent occurs.
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the inputvoltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design ofhot-insertion systems where it is not possible to turn off the power switch before input power is removed. TheUVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if theswitch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI andvoltage overshoots.
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UNIVERSAL SERIAL BUS (USB) APPLICATIONS
HOST/SELF-POWERED AND BUS-POWERED HUBS
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
APPLICATION INFORMATION (continued)
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed forlow-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USBinterface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided fordifferential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where poweris distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 Vfrom the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumptionrequirements:
•Hosts/self-powered hubs (SPH)•Bus-powered hubs (BPH)•Low-power, bus-powered functions•High-power, bus-powered functions•Self-powered functions
SPHs and BPHs distribute data and power to downstream functions. The TPS206x has higher current capabilitythan required by one USB port; so, it can be used on the host side and supplies power to multiple downstreamports or functions.
Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (seeFigure 27 ). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstreamconnection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protectionand must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,and stand-alone hubs.
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IN
OC1
EN1
OC2
EN2
GND
0.1 µF
2
8
3
5
4
7
33 µF
33 µF
GND
1
OUT1
TPS2062
Power Supply
D+
D−
VBUS
GND
D+
D−
VBUS
Downstream
USB Ports
USB
Controller
3.3 V 5 V
33 µFGND
OUT2
D+
D−
VBUS
33 µFGND
D+
D−
VBUS
6
0.1 µF
0.1 µF
0.1 µF
0.1 µF
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
APPLICATION INFORMATION (continued)
Figure 27. Typical Four-Port USB Host / Self-Powered Hub
BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required topower up with less than one unit load. The BPH usually has one embedded function, and power is alwaysavailable to the controller of the hub. If the embedded function and hub require more than 100 mA on power up,the power to the embedded function may need to be kept off until enumeration is completed. This can beaccomplished by removing power or by shutting off the clock to the embedded function. Power switching theembedded function is not necessary if the aggregate power draw for the function and controller is less than oneunit load. The total current drawn by the bus-powered device is the sum of the current to the controller, theembedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-powerfunctions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up andcan draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44Ωand 10 µF at power up, the device must implement inrush current limiting (see Figure 28 ). With TPS206x, theinternal functions could draw more than 500 mA, which fits the needs of some applications such as motor drivingcircuits.
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IN
OC1
OC2
2
8
3
5
4
7
0.1 µF10 µFInternal
Function
OUT1
Power Supply
3.3 V
EN1
6
0.1 µF10 µF
OUT2 Internal
Function
0.1 µF
10 µF
USB
Control
GND
VBUS
D−
D+ TPS2062
EN2 GND
1
USB POWER-DISTRIBUTION REQUIREMENTS
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
APPLICATION INFORMATION (continued)
Figure 28. High-Power Bus-Powered Function
USB can be implemented in several ways, and, regardless of the type of USB device being developed, severalpower-distribution features must be implemented.•Hosts/SPHs must:– Current-limit downstream ports– Report overcurrent conditions on USB V
BUS•BPHs must:– Enable/disable power to downstream ports– Power up at <100 mA– Limit inrush current (<44 Ωand 10 µF)•Functions must:– Limit inrush currents– Power up at <100 mA
The feature set of the TPS206x allows them to meet each of these requirements. The integrated current-limitingand overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled risetimes meet the need of both input and output ports on bus-powered hubs, as well as the input ports forbus-powered functions (see Figure 29 ).
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DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D −
Upstream
Port
TPS2041B
SN75240
A
B
5 V
GND
C
D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2041 EN Input
OC EN
OUT
5-V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN
OC1
OUT1
TPS2062
EN2
OC2
OUT2
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
TPS76333
GENERIC HOT-PLUG APPLICATIONS
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
APPLICATION INFORMATION (continued)
Figure 29. Hybrid Self / Bus-Powered Hub Implementation
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.These are considered hot-plug applications. Such implementations require the control of current surges seen bythe main power supply and the card being inserted. The most effective way to control these surges is to limit andslowly ramp the current and voltage being applied to the card, similar to the way in which a power supplynormally turns on. Due to the controlled rise times and fall times of the TPS206x, these devices can be used toprovide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS206xalso ensures that the switch is off after the card has been removed, and that the switch is off during the nextinsertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card ormodule.
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Power
Supply
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
TPS2062
OC1
GND
EN1
IN
EN2
OUT1
OUT2
OC2 Block of
Circuitry
Block of
Circuitry
DETAILED DESCRIPTION
Power Switch
Charge Pump
Driver
Enable ( ENx or ENx)
Overcurrent ( OCx)
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
APPLICATION INFORMATION (continued)
Figure 30. Typical Hot-Plug Implementation
By placing the TPS206x between the V
CC
input and the rest of the circuitry, the input power reaches thesedevices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltageramp at the output of the device. This implementation controls system surge currents and provides ahot-plugging mechanism for any device.
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch,the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switchsupplies a minimum current of 1 A.
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gateof the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requireslittle supply current.
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associatedelectromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and falltimes of the output voltage.
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry toreduce the supply current. The supply current is reduced to less than 1 µA when a logic high is present on ENx,or when a logic low is present on ENx. A logic zero input on ENx, or a logic high input on ENx restores bias tothe drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOSlogic levels.
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition isencountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperatureshutdown occurs, the OCx is asserted instantaneously.
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Current Sense
Thermal Sense
Undervoltage Lockout
TPS2061 , TPS2062 , TPS2063TPS2065 , TPS2066 , TPS2067
SLVS490D – DECEMBER 2003 – REVISED FEBRUARY 2007
DETAILED DESCRIPTION (continued)
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently thanconventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitrysends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into itssaturation region, which switches the output into a constant-current mode and holds the current constant whilevarying the voltage on the load.
The TPS206x implements a thermal sensing to monitor the operating temperature of the power distributionswitch. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature risesto approximately 140 °C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch,thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device hascooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until thefault is removed. The open-drain false reporting output ( OCx) is asserted (active low) when an overtemperatureshutdown or overcurrent occurs.
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a controlsignal turns off the power switch.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2061D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2061DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2061DGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2061DGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2061DGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2061DGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2061DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2061DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062DGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2062DGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2062DGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2062DGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2062DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2063D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2063DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2063DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2063DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2065D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2065DG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 30-Mar-2007
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
no Sb/Br)
TPS2065DGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2065DGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2065DGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2065DGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2065DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2065DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066DGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2066DGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2066DGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2066DGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2066DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066ID PREVIEW SOIC D 8 75 TBD Call TI Call TI
TPS2066IDR PREVIEW SOIC D 8 2500 TBD Call TI Call TI
TPS2067D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2067DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2067DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2067DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Mar-2007
Addendum-Page 2
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Mar-2007
Addendum-Page 3
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2007
Pack Materials-Page 1
Device Package Pins Site Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2061DGNR DGN 8 LEN 330 12 5.2 3.3 1.6 8 12 NONE
TPS2061DR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1
TPS2062DGNR DGN 8 LEN 330 12 5.2 3.3 1.6 8 12 NONE
TPS2062DR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1
TPS2065DGNR DGN 8 NSE 330 12 5.3 3.3 1.3 8 12 NONE
TPS2065DR D 8 TAI 330 12 6.4 5.2 2.1 8 12 Q1
TPS2065DR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1
TPS2066DGNR DGN 8 LEN 330 12 5.2 3.3 1.6 8 12 NONE
TPS2066DR D 8 FMX 330 0 6.4 5.2 2.1 8 12 Q1
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TPS2061DGNR DGN 8 LEN 566.0 155.0 150.0
TPS2061DR D 8 FMX 342.9 336.6 20.6
TPS2062DGNR DGN 8 LEN 566.0 340.5 21.1
TPS2062DR D 8 FMX 342.9 336.6 20.6
TPS2065DGNR DGN 8 NSE 370.0 355.0 75.0
TPS2065DR D 8 TAI 346.0 346.0 61.0
TPS2065DR D 8 FMX 342.9 336.6 20.6
TPS2066DGNR DGN 8 LEN 566.0 340.5 21.1
TPS2066DR D 8 FMX 342.9 336.6 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2007
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2007
Pack Materials-Page 3
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