3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
MDS 2308-1H D 4Revision 081505
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK2308-1H
AC Electrical Characteristics
VDD = 3.3 V ±10%, Ambient Temperature -40 to +85°C (Industrial), 0 to 70°C (Commercial)
Note 1: With CLKIN = 100 MHz, FBIN to CLKA4, all outputs at 100 MHz
Note 2: When there is no clock signal present at CLKIN, the MK2308-1H will enter power down mode. The
PLL is stopped and the outputs are tri-state.
Note 3: With VDD at a steady rate and valid clocks at CLKIN and FBIN
Thermal Characteristics 16TSSOP
Output High Voltage,
CMOS level
VOH IOH = -4 mA VDD-0.4 V
Operating Supply Current IDD No Load, S2 = 1, S1 = 1,
Note 1
70 mA
Power Down Supply
Current
IDDPD CLKIN = 0, S2 = 0, S1 = 1 12 µA
CLKIN = 0, Note 2 12 µA
Short Circuit Current IOS Each output ±70 mA
Input Capacitance CIN S2, S1, FBIN 5 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Parameter Symbol Conditions Min. Typ. Max. Units
Input Clock Frequency fIN See table on page 2 10 133 MHz
Output Clock Frequency See table on page 2 10 133 MHz
Output Rise Time tOR 0.8 to 2.0V, CL=30pF 1.5 ns
Output Fall Time tOF 2.0 to 0.8V, CL=30pF 1.25 ns
Output Clock Duty Cycle tDC measured at VDD/2 45 50 55 %
Device to Device Skew rising edges at VDD/2 700 ps
Output to Output Skew rising edges at VDD/2 200 ps
Input to Output Skew rising edges at VDD/2, FBIN to
CLKA4, S1 = 1, S0 = 1, Note 1
±250 ps
Maximum Absolute JItter CL=15 pF, measured at 66.67M 130 ps
Cycle to Cycle Jitter CL=30 pF, measured at 66.67M 200 ps
CL=15 pF, measured at 66.67M 200 ps
CL=15 pF, measured at 133.33M 100 ps
PLL Lock Time Note 3 1.0 ms
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
θJA Still air 78 °C/W
θJA 1 m/s air flow 70 °C/W
θJA 3 m/s air flow 68 °C/W
Thermal Resistance Junction to Case θJC 37 °C/W