1
FEATURES
DESCRIPTION
APPLICATIONS
VIN5V
L1
10 HmD1
VIN SW
FB
GND
CTRL
COMP
C2
4.7 Fm
C3
10nF
TPS 61170 R1
87.6kW
VOUT 12V/300mA
R2
10kW
R3
4.99kW
C1
4.7 Fm
L1: TOKO#A915_Y-100M
C1:MurataGRM188R61A475K
C2:MurataGRM21BR61E475K
D1: ONsemiMBR0540T1
*R3,C3:CompensationRCnetwork
TPS61170
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.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
1.2A High Voltage Boost Converter in 2x2mm
2
QFN Package
3-V to 18-V Input Voltage RangeHigh Output Voltage: Up to 38 V
The TPS61170 is a monolithic high voltage switchingregulator with integrated 1.2-A, 40-V power MOSFET.1.2-A integrated Switch
It can be configured in several standard1.2-MHz Fixed Switching Frequency
switching-regulator topologies, including boost and12 V at 300 mA and 24 V at 150 mA from 5-V
SEPIC. The device has a wide input-voltage range toInput (Typical) support applications with input voltage from multi-cellbatteries or regulated 5-V, 12-V power rails.Up to 93% Efficiency
The TPS61170 uses a 1.2-MHz switching frequency,On-The-Fly Output Voltage Reprogramming
allowing the use low-profile inductors and low-valueSkip-Switching Cycle for Output Regulation at
ceramic input and output capacitors. The externalLight Load
loop compensation gives the user flexibility toBuilt-in Soft Start
optimize loop compensation and transient response.The device has built-in protection features, such as6-Pin, 2 mm × 2 mm QFN Package
pulse-by-pulse overcurrent limit, soft start and thermalshutdown.5-V to 12-V and 24-V, 12-V to 24-V Boost
The feedback reference voltage of the FB pin isConverter
1.229V. It can be lowered using a 1-wire digitalinterface (Easyscale™ protocol) through the CTRLBuck Boost Regulation Using SEPIC Topology
pin. Alternatively, a pulse width-modulation (PWM)ADSL Modems
signal can be applied to the CTRL pin. The duty cycleof the signal reduces the feedback reference voltageproportionally.
The TPS61170 is available in a 6-pin 2 mm × 2 mmQFN package, allowing a compact power-supplysolution.
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
PACKAGE MARKING
40 ° C to 85 ° C TPS61170DRV BZS
(1) For the most current package and ordering information, see the TI Web site at www.ti.com .(2) The DRV package is available in tape and reel. Add R suffix (TPS61170DRVR) to order quantities of 3000 parts per reel or add T suffix(TPS61170DRVT) to order 250 parts per reel.
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
Supply Voltages on VIN
(2)
0.3 to 20 VVoltages on CTRL
(2)
0.3 to 20 VV
I
Voltage on FB and COMP
(2)
0.3 to 3 VVoltage on SW
(2)
0.3 to 40 VP
D
Continuous Power Dissipation See Dissipation Rating TableT
J
Operating Junction Temperature Range 40 to 150 ° CT
STG
Storage Temperature Range 65 to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
DERATING FACTORBOARD PACKAGE R
θJC
R
θJA
T
A
< 25 ° C T
A
= 70 ° C T
A
= 85 ° CABOVE T
A
= 25 ° C
Low-K
(1)
DRV 20 ° C/W 140 ° C/W 7.1 mW/ ° C 715 mW 395 mW 285 mWHigh-K
(2)
DRV 20 ° C/W 65 ° C/W 15.4 mW/ ° C 1540 mW 845 mW 615 mW
(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground planesand 2-ounce copper traces on top and bottom of the board.
MIN TYP MAX UNIT
V
I
Input voltage range, VIN 3 18 VV
O
Output voltage range VIN 38 VL Inductor
(1)
10 22 µHC
I
Input capacitor 1 µFC
O
Output capacitor 1 10 µFT
A
Operating ambient temperature 40 85 ° CT
J
Operating junction temperature 40 125 ° C
(1) These values are recommended values that have been successfully tested in several applications. Other values may be acceptable inother applications but should be fully tested by the user.
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ELECTRICAL CHARACTERISTICS
TPS61170
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.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
VIN = 3.6 V, CTRL = VIN, T
A
= 40 ° C to 85 ° C, typical values are at T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
V
I
Input voltage range, VIN 3.0 18 VI
Q
Operating quiescent current into VIN Device PWM switching no load 2.3 mAI
SD
Shutdown current CRTL=GND, VIN = 4.2 V 1 µAUVLO Under-voltage lockout threshold VIN falling 2.2 2.5 VV
hys
Under-voltage lockout Hysteresis 70 mV
ENABLE AND REFERENCE CONTROL
V
(CTRLh)
CTRL logic high voltage VIN = 3 V to 18 V 1.2 VV
(CTRL)
CTRL logic low voltage VIN = 3 V to 18 V 0.4 VR
(CTRL)
CTRL pull down resistor 400 800 1600 k
t
off
CTRL pulse width to shutdown CTRL high to low 2.5 mst
es_det
Easy Scale detection time
(1)
CTRL pin low 260 µst
es_delay
Easy Scale detection delay 100 µst
es_win
Easy Scale detection window time 1 ms
VOLTAGE AND CURRENT CONTROL
V
REF
Voltage feedback regulation voltage 1.204 1.229 1.254 VVoltage feedback regulation voltage underV
(REF_PWM)
V
FB
= 492 mV 477 492 507 mVreprogramI
FB
Voltage feedback input bias current V
FB
= 1.229 V 200 nAf
S
Oscillator frequency 1.0 1.2 1.5 MHzD
max
Maximum duty cycle V
FB
= 100 mV 90% 93%t
min_on
Minimum on pulse width 40 nsI
sink
Comp pin sink current 100 µAI
source
Comp pin source current 100 µAG
ea
Error amplifier transconductance 240 320 400 µmhoR
ea
Error amplifier output resistance 5 pF connected to COMP 6 M
f
ea
Error amplifier crossover frequency 5 pF connected to COMP 500 kHz
POWER SWITCH
VIN = 3.6 V 0.3 0.6R
DS(on)
N-channel MOSFET on-resistance VIN = 3.0 V 0.7I
LN_NFET
N-channel leakage current V
SW
= 35 V, T
A
= 25 ° C 1 µA
OC and SS
I
LIM
N-Channel MOSFET current limit D = D
max
0.96 1.2 1.44 AI
LIM_Start
Start up current limit D = D
max
0.7 At
Half_LIM
Time step for half current limit 5 mst
REF
Vref filter time constant 180 µst
step
V
REF
ramp up time 213 µs
(1) EasyScale communication is allowed immediately after the CTRL pin has been low for more than t
es_det
. To select EasyScale™ mode,the CTRL pin must be low for more than t
es_det
the end of t
es_win
.
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PIN ASSIGNMENTS
VIN
CTRL
SW
FB
COMP
GND
TOP VIEW
Thermal
Pad
6-PIN2mmx2mmx0.8mmQFN
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)VIN = 3.6 V, CTRL = VIN, T
A
= 40 ° C to 85 ° C, typical values are at T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EasyScale TIMING
t
start
Start time of program stream 2 µst
EOS
End time of program stream 2 360 µst
H_LB
High time low bit Logic 0 2 180 µst
L_LB
Low time low bit Logic 0 2 × t
H_LB
360 µst
H_HB
High time high bit Logic 1 2 × t
L_HB
360 µst
L_HB
Low time high bit Logic 1 2 180 µsV
ACKNL
Acknowledge output voltage low Open drain, R
pullup
=15 k to Vin 0.4 Vt
valACKN
Acknowledge valid time See
(2)
2µst
ACKN
Duration of acknowledge condition See
(2)
512 µs
THERMAL SHUTDOWN
T
shutdown
Thermal shutdown threshold 160 ° CT
hysteresis
Thermal shutdown threshold hysteresis 15 ° C
(2) Acknowledge condition active 0, this condition will only be applied if the RFA bit is set. Open drain output, line needs to be pulled highby the host with resistor load.
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
VIN 6 I The input supply pin for the IC. Connect VIN to a supply voltage between 3 V and 18 V.SW 4 I This is the switching node of the IC. Connect SW to the switched side of the inductor.GND 3 O GroundFB 1 I Feedback pin for current. Connect to the center tap of a resistor divider to program the output voltage.Output of the transconductance error amplifier. Connect an external RC network to this pin to compensateCOMP 2 O
the regulator.
Control pin of the boost regulator. CTRL is a multi-functional pin which can be used for enable the deviceCTRL 5 I
and control the feedback voltage with a PWM signal and digital communications.The thermal pad should be soldered to the analog ground plane to avoid thermal issue. If possible, useThermal Pad
thermal via to connect to ground plane for ideal power dissipation.
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FUNCTIONAL BLOCK DIAGRAM
SW
Ramp
Generator
Oscillator
Current
Sensor
CTRL
GND
C3
L1
+
FB
BandGap
D1
Error
Amplifer
2
1
R2
C2
Vin
C1
PWMControl
4
6
Soft
Start-up
5
3
COMP
R1
R3
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
TPS61170
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.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
Circuit of Figure 1, L = TOKO A915_Y-100M, D1 = ONsemi MBR0540T1, unless otherwise noted. FIGURE
Efficiency VIN = 5V; VOUT = 12V,18V,24V,30V; Figure 2Efficiency VIN = 5V, 8.5V, 12V; VOUT = 24V; Figure 3Output voltage accuracy I
LOAD
= 100 mA Figure 4Switch current limit T
A
= 25 ° C Figure 5Switch current limit Figure 6Error amplifier transconductance Figure 7Easyscale step Figure 8PWM switching operation VIN = 5V; VOUT = 12V; I
LOAD
= 250mA; Figure 9Load transient response VIN = 5V; VOUT = 12V; I
LOAD
= 50mA to 150mA; Figure 10Start-up VIN = 5V; VOUT = 12V; I
LOAD
= 250mA; Figure 11Skip-cycle switching VIN = 9V ; VOUT = 12V, I
LOAD
= 100 µA ; Figure 12
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40
50
60
70
80
90
100
0 50 100 150 200 250 300
VOUT =24V
VIN=8.5V
VIN=5V
VIN=12V
Efficiency-%
OutputCurrent-mA
40
50
60
70
80
90
100
0 50 100 150 200 250 300
VOUT =12V
VOUT =18V
VOUT =24V
VOUT =30V
Efficiency-%
OutputCurrent-mA
VIN=5V
11.88
11.90
11.92
11.94
11.96
3 4 5 6 7 8 9 10 11
V -InputVoltage-V
I
T =25°C
A
I =100mA
LOAD
V-OutputVoltage-V
O
T =85°C
A
T =-40°C
A
800
900
1000
1100
1200
1300
1400
1500
1600
20 30 40 50 60 70 80 90
DutyCycle-%
SwitchCurrentLimit- A
800
900
1000
1100
1200
1300
1400
1500
1600
-40 -20 0 20 40 60 80 100 120 140
Temperature- C°
SwitchCurrentLimit-mA
0
100
200
300
400
500
-40 -20 0 20 40 60 80 100 120 140
Temperature- C°
Error AmplifierTransconductance-mhos
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
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EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 2. Figure 3.
OUTPUT VOLTAGE SWITCH CURRENT LIMITvs vsINPUT VOLTAGE DUTY CYCLE
Figure 4. Figure 5.
SWITCH CURRENT LIMIT ERROR AMPLIFIER TRANSCONDUCTANCEvs vsTEMPERATURE TEMPERATURE
Figure 6. Figure 7.
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0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
EasyScaleStep
FBVoltage-V
CTRL 5V/div
VOUT 5V/div
COMP 500mV/div
I 500mA/div
L
t-1ms/div
VOUT 200mV/div AC
I 100mA/div
LOAD
t-40 s/divm
SW5V/div
VOUT 20mV/div AC
I 50mA/div
L
t-400ns/div
TPS61170
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.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
FB VOLTAGE
vsEASY SCALE STEP PWM SWITCHING OPERATION
Figure 8. Figure 9.
LOAD TRANSIENT RESPONSE START-UP
Figure 10. Figure 11.
SKIP-CYCLE SWITCHING
Figure 12.
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DETAILED DESCRIPTION
OPERATION
SOFT START-UP
OVERCURRENT PROTECTION
UNDERVOLTAGE LOCKOUT (UVLO)
THERMAL SHUTDOWN
ENABLE AND SHUTDOWN
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
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The TPS61170 integrates a 40-V low side FET for up to 38-V output voltages. The device regulates the outputwith current mode PWM (pulse width modulation) control. The switching frequency of PWM is fixed at 1.2MHz.The PWM control circuitry turns on the switch at the beginning of each switching cycle. The input voltage isapplied across the inductor and stores the energy as inductor current ramps up. During this portion of theswitching cycle, the load current is provided by the output capacitor. When the inductor current rises to thethreshold set by the error amplifier output, the power switch turns off and the external Schottky diode is forwardbiased. The inductor transfers stored energy to replenish the output capacitor and supply the load current. Thisoperation repeats in every switching cycle. As shown in the block diagram, the duty cycle of the converter isdetermined by the PWM control comparator which compares the error amplifier output and the current signal.
A ramp signal from oscillator is added to the current ramp. This slope compensation is to avoid sub-harmonicoscillation that is intrinsic to the current mode control at duty cycle higher than 50%. The feedback loop regulatesthe FB pin to a reference voltage through an error amplifier. The output of the error amplifier is connected to theCOMP pin. An external RC compensation network is connected to the COMP pin to optimize the feedback loopfor stability and transient response.
Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device isenabled by a logic high signal on the CTRL pin, the FB pin reference voltage ramps up in 32 steps, each steptakes 213 µs. This ensures that the output voltage rises slowly to reduce inrush current. Additionally, for the first5msec after the COMP voltage ramps, the current limit of the PWM switch is set to half of the normal current limitspec. Therefore, during this period the input current is kept below 700mA (typical). See the start-up waveform fora typical example, Figure 11 .
TPS61170 has a cycle-by-cycle overcurrent limit feature that turns off the power switch once the inductor currentreaches the overcurrent limit. The PWM circuitry resets itself at the beginning of the next switch cycle. During anover-current event, this results in a decrease of output voltage with respect to load. The current limit threshold aswell as input voltage, output voltage, switching frequency and inductor value determine the maximum availableoutput current. Larger inductor values increases the current output capability because of the reduced currentripple. See the APPLICATION INFORMATION section for the output current calculation.
An undervoltage lockout prevents mis-operation of the device at input voltages below typical 2.2V. When theinput voltage is below the undervoltage threshold, the device remains off and the internal switch FET is turnedoff. The undervoltage lockout threshold is set below minimum operating voltage of 3V to avoid any transient VINdip triggering the UVLO and causing the device to reset. For the input voltages between UVLO threshold and 3V,the device maintains its operation, but the specifications are not ensured.
An internal thermal shutdown turns off the device when the typical junction temperature of 160 ° C is exceeded.The IC restarts when the junction temperature drops by 15 ° C.
The TPS61170 enters shutdown when the CTRL voltage is less than 0.4V for more than 2.5ms. In shutdown, theinput supply current for the device is less than 1 µA (max). The CTRL pin has an internal 800k pull downresistor to disable the device when the pin is left unconnected.
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FEEDBACK REFERENCE PROGRAM MODE SELECTION
CTRL
low
high
FB
200mVxdutycycle
Insertbattery
CTRL
low
high
FB
Insertbattery
Programming
code
FBramp Shutdowndelay
t
EnterESmode
Timingwindow Programmingcode
50mV 50mV
EnterESmode
PWMsignal
Startup
delay
PWM
mode
Startupdelay
FBramp
Programmedvalue
(ifnotprogrammed, 200mVdefault )
Shutdown
delay
IC
Shutdown
Startupdelay
FBramp
ES
mode ESdetectdelay
ESdetecttime
PWM PROGRAM MODE
VFB +Duty 1.229 V
(1)
TPS61170
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.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
The CTRL pin is used for changing the FB pin reference voltage on-the-fly. There are two methods to programthe reference voltage, PWM signal and 1 wire interface (EasyScale™). The program mode is selected each timethe device is enabled. The default mode is the PWM signal which uses the duty cycle of the CTRL pin signal tomodulate the reference voltage. To enter the 1 wire interface mode, the following digital pattern on the CTRL pinmust be recognized by the IC every time the IC starts from the shutdown mode.1. Pull CTRL pin high to enable the TPS61170 and to start the 1 wire mode detection window.2. After the EasyScale detection delay (t
es_delay
, 100 µsec) expires, drive CTRL low for more than the EasyScaledetection time (t
es_detect
, 260 µsec).3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window(t
es_win
, 1msec) expires. EasyScale detection window starts from the first CTRL pin low to high transition.
The IC immediately enters the 1 wire mode once the above 3 conditions are met. The EasyScale communicationcan start before the detection window expires. Once the mode is programmed, it can not be changed withoutanother start up. This means the IC needs to be shutdown by pulling the CTRL low for 2.5ms and restarts. Seethe Mode Detection of Feedback Reference Program figure (Figure 13 ) for a graphical explanation.
Figure 13. Mode Detection of Feedback Reference Program
When the CTRL pin is constantly high, the FB voltage is regulated to 1.229V typically. However, the CTRL pinallows a PWM signal to reduce this regulation voltage. The relationship between the duty cycle and FB voltage isgiven in Equation 1 :
Where:
Duty = duty cycle of the PWM signal1.229 V = internal reference voltage
As shown in Figure 14 , the IC chops up the internal 1.229V reference voltage at the duty cycle of the PWMsignal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to theerror amplifier as the reference voltage for the FB pin regulation. The regulation voltage is independent of thePWM logic voltage level which often has large variations.
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VBG
1.229V
CTRL
Error
Amplifier
FB
1 WIRE PROGRAM MODE
EasyScale™
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
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For optimum performance, use the PWM mode in the range of 5kHz to 100kHz. The requirement of minimumfrequency comes from the EasyScale detection delay and detection time specification for the mode selection.The device can mistakenly enter 1 wire mode if the PWM signal frequency is less than 5kHz. Because there isan internal fixed ON-time error of 40nS, an impact on FB voltage absolute value needs to be considered whenthe PWM frequency is above 100kHz. For example, the additional duty cycle of 3.2% due to the ON-time errorincreases FB voltage in 800kHz PWM signal application. A compromise between PWM frequency and FBvoltage accuracy extends the frequency range. Since the CTRL pin is logic only, adding external RC filter to thepin does not work.
Figure 14. Block Diagram of Programmable FB Voltage Using PWM Signal
The CTRL pin features a simple digital interface to control the feedback reference voltage. The 1 wire mode cansave the processor power and battery life as it does not require a PWM signal all the time, and the processor canenter idle mode if available.
The TPS61170 adopts the EasyScale™ protocol, which can program the FB voltage to any of the 32 steps withsingle command. See the Table 1 for the FB pin voltage steps. The programmed reference voltage is stored inan internal register. The default value is full scale when the device is first enabled (V
FB
= 1.229V). A power resetclears the register value and reset it to default.
EasyScale is a simple but very flexible one pin interface to configure the FB voltage. The interface is based on amaster-slave structure, where the master is typically a microcontroller or application processor. Figure 15 andTable 1 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte.The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, twoaddress bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. TheAcknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScalecompared with other on pin interfaces is that its bit detection is in a large extent independent from the bittransmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec.
Table 1. Selectable FB Voltage
FB voltage
D4 D3 D2 D1 D0(mV)
0 0.000 0 0 0 0 01 0.031 0 0 0 0 12 0.049 0 0 0 1 03 0.068 0 0 0 1 14 0.086 0 0 1 0 05 0.104 0 0 1 0 16 0.123 0 0 1 1 07 0.141 0 0 1 1 18 0.160 0 1 0 0 0
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DATA IN
Start
DATA OUT ACK
RFA A1 A0 D4 D3 D2 D1 D0DA7
0
DA6
1
DA5
1
DA4
1
DA3
0
DA2
0
DA1
1
DA0
0
Device Address DATABYTE
EOS Start EOS
Start
TPS61170
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.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
Table 1. Selectable FB Voltage (continued)
FB voltage
D4 D3 D2 D1 D0(mV)
9 0.178 0 1 0 0 110 0.197 0 1 0 1 011 0.215 0 1 0 1 112 0.234 0 1 1 0 013 0.270 0 1 1 0 114 0.307 0 1 1 1 015 0.344 0 1 1 1 116 0.381 1 0 0 0 017 0.418 1 0 0 0 118 0.455 1 0 0 1 019 0.492 1 0 0 1 120 0.528 1 0 1 0 021 0.565 1 0 1 0 122 0.602 1 0 1 1 023 0.639 1 0 1 1 124 0.713 1 1 0 0 025 0.787 1 1 0 0 126 0.860 1 1 0 1 027 0.934 1 1 0 1 128 1.008 1 1 1 0 029 1.082 1 1 1 0 130 1.155 1 1 1 1 031 1.229 1 1 1 1 1
Figure 15. EasyScale™ Protocol Overview
Table 2. EasyScale™ Bit Description
BIT TRANSMISSIONBYTE NAME DESCRIPTIONNUMBER DIRECTION
7 DA7 0 MSB device address6 DA6 15 DA5 1Device
4 DA4 1Address
INByte
3 DA3 072 hex
2 DA2 01 DA1 10 DA0 0 LSB device address
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LowBit
(Logic0)
HighBit
(Logic1)
tLow tHigh tLOW tHigh
EasyScaleTiming,withoutacknowledgeRFA =0
DA7
0
tStart
StaticHigh StaticHigh
DATA IN
tStart
TEOS TEOS
DA0
0
RFA
0
D0
1
AddressByte DATA Byte
EasyScaleTiming,withacknowledgeRFA =1
StaticHigh
tACKN
Acknowledge
true,DataLine
pulleddownby
device
DATA IN
DATA OUT Acknowledge
false,nopull
down
Controllerneedsto
PullupDataLineviaa
resistortodetect ACKN
ACKN
DA7
0
StaticHigh
TEOS tvalACK
DA0
0
RFA
1
D0
1
tStart tStart
AddressByte DATA Byte
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
www.ti.com
Table 2. EasyScale™ Bit Description (continued)
BIT TRANSMISSIONBYTE NAME DESCRIPTIONNUMBER DIRECTION
7 (MSB) RFA Request for acknowledge. If high, acknowledge is applied by device6 A1 0 Address bit 15 A0 0 Address bit 04 D4 Data bit 4Data byte IN3 D3 Data bit 32 D2 Data bit 21 D1 Data bit 10 (LSB) D0 Data bit 0Acknowledge condition active 0, this condition will only be applied in case RFA bit isset. Open drain output, Line needs to be pulled high by the host with a pullupACK OUT
resistor. This feature can only be used if the master has an open drain output stage.In case of a push pull output stage Acknowledge condition may not be requested!
Figure 16. EasyScale™ Bit Coding
All bits are transmitted MSB first and LSB last. Figure 16 shows the protocol without acknowledge request (BitRFA = 0), Figure 16 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and databyte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least t
start
(2 µs) beforethe bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition isneeded prior to the device address byte. The transmission of each byte is closed with an End of Streamcondition for at least t
EOS
(2 µs).
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Product Folder Link(s): TPS61170
TPS61170
www.ti.com
.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between t
LOW
andt
HIGH
. It can be simplified to:High Bit: t
HIGH
> t
LOW
, but with t
HIGH
at least 2x t
LOW
, see Figure 16 .Low Bit: t
HIGH
< t
LOW
, but with t
LOW
at least 2x t
HIGH
, see Figure 16 .
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending onthe relation between t
HIGH
and t
LOW
, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:Acknowledge is requested by a set RFA bit.The transmitted device address matches with the device address of the device.16 bits is received correctly.
If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time t
ACKN
, which is 512 µsmaximum then the Acknowledge condition is valid after an internal delay time t
valACK
. This means that the internalACKN-MOSFET is turned on after t
valACK
, when the last falling edge of the protocol was detected. The mastercontroller keeps the line low in this period. The master device can detect the acknowledge condition with its inputby releasing the CTRL pin after t
valACK
and read back a logic 0. The CTRL pin can be used again after theacknowledge condition ends.
Note that the acknowledge condition may only be requested if the master device has an open drain output. Forthe push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500 µA isrecommended for such cases as:an accidentally requested acknowledge, orto protect the internal ACKN-MOSFET.
Copyright © 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS61170
APPLICATION INFORMATION
PROGRAM OUTPUT VOLTAGE
FB
TPS61170
R2
R1
VOUT
R1 Vout
Vout = 1.229 V x + 1 R1 = R2 x 1
R2 1.229 V
-
æ ö æ ö
ç ÷ ç ÷
è ø è ø
(2)
MAXIMUM OUTPUT CURRENT
ú
û
ù
ê
ë
é+
-+
´´
=
)
V
1
VVV
1
(FL
1
I
ininfout
s
P
(3)
out
P
limin
max_out V
)
2
I
I(V
I
h´-´
=
(4)
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
www.ti.com
Figure 17. Program Output Voltage
To program the output voltage, select the values of R1 and R2 (See Figure 17 ) according to Equation 2 .
Considering the leakage current through the resistor divider and noise decoupling to FB pin, an optimum valuefor R2 is around 10k. The output voltage tolerance depends on the VFB accuracy and the tolerance of R1 andR2.
The overcurrent limit in a boost converter limits the maximum input current, and thus the maximum input powerfor a given input voltage. The maximum output power is less than the maximum input power due to powerconversion losses. Therefore, the current-limit setting, input voltage, output voltage and efficiency can all affectthe maximum output current. The current limit clamps the peak inductor current; therefore, the ripple must besubtracted to derive the maximum DC current. The ripple current is a function of the switching frequency,inductor value and duty cycle. The following equations take into account of all the above factors for maximumoutput current calculation.
where:
I
P
= inductor peak to peak rippleL = inductor valueV
f
= Schottky diode forward voltageF
s
= switching frequencyV
out
= output voltage
where:
I
out_max
= Maximum output current of the boost converterI
lim
= overcurrent limitη= efficiency
For instance, when V
in
is 5 V, V
out
is 12 V, the inductor is 10 µH, the Schottky forward voltage is 0.2 V; and thenthe maximum output current is 300 mA in typical operation.
14 Submit Documentation Feedback Copyright © 2007 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
SWITCH DUTY CYCLE
D+Vout *Vin
Vout
(5)
INDUCTOR SELECTION
Iin_DC +Vout Iout
Vin h
(6)
TPS61170
www.ti.com
.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
The maximum switch duty cycle (D) of the TPS61170 is 90% (min). The duty cycle of a boost converter undercontinuous conduction mode (CCM) is given by:
For a 5V to 12V application, the duty cycle is 58.3%, and for a 5V to 24V application, the duty cycle is 79.2%.The duty cycle must be lower than the maximum specification of 90% in the application; otherwise, the outputvoltage can not be regulated.
Once the PWM switch is turned on, the TPS61170 has minimum ON pulse width. This sets the limit of theminimum duty cycle. For operating low duty cycle, the TPS61170 enters pulse-skipping mode. In this mode, thedevice keeps the power switch off for several switching cycles to keep the output voltage in regulation. Thisoperation typically occurs in light load condition when the PWM operates in discontinuous mode. See theFigure 12 .
The selection of the inductor affects steady state operation as well as transient behavior and loop stability. Thesefactors make it the most important component in power regulator design. There are three important inductorspecifications, inductor value, DC resistance and saturation current. Considering inductor value alone is notenough.
The inductor s value determines the inductor ripple current. It is recommended that the peak-to-peak ripplecurrent given by Equation 3 be set to 30 40% of the DC current. Also, the inductor value should not be beyondthe range in the recommended operating conditions table. It is a good compromise of power losses and inductorsize. Inductor DC current can be calculated as
Inductor values can have ± 20% tolerance with no current bias. When the inductor current approaches saturationlevel, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor vendor definessaturation current. Using an inductor with a smaller inductance value forces discontinuous PWM where theinductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter smaximum output current, causes large input voltage ripple and reduces efficiency. In general, large inductancevalue provides much more output and higher conversion efficiency. Small inductance value can give better theload transient response. For these reasons, a 10 µH to 22 µH inductor value range is recommended. Table 3 liststhe recommended inductor for the TPS61170.
TPS61170 has built-in slope compensation to avoid sub-harmonic oscillation associated with current modecontrol. If the inductor value is lower than 10 µH, the slope compensation may not be adequate, and the loop canbe unstable. Therefore, customers need to verify the inductor in their application if it is different from therecommended values.
Table 3. Recommended Inductors for TPS61170
L DCR MAX SATURATION CURRENT SIZEPART NUMBER VENDOR(µH) (m ) (A) (L × W × H mm)
A915_Y-100M 10 90 1.3 5.2 × 5.2 × 3.0 TOKOVLCF5020T-100M1R1-1 10 237 1.1 5 × 5 × 2.0 TDKCDRH4D22/HP 10 144 1.2 5 × 5 × 2.4 SumidaLQH43PN100MR0 10 247 0.84 4.5 × 3.2 × 2.0 Murata
Copyright © 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS61170
SCHOTTKY DIODE SELECTION
COMPENSATION CAPACITOR SELECTION
P1
1
f =
2 x 6 M x C3p W
(7)
P2
2
f =
2 x Rout x C2p
(8)
2
RHPZ
Rout
f = x
2 x L
Vin
Voutp
æ ö
ç ÷
è ø
(9)
Z
1
f =
2 x R3 x C3p
(10)
1.229
A =
Vout
Vin 1
x Gea x 6 M x x Rout x
Vout x Rsense 2
W
(11)
INPUT AND OUTPUT CAPACITOR SELECTION
Cout +ǒVout *VinǓIout
Vout Fs Vripple
(12)
Vripple_ESR +Iout RESR
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
www.ti.com
The high switching frequency of the TPS61170 demands a high-speed rectification for optimum efficiency.Ensure that the diode s average and peak current rating exceeds the average output current and peak inductorcurrent. In addition, the diode s reverse breakdown voltage must exceed the switch FET rating voltage of 40V.So, the ONSemi MBR0540 is recommended for TPS61170. However, Schottky diode of low rating voltage canbe used for low output to save the solution size and cost. For example, 12V output with 20V diode is a goodchoice.
The TPS61170 has an external compensation, COMP pin, which allows the loop response to be optimized foreach application. The COMP pin is the output of the internal error amplifier. An external resistor R3 and ceramiccapacitors C3 are connected to COMP pin to provide a pole and a zero. This pole and zero, along with theinherent pole an zero in a current mode control boost converter, determine the close loop frequency response.This is important to a converter stability and transient response.
The following equations summarize the poles, zeros and DC gain in TPS61170, as shown in the block diagram.They include the dominant pole (f
P1
), the output pole (f
P2
) of a boost converter, the right-half-plane zero (f
RHPZ
) ofa boost converter, the zero (f
Z
) generated by R3 and C3, and the DC gain (A).
where Rout is the load resistance, Gea is the error amplifier transconductance located in the ELECTRICALCHARACTERISTICS table, Rsense (100m ) is a sense resistor in the current control loop. These equationshelps generate a simple bode plot for TPS61170 loop analysis.
Increasing R3 or reducing C3 increases the close loop bandwidth which improves the transient response.Adjusting R3 and C3 toward opposite direction increase the phase, and help loop stability. For most of theapplications, the recommended value of 10k and 680pF makes an ideal compromise between transient responseand loop stability. To optimize the compensation, use C3 in the range of 100pF to 10nF, and R3 of 10k. See theTI application report for thorough analysis and description of the boost converter small signal model andcompensation design.
The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. Thisripple voltage is related to the capacitor s capacitance and its equivalent series resistance (ESR). Assuming acapacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated usingEquation 12 .
Where, V
ripple
= peak-to-peak output ripple. The additional output ripple component caused by ESR is calculatedusing:
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum orelectrolytic capacitors are used.
16 Submit Documentation Feedback Copyright © 2007 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
LAYOUT CONSIDERATIONS
CTRL
GND
C3
L1
R2
Vin
CTRL
SW
FB
COMP
GND
C1 Vin
C2
Vout
Minimizethe
areaofthis
trace
Placeenough
VIAsaround
thermalpadto
enhancethermal
performance
R3
R1
Note: minimizethetrace
areaatFBpinand
COMP pin
THERMAL CONSIDERATIONS
TPS61170
www.ti.com
.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
Care must be taken when evaluating a ceramic capacitor s derating under dc bias, aging and AC signal. Forexample, larger form factor capacitors (in 1206 size) have a resonant frequencies in the range of the switchingfrequency. So, the effective capacitance is significantly lower. The DC bias can also significantly reducecapacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore,choose a ceramic capacitor with a voltage rating at least 1.5X its expected dc bias voltage.
The capacitor in the range of 1 µF to 4.7 µF is recommended for input side. The output requires a capacitor in therange of 1 µF to 10 µF. The output capacitor affects the loop stability of the boost regulator. If the output capacitoris below the range, the boost regulator can potentially become unstable.
The popular vendors for high value ceramic capacitors are:TDK (http://www.component.tdk.com/components.php )Murata (http://www.murata.com/cap/index.html )
As for all switching power supplies, especially those high frequency and high current ones, layout is an importantdesign step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.To maximize efficiency, switch rise and fall times are made as short as possible. To prevent radiation of highfrequency resonance problems, proper layout of the high frequency switching path is essential. Minimize thelength and area of all traces connected to the SW pin and always use a ground plane under the switchingregulator to minimize interplane coupling. The high current path including the switch, Schottky diode, and outputcapacitor, contains nanosecond rise and fall times and should be kept as short as possible. The input capacitorneeds not only to be close to the VIN pin, but also to the GND pin in order to reduce the IC supply ripple.Figure 18 shows a sample layout
Figure 18. PCB Layout Recommendation
The maximum IC junction temperature should be restricted to 125 ° C under normal operating conditions. Thisrestriction limits the power dissipation of the TPS61170. Calculate the maximum allowable dissipation, P
D(max)
,and keep the actual dissipation less than or equal to P
D(max)
. The maximum-power-dissipation limit is determinedusing Equation 13 :
Copyright © 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS61170
PD(max) +125°C*TA
RqJA
(13)
ADDITIONAL TYPICAL APPLICATIONS
D1
VIN SW
FB
GND
CTRL
COMP
C3
680 pF
TPS 61170
L1
10 Hm
C1
4.7 Fm
C2
4.7 Fm
R1
185.1kW
R2
10kW
R3
10kW
L1: TOKO#A915_Y-100M
C1:MurataGRM188R61A475K
C2:MurataGRM32ER71H475K
D1: ONsemiMBR0540T1
VIN12V VOUT 24V/300mA
VIN5V D1
VIN SW
FB
GND
CTRL
COMP
C3
680pF
TPS 61170
ON/ OFF
ProgramFB
L1
10 Hm
R1
87.6kW
R2
10kW
R3
10kW
C1
4.7 Fm
VOUT 12V/300mA
C2
4.7 Fm
L1: TOKO#A915_Y-100M
C1:MurataGRM188R61A475K
C2:MurataGRM21BR61E475K
D1: ONsemiMBR0540T1
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
www.ti.com
where, T
A
is the maximum ambient temperature for the application. R
θJA
is the thermal resistancejunction-to-ambient given in Power Dissipation Table.
The TPS61170 comes in a thermally enhanced QFN package. This package includes a thermal pad thatimproves the thermal capabilities of the package. The R
θJA
of the QFN package greatly depends on the PCBlayout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Usingthermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCBAttachment application report (SLUA271 ).
Figure 19. 12V to 24V DCDC Power Conversion
Figure 20. 5V to 12V DCDC Power Conversion With Programmable Feedback Reference Voltage
18 Submit Documentation Feedback Copyright © 2007 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
VIN9Vto15V D1
VIN SW
FB
GND
CTRL
COMP
C3
220 nF
TPS 61170
ON /OFF
DIMMING
CONTROL
L1
10 Hm
R1
87.6kW
C1
4.7 Fm
VOUT 12V/300mA
C4
1 Fm
C2
4.7 Fm
L2
10 Hm
R2
10kW
L1: TOKO#A915_Y-100M
C1:MurataGRM188R61A475K
C2:MurataGRM21BR61E475K
D1: ONsemiMBR0540T1
*L1,L2canbereplacedby1:1transformer
VIN SW
FB
GND
CTRL
COMP
10 nF
TPS61170
L1: TOKOB1000AS-220M
C1: MurataGRM188R61A475K
C2: MurataGRM21BR71H105K
C3, C4: MurataGRM32ER71H475K
D1 D3: B140
10k
D1
D2
Vo = 1.23 x (R1+R2)/ R2;
D3
VIN4.5Vto15V
C1
4.7 Fm
L1
22 HmC2
1 Fm
C3
4.7 Fm
C4
4.7 Fm
R2
10kW
V
48V/60mA
O
R1
380kW
TPS61170
www.ti.com
.................................................................................................................................................... SLVS789B NOVEMBER 2007 REVISED MAY 2009
Figure 21. 12V SEPIC (Buck-Boost) Converter
Figure 22. 48V Phantom Power Application Circuit
Copyright © 2007 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS61170
D1
VIN SW
FB
GND
CTRL
COMP
D2
D3
D4
Q1
Q2
VIN
L1: TOKOB992AS-330M
C1: MurataGRM188R61A475K
C2, C3: MurataGRM21BR71H105K
C4, C5: MurataGRM32ER71H475K
D1 D4: B140
Q1: BCM62B
Q2: MMBT3904TT1
Vo2 = 1.23 x (R1/ R2); Vo1 = 2Vo2
VIN3.3V
C1
4.7 Fm
L1
33 Hm
10nF
10kW
TPS61170
C2
1 Fm
C3
1 Fm
C4
4.7 Fm
V
-48V/30mA
O1
V
-24V/40mA
O2
R1
23.7kW
C5
4.7 Fm
1kW1kW
R2
1.24kW
VIN SW
FB
GND
CTRL
COMP
10nF
L1: EPCOSN97
C1: MurataGRM21BR61E475K
C2: MurataGRM32ER71H475K
D1: MURA160
D1
Vo = 1.23x (R1+R2)/ R2;
1 10 2 9 3 8
VIN12V
L1
15 Hpins1-10m
C2
4.7 Fm
V
48V/75mA
O
39pF
5.6 W
R2
2.61kW
R1
100kW
TPS61170
C1
4.7 Fm
60kW
TPS61170
SLVS789B NOVEMBER 2007 REVISED MAY 2009 ....................................................................................................................................................
www.ti.com
Figure 23. 24V / 48V Buck-Boost Converter from 3.3-V Input
Figure 24. 12V to 48V Flyback Topology
20 Submit Documentation Feedback Copyright © 2007 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS61170DRVR ACTIVE SON DRV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61170DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61170DRVT ACTIVE SON DRV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61170DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Apr-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS61170DRVR SON DRV 6 3000 330.0 12.4 2.2 2.2 1.1 8.0 12.0 Q2
TPS61170DRVT SON DRV 6 250 180.0 12.4 2.2 2.2 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Apr-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS61170DRVR SON DRV 6 3000 346.0 346.0 29.0
TPS61170DRVT SON DRV 6 250 190.5 212.7 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Apr-2009
Pack Materials-Page 2
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
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DLP® Products www.dlp.com Communications and www.ti.com/communications
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DSP dsp.ti.com Computers and www.ti.com/computers
Peripherals
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Interface interface.ti.com Energy www.ti.com/energy
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Microcontrollers microcontroller.ti.com Security www.ti.com/security
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