1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ACTS240MS
High Reliability, Radiation Hardened
Octal Buffer/Line Driver, Three-State
Pinouts
20 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T2 0,
LEAD FINISH C
TOP VIEW
20 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP4-F20,
LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
AEN
AI1
BO4
AI2
BO3
AI3
AI4
BO2
BO1
GND
VCC
AO1
BI4
AO2
BEN
BI3
AO3
BI2
AO4
BI1
2
3
4
5
6
7
8
120
19
18
17
16
15
14
13
9
10
12
11
AEN
AI1
BO4
AI2
BO3
AI3
AI4
BO2
BO1
GND
VCC
AO1
BI4
AO2
BEN
BI3
AO3
BI2
AO4
BI1
Features
• Devices QML Qualif ied in Accordance w it h M IL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96717 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
• S E U LE T T h re s h old . . . . . . . . . . . . . . . . . . . . . . . > 1 0 0 M EV-cm 2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/ s, 20ns Pulse
• Latch-Up Fr ee Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reducti on Compared to ALSTTL Logic
• DC Operating Volt age Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logi c Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay. . . . . . . . . . . . . . . 17.5ns (Max), 12ns (Typ)
Description
The Intersil ACTS240MS is a Radiation Hardened High Reliability, High-
Speed CMOS/SOS having two active low enable inputs.
The ACTS240MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. Thi s device is a member of a radiation hardened,
high-spe ed, CMOS/SOS Logic Family.
The ACTS240MS is supplied in a 20 lead Ceramic Flat pack (K suffix) or
a Dual-In-Li ne Ceramic Package (D suffix).
January 1996
Spec Number 518783
File Number 3186.1
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE
5962F9671701VRC -55oC to +125oC MIL-PRF-3853 5 Cl ass V 20 Lead SBDIP
5962F9671701VXC -55oC to +125oC MI L-PRF-38 535 Class V 20 Lead Ceram ic Flatpack
ACTS240D/Sample 25oC Sample 20 Lead SBDIP
ACTS240K/Sample 25oC Sample 20 Lead Ceramic Flatpack
ACTS240HMSR 25oCDie Die
tle
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2
ACTS240MS
Functional Diagram
TRUTH TABLE
INPUTS OUTPUT
AE, BE AIn, BIn AOn, BOn
LLH
LHL
HXZ
NOTE: H = High Volt age Level, L = Low Voltag e Level,
X = Immateria l, Z = High Impedance
P
N
AE
AI1
AO1
P
N
AI2
AO2
P
N
AI3
AO3
P
N
AI4
AO4
NOTE: (1 of 2)
1(19)
2(11)
4(13)
6(15)
8(17)
18(9)
16(7)
14(5)
12(3)
Spec Number 518783
3
ACTS240MS
Die Char acteris tics
DIE DIMENSIONS:
100 mils x 100 mil s
2.54mm x 2.54mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
BOND PAD SIZE:
110µm x 110µm
4.4 mils x 4.4 mils
Metallization Mask Layout
ACTS240MS
BO4 (3)
AI2 (4)
BO3 (5)
AI3 (6)
BO2 (7)
AI4 (8)
VCC
BO1 (9)
AO4 (12)
(13) BI2
(14) AO3
(15) BI3
(16) AO2
(17) BI4
(18) AO1
(20)
VCC
(20)
AEN
(1)
AI1
(2) BEN
(19)
(11)
BI1
(10)
GND
(10)
GND
Spec Number 518783
All Inter sil semiconductor pr oducts are manufactured, assembled and tested under ISO9000 quality systems certificati on.
Intersi l prod ucts are sold by descripti on only. Intersil Corporation r eserves the right to mak e changes in ci rcuit design and/ or spec ificatio ns at any time w ithout notic e.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its u se. No license is granted by implication or otherwise under any paten t or patent rights of Intersil or its subsidiaries.
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