74LVTH162373DGGE4 - TEXAS INSTRUMENTS

October 2000

Revised June 2005

74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the

Outputs

74LVTH162373

Low Voltage 16-Bit Transparent Latch with

3-STATE Outputs and

25: Series Resistors in the Outputs

General Descript ion

The LVTH162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear transparent to the data when the Latch Enable (LE)

is HIGH. When LE is LOW, the data that meets the setup

time is la tched. D ata appear s on the b us when th e Output

Enable (O E ) is LOW. When OE is HIG H , the o utp uts are in

a high impedance state.

The LVTH162373 is designed with equivalent 25

series

resistance in both the HIGH and LOW states of the output.

This design reduces line noise in applications such as

memory addr ess drivers, clock drive rs, and bus transc eiv-

ers/transmitters.

The LVTH162373 data inputs inclu de bushold, elim inating

the need for external pull-up resistors to hold unused

inputs.

These latches are designed for low-voltage (3.3V) VCC

applications, bu t with the capability to provide a TTL inte r-

face to a 5V environment. The LVTH162373 is fabricated

with an advanced BiCMOS technology to achieve high

speed ope rat ion simi lar to 5V ABT wh ile mai ntaining a low

power dissipation.

Features

■Input and output interface capability to systems at

5V VCC

■Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs

■Live insertion /extracti on per mitt ed

■Power Up/Down high impedance provides glitch-free

bus loading

■Outputs include equivalent series resistance of 25

make external termination resistors unnecessary and

reduce overshoot and undershoot

■Functionally compatible with the 74 series 16373

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human-body model

2000V

Machine model

200V

Charged-device model

1000V

Ordering Code:

Note 1: Use this Order Number to receive devices in Tape and Reel.

Logic Symbol

Order Number Package

Number Package Description

74LVTH162373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

[TUBES]

74LVTH162373MEX

(Note 1) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

[TAPE and REEL]

74L V TH162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TUBES]

74LVTH162373MTX

(Note 1) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TAPE and REEL]

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74LVTH162373

Connection Diagram Pin Descriptions

Truth Tables

HIGH Voltag e Level

LOW Voltage Le ve l

Immaterial

HIGH Im pedance

Previous output prior to HIGH-to-LOW transition of LE

Functional Description

The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each

byte functioning identically, but independent of the other . Control pins can be shorted together to obtain full 16-bit operation.

The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the

latches. In this con dition the latches are transparent, i.e, a latch outpu t will change states each tim e its D input changes.

When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW

transi tion of LEn. The 3-S TATE standard outp uts are co ntrolled by the Ou tput Ena ble (OE n) inp ut. When OEn is LOW, the

standard outputs a re in the 2-state m ode. When OEn is HI GH, the standard ou tputs are i n the high imped ance mod e but

this does not interfere with entering new data into the latches.

Pin Names Description

OEn Output Enable Input (Active LOW)

LEn Latch Enable Input

I0–I15 Inputs

O0–O15 3-STATE Outputs

Inputs Outputs

LE1OE1 I0–I7 O0–O7

X H X Z

H L L L

H L H H

L L X O

Inputs Outputs

LE2OE2 I8–I15 O8–O15

X H X Z

H L L L

H L H H

L L X O

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74LVTH162373

Logic Diagrams

Please not e t hat these diagram s are provided only fo r t he understa nding of logic operat ions and s hould not be used to e stimate propagation delays .

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74LVTH162373

Absolute Maximum Ratings(Note 2)

Recommended Operating Conditions

Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyo nd those in dic ated may adver s ely affec t device rel iability. Fun c tio nal opera ti on under ab s olute maximum rated con dit ions is not implied.

Note 3: IO Absolute Maximum Rating must be observed.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



4.6 V

VIDC Input Voltage



0.5 to



7.0 V

VODC Output Voltage



0.5 to



7.0 Output in 3-STATE V



0.5 to



7.0 Output in HIGH or LOW State (Note 3)

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA

IODC Output Current 64 VO

VCC Output at HIGH State mA

128 VO

VCC Output at LOW State

ICC DC Supply Current per Supply Pin

64 mA

IGND DC Ground Current per Ground Pin

128 mA

TSTG Storage Temperature



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage 2.7 3.6 V

VIInput Voltage 0 5.5 V

IOH HIGH Level Output Current



12 mA

IOL LOW Level Output Current 12 mA

TAFree-Air Operating Temperature



40 85

V Input Edge Rate , VIN

0.8V–2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter VCC T A



C to



CUnits Conditions

(V) Min Max

VIK Input Clamp Diode Voltage 2.7



1.2 V II



18 mA

VIH Input HIGH V olt age 2.7–3.6 2.0 V VO

0.1V or

VIL Input LOW V olt ag e 2.7–3.6 0.8 V VO

VCC



0.1V

VOH Output HIGH Voltage 2.7–3.6 VCC



0.2 VIOH



100

3.0 2.0 IOH



12mA

VOL Output LOW Voltage 2.7 0.2 VIOL

100

3.0 0.8 IOL

12 mA

II(HOLD) Bushold Input Minimum Drive 3.0 75

AVI

0.8V



75 VI

2.0V

II(OD) Bushold Input Over-Drive 3.0 500

A(Note 4)

Current to Change State



500 (Note 5)

IIInput Current 3.6 10

5.5V

Control Pins 3.6

0V or VCC

Data Pins 3.6



VCC

IOFF Power Off Leakage Current 0

100

A0V

VI or VO

5.5V

IPU/PD Power Up/Down 3-STATE 0–1.5V

100

AVO

0.5V to 3.0V

Output Current VI

GND or VCC

IOZL 3-STATE Output Leakage Current 3.6



0.5V

IOZH 3-STATE Output Leakage Current 3.6 5

3.0V

IOZH



3-STATE Output Leakage Current 3.6 10



5.5V

ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH

ICCL Power Supply Current 3.6 5 mA Outputs LOW

ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled

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74LVTH162373

DC Electrical Characteristics (Continued)

Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.

Note 5: An external driver mus t s ink at least the s pec if ied current to switc h f rom HIG H -t o-LOW.

Note 6: This is the incr eas e in sup ply c urrent for eac h input tha t is at t he specified voltage lev el rather th an VCC or GND.

Dynamic Switching Characteristics (Note 7)

Note 7: Characterized in SSOP packa ge. Guaranteed parameter, but not te sted.

Note 8: Max number of outp uts defined as (n). n



1 data inpu ts are driven 0V t o 3V. Output und er test he ld LOW.

AC Electrical Characteristics

Note 9: Skew is def ined as t he abso lute valu e of the difference between the actual propagation delay for a ny t w o separat e outputs of the same d evi ce. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HI GH (t OSLH).

Capacitance (Note 10)

Note 10: C apacitanc e is m easured at fr equency f

1 MHz, per MIL-STD -883, M et hod 3012.

Symbol Parameter VCC T A



C to



CUnits Conditions

(V) Min Max

ICCZ



Power Supply Current 3.6 0.19 mA VCC

5.5V,

Outputs Disabled

ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC



0.6V

(Note 6) Other Inputs at VCC or GND

Symbol Parameter VCC TA

CUnits Conditions

(V) Min Typ Max CL

50 pF, RL

500

VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8)

VOLV Quiet Output Minimum Dynamic VOL 3.3



0.8 V (Note 8)

Symbol Parameter



C to



C, CL

50pF, RL

500

UnitsVCC

3.3V

0.3V VCC

2.7V

Min Max Min Max

tPHL Propagation Delay 1.3 4.8 1.3 5.3 ns

tPLH Dn to On1.4 4.8 1.4 5.1

tPHL Propagation Delay 1.7 5.0 1.7 5.1 ns

tPLH LE to On1.4 5.1 1.4 5.8

tPZL Output Enable Time 1.6 5.0 1.6 6.0 ns

tPZH 1.0 5.4 1.0 6.6

tPLZ Output Disable Time 1.6 5.1 1.6 5.0 ns

tPHZ 1.8 5.4 1.8 5.7

tSSetup Time, Dn to LE 1.0 0.8 ns

tHHold Time, Dn to LE 1.0 1.1 ns

tWLE Pulse Width 3.0 3.0 ns

tOSHL Output to Output Skew (Note 9) 1.0 1.0 ns

tOSLH 1.0 1.0

Symbol Parameter Conditions Typical Units

CIN Input Capaci tance VCC

OPEN, VI

0V or VCC 4pF

COUT Output Capacitance VCC

3.0V, VO

0V or VCC 8pF

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74LVTH162373

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Packag e Num b er MS48A

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74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the

Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide

Package Number MTD48

Fairchild does not assum e any responsibility for use of any circuitry described, n o circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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