MCP6N11-100E/SN - MICROCHIP - Datasheet.Directory

MCP6N11

Features

• Rail-to-Rail Input and Output

• Gain Set by 2 External Resistors

• Minimum Gain (GMIN) Options:

1, 2, 5, 10 or 100 V/V

• Common Mode Rejection Ratio (CMRR): 115 dB

(typical, GMIN =100)

• Power Supply Rejection Ratio (PSRR): 112 dB

(typical, GMIN =100)

• Bandwidth: 500 kHz (typical, Gain = GMIN)

• Supply Current: 800 μA/channel (typical)

• Single Channel

• Enable/VOS Calibration pin: (EN/CAL)

• Power Supply: 1.8V to 5.5V

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• High Side Current Sensor

• Wheatstone Bridge Sensors

• Difference Amplifier with Level Shifting

• Power Control Loops

Design Aids

• Microchip Advanced Part Selector (MAPS)

• Demonstration Board

• Application Notes

Block Diagram

Description

Microchip Technology Inc. offers the single MCP6N11

instrumentation amplifier (INA) with Enable/VOS Cali-

bration pin (EN/CAL) and several minimum gain

options. It is optimized for single-supply operation with

rail-to-rail input (no common mode crossover distor-

tion) and output performance.

Two external resistors set the gain, minimizing gain

error and drift-over temperature. The reference voltage

(VREF) shifts the output voltage (VOUT).

The supply voltage range (1.8V to 5.5V) is low enough

to support many portable applications. All devices are

fully specified from -40°C to +125°C.

These parts have five minimum gain options (1, 2, 5, 10

and 100 V/V). This allows the user to optimize the input

offset voltage and input noise for different applications.

Typical Application Circuit

Package Types

RFVFG

VOUT

Low Power

VSS

VDD

EN/CAL

VOUT

Calibration

VREF

RM4

GM2 Σ

VREF

GM3

VTR

VIP

VIM

GM1

VIP

VIM

POR

10 Ω

VDD

IDD

VBAT

+1.8V

+5.5V

VOUT

VREF

VFG

200 kΩ

10 kΩ

MCP6N11

SOIC

VIP

VIM

VSS

VDD

VOUT

5VREF

EN/CALVFG

MCP6N11

2×3 TDFN *

VIP

VIM

VSS

VDD

VOUT

5VREF

EN/CALVFG

* Includes Exposed Thermal Pad (EP); see Table 3-1.

500 kHz, 800 µA Instrumen t ation Amplifier

MCP6N11

Minimum Gain Options

Table 1 shows key specifications that differentiate

between the different minimum gain (GMIN) options.

See Section 1.0 “Electrical Characteristics”,

Section 6.0 “Packaging Information” and Product

Identification System for further information on GMIN.

TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

Part No.

GMIN

(V/V)

Nom.

VOS

(±mV)

Max.

∆VOS/∆TA

(±µV/°C)

Typ.

CMRR (dB)

Min.

VDD =5.5V

PSRR

(dB)

Min.

VDMH

(V)

Max.

GBWP

(MHz)

Nom.

Eni

(µVP-P)

Nom.

(f = 0.1 to 10 Hz)

eni

(nV/√Hz)

Nom.

(f = 10 kHz)

MCP6N11-001 1 3.0 90 70 62 2.70 0.50 570 950

MCP6N11-002 2 2.0 45 78 68 1.35 1.0 285 475

MCP6N11-005 5 0.85 18 80 75 0.54 2.5 114 190

MCP6N11-010 10 0.50 9.0 81 81 0.27 5.0 57 95

MCP6N11-100 100 0.35 2.7 88 86 0.027 35 18 35

MCP6N11

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD –V

SS .......................................................................6.5V

Current at Input Pins †† ...............................................±2 mA

Analog Inputs (VIP and VIM)†† ..... VSS – 1.0V to VDD +1.0V

All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V

Difference Input Voltage....................................... |VDD –V

SS|

Output Short Circuit Current ................................Continuous

Current at Output and Supply Pins ............................±30 mA

Storage Temperature ...................................-65°C to +150°C

Max. Junction Temperature ........................................ +150°C

ESD protection on all pins (HBM, CDM, MM)

.≥

2 kV, 1.5 kV, 3 00V

†Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at those or any other

conditions above those indicated in the operational

listings of this specification is not implied. Exposure to

maximum rating conditions for extended periods may

affect device reliability.

†† See Section 4.2.1.2 “Input Voltage Limits” and

Section 4.2.1.3 “Input Current Limits”.

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD,

VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL and GDM =G

MIN; see Figure 1-6 and Figure 1-7.

Parameters Sym Min Typ Max Units GMIN Conditions

Input Offset

Input Offset Voltage,

Calibrated

VOS -3.0 — +3.0 mV 1 (Note 2)

-2.0 — +2.0 mV 2

-0.85 — +0.85 mV 5

-0.50 — +0.50 mV 10

-0.35 — +0.35 mV 100

Input Offset Voltage

Trim Step

VOSTRM —0.36—mV1

—0.21—mV2

—0.077—mV5

—0.045—mV10

—0.014—mV100

Input Offset Voltage

Drift

ΔVOS/ΔTA—±90/G

MIN — µV/°C 1 to 10 TA= -40°C to +125°C

(Note 3)

— ±2.7 — µV/°C 100

Power Supply

Rejection Ratio

PSRR 62 82 — dB 1

68 88 — dB 2

75 96 — dB 5

81 102 — dB 10

86 112 — dB 100

Note 1: VCM = (VIP + VIM) / 2, VDM = (VIP – VIM) and GDM = 1 + RF/RG

2: The VOS spec limits include 1/f noise effects.

3: This is the input offset drift without VOS re-calibration; toggle EN/CAL to minimize this effect.

4: These specs apply to both the VIP

, VIM input pair (use VCM) and to the VREF

, VFG input pair (VREF takes VCM’s place).

5: This spec applies to the VIP

, VIM, VREF and VFG pins individually.

6: Figure 2-11 and Figure 2-19 show the VIVR and VDMR variation over temperature.

7: See Section 1.5 “Explanation of DC Error Specs”.

MCP6N11

Input Current and Impedance (Note 4)

Input Bias Current IB— 10 — pA all

Across Temperature — 80 — pA TA= +85°C

Across Temperature 0 2 5 nA TA= +125°C

Input Offset Current IOS —±1—pA

Across Temperature — ±5 — pA TA= +85°C

Across Temperature -1 ±0.05 +1 nA TA= +125°C

Common Mode Input

Impedance

ZCM —10

13||6 — Ω||pF

Differential Input

Impedance

ZDIFF —10

13||3 — Ω||pF

Input Common Mode Voltage (VCM or VREF) (Note 4)

Input Voltage Range VIVL ——V

SS −0.2 V all (Note 5, Note 6)

VIVH VDD +0.15 — — V

Common Mode

Rejection Ratio

CMRR 62 79 — dB 1 VCM = VIVL to VIVH,

VDD =1.8V

69 87 — dB 2

75 101 — dB 5

79 107 — dB 10

86 119 — dB 100

70 94 — dB 1 VCM = VIVL to VIVH,

VDD =5.5V

78 100 — dB 2

80 108 — dB 5

81 114 — dB 10

88 115 — dB 100

Common Mode

Non-Linearity

INLCM -1000 ±115 +1000 ppm 1 VCM = VIVL to VIVH,

VDM =0V,

VDD =1.8V (Note 7)

-570 ±27 +570 ppm 2

-230 ±11 +230 ppm 5

-125 ±6 +125 ppm 10

-50 ±2 +50 ppm 100

-400 ±42 +400 ppm 1 VCM = VIVL to VIVH,

VDM =0V,

VDD =5.5V (Note 7)

-220 ±10 +220 ppm 2

-100 ±4 +100 ppm 5

-50 ±2 +50 ppm 10

-30 ±1 +30 ppm 100

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD,

VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL and GDM =G

MIN; see Figure 1-6 and Figure 1-7.

Parameters Sym Min Typ Max Units GMIN Conditions

Note 1: VCM = (VIP + VIM) / 2, VDM = (VIP – VIM) and GDM = 1 + RF/RG

2: The VOS spec limits include 1/f noise effects.

3: This is the input offset drift without VOS re-calibration; toggle EN/CAL to minimize this effect.

4: These specs apply to both the VIP

, VIM input pair (use VCM) and to the VREF

, VFG input pair (VREF takes VCM’s place).

5: This spec applies to the VIP

, VIM, VREF and VFG pins individually.

6: Figure 2-11 and Figure 2-19 show the VIVR and VDMR variation over temperature.

7: See Section 1.5 “Explanation of DC Error Specs”.

MCP6N11

Input Differential Mode Voltage (VDM) (Note 4)

Differential Input

Voltage Range

VDML -2.7/GMIN ——VallV

REF = (VDD –G

DMVDM)/2

(Note 6)

VDMH — — +2.7/GMIN V

Differential Gain Error gE-1 ±0.13+1% V

DM = VDML to VDMH,

Differential Gain Drift ΔgE/ΔTA— ±0.0006 — %/°C VREF = (VDD –G

DMVDM)/2

Differential

Non-Linearity

INLDM -500 ±30 +500 ppm 1 (Note 7)

-800 ±40 +800 ppm 2, 5

-2000 ±100 +2000 ppm 10, 100

DC Open-Loop Gain AOL 61 84 — dB 1 VDD =1.8V,

68 90 — dB 2 VOUT = 0.2V to 1.6V

76 98 — dB 5

78 104 — dB 10

86 116 — dB 100

70 94 — dB 1 VDD =5.5V,

77 100 — dB 2 VOUT = 0.2V to 5.3V

84 108 — dB 5

90 114 — dB 10

97 125 — dB 100

Output

Minimum Output

Voltage Swing

VOL ——V

SS +15 mV all V

DM =-V

DD/(2GDM),

VDD =1.8V,

VREF = VDD/2 – 1V

——V

SS +25 mV V

DM =-V

DD/(2GDM),

VDD =5.5V,

VREF = VDD/2 – 1V

Maximum Output

Voltage Swing

VOH VDD −15 — — mV VDM =V

DD/(2GDM),

VDD =1.8V,

VREF = VDD/2 + 1V

VDD −25 — — mV VDM =V

DD/(2GDM),

VDD =5.5V,

VREF = VDD/2 + 1V

Output Short Circuit

Current

ISC —±8—mA V

DD = 1.8V

—±30—mA V

DD = 5.5V

Power Supply

Supply Voltage VDD 1.8 — 5.5 V all

Quiescent Current

per Amplifier

IQ0.5 0.8 1.1 mA IO = 0

POR Trip Voltage VPRL 1.1 1.4 — V

VPRH —1.41.7V

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD,

VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL and GDM =G

MIN; see Figure 1-6 and Figure 1-7.

Parameters Sym Min Typ Max Units GMIN Conditions

Note 1: VCM = (VIP + VIM) / 2, VDM = (VIP – VIM) and GDM = 1 + RF/RG

2: The VOS spec limits include 1/f noise effects.

3: This is the input offset drift without VOS re-calibration; toggle EN/CAL to minimize this effect.

4: These specs apply to both the VIP

, VIM input pair (use VCM) and to the VREF

, VFG input pair (VREF takes VCM’s place).

5: This spec applies to the VIP

, VIM, VREF and VFG pins individually.

6: Figure 2-11 and Figure 2-19 show the VIVR and VDMR variation over temperature.

7: See Section 1.5 “Explanation of DC Error Specs”.

MCP6N11

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA=25°C, V

DD = 1.8V to 5.5V, VSS = GND,

EN/CAL =V

DD, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL= 60 pF and GDM =G

MIN;

see Figure 1-6 and Figure 1-7.

Parameters Sym Min Typ Max Units GMIN Conditions

AC Response

Gain Bandwidth

Product

GBWP — 0.50 GMIN — MHz 1 to 10

— 35 — MHz 100

Phase Margin PM — 70 — ° all

Open-Loop Output

Impedance

ROL —0.9—kΩ1 to 10

—0.6—kΩ100

Power Supply

Rejection Ratio

PSRR — 94 — dB all f < 10 kHz

Common Mode

Rejection Ratio

CMRR — 104 — dB 1 to 10 f < 10 kHz

— 94 — dB 100 f < 10 kHz

Step Response

Slew Rate SR — 3 — V/µs 1 to 10 VDD =1.8V

—9—V/µs V

DD =5.5V

— 2 — V/µs 100 VDD =1.8V

—6—V/µs V

DD =5.5V

Overdrive Recovery,

Input Common Mode

tIRC —10—µs allV

CM =V

SS –1V (or V

DD + 1V) to VDD/2,

GDMVDM = ±0.1V, 90% of VOUT change

Overdrive Recovery,

Input Differential

Mode

tIRD —5—µs V

DM =V

DML –(0.5V)/G

MIN

(or VDMH +(0.5V)/G

MIN) to 0V,

VREF =(V

DD –G

DMVDM)/2,

90% of VOUT change

Overdrive Recovery,

Output

tOR —8—µs G

DM =2G

MIN, GDMVDM =0.5V

DD to 0V,

VREF =0.75V

DD (or 0.25VDD),

90% of VOUT change

Noise

Input Noise Voltage Eni — 570/GMIN —µV

P-P 1 to 10 f = 0.1 Hz to 10 Hz

—18 —µV

P-P 100

Input Noise Voltage

Density

eni — 950/GMIN —nV/√Hz 1 to 10 f = 100 kHz

—35 —nV/√Hz 100

Input Current Noise

Density

ini —1—fA/√Hz all f = 1 kHz

MCP6N11

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA= 25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD,

VCM = VDD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL= 60 pF and GDM =G

MIN;

see Figure 1-6 and Figure 1-7.

Parameters Sym Min Typ Max Units GMIN Conditions

EN/CAL Low Specifications

EN/CAL Logic

Threshold, Low

VIL VSS —0.2V

DD Vall

EN/CAL Input Current,

Low

IENL — -0.1 — nA EN/CAL = 0V

GND Current ISS -7 -2.5 — µA EN/CAL = 0V, VDD =5.5V

Amplifier Output Leakage IO(LEAK) — 10 — nA EN/CAL = 0V

EN/CAL High Specifications

EN/CAL Logic

Threshold, High

VIH 0.8 VDD VDD Vall

EN/CAL Input Current,

High

IENH — -0.01 — nA EN/CAL = VDD

EN/CAL Dynamic Specifications

EN/CAL Input Hysteresis VHYST —0.2 —Vall

EN/CAL Low to Amplifier

Output High-Z Turn-off

Time

tOFF — 3 10 µs EN/CAL = 0.2VDD to VOUT = 0.1(VDD/2),

VDMGDM = 1 V, VL=0V

EN/CAL High to

Amplifier Output

On Time

tON 12 20 28 ms EN/CAL = 0.8VDD to VOUT = 0.9(VDD/2),

VDMGDM = 1 V, VL=0V

EN/CAL Low to

EN/CAL High low time

tENLH 100 — — µs Minimum time before externally

releasing EN/CAL (Note 1)

Amplifier On to

EN/CAL Low Setup Time

tENOL —100— µs

POR Dynamic Specifications

VDD ↓ to Output Off tPHL —10— µsallV

L=0V, V

DD = 1.8V to

VPRL –0.1V step,

90% of VOUT change

VDD ↑ to Output On tPLH 140 250 360 ms VL=0V, V

DD = 0V to VPRH +0.1V step,

90% of VOUT change

Note 1: For design guidance only; not tested.

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = 1.8V to 5.5V, VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA-40 — +125 °C

Operating Temperature Range TA-40 — +125 °C (Note 1)

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 8L-SOIC θJA —150—°C/W

Thermal Resistance, 8L-TDFN (2×3) θJA —53—°C/W

Note 1: Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (+150°C).

MCP6N11

1.3 Timing Diagrams

FIGURE 1-1: Common Mode Input

Overdrive Re covery Timing Diagram.

FIGURE 1-2: Differential Mode Input

Overdrive Re covery Timing Diagram.

FIGURE 1-3: Output Overdrive Recovery

Timing Diagram.

FIGURE 1-4: POR Timing Diagram.

FIGURE 1-5: EN/CAL Timing Diagram.

VOUT

tIRC

VDM

VCM

±(1V)/GDM

VOUT

tIRD

VCM

VDM

VDD/2

VOUT

tOR

VCM

VDM

VDD/2

1.8V

VPRL –0.1V

High-Z

VOUT

VDD

tPHL tPLH

VPRH +0.1V

High-Z

VOUT

EN/CAL

tOFF tON

tENLH

tENOL

MCP6N11

1.4 DC Test Circuits

1.4.1 INPUT OFFSET TEST CIRCUIT

Figure 1-6 is used for testing the INA’s input offset

errors and input voltage range (VE, VIVL and VIVH; see

Section 1.5.1 “Input Offset Related Errors” and

Section 1.5.2 “Input Offset Common Mode Non-

linearity”). U2 is part of a control loop that forces VOUT

to equal VCNT

; U1 can be set to any bias point.

FIGURE 1-6: Test Circuit for Common

Mode (Input Offset).

When MCP6N11 is in its normal range of operation, the

DC output voltages are (where VE is the sum of input

offset errors and gE is the gain error):

EQUATION 1-1:

Table 1-5 gives the recommended RF and RG values

for different GMIN options.

1.4.2 DIFFERENTIAL GAIN TEST CIRCUIT

Figure 1-7 is used for testing the INA’s differential gain

error, non-linearity and input voltage range (gE, INLDM,

VDML and VDMH; see Section 1.5.3 “Differential Gain

Error and Non-linearity”). RF and RG are 0.01% for

accurate gain error measurements.

FIGURE 1-7: Test Circuit for Differential

Mode.

The output voltages are (where VE is the sum of input

offset errors and gE is the gain error):

EQUATION 1-2:

To keep VREF

, VFG and VOUT within their ranges, set:

EQUATION 1-3:

Table 1-6 shows the recommended RF and RG

. They

produce a 10 kΩ load; VL can usually be left open.

TABLE 1-5: SELECTING RF AND RG

GMIN

(V/V)

Nom.

(Ω)

Nom.

(Ω)

Nom.

GDM

(V/V)

Nom.

GDMVOS

(±V)

Max.

(kHz)

Nom.

1 100k 499 201.4 0.60 2.5

2 0.40 5.0

5 100k 100 1001 0.85 2.5

10 0.50 5.0

100 0.35 35

VCM 100 nF

VDD

2.2 µF

VREF

12.7 kΩ

100 nF CCNT

MCP6N11

MCP6H01

VCNT

63.4 kΩ

RCNT

63.4 kΩ

VOUT

10 nF

1kΩ

GDM 1R

FRG

⁄

VOUT VCNT

VMVREF GDM 1g

+()VE

TABLE 1-6: SELECTING RF AND RG

GMIN

(V/V)

Nom.

(Ω)

Nom.

(Ω)

Nom.

GDM

(V/V)

Nom.

10Open1.000

2 4.99k 4.99k 2.000

5 8.06k 2.00k 5.030

10 9.09k 1.00k 10.09

100 10.0k 100 101.0

6.34 kΩ

1kΩ

VCM +V

DM/2

100 nF

VOUT

–

100 nF

VDD

2.2 µF

6.34 kΩ

VREF

VFG

VCM –V

DM/2

0.01%

MCP6N11

GDM 1R

FRG

⁄

VMVOUT VREF

–=

VOUT VREF GDM 1g

+()VDM VE

+()+=

DM 1g

+()VDM VE

+()=

VREF VDD GDMVDM

–()2

⁄

MCP6N11

1.5 Explanation of DC Error Specs

1.5.1 INPUT OFFSET RELATED ERRORS

The input offset error (VE) is extracted from input offset

measurements (see Section 1.4.1 “Input Offset Test

Circuit”), based on Equation 1-1:

EQUATION 1-4:

VE has several terms, which assume a linear response

to changes in VDD, VSS, VCM, VOUT and TA (all of which

are in their specified ranges):

EQUATION 1-5:

Equation 1-2 shows how VE affects VOUT

1.5.2 INPUT OFFSET COMMON MODE

NON-LINEARITY

The input offset error (VE) changes non-linearly with

VCM. Figure 1-8 shows VE vs. VCM, as well as a linear

fit line (VE_LIN) based on VOS and CMRR. The op amp

is in standard conditions (ΔVOUT =0, V

DM =0, etc.).

VCM is swept from VIVL to VIVH. The test circuit is in

Section 1.4.1 “Input Offset Test Circuit” and VE is

calculated using Equation 1-4.

FIGURE 1-8: Input Offset Error vs.

Common Mode Input Voltage.

Based on the measured VE data, we obtain the

following linear fit:

EQUATION 1-6:

The remaining error (ΔVE) is described by the Common

Mode Non-Linearity spec:

EQUATION 1-7:

The same common mode behavior applies to VE when

VREF is swept, instead of VCM, since both input stages

are designed the same:

EQUATION 1-8:

1.5.3 DIFFERENTIAL GAIN ERROR AND

NON-LINEARITY

The differential errors are extracted from differential

gain measurements (see Section 1.4.2 “Differential

Gain Test Circuit”), based on Equation 1-2. These

errors are the differential gain error (gE) and the input

offset error (VE, which changes non-linearly with VDM):

EQUATION 1-9:

These errors are adjusted for the expected output, then

referred back to the input, giving the differential input

error (VED) as a function of VDM:

EQUATION 1-10:

VEVMVREF

–

GDM 1g

+()

---------------------------------=

Where:

PSRR, CMRR and AOL are in units of V/V

TA is in units of °C

VDM =0

VEVOS

VDD

VSS

–

PSRR

---------------------------------

VCM

CMRR

-----------------

VREF

CMRR

-----------------+++=

VOUT

AOL

-----------------

VOS

-------------

⋅

VE, VE_LIN (V)

VCM (V)

VIVL VIVH

VDD/2

VE_LIN

ΔVE

Where:

VE_LIN VOS VCM VDD 2

⁄

–

CMRR

-----------------------------------+=

VOS V2

CMRR

-----------------V3V1

–

VIVH VIVL

–

------------------------------=

Where:

INLCM max

VIVH VIVL

–

------------------------------=

VEVEVE_LIN

–=

VE_LIN VOS VREF VDD 2

⁄

–

CMRR

-------------------------------------+=

INLCM max

VIVH VIVL

–

------------------------------=

GDM 1R

FRG

⁄

VMGDM 1g

+()VDM V+ E

()=

VED VM

GDM

------------V

–=

MCP6N11

Figure 1-9 shows VED vs. VDM, as well as a linear fit

line (VED_LIN) based on VE and gE. The op amp is in

standard conditions (ΔVOUT =0, etc.). V

DM is swept

from VDML to VDMH.

FIGURE 1-9: Differential Input Error vs.

Differential Input Voltage.

Based on the measured VED data, we obtain the

following linear fit:

EQUATION 1-11:

Note that the VE value measured here is not as

accurate as the one obtained in Section 1.5.1 “Input

Offset Related Errors”.

The remaining error (ΔVED) is described by the

Differential Mode Non-Linearity spec:

EQUATION 1-12:

VED, VED_LIN (V)

VDM (V)

VDML VDMH

VED_LIN

VED

ΔVED

Where:

VED_LIN 1g

+()VEgEVDM

gEV3V1

–

VDMH VDML

–

----------------------------------- 1–=

VEV2

----------------=

Where:

INLDM max

VED

VDMH VDML

–

-----------------------------------=

VED VED VED_LIN

–=

MCP6N11

NOTES:

MCP6N11

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

2.1 DC Voltages and Currents

FIGURE 2-1: Normalized Input Offset

Voltage, with GMIN = 1 to 10.

FIGURE 2-2: Normalized Input Offset

Voltage, with GMIN = 100.

FIGURE 2-3: Normalized Input Offset

Voltage Drift, with GMIN = 1 to 10.

FIGURE 2-4: Normalized Input Offset

Voltage Drift, with GMIN = 100.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

30%

35%

330 Samples

TA=

25%

30%

rrence

TA+25°C

VDD = 1.8V and 5.5V

RTO

20%

f Occu

GMIN = 1

MIN

=2to10

10%

15%

tage of

MIN

=2to10

10%

Percent

-2.

-1.

-0.

Normalized Input Offset Voltage; G

MIN

(mV)

12%

14%

330 Samples

GMIN = 100

10%

12%

rrence

MIN

TA= +25°C

VDD = 1.8V and 5.5V

RTO

Occu

age o

ercen

-18

-16

-14

-12

-10

-8

-6

-4

-2

Normalized Input Offset Voltage; G

MIN

(mV)

25%

No VOS Re-calibration

330 Sam

les

20%

urren

GMIN = 1 to 10

VDD = 5.5V

RTO

15%

of Oc

10%

ntage

Perc

600

500

300

100

300

500

600

Normalized Input Offset Voltage Drift;

MIN

(V

/T

) (μV/°C)

16%

18%

No VOS Re-calibration

330 Sam

les

12%

14%

urren

GMIN = 100

VDD = 5.5V

RTO

10%

of Oc

ntage

Perc

200

000

-800

-600

-400

-200

200

400

600

800

000

200

Normalized Input Offset Voltage Drift;

MIN

(V

/T

) (μV/°C)

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

FIGURE 2-5: Normalized Input Offset

Voltage vs. Power Supply Voltage, with

VCM = 0V and GMIN =1 to 10.

FIGURE 2-6: Normalized Input Offset

Voltage vs. Power Supply Voltage, with

VCM = 0V and GMIN =100.

FIGURE 2-7: Normalized Input Offset

Voltage vs. Power Supply Voltage, with

VCM =V

DD and GMIN = 1 to 10.

FIGURE 2-8: Normalized Input Offset

Voltage vs. Power Supply Voltage, with

VCM =V

DD and GMIN = 100.

FIGURE 2-9: Normalized Input Offset

Voltage vs. Output Voltage, with GMIN = 1 to 10.

FIGURE 2-10: Normalized Input Offset

Voltage vs. Output Voltage, with GMIN = 100.

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

d Input Offset Voltage;

MIN

(mV)

-40°C

-2.5

-2.0

-1.5

-1.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Normalized

Power Supply Voltage

Representative Part

VCM = VSS

GMIN = 1 to 10

RTO

+25°C

+85°C

+125°C

ge;

t Volt

Offs

S(mV)

-5

Inpu

MINVO

-15

-10

alize

Representative Part

= V

-40°C

25°C

-25

-20

Nor

GMIN = 100

RTO

125°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Input Offset Voltage;

MIN

(mV)

Representative Part

VCM = VDD

GMIN = 1 to 10

RTO

-40°C

+25°C

+85°C

+125°C

-1.2

-1.0

-0.8

-0.6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Normalize

Power Supply Voltage

-2

d Input Offset Voltage;

MIN

(mV)

Representative Part

VCM = VDD

GMIN = 100

RTO

-10

-8

-6

-4

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Normalized

Power Supply Voltage

-40°C

+25°C

+85°C

+125°C

-0.5

0.0

0.5

1.0

1.5

2.0

Input Offset Voltage;

MIN

(mV)

Representative Part

GMIN = 1 to 10

RTO

VDD = 5.5V

VDD = 1.8V

-2.0

-1.5

-1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Normalize

Output Voltage (V)

-1

Input Offset Voltage;

MIN

(mV)

Representative Part

GMIN = 100

RTO

VDD = 5.5V

VDD = 1.8V

-6

-5

-4

-3

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Normalize

Output Voltage (V)

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

FIGURE 2-11: Input Common Mode

Voltage Headroom vs. Ambient Temperature.

FIGURE 2-12: Normalized Input Offset

Voltage vs. Common Mode Voltage, with

VDD = 1.8V and GMIN =1 to 10.

FIGURE 2-13: Normalized Input Offset

Voltage vs. Common Mode Voltage, with

VDD = 1.8V and GMIN =100.

FIGURE 2-14: Normalized Input Offset

Voltage vs. Common Mode Voltage, with

VDD = 5.5V and GMIN = 1 to 10.

FIGURE 2-15: Normalized Input Offset

Voltage vs. Common Mode Voltage, with

VDD = 5.5V and GMIN =100.

FIGURE 2-16: Normalized CMRR and

PSRR vs. Ambient Temperature.

0.4

0.5

1 Wafer Lot

VIVH –V

0.2

0.3

eadro

0.1

0.2

nge

)

= 1.8V

-0.1

age R

(

VDD = 5.5V

-0.3

ut Vol

-0.5

-0.4

Inp

VIVL –V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

-0.5

0.0

0.5

1.0

1.5

2.0

d Input Offset Voltage;

MIN

(mV)

VDD = 1.8V

Representative Part

GMIN = 1 to 10

RTO

-2.0

-1.5

-1.0

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Normalized

Input Common Mode Voltage (V)

+125°C

+85°C

+25°C

-40°C

-5

d Input Offset Voltage;

MIN

(mV)

VDD = 1.8V

Representative Part

GMIN = 100

RTO

-15

-10

-5

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Normalized

Input Common Mode Voltage (V)

+125°C

+85°C

+25°C

-40°C

-0.5

0.0

0.5

1.0

1.5

2.0

d Input Offset Voltage;

MIN

(mV)

VDD = 5.5V

Representative Part

GMIN = 1 to 10

RTO

+125°C

+85

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Normalized

Input Common Mode Voltage (V)

+85°C

+25°C

-40°C

-5

d Input Offset Voltage;

MIN

(mV)

VDD = 5.5V

Representative Part

GMIN = 100

RTO

-15

-10

-5

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Normalized

Input Common Mode Voltage (V)

+125°C

+85°C

+25°C

-40°C

105

110

)

CMRR / GMIN, VDD = 1.8V:

MIN

1 100

CMRR / GMIN, VDD = 5.5V:

MIN

1to10

100

SRR;

MIN

100

GMIN = 2 to 10

MIN

1to10

GMIN = 100

RR,

RR /

ized C

MIN

, P

ormal

RR /

PSRR / G

MIN

PSRR / G

MIN

GMIN = 1 to 10

GMIN = 100

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

FIGURE 2-17: Normalized DC Open-Loop

Gain vs. Ambient Temperature.

FIGURE 2-18: The MCP6N11 Shows No

Phase Reversal vs. Common Mode Voltage.

FIGURE 2-19: Normalized Differential

Mode Voltage Range vs. Ambient Temperature.

FIGURE 2-20: Normalized Differential Input

Error vs. Differential Voltage, with GMIN =1.

FIGURE 2-21: Normalized Differential Input

Error vs. Differential Voltage, with

GMIN = 2 to 100.

FIGURE 2-22: The MC P6N11 Shows N o

Phase Reversal vs. Differential Voltage, with

VDD =5.5V.

105

110

in;

100

op G

)

DD = 5.5V

VDD = 1.8V

pen-L

(dB

)

/ G

alize

GMIN = 1 to 10

= 100

Nor

MIN

= 100

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

5.5

6.0

Representative Part

= 5.5V

4.5

5.0

(V)

100

3.5

ltage

100

GDM = 1

2.0

2.5

put V

VIM = -0.20V

1.0

1.5

2.0

IM = VDD + 0.15V

0.0

0.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Non-inverting Input Voltage; V

(V)

3.8

4.0

)

1 Wafer Lot

GMINVDMH = -GMINVDML

3.4

3.6

al Inp

DMH

(

RTO

3.2

3.4

ferent

; G

MIN

2.8

ed Di

Rang

2.4

2.6

rmali

ltage

2.0

2.2

Note: For GMIN = 1,

VDMH = minimum of plot value and VDD

-50 -25 0 25 50 75 100 125

Axis Title

-1

ized Differential Input

or; G

MIN

(mV)

Representative Part

VED = (VOUT –V

REF)/GDM –V

GMIN = 1

RTO

VDD = 1.8V

VDD = 5.5V

-5

-4

-3

-5-4-3-2-1012345

Normal

Normalized Differential Input Voltage;

MIN

(V)

Representative Part

OUT

–

REF

)/G

–

ial In

mV)

OUT

REF

)/G

GMIN = 2 to 100

RTO

fferen

(

-1

ized D

or; G

-3

ormal

-5

Normalized Differential Input Voltage;

MIN

(V)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

put Voltage (V)

Representative Part

VDD = 5.5V

VREF = (VDD –G

DMVDM)/2

0.0

0.5

1.0

1.5

-7-6-5-4-3-2-101234567

Differential Input Voltage (V)

GMIN = 1

GMIN = 2

GMIN = 5

GMIN = 10

GMIN = 100

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

FIGURE 2-23: Input Bias and Offset

Currents vs. Ambient Temperature, with

VDD = +5.5V.

FIGURE 2-24: Input Bias Current vs.

Input Voltage (below VSS).

FIGURE 2-25: Input Bias and Offset

Currents vs. Common Mode Input Voltage, with

TA= +85°C.

FIGURE 2-26: Input Bias and Offset

Currents vs. Common Mode Input Voltage, with

TA= +125°C.

FIGURE 2-27: Output Voltage Headroom

vs. Output Current.

FIGURE 2-28: Output Voltage Headroom

vs. Ambient Temperature.

1.E-10

1.E-09

1.E-08

, Offset Currents (A)

VDD = 5.5V

VCM = VDD

100p

10n

1.E-12

1.E-11

25 45 65 85 105 125

Input Bia

Ambient Temperature (°C)

| IOS |

10p

1E09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

urrent Magnitude (A)

+125°C

+85°C

+25°C

-40°

100μ

10μ

1μ

100n

10n

1.E-12

1.E-11

1.E-10

1.E-09

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Cu

Input Voltage (V)

-40 C

100p

10p

-20

100

s, Offset Currents (pA)

Representative Part

TA= +85°C

VDD = 5.5V

IOS

-100

-80

-60

-40

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Input Bias

Common Mode Input Voltage (V)

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

s, Offset Currents (nA)

Representative Part

TA= +125°C

VDD = 5.5V

IOS

-2.5

-2.0

-1.5

-1.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Input Bias

Common Mode Input Voltage (V)

1000

om (

=18V

VDD = 5.5V

100

eadr

100

ltage

VDD –V

put Vo

OL –

Out

0.1 1 10

Output Current Magnitude (mA)

(mV)

VDD –V

room

VDD = 5.5V

t Hea

Outp

DD = 1.8V

VOL –V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

FIGURE 2-29: Output Short Circuit Current

vs. Power Supply Voltage.

FIGURE 2-30: Supply Current vs. Power

Supply Voltage.

FIGURE 2-31: Supply Current vs. Common

Mode Input Voltage.

-10

ort Circuit Current (mA)

+125°C

+85°C

+25°C

-40°C

-50

-40

-30

-20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Output Sho

Power Supply Voltage (V)

400

500

600

700

800

900

1000

1100

ply Current (μA)

+125°C

+85°C

+25°C

100

200

300

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Sup

Power Supply Voltage (V)

-40°C

1000

1100

800

900

μA)

VDD = 5.5V

600

700

rrent (

VDD = 1.8V

400

500

ply C

200

300

Sup

100

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

2.2 Frequency Response

FIGURE 2-32: CMRR vs. Frequency.

FIGURE 2-33: PSRR vs. Frequency.

FIGURE 2-34: Normalized Open-Loop

Gain vs. Frequency.

FIGURE 2-35: Nor mal ized Gain B an dwi dth

Product and Phase Margin vs. Ambient

Temperature.

FIGURE 2-36: Closed-Loop Output

Impedance vs. Frequency.

FIGURE 2-37: Gain Peaking vs.

Normalized Capacitive Load.

100

CMRR (dB)

MIN

VDD = 5.5V

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

MIN

GMIN = 2

GMIN = 5

GMIN = 10

GMIN = 100

1k 10k 100k 1M

110

120

VDD = 5.5V

100

(dB)

PSR

GMIN = 1

GMIN = 2

MIN

= 5

MIN

GMIN = 10

GMIN = 100

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

1k 10k 100k 1M

-90

-60

100

120

150

-120

p Gai

(°)

p Gai

(dB)



AOL/GMIN

210

-180

150

en-Lo

MIN

en-Lo

| AOL/GMIN |

-240

210

ed O

se; A

ed O

ude;

-300

-270

-40

-20

rmali

agni

GMIN = 1

GMIN = 2

-360

-330

-80

-60

MIN

GMIN = 10

GMIN = 100

1.E+4 1.E+5 1.E+6 1.E+7

Frequency (Hz)

10k 100k 1M 10M

140

150

0.45

0.50

)

120

130

035

0.40

°)

dwit

(MHz

)

100

110

120

025

0.30

rgin (

in Ba

P/G

GMIN = 1

MIN

= 2

GBWP

100

0.20

ase M

zed G

; GB

MIN

GMIN = 5

GMIN = 10

GMIN = 100

GBWP

0.10

0.15

ormal

roduc

0.00

0.05

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

1.E+04

10k

peda

MIN

= 1 to 10

1.E+03

put I

)

MIN

1E+02

p Ou

(

100

GMIN = 100

E+02

ed-Lo

100

1E+01

Clo

GDM/GMIN = 1

E+01

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

1k 10k 100k 1M 10M

MIN

GMIN = 10

MIN

= 2

= 5

= 10

GDM = 20

= 50

ing (d

= 100

n Pea

GMIN = 100

GDM = 200

= 500

Gai

1.E+1 1.E+2 1.E+3

Normalized Capacitive Load; C

MIN

) (F)

10p 100p 1n

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

2.3 Noise

FIGURE 2-38: Normalized Input Noise

Voltage Density vs. Frequency.

FIGURE 2-39: Normalized Input Noise

Voltage Density vs. Input Common Mode

Voltage, with f = 100 Hz.

FIGURE 2-40: Normalized Input Noise

Voltage Density vs. Input Common Mode

Voltage, with f = 10 kHz.

FIGURE 2-41: Normalized Input Noise

Voltage vs. Time, with GMIN = 1 to 10.

FIGURE 2-42: Normalized Input Noise

Voltage vs. Time, with GMIN = 100.

1000

RTO

100

Volt

Hz)

100μ

t Nois

GMIN = 100

d Inp

y; G

maliz

Densi

1μ

GMIN = 10

GMIN = 5

MIN

0.1

100n

MIN

GMIN = 1

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6

Frequency (Hz)

0.1 100 1k1 10 100k 1M10k

Voltag



Hz)

= 100

Noise

(μV/



VDD = 1.8V

VDD = 5.5V

MIN

100

GMIN = 10

GMIN = 5

MIN

Input

;

MIN

GMIN = 1

alized

nsity

;

Nor

f = 100 Hz

RTO

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

4.0

3.0

Voltag



Hz)

2.5

Noise

(μV/



VDD = 1.8V

VDD = 5.5V

GMIN = 100

GMIN = 10

MIN

= 5

1.5

Input

;

MIN

GMIN = 2

GMIN = 1

1.0

alized

nsity

;

0.0

Nor

f = 10 kHz

RTO

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

0.4

0.5

Representative Part

MIN

= 1 to 10

Analog NPBW = 0.1 Hz

Sam

le Rate = 4 SPS

0.3

oise;

)

MIN

RTO

0.1

nput

) (mV

)

-0.1

lized I

MIN

(

-0.3

-0.2

Norm

-0.5

-0.4

0 5 10 15 20 25 30 35

Time (min)

2.0

Representative Part

MIN

= 100

Analog NPBW = 0.1 Hz

Sam

le Rate = 4 SPS

1.0

oise;

)

MIN

RTO

0.5

nput

) (mV

)

-0.5

lized I

MIN

(

-1.0

Norm

-2.0

-1.5

0 5 10 15 20 25 30 35

Time (min)

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

2.4 Time Response

FIGURE 2-43: Small Signal Step

Response.

FIGURE 2-44: Large Signal Step

Response.

FIGURE 2-45: Slew Rate vs. Ambient

Temperature.

FIGURE 2-46: Maximum Output Voltage

Swing vs. Frequency.

FIGURE 2-47: Common Mode Input

Overdrive Recovery Time vs. Normalized Gain.

FIGURE 2-48: Differential Input Overdrive

Recovery Time vs. Normalized Gain.

)

VDD = 5.5V

GDM = GMIN

V/div

)

RF+ RG= 10 k

e (10

MIN

=1to10

Voltag

MIN

GMIN = 100

utput

0 2 4 6 8 10 12 14 16 18 20

Time (μs)

5.0

5.5

)

VDD = 5.5V

= G

MIN

4.0

4.5

V/div

)

MIN

RF+ RG= 10 k

3.0

3.5

(10

2.0

2.5

oltag

GMIN = 1 to 10

GMIN = 100

1.0

1.5

utput

0.0

0.5

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Time (μs)

)

e (V/μ

1t 10

=55V

w Ra

MIN =

GMIN = 100

VDD = 1.8V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

ingge Sw

VDD = 5.5V

t Volta

-P

)

VDD = 1.8V

Outpu

GMIN = 1 to 10

GMIN = 100

imum

1.E+4 1.E+5 1.E+6

Frequency (Hz)

10k 100k 1M

1000

)

GDMVDM = ±1V

100

Volta

IRC

(μ

= 5.5V

100

Mode

very;

VDD = 1.8V

mmo

e Rec

ut C

erdri

GMIN = 100

GMIN = 1

GMIN = 10

1 10 100

Normalized Gain; G

MIN

1000

)

100

Volt

IRD

(μ

5.5V

100

l Mod

very;

VDD = 1.8V

5.5V

renti

e Rec

ut Diff

erdri

GMIN = 100

GMIN = 1

GMIN = 10

1 10 100

Normalized Gain; G

MIN

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

FIGURE 2-49: Output Overdrive Recovery

Time vs. Normalized Gain.

FIGURE 2-50: The MCP6N11 Shows No

Phase Reversal vs. Common Mode Input

Overdrive, w ith VDD =5.5V.

FIGURE 2-51: The MC P6N11 Shows N o

Phase Reversal vs. Differential Input Overdrive,

with VDD =5.5V.

100

1000

t Overdrive Recovery;

(μs)

GMIN = 10

GDM = 2GMIN

VREF = 0.75VDD

GMIN = 1

VDD = 1.8V

VDD = 5.5V

1 10 100

Outpu

Normalized Gain; G

MIN

GMIN = 100

VDD = 5.5V

0.1V

VCM

Outp

0.1V

f = 10 kHz

Mode

s (V)

mmon

oltag

ut Co

OUT,

MIN =

VOUT, GMIN = 100

-1

0 102030405060708090100

Time (μs)

VDD = 5.5V VIP

es (V)

Volta

VOUT, GMIN = 1

VOUT, GMIN = 100

-1

utput

-2

put,

-4

-3

VIM

0 102030405060708090100

Time (μs)

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

2.5 Enable/Calibration and POR Responses

FIGURE 2-52: EN/CAL and Output V oltage

vs. Time, with VDD =1.8V.

FIGURE 2-53: EN/CAL and Output V olt age

vs. Time, with VDD =5.5V

FIGURE 2-54: EN/CAL Hysteresis vs.

Ambient Temperature.

FIGURE 2-55: EN/CAL Turn On Time vs.

Ambient Temp eratu re .

FIGURE 2-56: Power Supply On and Off

and Output Voltage vs. Time.

FIGURE 2-57: POR Trip Vo ltages and

Hysteresis vs. Temperature.

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

, Output Voltage (V)

VDD = 1.8V

VL= 0V

INA

turns off

Calibration

Starts INA

turns on

-0.2

0.0

0.2

0.4

0 102030405060708090100

EN/CAL

Time (ms)

EN/CAL VOUT

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

, Output Voltage (V)

VDD = 5.5V

VL= 0V

INA

turns off

Calibration

Starts INA

turns on

-0.5

0.0

0.5

1.0

1.5

0 102030405060708090100

EN/CAL

Time (ms)

EN/CAL VOUT

0.55

0.60

0.45

0.50

s (V)

VDD = 5.5V

030

0.35

0.40

teresi

020

0.25

L Hy

0.10

0.15

EN/C

VDD = 1.8V

0.00

0.05

0.10

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

;

(

VDD = 5.5V

Time

;

VDD = 1.8V

urn O

CAL T

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

1.6

1.8

(V)

VL= 0V

1.4

oltag

1.0

tput

0.6

ply, O

VDD VOUT

0.2

0.4

r Sup

Off

-0.2

0.0

Pow

Calibrating

Off

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (s)

006

0.08

0.10

0.12

0.14

0.16

0.18

1.2

1.3

1.4

1.5

1.6

1.7

Hysteresis (V)

Trip Voltages (V)

VPRH –V

PRL

VPRH

0.00

0.02

0.04

0.8

0.9

1.0

-50 -25 0 25 50 75 100 125

POR

Ambient Temperature (°C)

VPRL

MCP6N11

Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =V

DD, VCM = VDD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.

FIGURE 2-58: Quiescent Current in

Shutdown vs. Power Supply Voltage. FIGURE 2-59: Output Leakage Current vs.

Output Voltage.

0.0

nt;

EN/CAL = 0V

-0.5

Curr

-1.0

uppl

-1.5

ower

(

-2.0

ative

+125°C

+85

-2.5

Neg

+85

+25°C

-40°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

1.E-07

)

EN/CAL = 0V

= 5.5V

100n

1.E-08

ent (

+125°C

10n

1.E-09

e Cur

+85°C

1.E-10

eaka

100p

1.E-11

tput

10p

1.E-12

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Output Voltage (V)

MCP6N11

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

3.1 Analog Signal Inputs

The non-inverting and inverting inputs (VIP

, and VIM)

are high-impedance CMOS inputs with low bias

currents.

3.2 Analog Feedback Input

The analog feedback input (VFG) is the inverting input

of the second input stage. The external feedback

components (RF and RG) are connected to this pin. It is

a high-impedance CMOS input with low bias current.

3.3 Analog Reference Input

The analog reference input (VREF) is the non-inverting

input of the second input stage; it shifts VOUT to its

desired range. The external gain resistor (RG) is

connected to this pin. It is a high-impedance CMOS

input with low bias current.

3.4 Analog Output

The analog output (VOUT) is a low-impedance voltage

output. It represents the differential input voltage

(VDM =V

IP –V

IM), with gain G

DM and is shifted by

VREF

. The external feedback resistor (RF) is connected

to this pin.

3.5 Power Supply Pins

The positive power supply (VDD) is 1.8V to 5.5V higher

than the negative power supply (VSS). For normal

operation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply; VDD will

need bypass capacitors.

3.6 Digital Enable and VOS Calibration

Input

This input (EN/CAL) is a CMOS, Schmitt-triggered

input that controls the active, low power and VOS

calibration modes of operation. When this pin goes low,

the part is placed into a low power mode and the output

is high-Z. When this pin goes high, the amplifier’s input

offset voltage is corrected by the calibration circuitry,

then the output is re-connected to the VOUT pin, which

becomes low impedance, and the part resumes normal

operation.

3.7 Exposed Thermal Pad (EP)

There is an internal connection between the Exposed

Thermal Pad (EP) and the VSS pin; they must be

connected to the same potential on the Printed Circuit

Board (PCB).

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (θJA).

TABLE 3-1: PIN FUNCTION TABLE

MCP6N11

Symbol Description

SOIC TDFN

11 V

FG Feedback Input

22 V

IM Inverting Input

33 V

IP Non-inverting Input

44 V

SS Negative Power Supply

55 V

REF Reference Input

66 V

OUT Output

77 V

DD Positive Power Supply

88 EN/CAL Enable/VOS Calibrate Digital Input

— 9 EP Exposed Thermal Pad (EP); must be connected to VSS

MCP6N11

NOTES:

MCP6N11

4.0 APPLICATIONS

The MCP6N11 instrumentation amplifier (INA) is

manufactured using Microchip’s state of the art CMOS

process. It is low cost, low power and high speed,

making it ideal for battery-powered applications.

4.1 Basic Performance

4.1.1 STANDARD CIRCUIT

Figure 4-1 shows the standard circuit configuration for

these INAs. When the inputs and output are in their

specified ranges, the output voltage is approximately:

EQUATION 4-1:

FIGURE 4-1: Standard Circuit.

For normal operation, keep:

•V

, VIM, VREF and VFG between VIVL and VIVH

•V

IP – VIM (i.e., VDM) between VDML and VDMH

•V

OUT between VOL and VOH

4.1.2 ARCHITECTURE

Figure 4-2 shows the block diagram for these INAs.

FIGURE 4-2: MCP6N11 Block Diagram.

The input offset voltage (VOS) is corrected by the

voltage VTR. Each time a VOS Calibration event occurs,

VTR is updated to the best value (at that moment).

These events are triggered by either powering up

(monitored by the POR) or by toggling the EN/CAL pin

high. The current out of GM3 (I3) is constant and very

small (assumed to be zero in the following discussion).

The input signal is applied to GM1. Equation 4-2 shows

the relationships between the input voltages (VIP and

VIM) and the common mode and differential voltages

(VCM and VDM).

EQUATION 4-2:

The negative feedback loop includes GM2, RM4, RF and

. These blocks set the DC open-loop gain (AOL) and

the nominal differential gain (GDM):

EQUATION 4-3:

AOL is very high, so I4 is very small and I1 + I2 ≈ 0. This

makes the differential inputs to GM1 and GM2 equal in

magnitude and opposite in polarity. Ideally, this gives:

EQUATION 4-4:

For an ideal part, changing VCM, VSS or VDD produces

no change in VOUT. VREF shifts VOUT as needed.

The different GMIN options change GM1, GM2 and the

internal compensation capacitor. This results in the

performance trade-offs shown in Tab le 1.

VOUT ≈VREF +G

DMVDM

Where:

GDM =1+R

F/R

VOUT

VIP

VDD

VIM

VREF

VFG

MCP6N11

RFVFG

VOUT

Low Power

VSS

VDD

EN/CAL

VOUT

VOS Calibration

VREF

RM4

GM2 Σ

VREF

GM3

VTR

VIP

VIM

GM1

VIP

VIM

POR

VIP VCM VDM 2

⁄

VIM VCM VDM 2

⁄

–=

VCM VIP VIM

+()2

⁄

VDM VIP VIM

–=

AOL GM2RM4

GDM 1R

FRG

⁄

VFG VREF

–()VDM

VOUT VDMGDM VREF

MCP6N11

4.1.3 DC ERRORS

Section 1.5 “Explanation of DC Error Specs”

defines some of the DC error specifications. These

errors are internal to the INA, and can be summarized

as follows:

EQUATION 4-5:

The non-linearity specs (INLCM and INLDM) describe

errors that are non-linear functions of VCM and VDM,

respectively. They give the maximum excursion from

linear response over the entire common mode and

differential ranges.

The input bias current and offset current specs (IB and

IOS), together with a circuit’s external input resistances,

give an additional DC error. Figure 4-3 shows the

resistors that set the DC bias point.

FIGURE 4-3: DC Bias Resistors.

The resistors at the main input (RIP and RIM) and its

input bias currents (IBP and IBM) give the following

changes in the INA’s bias voltages:

EQUATION 4-6:

The best design results when RIP and RIM are equal

and small:

EQUATION 4-7:

The resistors at the feedback input (RR, RF and RG)

and its input bias currents (IBR and IBF) give the

following changes in the INA’s bias voltages:

EQUATION 4-8:

The best design results when GDMRR and RF are equal

and small:

EQUATION 4-9:

Where:

VOUT VREF GDM 1g

+()VDM

VED

+()+=

DM 1g

+()VE

+()+

Where:

PSRR, CMRR and AOL are in units of V/V

TA is in units of °C

VEVOS

VDD

VSS

–

PSRR

---------------------------------

VCM

CMRR

-----------------

VREF

CMRR

-----------------+++=

VOUT

AOL

-----------------

VOS

-------------

⋅

VED INLDM VDMH VDML

–()

≤

VEINLCM VIVH VIVL

–()

≤

VOUT

VIP

VDD

VIM

VREF

RIP

RIM

IBP

IBM VFG

IBF

IBR

MCP6N11

Where:

CMRR is in units of V/V

VIP IBPRIP

–IB

–IOS

--------–

⎝⎠

⎛⎞

RIP

VIM IBMRIM

–IB

–IOS

--------+

⎝⎠

⎛⎞

RIM

VCM

VIP

VIM

---------------------------------=

I–BRIP RIM

-------------------------

⎝⎠

⎛⎞

I–OS

-----------R–IP RIM

----------------------------

⎝⎠

⎛⎞

VDM

VIP

VIM

–=

BR–IP RIM

+()

IOS

--------R

IP RIM

+()–=

VOUT GDM

VDM

VCM

CMRR

-----------------+

⎝⎠

⎛⎞

Where:

RIP =RIM

RTOL = tolerance of RIP and RIM

VOUT GDM

VDM

≈

DM 2IB

RTOL IOS

–±()RIP

≈

Where:

IB2 meets the IB spec, but is not equal to IB

IOS2 meets the IOS spec, but is not equal to IOS

ΔVREF IBRRR

–IB2

–IOS2

----------–

⎝⎠

⎛⎞

ΔVFG ΔVREF ,≈

ΔVOUT IB2RFGDMRR

–()

IOS2

---------- RFGDMRR

+()+≈

due to high AOL

Where:

GDMRR=RF

RTOL = tolerance of RR, RF and RG

ΔVOUT 2IB2εRTOL IOS2

+()±()RF

≈

MCP6N11

4.1.4 AC PERFORMANCE

The bandwidth of these amplifiers depends on GDM

and GMIN:

EQUATION 4-10:

The bandwidth at the maximum output swing is called

the Full Power Bandwidth (fFPBW). It is limited by the

Slew Rate (SR) for many amplifiers, but is close to fBW

for these parts:

EQUATION 4-11:

CMRR is constant from DC to about 1 kHz.

4.1.5 NOISE PERFORMANCE

As shown in Figures 2-41 and 2-42, the 1/f noise

causes an apparent wander in the DC output voltage.

Changing the measurement time or bandwidth has little

effect on this noise.

We recommend re-calibrating VOS periodically, to

reduce 1/f noise wander. For example, VOS could be

re-calibrated at least once every 15 minutes; more

often when temperature or VDD change significantly.

4.2 Functional Blocks

4.2.1 RAIL-TO-RAIL INPUTS

Each input stage uses one PMOS differential pair at the

input. The output of each differential pair is processed

using current mode circuitry. The inputs show no

crossover distortion vs. common mode voltage.

With this topology, the inputs (VIP and VIM) operate

normally down to VSS – 0.2V and up to VDD + 0.15V at

room temperature (see Figure 2-11). The input offset

voltage (VOS) is measured at VCM =V

SS –0.2V and

VDD + 0.15V (at +25°C), to ensure proper operation.

4.2.1.1 Phase Reversal

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figures 2-18 and 2-50 show an input voltage

exceeding both supplies with no phase inversion.

The input devices also do not exhibit phase inversion

when the differential input voltage exceeds its limits;

see Figures 2-22 and 2-51.

4.2.1.2 Input Voltage Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the voltages at

the input pins (see Section 1.1 “Absolute Maximum

Ratings †”). This requirement is independent of the

current limits discussed later on.

The ESD protection on the inputs can be depicted as

shown in Figure 4-4. This structure was chosen to

protect the input transistors against many (but not all)

overvoltage conditions, and to minimize input bias

current (IB).

FIGURE 4-4: Simplified Analog Input ESD

Structures.

Where:

fBW = -3 dB bandwidth

fGBWP = Gain bandwidth product

fBW fGBWP

GDM

---------------≈

0.50 MHz()GMIN GDM

⁄

(),

≈

0.35 MHz()GMIN GDM

⁄

(),

≈

GMIN =1, …,10

GMIN =100

Where:

VO= Maximum output voltage swing

≈VOH –V

fFPBW SR

----------

≈

fBW

≈, for these parts

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIP

VSS

Input

Stage

Bond

Pad VIM

INA Input

MCP6N11

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below VSS. They also

clamp any voltages that go too far above VDD; their

breakdown voltage is high enough to allow normal

operation, but not low enough to protect against slow

overvoltage (beyond VDD) events. Very fast ESD

events (that meet the spec) are limited so that damage

does not occur.

In some applications, it may be necessary to prevent

excessive voltages from reaching the op amp inputs.

Figure 4-5 shows one approach to protecting these

inputs. D1 and D2 may be small signal silicon diodes,

Schottky diodes for lower clamping voltages or diode-

connected FETs for low leakage.

FIGURE 4-5: Protecting the Analog Inputs

Against High Voltages.

4.2.1.3 Input Current Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

into the input pins (see Section 1.1 “Absolute Maxi-

mum Ratings †”). This requirement is independent of

the voltage limits previously discussed.

Figure 4-6 shows one approach to protecting these

inputs. The resistors R1 and R2 limit the possible

current in or out of the input pins (and into D1 and D2).

The diode currents will dump onto VDD.

FIGURE 4-6: Protecting the Analog Inputs

Against High Currents.

It is also possible to connect the diodes to the left of the

resistor R1 and R2. In this case, the currents through

the diodes D1 and D2 need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIP and VIM)

should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the common

mode voltage (VCM) is below ground (VSS); see

Figure 2-25.

4.2.1.4 Input Voltage Ranges

Figure 4-7 shows possible input voltage values

(VSS = 0V). Lines with a slope of +1 have constant VDM

(e.g., the VDM = 0 line). Lines with a slope of -1 have

constant VCM (e.g., the VCM =V

DD/2 line).

For normal operation, VIP and VIM must be kept within

the region surrounded by the thick blue lines. The

horizontal and vertical blue lines show the limits on the

individual inputs. The blue lines with a slope of +1 show

the limits on VDM; the larger GMIN is, the closer they are

to the VDM = 0 line.

The input voltage range specs (VIVL and VIVH) change

with the supply voltages (VSS and VDD, respectively).

The differential input range specs (VDML and VDMH)

change with minimum gain (GMIN). Temperature also

affects these specs.

To take full advantage of VDML and VDMH, set VREF

(see Figure 1-6 and Figure 1-7) so that the output

(VOUT) is centered between the supplies (VSS and

VDD).

FIGURE 4-7: Input Voltage Ranges.

VDD

MCP6N11

min(R1,R

2)>VSS –min(V

1,V

2mA

VDD

MCP6N11

min(R1,R

2)>max(V1,V

2)–V

2mA

VIP

VIM

VDM =0

VIVH

VIVL

VIVH

VIVL

VDM=VDMH

VCM =V

DD/2

VDM =VDMH

VDD

MCP6N11

4.2.2 ENABLE/VOS CALIBRATION

(EN/CAL)

These parts have a Normal mode, a Low Power mode

and a VOS Calibration mode.

When the EN/CAL pin is high and the internal POR

(with delay) indicates that power is good, the part

operates in its Normal mode.

When the EN/CAL pin is low, the part operates in its

Low Power mode. The quiescent current (at VSS) drops

to -2.5 µA (typical), the amplifier output is put into a

high-impedance state. Signals at the input pins can

feed through to the output pin.

When the EN/CAL pin goes high and the internal POR

(with delay) indicates that power is good, the amplifier

internally corrects its input offset voltage (VOS) with the

internal common mode voltage at mid-supply (VDD/2)

and the output tri-stated (after tOFF). Once VOS Calibra-

tion is completed, the amplifier is enabled and normal

operation resumes.

The EN/CAL pin does not operate normally when left

floating. Either drive it with a logic output, or tie it high

so that the part is always on.

4.2.3 POR WITH DELAY

The internal POR makes sure that the input offset

voltage (VOS) is calibrated whenever the supply

voltage goes from low voltage (< VPRL) to high voltage

(> VPRH). This prevents corruption of the VOS trim reg-

isters after a low-power event.

After the POR goes high, the internal circuitry adds a

fixed delay (tPLH), before telling the VOS Calibration

circuitry (see Figure 4-2) to start. If the EN/CAL pin is

toggled during this time, the fixed delay is restarted

(takes an additional time tPLH).

4.2.4 PARITY DETECTOR

A parity error detector monitors the memory contents

for any corruption. In the rare event that a parity error is

detected (e.g., corruption from an alpha particle), a

POR event is automatically triggered. This will cause

the input offset voltage to be re-corrected, and the op

amp will not return to normal operation for a period of

time (the POR turn on time, tPLH).

4.2.5 RAIL-TO-RAIL OUTPUT

The Minimum Output Voltage (VOL) and Maximum

Output Voltage (VOH) specs describe the widest output

swing that can be achieved under the specified load

conditions.

The output can also be limited when VIP or VIM exceeds

VIVL or VIVH, or when VDM exceeds VDML or VDMH.

4.3 Applications Tips

4.3.1 MINIMUM STABLE GAIN

There are different options for different Minimum Stable

Gains (1, 2, 5, 10 and 100 V/V; see Tab l e 1- 1). The

differential gain (GDM) needs to be greater than or

equal to GMIN in order to maintain stability.

Picking a part with higher GMIN has the advantages of

lower Input Noise Voltage Density (eni), lower Input

Offset Voltage (VOS) and increased Gain Bandwidth

Product (GBWP); see Table 1. The Differential Input

Voltage Range (VDMR) is lower for higher GMIN, but the

output voltage range would limit VDMR anyway, when

GDM ≥2.

4.3.2 CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for amplifiers. As the load capacitance

increases, the feedback loop’s phase margin

decreases, and the closed-loop bandwidth is reduced.

This produces gain peaking in the frequency response,

with overshoot and ringing in the step response. Lower

gains (GDM) exhibit greater sensitivity to capacitive

loads.

When driving large capacitive loads with these

instrumentation amps (e.g., > 100 pF), a small series

resistor at the output (RISO in Figure 4-8) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-8: Output Resistor, RISO

stabilizes large capacitive load s.

Figure 4-9 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CLGMIN/GDM), where

GDM is the circuit’s differential gain (1 + RF/R

G) and

GMIN is the minimum stable gain.

RISO

VOUT

VDD

VREF

VFG

MCP6N11

FIGURE 4-9: Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double check the

resulting frequency response peaking and step

response overshoot on the bench. Modify RISO’s value

until the response is reasonable.

4.3.3 GAIN RESISTORS

Figure 4-10 shows a simple gain circuit with the INA’s

input capacitances at the feedback inputs (VREF and

VFG). These capacitances interact with RG and RF to

modify the gain at high frequencies. The equivalent

capacitance acting in parallel to RG is CG=C

DM +C

plus any board capacitance in parallel to RG

. CG will

cause an increase in GDM at high frequencies, which

reduces the phase margin of the feedback loop (i.e.,

reduce the feedback loop's stability).

FIGURE 4-10: Simple Ga in C irc uit with

Parasiti c Capacitances.

In this data sheet, RF+R

G=10kΩ for most gains (0Ω

for GDM = 1); see Table 1-6. This choice gives good

Phase Margin. In general, RF (Figure 4-10) needs to

meet the following limits to maintain stability:

EQUATION 4-12:

4.3.4 SUPPLY BYPASS

With these INAs, the power supply pin (VDD for single

supply) should have a local bypass capacitor (i.e.,

0.01 µF to 0.1 µF) within 2 mm for good high frequency

performance. Surface mount, multilayer ceramic

capacitors, or their equivalent, should be used.

These INAs require a bulk capacitor (i.e., 1.0 µF or

larger) within 100 mm, to provide large, slow currents.

This bulk capacitor can be shared with other nearby

analog parts as long as crosstalk through the supplies

does not prove to be a problem.

1.E+03

1.E+04

mmended R

ISO

()

10k

1.E+02

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06

Rec

Normalized Load Capacitance;

MIN

(F)

100

100p 1n 10n 100n 1μ

GMIN = 1 to 10

GMIN = 100

VOUT

VDD

VREF

VFG

CDM

CCM

MCP6N11

Where:

α≤0.25

GDM ≥GMIN

fGBWP = Gain Bandwidth Product

CG=CDM +CCM + (PCB stray capacitance)

RF0=

For GDM =1:

GDM

fGBWPCG

------------------------------

For GDM >1:

MCP6N11

4.4 Typical Applications

4.4.1 HIGH INPUT IMPEDANCE

DIFFERENCE AMPLIFIER

Figure 4-11 shows the MCP6N11 used as a difference

amplifier. The inputs are high impedance and give good

CMRR performance.

FIGURE 4-11: Difference Amp lifier.

4.4.2 DIFFERENCE AMPLIFIER FOR

VERY LARGE COMMON MODE

SIGNALS

Figure 4-12 shows the MCP6N11 INA used as a

difference amplifier for signals with a very large

common mode component. The input resistor dividers

(R1 and R2) ensure that the voltages at the INA’s inputs

are within their range of normal operation. The

capacitors C1, with the parasitic capacitances C2 (the

resistors’ parasitic capacitance plus the INA’s input

common mode capacitance, CCM), set the same

division ratio, so that high-frequency signals (e.g., a

step in voltage) have the same gain. Select the INA

gain to compensate for R1 and R2’s attenuation. Select

R1 and R2’s tolerances for good CMRR.

FIGURE 4-12: Difference Amp li fie r with

Very Large Common Mode Component.

4.4.3 HIGH SIDE CURRENT DETECTOR

Figure 4-13 shows the MCP6N11 INA used as to detect

and amplify the high side current in a battery powered

design. The INA gain is set at 21 V/V, so VOUT changes

210 mV for every 1 mA of IDD current. The best GMIN

option to pick would be a gain of 10 (MCP6N11-010).

FIGURE 4-13: High Side Current Detector.

4.4.4 WHEATSTONE BRIDGE

Figure 4-14 shows the MCP6N11 single

instrumentation amp used to condition the signal from

a Wheatstone bridge (e.g., strain gage). The overall

INA gain is set at 201 V/V. The best GMIN option to pick,

for this gain, is 100 V/V (MCP6N11-100).

FIGURE 4-14: Wheatstone Bridge

Amplifier.

VOUT

VIP

VDD

VIM

VREF

VFG

MCP6N11

VOUT

VDD

VREF

VFG

C1C2

MCP6N11

IDD =(VBAT –V

DD)

(10

)

=(VOUT –V

REF)

(10

) (21.0 V/V)

10 Ω

VDD

IDD

VBAT

+1.8V

+5.5V

VOUT

VREF

VFG

200 kΩ

10 kΩ

MCP6N11

VOUT

VREF

VFG

200 kΩ

1kΩ

VDD

RW1

RW2

RW1 U1

MCP6N11

NOTES:

MCP6N11

5.0 DESIGN AIDS

Microchip provides the basic design aids needed for

the MCP6N11 instrumentation amplifiers.

5.1 Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps efficiently identify

Microchip devices that fit a particular design

requirement. Available at no cost from the Microchip

website at www.microchip.com/maps, the MAPS is an

overall selection tool for Microchip’s product portfolio

that includes Analog, Memory, MCUs and DSCs. Using

this tool, a customer can define a filter to sort features

for a parametric search of devices and export

side-by-side technical comparison reports. Helpful links

are also provided for Data sheets, Purchase and

Sampling of Microchip parts.

5.2 Analog Demonstration Board

Microchip offers a broad spectrum of Analog

Demonstration and Evaluation Boards that are

designed to help customers achieve faster time

to market. For a complete listing of these boards

and their corresponding user’s guides and technical

information, visit the Microchip web site at

www.microchip.com/analog tools.

5.3 Application Notes

The following Microchip Application Notes are

available on the Microchip web site at www.microchip.

com/appnotes and are recommended as supplemental

reference resources.

•AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

•AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

•AN1228: “Op Amp Precis ion Design: Random

Noise”, DS01228

Some of these application notes, and others, are listed

in the design guide:

•“Signal Chain Design Guide”, DS21825

MCP6N11

NOTES:

MCP6N11

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

8-Lead SOIC (150 mil) (MCP6N11)

8-Lead TDFN (2×3) (MCP6N11) Example

Device Code

MCP6N11-001 AAQ

MCP6N11-002 AAR

MCP6N11-005 AAS

MCP6N11-010 AAT

MCP6N11-100 AAU

Note: Applies to 8-Lead 2x3 TDFN

Note: The example is for a

MCP6N11-001 part.

NNN

6N11001E

SN^^ 1121

256

AAQ

121

Example

MCP6N11

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6N11

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6N11

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MCP6N11

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6N11

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6N11

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MCP6N11

NOTES:

MCP6N11

APPENDIX A: REVISION HISTORY

Revision A (October 2011)

• Original Release of this Document.

MCP6N11

NOTES:

MCP6N11

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6N11 Single Instrumentation Amplifier

MCP6N11T Single Instrumentation Amplifier

(Tape and Reel)

Gain Option: 001 = Minimum gain of 1 V/V

002 = Minimum gain of 2 V/V

005 = Minimum gain of 5 V/V

010 = Minimum gain of 10 V/V

100 = Minimum gain of 100 V/V

Temperature Range: E = -40°C to +125°C

Package: MNY = 2×3 TDFN, 8-lead *

SN = Plastic SOIC (150mil Body), 8-lead

* Y = nickel palladium gold manufacturing designator. Only

available on the TDFN package.

Examples:

a) MCP6N11T-001E/MNY: Tape and Reel,

Minimum gain = 1,

Extended temperature,

8LD 2×3 TDFN.

b) MCP6N11-002E/SN: Minimum gain = 2,

Extended temperature,

8LD SOIC.

PART NO. –X /XX

PackageGain

Option

Device

Temperature

Range

MCP6N11

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-685-3

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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