MC10172 Dual Binary to 1-4 Decoder (High) The MC10172 is a binary-coded 2 line to dual 4 line decoder with selected outputs high. With either E0 or E1 low, the corresponding selected 4 outputs are low. The common enable E, when high, forces all outputs low. * PD = 325 mW typ/pkg (No Load) * tpd = 4.0 ns typ * tr, tf = 2.0 ns typ (20%-80%) http://onsemi.com MARKING DIAGRAMS 16 LOGIC DIAGRAM E0 14 CDIP-16 L SUFFIX CASE 620 10 Q0 3 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 MC10172L AWLYYWW 1 11 Q0 2 16 12 Q0 1 PDIP-16 P SUFFIX CASE 648 A9 13 Q0 0 MC10172P AWLYYWW 1 3 Q1 3 1 B7 4 Q1 2 PLCC-20 FN SUFFIX CASE 775 5 Q1 1 E 15 10172 AWLYYWW 6 Q1 0 E1 2 A WL YY WW DIP PIN ASSIGNMENT VCC1 1 16 VCC2 E1 2 15 E Q13 3 14 E0 Q12 4 13 Q00 Q11 5 12 Q01 Q10 6 11 Q02 B 7 10 Q03 VEE 8 9 A = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC10172L CDIP-16 25 Units / Rail MC10172P PDIP-16 25 Units / Rail MC10172FN PLCC-20 46 Units / Rail Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). TRUTH TABLE E L L L L L L H E1 H H H H L H X E0 H H H H H L X A L L H H L L X B L H L H L L X Q10 H L L L L H L Q11 L H L L L L L Semiconductor Components Industries, LLC, 2000 March, 2000 - Rev. 6 Q12 L L H L L L L Q13 L L L H L L L Q00 H L L L H L L Q01 L H L L L L L 1 Q02 L L H L L L L Q03 L L L H L L L Publication Order Number: MC10172/D MC10172 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Symbol Pin Under Test Power Supply Drain Current IE 8 85 IinH 14 350 Input Current -30C Min +25C Max Min +85C Max Unit 77 85 mAdc 220 220 Adc Typ Max 65 Adc IinL 14 0.5 VOH 6 13 -1.060 -1.060 -0.890 -0.890 -0.960 -0.960 -0.810 -0.810 -0.890 -0.890 -0.700 -0.700 Vdc Logic 0 VOL 13 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc Logic 1 VOHA 6 13 -1.080 -1.080 Logic 0 VOLA 6 13 Output Voltage Logic 1 Output Voltage Threshold Voltage Threshold Voltage 0.5 Min 0.3 -0.980 -0.980 -0.910 -0.910 -1.655 -1.655 -1.630 -1.630 Vdc -1.595 -1.595 Switching Times (50 Load) Propagation Delay Vdc ns t7+6- t7-6+ t7+13- t7-13+ 6 6 13 13 1.5 1.5 1.5 1.5 6.2 6.2 6.2 6.2 1.5 1.5 1.5 1.5 4.0 4.0 4.0 4.0 6.0 6.0 6.0 6.0 1.5 1.5 1.5 1.5 6.4 6.4 6.4 6.4 Rise Time (20 to 80%) t6+ t13+ 6 13 1.0 1.0 3.3 3.3 1.1 1.1 2.0 2.0 3.3 3.3 1.1 1.1 3.4 3.4 Fall Time (20 to 80%) t6- t13- 6 13 1.0 1.0 3.3 3.3 1.1 1.1 2.0 2.0 3.3 3.3 1.1 1.1 3.4 3.4 http://onsemi.com 2 MC10172 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE Symbol Power Supply Drain Current Input Current -30C -0.890 -1.890 -1.205 -1.500 -5.2 +25C -0.810 -1.850 -1.105 -1.475 -5.2 +85C -0.700 -1.825 -1.035 -1.440 -5.2 Pin Under Test IE 8 IinH 14 IinL 14 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VOH 6 13 2 14 Output Voltage Logic 0 VOL 13 15 Threshold Voltage Logic 1 VOHA 6 13 Threshold Voltage Logic 0 VOLA 6 13 Propagation Delay VEE (VCC) Gnd 8 1, 16 8 1, 16 8 1, 16 8 8 1, 16 1, 16 8 1, 16 8 8 1, 16 1, 16 7 9 8 8 1, 16 1, 16 VILAmax 14 Logic 1 (50 Load) VIHAmin 14 Output Voltage Switching Times VILmin 2,7,9,14 2 14 2,9,14 2,7,14 +1.11V +0.31V Pulse In Pulse Out -3.2 V +2.0 V t7+6- t7-6+ t7+13- t7-13+ 6 6 13 13 2 2 14 14 9, 14 9, 14 2, 9 2,9 7 7 7 7 6 6 13 13 8 8 8 8 1, 16 1, 16 1, 16 1, 16 Rise Time (20 to 80%) t6+ t13+ 6 13 2 14 9, 14 2, 9 7 7 6 13 8 8 1, 16 1, 16 Fall Time (20 to 80%) t6- t13- 6 13 2 14 9, 14 2, 9 7 7 6 13 8 8 1, 16 1, 16 Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 3 MC10172 PACKAGE DIMENSIONS PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C 0.007 (0.180) M T L-M B Y BRK -N- U N S 0.007 (0.180) M T L-M S S N S D -L- -M- Z W 20 D 1 G1 X V 0.010 (0.250) S T L-M S N S VIEW D-D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S 0.007 (0.180) M T L-M H S N S Z K1 K C E F 0.007 (0.180) M T L-M S 0.004 (0.100) G J -T- VIEW S G1 0.010 (0.250) S T L-M S N S VIEW S SEATING PLANE NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 --- N S MC10172 PACKAGE DIMENSIONS -A- 16 9 1 8 -B- CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N -T- K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M -A- 9 1 8 B F C L S -T- SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M http://onsemi.com 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC10172 Notes http://onsemi.com 6 MC10172 Notes http://onsemi.com 7 MC10172 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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