C712 SICON 53mm Inverter Thyristor POWER 2000V / 1125A Operation to 3 kHz The C712 Reverse Blocking Thyristor has proven performance in forced commutation circuits operating to 3KHZ. It is recommended for use with an anti-parallel soft recovery diode as utilized in most PWM nverters. The C712 internal gate structure has an involute, interdigitated gate pattern needed to enhance the initially turned on area for high di/dt capability. FEATURES: 0 Proven mature design. 0 Low switching loss at high frequency. 0 60 us maximum turn-off time with feedback diode. G Involute, interdigitate gate. 0 Narrow pulse capability for PWM inverter commutation socket. MAXIMUM ALLOWABLE RATINGS AMPLIFYING GATE 4 ) THYRISTOR (SCR) PRESSPAK Vorm/Vram! Voam/Vram! TRANSIENT PEAK REVERSE TYPE REPETITIVE REPETITIVE VOLTAGE, Vasu! Ty = -40C to +425C Ty = OC to +125C Ty = 40C to +125C C712L 2000 Volts 2100 Volts 2100 Volts C712PT 1900 2000 2000 C712PN 1800 1900 1900 C712PS 1700 1800 1800 C712PM 1600 1700 1700 C712PE 500 1600 1600 Consult factory for lower sated voltage devices. Peak One-Cycle Surge On-State Current, Ipgpy (8.3 msec)... 2 ee eee eee ee eter e eens 20,000 Amperes Maximum Rate-of-Rise of Anode Current Turn-On Interval (Switching From 1200 Volis).........-.--+- 800 A/ysec Repetitive di/dt Rating? ... 2... 0. eee eee cece ane eee eee ee ewe eer eeeeeee 200 Ajpsec P| (for fusing} (at 8.3 milliseconds)... 2.0.00 cee eee eee eee e eee ee eer esees 1,660,000 Ampere? Seconds Peak Gate Power Dissipation, Poy. .---- eee eee cee eee ener eee eee neees eee 100 Watts Average Gate Power Dissipation, Pacay) -- me ce ee er etre rete t eee rete ntaneseernees 5 Watts Peak Reverse Gate Voltage, Varo -+ ++ cece nec e cee ewe ce ee teeta teen eee eeeaeetsenres 20 Volis Storage and Operating Temperature, Tetg and Ty 2... 022 et cee ee eee nn eens see deaaene Refer Above Mounting Force Required... 00. ee cee eee ecw ee tet eee meet eee ee ne eteees 000 Lb. + 1000 0 Lb. 22.2 KN + 4.4 --0 KN NOTES: 110 mscc voltage sincwave. 2di/di rating established in accordance with EIA-NEMA Standard RS-397, Section 5.2.2. This di/dt is in addition to the discharge ofa 0.25 pf, 20 ohm snubber circuit in parallel with the DUT. 1 of 4 175 Great Valley Pkwy., Malvern, PA 19355, USA C712 REV A. 10/11/2001CHARACTERISTICS TEST SYMBOL] MIN. TYP. MAX, UNITS TEST CONDITIONS Peak Reverse and On- Iprm - 20 60 mA [| Ty = +125C, V = Vorw = Var State Blocking Current and InRM Effective Thermal Resist- Ric - - 023 | C/Watt | Doubie-Side Cooled (DC) ance, Junction-to-Case Critical Linear Rate-of-Rise | dv/dt $00 - - Viusec | T; = +125C, Voz = .80 Rated Vea of Forward Blocking Voit- Gate Open, age {Higher values may cause device switching) Delay Time tg ~ 1.5 - psec Switching from 140 Volts, 20 Volt, 10 Ohm Gat: 0.5 psec Rise Time, Ty = 25C Gate Pulse Width ~ _~ 10 usec T; = 25C Necessary To Trigger Gate Trigger Current Iot _ 120 J - mAdc | Tc = 25C, Vp = 10 Vdc, Ry = 3 Ohms daot for operational use} 5.0 30 - Te = +125C, Vp = .5 x Rated, Ry = 1000 Obms Gate Trigger Voltage Vot - 3.0 - Vde Te = OC to 125C, Vp = 10 Vde, Ry = {not for operational use) 3 Ohms Peak On-State Voltage Vrm - - 1.45 Volts | To = +125C, Ty = 1000 Amps. Peak Duty Cycle = 0.01% Conventional Circuit Com- tg - - 55 psec} (1) Te = +125C mutated Turn-Off Time (2) Ir = 1000A (With Reverse Voltage} (3) Va # 50 Volts (4) 80% Vprn Reapplied (5) Rate-of-Rise of Forward Blocking Volt- age = A400V /us (6) Gate Bias = Open During Turn-Off Interval = 0 Volts, 100 Ohms (7) Duty Cycle < 0.01% Conventional Circuit Com- ta - 55 60 psec 7 (3) Te = +125C mutated Turn-Off Time (2) Iz = 1000A (With Feedback Diode) (3) Vp = 2 Volts Min. (4) 80% Vorm Reapplied (5) Rate-of-Rise of Forward Blocking Volt- age = 400V /us (6) Gate Bias = Open During Tum-Off Interval (7) Duty Cycle 0.01% ig OR-STATE CURREHT (KA) 2 i (712 | Tj = 1259 5 Lf 3 yo 2 7 1 0.5 | 1 2 3 a $ 6 ON-STATE OLTAGE {VOLTS} FORWARD CONDUCTION CHARACTERISTIC ON-STATE T REG (AMPS) OR Gp (MICROCOULOMBS) 2 of 4 175 Great Valley Pkwy., Malvern, PA 19355, USA 8 8 di/dt { AMPS/asec) RECOVERED CHARGE [125c) C712 REV A. 10/11/2001SINUSOIDAL CURRENT WAVEFORMS TRAPEZOIDAL CURRENT WAVEFORMS 10 Te = 65C 6 z ; 3 3 = 4 s e = 3 a g i pe 2 # = $0 100 200 400 GOOBOOROO 2000 0006000B0C0I0D00 PULSE BASE WIDTH ( SEC) PULSE BASE WIDTH Lu sac) MAXIMUM ALLOWABLE PEAK ON-STATE CURRENT MAXIMUM ALLOWABLE PEAK ON-STATE CURRENT VS. PULSE WIDTH [Tg = 65C) FOR TRAPEZOIDAL CURRENT WAVEFORMS FOR (Te = 650C) (di/dt = 100A/us) 202 WATT/SEC/ PEAK FORWARD CURRENT ([KILOAMPS} FORWARD CURAENT [KILOAMPS) + rv PULSE BASE (SEC) PULSE BASE WIDTH (nSEC) ENERGY PER PULSE FOR SINUSOIDAL PULSES ENERGY PER PULSE FOR TRAPEZOIDAL CURRENT WAVEFORMS ay (asus) av,/dt (V/us} at 100 300 500 Tao 1000 10 166 481 -654 .743 816 NOTES: l- On-state ratings and energies do not : i nclude reverse recovery as a bypass jade is anticipated. A snubber 30 2267 2502 774 2335 27 discharge of 50A is included. 50 +168 503 -812 1.02 1.2 2- If no bypass diode js used with this thyristor, the additional switching . . . -07 29 energy can besignificant. Refer to 79 168 Rascal = sd the table on the left. 100 ~168 +505 839 4.11 1.37 3- The full cycle average power dissipation is the sum of the on-state and recovery s00 169 508 rr 1.18 1.60 energies times the operating frequency, accordingly MAXIMUM RECOVERY ENERGY (JOULES) Par = Ce tan). f AV WF R* dip/at \ t XN Le dy p/dt Trec > % _ __ 1600V 3 of 4 175 Great Valley Pkwy. Malvern, PA 19355, USA C712 REV A. 10/11/2001x wu } ry ~ MAXIMUM -s BYNAMIC 2 A Pa se 3 a = a w 8 w 3 gS Pus on > =e Bs #9 ww a MINIMUM 3 STATIC 1 2 3 INSTANTANEOUS CURRENT (A) - GATE SUPPLY Igg OR THYRISTOR GATE Ick = R 8 Be z TRANSIENT THERMAL IMPEDANCE *C/WATT ot o2 O 06 08 1 4 6 61 TIME SECONDS THYRISTOR GATE IMPESANCE This 1s enhanced by fast rising gate voltage, increasing anode bias and temperature. evelt is shown at a minimum for de voltage, zero bias and low temperature. sitt is shown at a maximum for operating bias and recoemended gate vas GATE SUPPLY .-Load Ifnes (A) and (B) are operational, however, {A) Is recommended to achieve maximum life at full di/dt rating and snubber discharge. The short circuit current rise time should be approximately Q.5us and the duration longer than the expected delay me. MINIMUM ACCEPTABLE GATE CURRENT .aThe intersection of the load line and the gate characteristic (encircled) indicates the desired value of gate current needed to flow into the thyristor. . NOTES: i. Add .006C W to account for both case to dissipator interfaces when properly mounted: e.g., Rays = 029C W. See Mounting Instructions. 2. DC Thermal Impedance is based on average full cycle junction temperature. Instantaneous junction temperature may be calculated using the following modifications: end of conducting portion of cycle ~ 120 sq. wave add .0025C W along entire curve 180 sq. wave add .0018C W along entire curve 180 sine wave add .0010C W along entire curve @ end of cycle any wave, subtract .001C along entire curve. 3. Ask for genera! mounting instructions. OUTLINE DRAWING CATHODE ANODE ELEMENTARY DIAG TERM D BE PLATED SURF Kk =-- 80 Inches Millimeters Symbol Notes Min. Max. Min. Max. A 0.200 0.246 5.08 6.10 J oB 0.140 3.56 -- c 16.000 | 20.000 | 406.40 | 508.00 oD 1.700 1.900 43.18 48.26 gE 2.960 _ 75.18 F 1.000 4.070 25.40 27.18 ==24 TERMINAL @) WHITE WIRE G _ _ _. _ 2 fG SEE NOTE 1 <I yenminay G) RED wih SEE NOTE oa H 005 | 067 | 0.13 | 1.70 RR oN J 0.136 | 0.146 3.45 371 TERM @ "90" PLATED t | K .070 100 1.78 | 254 SURF t<< Vv L 2500 | 63.50 t . M 030 _ 0.76 _ . Anode-Cathode Pole Faces @) @ Nickel Plated Copper. NOLES . Mating Surface Requirement TIR =.0005 mch Finish 32. . Mounting Force. $000-6000 Lb., 22.4-26.7 KN. |. Electrical Insulation. Glazed Ceramic. Creepage | in. (25.4mm). Sinke a ee ee 4 of 4 175 Great Valley Pkwy., Malvern, PA 19355, USA 1. Contour and orientation of term lugs is undefined. 2. Glazed ceramic insulator wath | O0inch (275.40 mnt) surface creepage, min $, in. (15.9mm) . Gate Leads @ G@ 18 in. #22 Terminated with #8 Ring Terminal. Cathode Wire-Red. Gate Wire-White. C712 REV A. 10/11/2001