MCP6402T-H/SN - MICROCHIP TECHNOLOGY

MCP6401/1R/1U/2/4/6/7/9

Features

• Low Quiescent Current: 45 µA (typical)

• Gain Bandwidth Product: 1 MHz (typical)

• Rail-to-Rail Input and Output

• Supply Voltage Range: 1.8V to 6.0V

• Unity Gain Stable

• Extended Temperature Ranges:

- -40°C to +125°C (E temp)

- -40°C to +150°C (H temp)

• No Phase Reve rsal

Applications

• Port ab le Equi pm ent

• Battery Powered System

• Medical Instrumentation

• Automo tive Elec tronics

• Data Acquisition Equipment

• Sensor C onditioning

• Analog Active Filters

Design Aids

• SPICE Ma cr o Models

•FilterLab

® Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Typical Application

Description

The Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 family of operational

amplifiers (op amps) has low quiescent current

(45 µA, typical) and rail-to-rail input and output

operation. This family is unity gain stable and has a

gain bandwidth product of 1 MHz (typical). These

device s ope rate with a powe r supply vo lt age of 1.8V to

6.0V. These features make the family of op amps well

suited for si ngl e-s upp ly, battery-powered appli ca tio ns .

The MC P6401/1R/1U /2/4/6/7 /9 family is design ed with

Microchip’s advanced CMOS process and offered in

single, dual and quad packages. The devices are

availa ble i n tw o ext ended tempe rature ranges (E te mp

and H temp) with different package types, which

makes them well-suited for automotiv e and industrial

applications.

VOUT

VIN

Precision Half-Wave Rectifier

MCP6401

1 MHz, 45 µA Op A mps

MCP6401/1R/1U/2/4/6/7/9

E Temp Package Types H Temp Package Types

VSS

VIN–

VIN+

VDD

VOUT

SOT-23-5

VDD

VIN–

VIN+

VSS

VOUT

SC70-5, SOT-23-5

VDD

VOUT

VIN–

VSS

VIN+

SOT-23-5

MCP6401 MCP6401R

MCP6401U

MCP6402

SOIC

VINA+

VINA–

VSS

VOUTA VDD

VOUTB

VINB–

VINB+

MCP6404

VINA+

VINA–

VSS

VOUTA

VDD

VOUTD

VIND–

VIND+

OUTB

VINB–

VINB+VINC+

VINC–

VOUTC

SOIC, TSSOP

MCP6402

VINA+

VINA–

VSS

VINB–

5VINB+

VOUTA

VDD

2x3 TDFN

VOUTB

* Includes Exposed Thermal Pad (EP); see Table 3-1.

E temp: -40°C to +125°C

VDD

VIN–VIN+

VSS

VOUT

SOT-23-5

MCP6401 MCP6402

SOIC

VINA+

VINA–

VSS

VOUTA VDD

VOUTB

VINB–

VINB+

MCP6404

VINA+

VINA–

VSS

VOUTA

VDD

VOUTD

VIND–

VIND+

OUTB

VINB–

VINB+VINC+

VINC–

VOUTC

SOIC

VDD

VIN–

VIN+

VSS

VOUT

SOT-23-5

MCP6406

MCP6407

SOIC

VINA+

VINA–

VSS

VOUTA VDD

VOUTB

VINB–

VINB+

MCP6409

VINA+

VINA–

VSS

VOUTA

VDD

VOUTD

VIND–

VIND+

OUTB

VINB–

VINB+V

INC+

VINC–

VOUTC

SOIC

H temp: -40°C to +150°C

MCP6401/1R/1U/2/4/6/7/9

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD – VSS ........................................................................7.0V

Current at Input Pins.....................................................±2 mA

Analog Inputs (VIN+, VIN-)†† .......... VSS – 1.0V to VDD + 1.0V

All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V

Difference Input Voltage ...................................... | VDD – VSS|

Output Short-Circuit Current ............................. ...Continuous

Current at Output and Supply Pins ............................±30 mA

Storage Temperature ....................................-65°C to +150°C

Maximum Junction Temperature (TJ)..........................+155°C

ESD Protection on All Pins (HBM; MM; CDM)....≥ 4 kV; 300V ,

1500V

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operatio n of the devic e at those or an y other con ditions

above those indicated in the operational listings of this

specification is not implied. Exposure to maximum rat-

ing conditions for extended periods may affect device

reliability.

†† See Section 4.1.2 “Input Voltage Limits”.

1.2 MCP6401/1R/1U/2/4 Electrical Specifications

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise ind ic ated , TA= +25°C, VDD = +1.8v to +6.0v, VSS =GND,

VCM =V

DD/2, VOUT ≈VDD/2, VL=V

DDD/2 and RL= 100 kΩ to VL (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Temp Parts

(Note 1)Conditions

Input Offset

Input Offset Voltage VOS -4.5 ±0.8 +4.5 mV E, H VCM = VSS

— ±1.0 — mV +125°C E

— ±1.5 — mV +150°C H

Input Offset Drift with

Temperature ΔVOS/ΔTA— ±2.0 — µV/°C -40°C

+125°C

CM = VSS

— ±2.5 — µV/°C -40°C

+150°C

Power Supply

Rejection Ratio PSRR 63 78 — dB E, H VCM = VSS

— 75 — dB +125°C E

— 73 — dB +150°C H

Input Bias Current and Impedance

Input Bias Current IB— 1 100 pA E, H

—30—pA+85°CE, H

— 800 — pA +125°C E

— 7 — nA +150°C H

Input Offset Current IOS —1—pA E, H

—5—pA+85°CE, H

— 20 — pA +125°C E

— 45 — pA +150°C H

Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands

for the one whose operating temperature range is from -40°C to +150°C.

2: Figure 2-14 shows how V CMR changes across temperature.

MCP6401/1R/1U/2/4/6/7/9

Comm on Mo de Inpu t

Impedance ZCM —10

13||6 — Ω||pF E, H

Differential Input

Impedance ZDIFF —10

13||6 — Ω||pF E, H

Common Mode

Comm on Mo de Inpu t

Vo lt age Range

(Note 2)

VCMR VSS-0.20 — VDD+0.20 V E, H VDD = 1.8V

VSS-0.05 — VDD+0.05 V +125°C E

VSS —V

DD V +150°C H

VSS-0.30 — VDD+0.30 V E, H VDD = 6.0V

VSS-0.15 — VDD+0.15 V +125°C E

VSS-0.10 — VDD+0.10 V +150°C H

Comm on Mo de

Rejection Ratio CMRR 56 71 — dB E, H VCM = -0.2V to 2.0V,

VDD = 1.8V

— 68 — dB +125°C E VCM = -0.05V to 1.85V,

VDD = 1.8V

— 65 — dB +150°C H VCM = 0V to 1.8V,

VDD = 1.8V

63 78 — dB E, H VCM = -0.3V to 6.3V,

VDD = 6.0V

— 76 — dB +125°C E VCM = -0.15V to 6.15V,

VDD = 6.0V

— 75 — dB +150°C H VCM = -0.1V to 6.1V,

VDD = 6.0V

Open-Loop Gain

DC Open-Loop Gain

(Large Signal) AOL 90 110 — dB E , H VOUT = 0.3V to VDD-

0.3V,

VCM = VSS

— 105 — dB +125°C E

— 100 — dB +150°C H

Output

High-Level Output

Voltage VOH 1.790 1.792 — V E, H VDD = 1.8V

RL = 10 kΩ

0.5V input overdrive

— 1.788 — V +125°C E

— 1.785 — V +150°C H

5.980 5.985 — V E, H VDD = 6.0V

RL = 10 kΩ

0.5V input overdrive

— 5.980 — V +125°C E

— 5.975 — V +150°C H

Low-Level Output

Voltage VOL — 0.008 0.010 V E, H VDD = 1.8V

RL = 10 kΩ

0.5V input overdrive

— 0.012 — V +125°C E

— 0.015 — V +150°C H

— 0.015 0.020 V E , H VDD = 6.0V

RL = 10 kΩ

0.5V input overdrive

— 0.020 — V +125°C E

— 0.025 — V +150°C H

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise ind ic ated , TA= +25°C, VDD = +1.8v to +6.0v, VSS =GND,

VCM =V

DD/2, VOUT ≈VDD/2, VL=V

DDD/2 and RL= 100 kΩ to VL (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Temp Parts

(Note 1)Conditions

Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands

for the one whose operating temperature range is from -40°C to +150°C.

2: Figure 2-14 shows how V CMR changes across temperature.

MCP6401/1R/1U/2/4/6/7/9

Output Short -Circ uit

Current ISC —±5—mA E, HV

DD = 1.8V

—±15—mA E, HV

DD = 6.0V

Power Supply

Supply Voltage VDD 1.8 — 6.0 V E, H

Quiescent Current

per Amplifier IQ20 45 70 µA E, H I O = 0, VDD = 5.0V

VCM = 0.2VDD

— 55 — µA +125°C E

— 60 — µA +150°C H

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise ind ic ated , TA= +25°C, VDD = +1.8v to +6.0v, VSS =GND,

VCM =V

DD/2, VOUT ≈VDD/2, VL=V

DDD/2 and RL= 100 kΩ to VL (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Temp Parts

(Note 1)Conditions

Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands

for the one whose operating temperature range is from -40°C to +150°C.

2: Figure 2-14 shows how V CMR changes across temperature.

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unles s otherw ise in dicated, TA= +25°C, V DD = +1.8 to +6.0V, VSS = GND, VCM =V

DD/2,

VOUT ≈VDD/2, VL=V

DD/2 , RL= 100 kΩ to VL and CL= 60 pF (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Parts Conditions

AC Response

Gain Bandwidth Product GBWP — 1 — MHz E, H

Phase Margin PM — 65 — ° E, H G = +1 V/V

Slew Rate SR — 0 .5 — V/µs E, H

Noise

Input Noise Voltage Eni — 3.6 — µVp-p E, H f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni —28—nV/√Hz E, H f = 1 kHz

Input Noise Current Density ini —0.6—fA/√Hz E, H f = 1 kHz

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Operati ng Tempe ratu re Ra nge TA-40 — +125 °C E temp par ts (Note 1)

TA-40 — +150 °C H temp parts (Note 1)

Storage Temperature Range TA-65 — +155 °C

Thermal Package Resistances

Thermal Resistance, 5L-SC70 θJA —331—°C/W

Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W

Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W

Thermal Resistance, 8L-2x3 TDFN θJA —52.5—°C/W

Thermal Resistance, 14L-SOIC θJA —95.3—°C/W

Thermal Resistance, 14L-TSSOP θJA —100—°C/W

Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +155°C.

MCP6401/1R/1U/2/4/6/7/9

1.3 MCP6406/7/9 Electrical Specifications

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise ind ic ated , TA= +25°C, VDD = +1.8V to +6.0V, VSS = GND,

VCM =V

DD/2, VOUT »V

DD/2, VL=V

DD/2 and RL= 100 kΩ to VL (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Temp Parts

(Note 1)Conditions

Input Offset

Input Offset Voltage VOS -4.5 — +4.5 mV E, H VCM = VSS

-5.0 ±1.0 +5.0 mV +125°C E

-5.5 ±1.5 +5.5 mV +150°C H

Input Offset Drift

with Temperature ΔVOS/DTA— ±2.0 — µV/°C -40°C

+125°C

CM = VSS

— ±2.5 — µV/°C -40°C

+150°C

Power Supply

Rejection Ratio PSRR 63 78 — dB E, H VCM = VSS

60 75 — dB +125°C E

58 73 — dB +150°C H

Input Bias Current and Impedance

Input Bias Current IB—±1100pA E, H

— 30 — pA +85°C E, H

— 800 2000 pA +125°C E

— 7 12 nA +150°C H

Input Offset Current IOS —1—pA E, H

— 5 — pA +85°C E, H

— 20 — pA +125°C E

— 45 — pA +150°C H

Comm on Mo de

Input Impedance ZCM —10

13||6 — Ω||pF E, H

Differential Input

Impedance ZDIFF —10

13||6 — Ω||pF E, H

Common Mode

Comm on Mo de

Input V oltage Range

(Note 2)

VCMR VSS-0.20 — VDD+0.20 V E, H VDD = 1.8V

VSS-0.05 — VDD+0.05 V +125°C E

VSS —V

DD V +150°C H

VSS-0.30 — VDD+0.30 V E, H VDD = 6.0V

VSS-0.15 — VDD+0.15 V +125°C E

VSS-0.10 — VDD+0.10 V +150°C H

Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands

for the one whose operating temperature range is from -40°C to +150°C.

2: Figure 2-14 shows how VCMR changes across temperature.

MCP6401/1R/1U/2/4/6/7/9

Comm on Mo de

Rejection Ratio CMRR 56 71 — dB E, H VCM = -0.2V to 2.0V,

VDD = 1.8V

53 68 — dB +125°C E VCM = -0.05V to 1.85V,

VDD = 1.8V

50 65 — dB +150°C H VCM = 0V to 1.8V,

VDD = 1.8V

63 78 — dB E, H VCM = -0.3V to 6.3V,

VDD = 6.0V

61 76 — dB +125°C E VCM = -0.15V to 6.15V,

VDD = 6.0V

60 75 — dB +150°C H VCM = -0.1V to 6.1V,

VDD = 6.0V

Open-Loop Gain

DC Open-Loop Gain

(Large Signal) AOL 90 110 — dB E, H VOUT = 0.3V to

VDD-0.3V, VCM = VSS

88 105 — dB +125°C E

85 100 — dB +150°C H

Output

High-Level Output

Voltage VOH 1.790 1.792 — V E, H V DD = 1.8V

RL = 10 kΩ

0.5V input overdrive

1.785 1.788 — V +125°C E

1.782 1.785 — V +150°C H

5.980 5.985 — V E, H VDD = 6.0V

RL = 10 kΩ

0.5V input overdrive

5.970 5.980 — V +125°C E

5.965 5.975 — V +150°C H

Low-Level Output

Voltage VOL — 0.008 0.010 V E, H VDD = 1.8V

RL = 10 kΩ

0.5V input overdrive

— 0.012 0.015 V +125°C E

— 0.015 0.018 V +150°C H

— 0.015 0.020 V E, H VDD = 6.0V

RL = 10 kΩ

0.5V input overdrive

— 0.020 0.030 V +125°C E

— 0.025 0.035 V +150°C H

Output Shor t-Circuit

Current ISC —±5—mA E, HV

DD = 1.8V

—±15—mA E, HV

DD = 6.0V

Power Supply

Supply Voltage VDD 1.8 — 6.0 V E, H

Quiescent Current

per Amplifier IQ20 45 70 µA E, H IO = 0, VDD = 5.0V

VCM = 0.2VDD

30 55 80 µA +125°C E

35 60 90 µA +150°C H

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise ind ic ated , TA= +25°C, VDD = +1.8V to +6.0V, VSS = GND,

VCM =V

DD/2, VOUT »V

DD/2, VL=V

DD/2 and RL= 100 kΩ to VL (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Temp Parts

(Note 1)Conditions

Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands

for the one whose operating temperature range is from -40°C to +150°C.

2: Figure 2-14 shows how VCMR changes across temperature.

MCP6401/1R/1U/2/4/6/7/9

TEMPERATURE SPECIFICATIONS

1.4 Test Circuits

The circuit used for most DC and AC tests is shown in

Figure 1-1. This circuit can independently set VCM and

VOUT; see Equation 1-1. Note that VCM is not the

circuit ’s Comm on Mode volt age ((VP+V

M)/2), and that

VOST includes VOS plus t h e e ffects ( on t he i n pu t o ffset

error, VOST) of temperature, CMRR, PSRR and AOL.

EQUATION 1-1:

FIGURE 1-1: AC and DC Test Circuit for

Most Spe cific ations.

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: U nless other wise indi cat ed, TA = +25°C, V DD = +1.8 to +6.0V, VSS = GND, VCM = V DD/2,

VOUT ≈VDD/2, VL = VDD/2 , RL = 100 k Ω to VL and CL = 60 pF (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Part Conditions

AC Response

Gain Bandwidth Product GBWP — 1 — MHz E, H

Phase Margin PM — 65 — ° E, H G = +1 V/V

Slew Rate SR — 0 .5 — V/µs E, H

Noise

Input Noise Voltage Eni — 3.6 — µVp-p E, H f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni —28—nV/√Hz E, H f = 1 kHz

Input Noise Current Density ini —0.6—fA/√Hz E, H f = 1 kHz

Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to + 6.0V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Operati ng Tempe ratu re Ra nge T A-40 — +125 ° C E temp parts (Note 1)

TA-40 — +150 °C H temp parts (Note 1)

Storage Temperature Range TA-65 — +155 °C

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23 θJA —220.7—°C/W

Thermal Resistance, 8L-SOIC θJA —149.5—°C/W

Thermal Resistance, 14L-SOIC θJA — 95.3 — °C/W

Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +155°C.

GDM RFRG

⁄

VCM VPVDD 2

⁄

+()2

⁄

VOUT VDD 2

⁄

()VPVM

–()VOST 1G

+()++=

Where:

GDM = Differential Mode Gain (V/V)

VCM = Op Amp’s Common Mode

Input Voltage (V)

VOST = Op Amp’s Total Input Offset

Voltage (mV)

VOST VIN– VIN+

–=

VDD

RGRF

VOUT

CB2

CB1

100 kΩ

RGRF

VDD/2

VP100 kΩ

100 kΩ

60 pF

100 kΩ

1µF100 nF

VIN–

VIN+

6.8 pF

MCP640x

MCP6401/1R/1U/2/4/6/7/9

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

FIGURE 2-1: Input Offset V o ltage.

FIGURE 2-2: Input Offset V o ltage.

FIGURE 2-3: Input Offset V o ltage.

FIGURE 2-4: Input Offset Voltage Drift.

FIGURE 2-5: Input Offset Voltage Drift.

FIGURE 2-6: Input Offset Voltage vs.

Common Mode Input Voltage with VDD = 6.0V.

Note: The gra phs and tab les prov ided fo llow ing this note are a sta tistic al sum mary b ased on a limit ed numb er of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

12%

15%

18%

21%

24%

-5-4-3-2-1012345

Input Offset Voltage (mV)

Percentage of Occurences

1760 Samples

VCM = VSS

12%

15%

18%

21%

24%

-5-4-3-2-1012345

Percentage of Occurences

Input Offset Voltage (mV)

1200 Samples

VCM = VSS

TA= +125ºC

12%

15%

18%

21%

24%

-5-4-3-2-1012345

Percentage of Occurences

Input Offset Voltage (mV)

1200 Samples

VCM = VSS

TA= +150ºC

10%

15%

20%

25%

30%

35%

40%

45%

-10-8-6-4-20246810

Percentage of Occurences

Input Offset Voltage Drift (μV/°C)

1760 Samples

VCM = VSS

TA= -40°C to +125°C

10%

15%

20%

25%

30%

35%

40%

45%

50%

-10-8-6-4-20246810

Percentage of Occurences

Input Offset Voltage Drift (μV/°C)

1200 Samples

VCM = VSS

TA= -40°C to +150°C

-1000

-800

-600

-400

-200

200

400

600

800

1000

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Input Offset Voltage (μV)

Common Mode Input Voltage (V)

TA= +150°C

TA= +125°C

TA= +85°C

VDD = 6.0V

Representative

Part

TA= +25°C

TA= -40°C

MCP6401/1R/1U/2/4/6/7/9

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

FIGURE 2-7: Input Offset Voltage vs.

Common Mode Input Voltage with VDD = 1.8V.

FIGURE 2-8: Input Offset Voltage vs.

Output Voltage.

FIGURE 2-9: Input Offset Voltage vs.

Power Supply Voltage.

FIGURE 2-10: Input Noise Voltage Density

vs. Frequency.

FIGURE 2-11: Input Noise V oltage Density

vs. Common Mode Input Voltage.

FIGURE 2-12: CMRR, PSRR vs.

Frequency.

-800

-600

-400

-200

200

400

600

800

1000

1200

1400

-0.5

-0.3

-0.1

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

2.3

Input Offset Voltage (μV)

Common Mode Input Voltage (V)

TA= +150°C

TA= +125°C

TA= +85°C

TA= +25°C

TA= -40°C

VDD = 1.8V

Representative

Part

-1000

-750

-500

-250

250

500

750

1000

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Output Voltage (V)

Input Offset Voltage (µV)

VDD = 6.0V

VDD = 1.8V

Representative Part

-500

-400

-300

-200

-100

100

200

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

Input Offset Voltage (μV)

Power Supply Voltage (V)

TA= +150°C

TA= +125°C Representative Part

TA= +85°C

TA= +25°C

TA= -40°C

100

1,000

0.1 1 10 100 1000 10000 100000

Frequency (Hz)

Input Noise Voltage Density

(nV/√Hz)

0.1 1 10 100 1k 10k 100k

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Common Mode Input Voltage (V)

Input Noise Voltage Density

(nV/√Hz)

f = 1 kHz

VDD = 6.0 V

100

10 100 1000 10000 100000 1000000

Frequency (Hz)

CMRR, PSRR (dB)

10 100 1k 10k 100k 1M

CMRR

PSRR+

PSRR-

Representative Part

MCP6401/1R/1U/2/4/6/7/9

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

FIGURE 2-13: CMRR, PSRR vs. Ambient

Temperature.

FIGURE 2-14: Common Mode Input

Voltage Range Limits vs. Ambient Temperature.

FIGURE 2-15: Input Bias, Offset Current

vs. Ambient Temperature.

FIGURE 2-16: Input Bias Current vs.

Common Mode Input Voltage.

FIGURE 2-17: Quiescent Current vs.

Ambient Temp eratu re .

FIGURE 2-18: Quiescent Current vs.

Power Supply Voltage.

-50 -25 0 25 50 75 100 125 150

CMRR,PSRR (dB)

Ambient Temperature (°C)

PSRR (VDD = 1.8V to 6.0V)

CMRR (VDD = 6.0V)

CMRR (VDD = 1.8V)

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

-50 -25 0 25 50 75 100 125 150

Common Mode Input Voltage

Range Limits (V)

Ambient Temperature (°C)

VCMR_L -V

SS @ VDD = 1.8V

VOL -V

SS @ VDD = 6.0V

VCMR_H -V

OH @ VDD = 6.0V

@ VDD = 1.8V

100

1000

10000

25 50 75 100 125 150

Input Bias Current, Input Offset

Current (pA)

Ambient Temperature (°C)

ut Bias Current

Input Offset Current

VDD = 6.0V

100

1000

10000

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Input Bias Current (pA)

Common Mode Input Voltage (V)

VDD = 6.0V

TA= +125°C

TA= +85°C

TA= +150°C

-50 -25 0 25 50 75 100 125 150

Quiescent Current

(μA/Amplifier)

Ambient Temperature (°C)

VCM = 0.2VDD

VDD = 6.0V

VDD = 5.0V

VDD = 1.8V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

Quiescent Current

(μA/Amplifier)

Power Supply Voltage (V)

VCM = 0.2VDD

TA= +125°C

TA= +85°C

TA= +25°C

TA= -40°C

TA= +150°C

MCP6401/1R/1U/2/4/6/7/9

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

FIGURE 2-19: Open-Loop Gain, Phase vs.

Frequency.

FIGURE 2-20: DC Open-Loop Gain vs.

Power Supply Voltage.

FIGURE 2-21: DC Open-Loop Gain vs.

Output Voltage Headroom.

FIGURE 2-22: Gain Bandwidth Product,

Phase Margin vs. Ambient Temperature.

FIGURE 2-23: Gain Bandwidth Product,

Phase Margin vs. Ambient Temperature.

FIGURE 2-24: Output Short Circuit Current

vs. Power Supply Voltage.

-20

100

120

1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+0 4 1.0E+05 1.0E+06 1.0E+07

Frequency (Hz)

Open-Loop Gain (dB)

-210

-180

-150

-120

-90

-60

-30

Open-Loop Phase (°)

Open-Loop Gain

Open-Loop Phase

VDD = 6.0V

0.1 1 10 100 1k 10k 100k 1M 10M

100

105

110

115

120

125

130

135

140

145

150

1.52.02.53.03.54.04.55.05.56.0

Power Supply Voltage (V)

DC Open-Loop Gain (dB)

RL = 10 kΩ

VSS + 0.3V < VOUT < VDD - 0.3V

100

105

110

115

120

125

130

135

140

145

150

0.00 0.05 0.10 0.15 0.20 0.25

Output Voltage Headroom

VDD - VOH or VOL-VSS (V)

DC Open-Loop Gain (dB)

VDD = 6.0V

VDD = 1.8V

Large Signal AOL

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

-50 -25 0 25 50 75 100 125 150

Phase Margin (°)

Gain Bandwidth Product (MHz)

Temperature (°C)

Gain Bandwidth Product

Phase Margin

VDD = 6.0V

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

-50 -25 0 25 50 75 100 125 150

Phase Margin (°)

Gain Bandwidth Product (MHz)

Temperature (°C)

Gain Bandwidth Product

Phase Margin

VDD = 1.8V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Output Short Circuit Current

(mA)

Power Supply Voltage (°V)

TA= -40°C

TA= +25°C

TA= +85°C

TA= +125°C

TA= +150°C

MCP6401/1R/1U/2/4/6/7/9

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

FIGURE 2-25: Output Voltage Swing vs.

Frequency.

FIGURE 2-26: Output Voltage Headroom

vs. Output Current.

FIGURE 2-27: Output Voltage Headroom

vs. Ambient Temperature.

FIGURE 2-28: Slew Rate vs . Ambi en t

Temperature.

FIGURE 2-29: Small Signal Non-Inverting

Pulse Response.

FIGURE 2-30: Small Signal Inverting Pulse

Response.

0.1

100 1000 10000 100000 1000000

Frequency (Hz)

Output Voltage Swing (VP-P)

VDD = 1.8V

VDD = 6.0V

100 1k 10k 100k 1M

0.1

100

1000

10 100 1000 10000

Output Current (mA)

Output Voltage Headroom

(mV)

0.01 0.1 1 10

VDD - VOH @ VDD = 1.8V

VOL - VSS @ VDD = 1.8V

VDD - VOH @ VDD = 6.0V

VOL - VSS @ VDD = 6.0V

RL = 10 kΩ

-50 -25 0 25 50 75 100 125 150

Output Voltage Headroom

VDD -V

OH or VOL -V

SS (mV)

Ambient Temperature (°C)

VDD -V

OH @ VDD = 1.8V

VOL -V

SS @ VDD = 1.8V

VDD -V

OH @ VDD = 6.0V

VOL -V

SS@ VDD = 6.0V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75 100 125 150

Slew Rate (V/μs)

Temperature (°C)

Falling Edge, VDD = 6.0V

Rising Edge, VDD = 6.0V

Falling Edge, VDD = 1.8V

Rising Edge, VDD = 1.8V

Time (2 µs/div)

Output Voltage (20 mv/div)

VDD = 6.0V

G = +1 V/V

Time (2 µs/div)

Output Voltage (20 mv/div)

VDD = 6.0V

G = -1 V/V

MCP6401/1R/1U/2/4/6/7/9

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

FIGURE 2-31: Large Signal Non-Inverting

Pulse Response.

FIGURE 2-32: Large Signal Inverting Pulse

Response.

FIGURE 2-33: The

MCP6401/1R/1U/2/4/6/7/9 Shows No Phase

Reversal.

FIGURE 2-34: Closed Loop Output

Impedance vs. Frequency.

FIGURE 2-35: Measured Input Current vs.

Input Voltage (below VSS).

FIGURE 2-36: Channel-to-Channel

Separation vs. Frequency (MCP6402/4/7/9 only).

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Time (20 µs/div)

Output Voltage (V)

VDD = 6.0V

G = +1 V/V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Time (20 µs/div)

Output Voltage (V)

VDD = 6.0V

G = -1 V/V

-1.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

Time (0.1 ms/div)

Input, Output Voltages (V)

VDD = 6.0V

G = +2 V/V

VOUT

VIN

100

1000

10000

1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06

Frequency (Hz)

Closed Loop Output

Impedance ()

GN:

101 V/V

11 V/V

1 V/V

10 100 1k 10k 100k 1M

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

-IIN (A)

VIN (V)

TA= -40°C

TA= +25°C

TA= +85°C

TA= +125°C

TA= +150°C

100

100n

10n

100

110

120

130

140

150

100 1000 10000 100000

Frequency (Hz)

Channel to Channel Separation

(dB)

100 1k 10k 100k

Input Referred

MCP6401/1R/1U/2/4/6/7/9

3.0 PIN DESCRIPTIONS

Descrip tions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE 1

MCP6401 MCP6401R MCP6401U MCP6402 MCP6404 MCP6406 MCP6407 MCP6409

Symbol Description

SC70-5,

SOT-23-5 SOT-23-5 SOT-23-5 SOIC 2x3

TDFN SOIC,

TSSOP SOT-23-5 SOIC SOIC

11 41111 11V

OUT, VOUTA Analog Output (op am p A)

44 32224 22V

IN–, VINA– I nvertin g Input (op amp A)

33 13333 33V

IN+, VINA+ Non-inverting Input (op amp A)

52 58845 84V

DD Positive Power Supply

—— —555 — 5 5V

INB+ Non-inverting Input (op amp B)

—— —666 — 6 6VINB–Inverting Input (op am p B)

—— —777 — 7 7V

OUTB Analog Output (op amp B)

— — ———8 — — 8 V

OUTC Analog Output (op amp C)

— — ———9 — — 9 V

INC– Inverting Input (op amp C)

—— ———10— —10V

INC+ Non-inverting Input (op amp C)

25 244112 411V

SS Negative Power Supply

—— ———12— —12V

IND+ Non-inverting Input (op amp D)

—— ———13— —13V

IND– Inverting Input (op amp D)

—— ———14— —14V

OUTD Analog Output (op amp D)

— — — — 9 — — — — EP Exposed Thermal Pad (EP); must be

connected to VSS.

MCP6401/1R/1U/2/4/6/7/9

3.1 Analog Output (VOUT)

The output pin is low-impedance voltage source.

3.2 Analog Inputs (VIN+, VIN-)

The non-inverting and inverting inputs are high-

impedance CMOS inputs with low bias currents.

3.3 Power Supply Pin (VDD, VSS)

The pos iti ve po we r s upp ly (VDD) is 1. 8V to 6. 0V h igh er

than the negative power supply (VSS). For normal

operation, the other pins are at voltages between VSS

and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply. VDD will

need bypass capacitors.

MCP6401/1R/1U/2/4/6/7/9

4.0 APPLICATION INFORMATION

The MCP6401/1R/1U/2/4/6/7/9 family of op amps is

manufac tured using Mi crochip’ s st ate-of-the-art CMOS

process and is specifically designed for low-power,

high-precision applications.

4.1 Rail-to-Rail Input

4.1.1 PHASE REVERSAL

The MCP6401/1R/1U/2/4/6/7/9 op amps are designed

to prevent phase reversal when the input pins exceed

the supply voltages. Figure 2-33 shows the input

voltage exceeding the supply voltage with no phase

reversal.

4.1.2 INPUT VOLTAGE LIMITS

In order to prevent damage and/or improper operation

of these am plifi ers, the c ircuit mus t limit th e volt ages at

the input pins (see Section 1.1 “Absolute Maximum

Ratings †”).

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to

protect the input transistors against many (but not all)

ove r-vol tage conditions, and to minimize the input bias

current (IB).

FIGURE 4-1: Simplified Analog Input ESD

Structures.

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below VSS. They also

clamp any voltages that go well above VDD; their

breakdown voltage is high enough to allow normal

operation, but not low enough to protect against slow

over-voltage (beyond VDD) events. Very fast ESD

event s (tha t m ee t th e s pec ) a re l im ite d s o t hat dam ag e

does not occur.

In some applications, it may be necessary to prevent

excessive voltages from reaching the op amp inputs;

Figure 4-2 shows one approach to protecting these

inputs.

FIGURE 4-2: Protecting the Analog

Inputs.

A significant amount of current can flow out of the

input s when t he Common M ode volt age (VCM) is below

ground (VSS); See Figure 2-35.

4.1.3 INPUT CURRENT LIMITS

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

into the input pins (see Section 1.1 “Absolute

Maximum Ratings †”).

Figure 4-3 shows one approach to protecting these

inputs. The resistors R1 and R2 limit the possible

current s in or out of the input pin s (and the ESD dio des,

D1 and D2). The diode currents will go through either

VDD or VSS.

FIGURE 4-3: Protecting the Analog

Inputs.

4.1.4 NORMAL OPERATION

The input stage of the MCP6401/1R/1U/2/4/6/7/9 op

amps use two differential input stages in parallel. One

operates at a low Common Mode input voltage (VCM),

while the other operates at a high VCM. With this

topology, the devic e opera tes wit h a VCM up to 300 mV

above VDD and 300 mV below VSS (see Figure 2-14).

The input offset voltage is measured at VCM = VSS –

0.3V and VDD + 0.3V to ensure proper operation.

The transition between the input stages occurs when

VCM is near VDD – 1.1V (see Figures 2-6 and 2-7). For

the best distortion performance and gain linearity, with

non-inverting gains, avoid this region of operation.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage Bond

Pad VIN–

VDD

MCP640x

VOUT

V1R1

VDD

min(R1,R2)> VSS –min(V

1, V2)

2mA

V2R2

MCP640x

VOUT

min(R1,R2)> max(V1,V2)–V

2mA

MCP6401/1R/1U/2/4/6/7/9

4.2 Rail-to-Rail Output

The output voltage range of the

MCP6401/1R/1U/2/4/6/7/9 op amps is VSS +20mV

(minimum) and VDD – 20 mV (maximum) when

RL=10kΩ is connected to VDD/2 and VDD =6.0V.

Refer to Figures 2-26 and 2-27 for more information.

4.3 Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. While a unity-gain buffer (G = +1 V/V) is the

most sensitive to capacitive loads, all gains show the

same general behavior.

When driving large capacitive loads with these op

amp s (e .g., > 100 pF when G = +1 V/V), a small se rie s

resistor at the output ( RISO in Figure 4-4) improv es the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitance lo ad.

FIGURE 4-4: Output Resistor, RISO

Stabilizes Large Capacitive Loads.

Figure 4-5 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

norma l iz ed lo ad ca paci tan c e (C L/GN), where GN is the

circuit 's noise gain. For non-inverti ng gains, GN a nd the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-5: Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double-check the

resulting frequency response peaking and step

response overshoot. Modify RISO’s value until the

response is reasonable. Bench evaluation and

simulations with the MCP6401/1R/1U/2/4/6/7/9 SPICE

macro model are very helpful.

4.4 Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single-supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good hi gh freque ncy p erfor mance. It can use a bulk

capa citor (i.e., 1 µF or larger) withi n 100 mm to provid e

large, s low curr ents. This bulk c ap a ci tor can be s hare d

with oth er analog parts.

4.5 Unused Op Amps

An unused op amp in quad packages (MCP6404 or

MCP640 9) shou ld be con figured as shown in Figure 4-

6. These circuits prevent the output from toggling and

causing crosstalk. Circuit A sets the op amp at its

minimu m noi se gain. The re sisto r di vider produc es an y

desired reference voltage within the output voltage

range of the op amp, which buffers that reference

voltage. Circuit B uses the minimum number of

components and operates as a comparator, but it may

draw more current.

FIGURE 4-6: Unused Op Amps.

VIN

RISO VOUT

–

MCP640x

100

1000

10000

1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06

Normalized Load Capacitance; CL/GN (F)

Recommended R ISO (Ω)

GN:

1 V/V

2 V/V

≥ 5 V/V

VDD = 6.0 V

RL = 10 kΩ

10p 100p 1n 10n 0.1µ 1µ

VDD

VREF

VREF VDD R2

R1R2

-------------------

¼ MCP6404 (A) ¼ MCP6404 (B)

MCP6401/1R/1U/2/4/6/7/9

4.6 PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

betwee n nearby traces is 1012Ω. A 5V dif ference would

cause 5 pA of current to flow; wh ic h is greater than the

MCP6401/1R/1U/2/4/6/7/9 family’s bias current at

+25°C (±1.0 pA, typical).

The easiest way to reduce surfac e leakage is to use a

guard ring around sensitive p ins (or t r ac es) . The gua rd

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-7.

FIGURE 4-7: Example Guard Ring Layout

for Inverting Gain.

1. Non-inverting Gain and Unity-Gain Buffer:

a) Connect the non-inverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

b) Connect the guard ring to the inverting input

pin (VIN–). This b iases th e g uard ri ng to the

Common Mode input voltage.

2. Inverting Gain and Transimpedance Gain

Amplifiers (convert current to voltage, such as

photo detectors):

a) Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., VDD/2 or ground).

b) Connect the inverting pin (VIN–) to the inp ut

with a wire that does not touch the PCB

surface.

4.7 Application Circuits

4.7.1 PRECISION HALF-WAVE

RECTIFIER

The precision half-wave rectifier, which is also known

as a super diode, is a configuration obtained with an

operational amplifier in order to have a circuit behave

like an i deal diode and rec tifier . It effec tively cancels the

forward vol t ag e drop of the diod e s o t hat very low le ve l

signal s can st ill be rectifi ed with mi nimal error. This can

be useful for high-precision signal processing. The

MCP6401/1R/1U/2/4/6/7/9 op amps have high input

impedance, low input bias current and rail-to-rail

input/output, which makes this device suitable for

preci sion rec tifi er appl ic ati ons .

Figure 4-8 shows a precision half-wave rectifi er an d its

transfer characteristic. The rectifier’s input impedance

is determ ined by the inp ut resistor R1. To avoid loadin g

effect, it must be driven from a low-impedance source.

When VIN is greater than zero, D1 is OFF , D2 is ON, and

VOUT is zero. When VIN is less than zero, D1 is ON, D 2

is OFF, and VOUT is the VIN with an amplification of

-R2/R1.

The rectifi er circui t sho wn in Figure 4-8 has the benef it

that the op amp never goes in saturation, so the only

thing affecting its frequency response is the

amplification and the gain bandwidth product.

FIGURE 4-8: Prec i sion Half -Wave

Rectifier.

Guard Ring VIN–V

IN+ VSS

VOUT

VIN

VOUT

VIN

-R2/R1

Transfer Characteristic

Precision Half-Wave Rectifier

MCP6401

MCP6401/1R/1U/2/4/6/7/9

4.7.2 BATTERY CURRENT SENSING

The MCP6401/1R/1U/2/4/6/7/9 op amps’ Common

Mode Input Range, which goes 0.3V beyond both

supply rails, supports their use in high-side and low-

side battery current sensing applications. The low

quiesc ent current (45 µA, typical) help s prolo ng battery

life, and the rail-to-rail output supports detection of low

currents.

Figure 4-9 shows a high-side battery current sensor

circuit. The 10Ω resistor is sized to minimize power

losses. The battery current (IDD) through the 10Ω

resistor causes its top terminal to be more negative

than the bottom terminal. This keeps the Common

Mode input voltage of the op amp below VDD, which is

within its allowed range. The output of the op amp will

also b e bel ow VDD, which is within its Max imum Output

Volta ge Sw ing spec ifi cat ion .

FIGURE 4-9: Suppl y Curre nt Sen si ng.

4.7.3 INSTRUMENTATION AMPLIFIER

The MCP6401/1R/1U/2/4/6/7/9 op amps are well

suited for conditioning sensor signals in battery-

powered application s. Figure 4-10 shows a two op amp

instrumentation amplifier, using the MCP6402, that

works well for applications requiring rejection of

Common Mode noise at higher gains. The reference

voltage (VREF) is supplied by a low impeda nc e so urc e.

In single supply applications, VREF is typically VDD/2.

FIGURE 4-10: Two Op Amp

Instrumentation Amplifier.

VDD

IDD

100 kΩ

1MΩ

1.8V VOUT

10Ω

6.0V

IDD VDD VOUT

–

10 V/V()10

()

⋅

------------------------------------------=

To load

MCP6401

VOUT V1V2

–()1R1

------2R1

---------++

⎝⎠

⎛⎞

VREF

VREF R1R2R2R1VOUT

½ MCP6402 ½ MCP6402

MCP6401/1R/1U/2/4/6/7/9

5.0 DESIGN AIDS

Microchip provides the basic design tools needed for

the MCP6401/1R/1U/2/4/6/7/9 family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model for the

MCP6401/1R/1U/2/4/6/7/9 op amp is available on the

Microchip web site at www.microchip.com. The model

was written and tested in official Orcad (Cadence)

owned PSPICE. For other simulators, translation may

be required.

The model covers a wide aspect of the op amp's

electric al speci fication s. Not onl y does the mod el cover

voltage, current, and resistance of the op amp, but it

also covers the temperature and noise effects on the

behavior of the op amp. The model has not been

verified outside of the specification range listed in the

op amp data sheet. The model behaviors under these

conditions cannot be guaranteed to match the actual

op amp performance.

Moreover, the model is intended to be an initial design

tool. Bench testing is a very important part of any

design and cannot be replaced with simulations. Also,

simulation results using this macro model need to be

validated by comparing them to the data sheet

specifications and characteristic curves.

5.2 FilterLab® Software

Microchip’s FilterLab® software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from the

Micro chi p web s ite at www.microchip.com/filterlab, the

FilterLab design tool provides full schematic diagrams

of the filter circuit with component values. It also

outputs the filter circuit in SPICE format, which can be

used with the macro model to simulate actual filter

performance.

5.3 Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps semiconductor

professionals efficiently identify Microchip devices that

fit a particular design requirement. Available at no cost

from the Microchip website at

www.microchip.com/maps, the MAPS is an overall

selection tool for Microchip’s product portfolio that

includes Analog, Memory , MCUs and DSCs. Using this

tool, you can define a filter to sort features for a

parametric search of devices and export side-by-side

technical comparison reports. Helpful links are also

provided for Datasheets, Purchase, and Sampling of

Microchip parts.

5.4 Analog Demonstration and

Evaluation Boards

Microchip offers a broad spectrum of Analog

Demonstration and Evaluation Boards that are

designe d to h elp you a chieve f aster tim e to market. F or

a complete listing of these boards and their

correspo nding user’s guides and tech nical info rmatio n,

visit www.microchip.com/analogtools, the Microchip

web site.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1

• MCP6XXX Amplifier Evaluation Board 2

• MCP6XXX Amplifier Evaluation Board 3

• MCP6XXX Amplifier Evaluation Board 4

• Active Filter Demo Board Kit

• 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N SOIC8EV

• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N

SOIC14EV

5.5 Application Notes

The following Microchip Analog Design Note and

Application Notes are available on the Microchip web

site at www.microchip.com/appnotes and are

recomm end ed as suppl em ental reference resourc es .

•ADN003: “Select the Right Operational Amplifier

for your Filtering Circuits”, DS21821

•AN722: “Operational Amplifier T opologies and DC

Specifications”, DS00722

•AN723: “Operational Amplifier AC Specifications

and Applications”, DS00723

•AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

•AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

•AN1177: “Op Amp Precision Design: DC Errors”,

DS01177

•AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

• AN1297: “Microchip’s Op Amp SPICE Macro

Models”, DS01297

•AN1332: “Current Sensing Circuit Concepts and

Fundamentals”, DS01332

These application notes and others are listed in the

design guide:

•“Signal Chain Design Guide”, DS21825

MCP6401/1R/1U/2/4/6/7/9

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

5-Lead SC70 (MCP6401 only) Example:

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the ful l Micro chip p art num ber can not be ma rked on one line , it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Example:

5-Lead SOT-23 Part Number Code

MCP6401T-E/OT NLNN

MCP6401T-H/OT U8NN

MCP6401RT-E/OT NMNN

MCP6401RT-H/OT U9NN

MCP6401UT-E/OT NPNN

MCP6401UT-H/OT V8NN

MCP6406T-E/OT ZXNN

MCP6406T-H/OT ZYNN

8-Lead TDFN (2 x 3) (MCP6402 only) Example:

8-Lead SOIC (150 mil) (MCP6401, MCP6402, MCP6407) Example:

(MCP6401/1R/1U, MCP6406)

Part Number Code

MCP6402T-E/MNY AAW

BL25

NL25

AAW

129

NNN

MCP6402E

SN ^^1129

256

MCP6401/1R/1U/2/4/6/7/9

Package Marking Information (Continued)

14-Lead TSSOP (MCP6404 only)Example:

14-Lead SOIC (150 mil) (MCP6404, MCP6409)Example:

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanume ric trac ea bil ity code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the even t the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

and

MCP6404

H/SL ^^

1129256

YYWW

NNN

XXXXXXXX

6404E/ST

1129

256

MCP6401/1R/1U/2/4/6/7/9





 

 

 

 



 

   

  

  

    

    

    

    

    

    

    

    

    

AA2

   

MCP6401/1R/1U/2/4/6/7/9



MCP6401/1R/1U/2/4/6/7/9

 !



 



 

   

  

  

  

    

    

    

    

    

    

    

    

   

    

    

123

A2 c

   

MCP6401/1R/1U/2/4/6/7/9