SMT4004FL - Summit Microelectronics, Inc.

Characteristics subject to change without notice

2049 2.2 9/13/00

SMT4004

SUMMIT

MICROELECTRONICS, Inc.

©SUMMIT MICROELECTRONICS, Inc., 2000 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • FAX 408-378-6586 • www.summitmicro.com

lProgrammable Voltage and Current Monitoring

wMonitors 4 independent supplies

wProgrammable Host-side Under- and Over-

Voltage Thresholds

wProgrammable Card-side Under-Voltage

Monitors

wProgrammable Card-side Circuit Breaker

Delay and QuickTrip™ Threshold Levels

lProgrammable Card-side Trakker Function

wProgrammable Slew Rate Control

wGuarantees and Enforces Supply Differential

Tracking

Distributed Power Hot-Swap Controller

FUNCTIONAL BLOCK DIAGRAM

FEATURES

lProgrammable Watchdog and Longdog Timers

(0 to 6.4 seconds)

lOperates From Any One of Four Supply Voltages

lNonvolatile Fault Register

wRecords Source of Any Interrupt

wReadable in “Dead Board” Environment

lAll Communications to Configuration Registers

and Memory Array are via 2-wire Serial Inter-

face

SUPPLY

MANAGER

SUPPLY

MANAGER

SUPPLY

MANAGER

SUPPLY

MANAGER

VO1

CB1

VI1

VO3

CB3

VI3

VO2

CB2

VI2

VO4

CB4

VI4

RST1#

RST2#

RST3#

RST4#

CROWBAR

CBFAULT

HEALTHY#

VGATE1

VGATE2

VGATE3

VGATE4

VGG_CAP

ENABLE

TRKR_IRQ#

SDA

SCL

WLDI

LDO#

WDO#

RESET &

STATUS

OUTPUT

CONTROL

LOGIC

CHARGE

PUMP &

VGATE

CONTROL

TIMER

LOGIC

MEMORY

& 2-WIRE

BUS

INTERFACE

TRAKKER

LOGIC

POWER

SUPPLY

ARBITRATION

SEQUENCE

ENABLE

LOGIC

UV_OVERRIDE

SEATED1#

PWR_ON SEATED2#

FORCE_SD IRQ_CLR#

MR#

1.25VREF

AGND PGND

PGND DGND

VDD_CAP

18 17

IRQ#

2049 BD 2.1

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

*COMMENT

Stresses listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions

outside those listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for extended

periods may affect device performance and reliability.

Temperature Under Bias .......................-55°C to 125°C

Storage Temperature ............................-65°C to 150°C

Lead Solder Temperature (10 secs) ...................300 °C

Terminal Voltage with Respect to GND:

V0, V1, V2, and V3........... -0.3V to 6.0V

All Others........................ -0.3V to 6.0V

PIN CONFIGURATION

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS*

The SMT4004 is a fully integrated programmable voltage

manager IC, providing supervisory functions and tracking

control for up to four independent power supplies. The

four internal managers perform the following functions:

Monitor source (bus-side) voltages for under- and over-

voltage conditions, monitor each supply for over-current

conditions, monitor back end (card-side) voltages for two

staged levels of under-voltage conditions, insure power to

the card-side logic tracks within the specified parametric

limits, and provide supply status information to a host

processor.

The SMT4004 incorporates nonvolatile programmable

circuits for setting all of the monitored thresholds for each

manager. Individual functions are also programmable

allowing interrupts or reset conditions to be generated by

any combination of events. Because of a proprietary

EEPROM technology that it employs it is also able to store

fault conditions as they occur. In the case of a catastrophic

failure the fault is recorded in the registers and then can be

read for analysis.

LDO#

WDO#

CROWBAR

1.25VREF

MR#

IRQ_CLR#

IRQ#

PGND

TRKR_IRQ#

SEATED1#

SEATED2#

UV_OVERRIDE

CB2

CB3

CB4

PWR_ON

VGATE1

VGATE2

VGATE3

VGATE4

VGG_CAP

FORCE_SD

HEALTHY#

CBFAULT

48-Pin TQFP

2049 PCon 2.1

RST1#

RST2#

RST3#

RST4#

PGND

DGND

AGND

VO1

VO2

VO3

VO4

ENABLE

WLDI

SCL

SDA

VDD_CAP

VI1

VI2

VI3

VI4

CB1

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

DC OPERATING CHARACTERISTICS

(Over Recommended Operating Conditions; Voltages are relative to GND)

2049 Elect Table 1.0

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00 52sµ

01 05sµ

10 001sµ

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00 001s/V

01 052s/V

10 005s/V

11 0001s/V

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V5=IV7.0 ×IVIVV

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SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

PIN DESCRIPTIONS AND DEVICE OPERATION

THE

TRAKKER

SUPPLY VOLTAGES

The VI inputs of all four supply managers are diode ORed

and tied to the device's internal VDD node. The

TRAKKER

will use the highest VI input for its supply voltage. At least

one VI input must be at or above 2.7V for proper device

operation.

VDD_CAP — Charge storage connection for the chip's

internal power suply. For most applications a 10µF

capacitor should be connected to his pin.

VGG_CAP — This pin should be tied to a capacitor to be

charged by the charge pump. The capacitor should be of

sufficient size so as to provide current to the VGATE

outputs under varying load conditions.

PGND — Power ground

DGND — Digital Ground

AGND — Analog Ground

TIMERS

LDO# — The longdog timer output is an active-low open-

drain output that can be wire-ORed with other open-drain

signals. The longdog timer is generally programmed to

generate an output at a time interval longer than the

watchdog timer. The time interval is programmed in

R1C

WDO# — The watchdog timer output is an active-low

open-drain output that can be wire-ORed with other open-

drain signals. The watchdog timer is generally pro-

grammed to generate an output at a time interval shorter

than the longdog timer. The time interval is programmed

in Register

R1C

WLDI — Watchdog and longdog timer reset input. A low-

to-high transition on this pin will reset both the watchdog

timer and the longdog timer.

The watchdog and longdog work in tandem: resetting one

resets the other. Generally, the longdog will be pro-

grammed to time out sometime after the watchdog. As an

example, the WDO# output could be used to generate a

warning interrupt and the LDO# output could be tied to a

system reset line.

Both timers can be turned off, facilitating system debug

and also allowing operating systems to ‘boot up’ and

configure themselves without interrupts or resets.

SUPPLY MANAGERS

The electrical placement of the SMT4004 on a printed

circuit card is such that it separates the host power supply

and any on-board DC-to-DC converters (or LDOs) from

the backend circuitry such as multiple DSPs, micropro-

cessors and associated glue logic. The host supplies, and

any other regulated voltages that will be “switched” by the

device, are referred to as bus-side voltages. The voltages

that are on the backend circuitry side of the switches are

referred to as card-side voltages.

The four supply manager blocks are identical. Each

contains three primary functional blocks: the first monitors

the bus-side voltages, the second monitors the card-side

voltages, and the third monitors over-current conditions

for that particular supply.

BUS-SIDE MANAGEMENT

Figure 1 illustrates the functional blocks of the four supply

managers. Each manager block can be independently

enabled or electrically removed from the device.

The VI input monitors the bus-side voltage for both under-

voltage and over-voltage conditions. The thresholds for

the under-voltage detection for VI inputs are programmed

in Registers

R00

through

R03

. The VI input is effectively

the VREF of a nonvolatile DAC. The DAC has been

designed so that the threshold can be determined by

multiplying the binary value of the Register times 20mV

and adding that to 0.9V in the formula PVIT = 0.9V + (0.2mV

), where

is the register value (0 - 255 decimal). This

allows very precise monitoring of voltages in the range of

0.9V to 6V without the use of external resistor divider

networks.

The over-voltage section works in a similar manner, with

the formula being Offset = (PVIT × 1.2) + [(0.04 × PVIT) ×

where

is the register value in

R04

through

R07

. All

enabled manager blocks must ensure their respective VI

inputs are within the programmed limits before the VGATE

outputs can be turned on and the

TRAKKER

logic en-

abled. The VI comparator outputs can also be used to

generate a general interrupt.

It should be noted that either one or both of the bus-side

monitors could be disabled via Registers

R04

through

R07

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

CARD-SIDE MANAGEMENT

On the card-side the

TRAKKER

monitors two program-

mable under-voltage thresholds on the VO inputs: UV1

and UV2. UV1 can be used to generate a warning interrupt

that the supply is decaying, and UV2 can be used to

generate a reset condition or a crowbar output. The card-

side under-voltage (UV1) threshold value is programmed

in Registers R08 through R0B. Like the bus-side thresh-

olds the levels can be programmed in 20mV increments

(on top of 0.9V). The second level (UV2) is determined by

the formula UV2 = UV1 – [(UV1 × 0.01) ×

], where

is the

value in Registers R0C through R0F.

It should be noted that either one or both of the card-side

monitors can be disabled via Registers

R0C

through

R0F

OVER-CURRENT PROTECTION

The CB inputs are the circuit breaker inputs for the supply

voltages. With a series resistor placed in the supply path

between VI and CB the circuit breaker will trip whenever

the voltage across the resistor exceeds 25mV.

Figure 1. Supply Manager Circuit

–

VREF

–

25mV

–

VREF

Programmable

Quick Trip

Threshold

Programmable

Delay

–

VOX

CBX

VIX

VGATE Enable

Quick Trip To Crowbar

To IRQ

To RST

VGATE and

TRAKKER

Logic

( = Programmable)

2049 Fig01 1.0

Comparator

Circuit

Breaker

Comparator

UV1

Comparator

UV2

Comparator

Quick

Trip

Comparator

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

The on-board electronic circuit breaker can be pro-

grammed to application specific levels. The circuit

breaker delay defines the period of time the voltage drop

across RS is greater than 25mV but less than VQCB before

the VGATE output will be shut down. This is effectively a

filter to prevent spurious shutdowns of VGATE. The

delays that can be programmed are 25µs, 50µs, 100µs

and 200µs. The programmable delay bits are located in

R1B

The Quick-Trip circuit breaker threshold (VQCB) can be set

to 150mV, 100mV, 75mV or off (Register

R1A

). This is the

threshold voltage drop across RS that is placed between

VSS and CBSense. If the voltage drop exceeds the

programmed threshold, the electronic circuit breaker will

immediately trigger with no delay.

The outputs of these comparators can be used to generate

interrupts and reset conditions and toggle the crowbar

output.

POWER-ON SEQUENCING

In order to begin sequencing of the card-side supplies

(ramping the VGATE outputs) a number of conditions

must be met. All enabled bus-side voltages must be above

their respective under-voltage thresholds, the card-side

voltages (

e.g.

, residual capacitor stored potentials) must

be near zero volts, and the following inputs must be

properly set.

ENABLE — When active the ENABLE input brings

the IC out of a standby mode where the charge pump

supplying the VGATE outputs is turned on (and

begins charging the VGG_CAP) and the bandgap

reference is turned on. The ENABLE input can be

programmed to be either active low (default from the

factory) or active high (Register

R1B

SEATED1# and SEATED2# — the SEATED inputs

are effectively two additional enable inputs that must

be low to enable the sequencing of the card-side

voltages. In a staggered pin environment these

inputs can be tied to the “short” pins, insuring the card

is fully seated before any power is applied to the card-

side logic. These inputs can also be tied to card

insertion switches to indicate proper seating.

PWR_ON — the PWR_ON input is the last input that

will typically be driven to enable power sequencing to

the card-side. The PWR_ON input can be pro-

grammed to be either active low (default from the

factory) or active high (Register

R1B

TRAKKING

AND SOFTSTART CONTROL

VGATE — The VGATE outputs are used to control the

“turning-on” of the card-side voltages. The ramp rate (for

both turn-on and turn-off) of the outputs is programmable

from 100V/s to 1000V/s (Register

R10

). The four outputs

ramp at the same slew-rate, so normally there will be no

differential voltage between any of the supplies until each

reaches its maximum level.

The ramp rates are inherently adaptive. That is, if the

difference between any VO input is greater than 100mV in

the linear region, the slew rate will be increased or de-

creased to minimize the differential. The comparisons are

made between VO1 and VO2, VO2 and VO3, VO3 and

VO4, and VO4 and VO1. If at any time a differential of

greater than 300mV is detected a pre-programmed (Reg-

ister

R10

) action can be taken. The

TRAKKER

can shut

down the offending supply, generate an interrupt output, or

ignore the situation.

If SoftStart is enabled (Registers

R0C

through

R0F

) the

supply or supplies designated will be ramped as soon as

the input conditions are met and no Trakking will be

performed. Any supply not designated as a softstart

supply will not be ramped until the designated supply has

reached its VO threshold. This type of operation would

commonly be used where a bus voltage (

e.g.

, 5V) is first

switched to a DC-to-DC converter or group of LDOs; and

then their outputs would be switched in a Trakking mode

to the card-side logic.

Supply managers designated for Trakking will not begin

start-up until the soft start channels are fully turned on.

The delay is approximated by the formula tD =16,000 ÷ SR,

where tD is the time delay in milliseconds between the

PWR_ON signal going high and the start of the tracking

ramp-up, and SR is the programmed start-up slew rate in

V/s. For example, the time delay for a programmed slew

rate of 500V/s is: tD = 16,000 ÷ 500 = 32ms.

POWER MANAGEMENT STATUS OUTPUTS

The

TRAKKER

has two types of status outputs that it

provides to the host system or host processor resident on

its board. One type of output is “hardwired” internally and

the other is programmable.

HEALTHY# — The HEALTHY output is an active-low

open-drain output that can be wire-ORed with other open-

drain signals. It is driven low when all of the enabled

managers’ card-side voltages are valid and there are no

over-current conditions. The signal is used to indicate the

power supplies are within their programmed operating

limits.

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

CBFAULT — CBFAULT is driven active whenever an

over-current condition is detected. It is a programmable

output that can be either an active high or active low

(factory default) output.

RESETS

RST1# to RST4# — Associated with each manager is a

reset output. They are active-low open-drain outputs that

can be wire-ORed with other open-drain signals. The user

can select UV1, UV2 and/or an over-current condition as

the trigger for the reset pulse by programming Registers

R11

and

R12

(the default condition from the factory is all

conditions generate a reset). The reset pulse width is

adjustable by writing to Register

R1C

(default condition

from the factory is pulse of 200ms).

MR# — When driven low the manual reset input will

automatically drive all four reset outputs low.

INTERRUPTS

IRQ# — the IRQ output is an active low open-drain output

that is driven low whenever one or more of its programmed

triggers is active. There are twenty programmable

sources for generating the interrupt: bus-side over- and

under-voltage, card-side under-voltage 1 and 2, and an

over-current condition. Each source is individually en-

abled by writing to Registers

R13, R14

and

R15

. The

default from the factory is to enable all sources. The IRQ#

output can only be cleared by bringing IRQ_CLR# low, or

after a power-down/power-up sequence.

TRKR_IRQ# — the

TRAKKER

interrupt indicates there

was a skew of greater than 300mV during the power on

cycle. The source of the TRKR_IRQ# is programmable

and can be initiated by any one of the managers. The

configuration Registers

R11

and

R12

select the source of

interrupt. Configuration Register

R10

enables the

TRKR_IRQ# output (or one of three other options). The

default from the factory is to enable all sources. The

TRKR_IRQ

# output can only be cleared by bringing

IRQ_CLR high or after a power-down/power-up se-

quence.

In order to avoid false interrupts during a power-on se-

quence there is a programmable “power-on interrupt hold-

off” register. The delay can be programmed from 200ms

to 1600ms. The interrupt hold-off is in Register

R15

and

its default value from the factory will be 1600ms.

FAULT REGISTER

Whenever an interrupt is generated the cause of the fault

will be recorded in the nonvolatile status Register. In order

to avoid false recordings during power-down situations,

no faults will be recorded if the PWR_ON input has been

deactivated. The fault Registers are located at

R1D

through

R1F

. The fault source is indicated by a “1” in the

assigned bit location. Overwriting the fault Register with

“0’s” is the only way to clear a recorded fault condition.

CROWBAR — The CROWBAR output is another form of

status output. The conditions to generate a crowbar

output are programmable in Register

R19

. Whenever one

of the conditions occurs the CROWBAR output will strobe.

Rapid shutdown of the card-side supplies may be required

to prevent damage to the DSP’s or microprocessors.

SCRs with a fast turn-on time make excellent crowbar

devices and only need a pulse of gate current to ‘trigger.’

MEMORY AND REGISTER ACCESS

A0, A1 & A2 — The address pins are biased either to the

highest VI pin or GND, and provide a mechanism for

assigning a unique address to the SMH4004.

SDA — SDA is a bidirectional serial data pin. It is

configured as an open drain output and will require a pull-

up to the highest VI pin.

SCL — SCL is the serial clock input.

MISCELLANEOUS MANAGER SIGNALS

1.25VREF — This pin is a 1.25V Reference output that can

be used in conjunction with external circuitry.

UV_OVERRIDE — The Under-Voltage Override input will

disable the under-voltage comparators. This can be used

for board test and also during system margining.

FORCE_SD — When asserted the Force Shut Down input

will immediately clamp the VGATE outputs to ground. This

can be used in conjunction with the CROWBAR. The

active level for FORCE_SD is programmable and acces-

sible in Register

R1B

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

There are four basic register types. The first are those that

set a monitoring threshold where the binary value written

to the register is multiplied times the base incremental

voltage. The second type enables or disables a specific

function: unless otherwise indicated a “1” will always

enable the function and a “0” will disable or deselect that

function. Note: only the enabled condition will be depicted

in the following tables. The third Register type allows

selection of various timer values. These are not incremen-

tal, like the thresholds, but specific bit patterns select

specific timer values. The fourth register type is the

nonvolatile fault register that records fault conditions. A “0”

in any bit location indicates its corresponding monitor

function was within specified limits when the fault oc-

curred. A “1” in any bit location indicates its corresponding

monitor function was outside its specified limits when the

fault occurred.

Bus-side Under-voltage Threshold

Registers 00, 01, 02 and 03 are identical. Their contents

select the under-voltage threshold for the VI1, VI2, VI3 and

VI4 inputs, respectively.

30R,20R,10R,00RretsigeR

7D6D5D4D3D2D1D0DnoitcA

11111111 V0.6=tnemtsujdadlohserhttsehgiH

00000000 V9.0=tnemtsujdadlohserhttsewoL

00000010 2(+V9.0=dlohserhT ×,V49.0=)V20.

.g.e

2049 Table01 1.0

Bus-side Under-voltage Threshold Enable and

Over-voltage Offset

Registers 04, 05, 06 and 07 are identical. Their contents

determine whetheror not the under- or over-voltage capa-

bilities are enabled, and establish the over-voltage offset

value for the VI1, VI2, VI3 and VI4 inputs, respectively.

70R,60R,50R,40RretsigeR

7D6D5D4D3D2D1D0DnoitcA

x1xxxxxx noitcetedegatlovrednuselbanE

xx1xxxxx noitcetedegatlovrevoselbanE

xxx00010 IV(=dlohserhT

DLOHSERHT

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IV40.

DLOHSERHT

erehw)

eulavyranibretsiger=

2049 Table02 1.0

Card-side Under-voltage Threshold

Registers 08, 09, 0A and 0B are identical. Their contents

select the under-voltage threshold for the VO1, VO2, VO3

and VO4 inputs, respectively.

B0R,A0R,90R,80RretsigeR

7D6D5D4D3D2D1D0DnoitcA

11111111 V0.6=tnemtsujdadlohserhttsehgiH

00000000 V9.0=tnemtsujdadlohserhttsewoL

00000010 2(+V9.0=dlohserhT ×,V49.0=)V20.

.g.e

2049 Table03 1.0

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

Card- side Under-voltage Threshold Enable

and Over-voltage Offset

Registers 0C, 0D, 0E and 0F are identical These registers

will either enable or disable their associated power man-

agement functions and soft start capability. Their contents

also determine whether the under- or over-voltage capa-

bilities are enabled and the contents establish the over-

voltage offset value for the VO1, VO2, VO3 and VO4

inputs, respectively.

F0R,E0R,D0R,C0RretsigeR

7D6D5D4D3D2D1D0DnoitcA

1xxxxxxx delbanelennahctnemeganamrewoP

x1xxxxxx gnikkarTelbanE=0;tratstfoselbanE=1

xx1xxxxx 2egatlovrednuselbanE

xxx00010 (–)1VU(=dlohserhT

×1VU ×erehw)10.0

eulavyranibretsiger=

2049 Table04 1.0

Addressing and Slew Rate Control

Configuration Register 10 is used to configure the ad-

dressing protocol for the TRAKKER. Bit 7 determines

whether the device will respond with an acknowledge to

any bus request addressing its device type identifier, or

whether it will be selective and only respond if the A2, A1

and A0 bits match the biasing of the external pins. Bit 6

selects the device type identifier to be used for the memory

array.

01RretsigeR

7D6D5D4D3D2D1D0DnoitcA

subdesaibniPotylnosdnopseR sesserdda

1x sesserddasubllaotsdnopseR

x00101reifitnediepyt-ecivedyromeM

x11101reifitnediepyt-ecivedyromeMnoitcalaitnereffidVm003rednu/revoREKKART

erongI

01 dnaylppusytluafehtnwodtuhS #QRI_RKRT

10 dnaseilppusllanwodtuhS #QRI_RKRT

11 #QRI_RKRTetareneG

)nootffo(hgihotwoletarwelsREKKART

s/V001

01 s/V052

10 s/V005

11 s/V0001

)ffootno(wolothgihetarwelsREKKART

00 s/V001

01 s/V052

10 s/V005

11 s/V0001

2049 Table05 1.0

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

Reset Source Select and

TRAKKER

IRQ Select (for Supply Managers 1 and 2)

Reset Source Select and

TRAKKER

IRQ Select (for Supply Managers 3 and 4)

11RretsigeR

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1-1OV2-1OVO1IV1RKRT1-2OV2-2OVO2IV2RKRT

1xxxxxxx 1#TSRsa1VU1edis-dracstceleS reggirt

x1xxxxxx 1#TSRsa2VU1edis-dracstceleS reggirt

xx1xxxxx reggirt1#TSRsa1IBCstceleS

xxx1xxxx tpurretninasarorre1KRTstceleS ecruos

xxxx1xxx 2#TSRsa1VU2edis-dracstceleS reggirt

xxxxx1xx 2#TSRsa2VU2edis-dracstceleS reggirt

xxxxxx1xreggirt2#TSRsa2IBCstceleS

xxxxxxx1tpurretninasarorre2KRTstceleS ecruos

21RretsigeR

7D6D5D4D3D2D1D0DnoitcA

1-3OV2-3OVO3IV3RKRT1-4OV2-4OVO4IV4RKRT

1xxxxxxx 3#TSRsa1VU3edis-dracstceleS reggirt

x1xxxxxx 3#TSRsa2VU3edis-dracstceleS reggirt

xx1xxxxx reggirt3#TSRsa3IBCstceleS

xxx1xxxx tpurretninasarorre3KRTstceleS ecruos

xxxx1xxx 4#TSRsa1VU4edis-dracstceleS reggirt

xxxxx1xx 4#TSRsa2VU4edis-dracstceleS reggirt

xxxxxx1xreggirt4#TSRsa4IBCstceleS

xxxxxxx1tpurretninasarorre4KRTstceleS ecruos

2049 Table06 1.0

2049 Table07 1.0

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

IRQ Source Select (for Supply Managers 1 and 2)

IRQ Source Select (for Supply Managers 3 and 4)

31RretsigeR

7D6D5D4D3D2D1D0DnoitcA

VO-1IVVU-1IV1-1OV2-1OVVO-2IVVU-2IV1-2OV2-2OV

1xxxxxxx #QRInasaVO1edis-substceleS reggirt

x1xxxxxx #QRInasaVU1edis-substceleS reggirt

xx1xxxxx #QRInasa1VU1edis-dracstceleS reggirt

xxx1xxxx #QRInasa2VU1edis-dracstceleS reggirt

xxxx1xxx #QRInasaVO2edis-substceleS reggirt

xxxxx1xx #QRInasaVU2edis-substceleS reggirt

xxxxxx1x#QRInasa1VU2edis-dracstceleS reggirt

xxxxxxx1#QRInasa2VU2edis-dracstceleS reggirt

41RretsigeR

7D6D5D4D3D2D1D0DnoitcA

VO-3IVVU-3IV1-3OV2-3OVVO-4IVVU-4IV1-4OV2-4OV

1xxxxxxx #QRInasaVO3edis-substceleS reggirt

x1xxxxxx #QRInasaVU3edis-substceleS reggirt

xx1xxxxx #QRInasa1VU3edis-dracstceleS reggirt

xxx1xxxx #QRInasa2VU3edis-dracstceleS reggirt

xxxx1xxx #QRInasaVO4edis-substceleS reggirt

xxxxx1xx #QRInasaVU4edis-substceleS reggirt

xxxxxx1x#QRInasa1VU4edis-dracstceleS reggirt

xxxxxxx1#QRInasa2VU4edis-dracstceleS reggirt

2049 Table08 1.0

2049 Table09 1.0

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

IRQ Power-on Delay and Source Select (for All Supply Managers)

CROWBAR Source Enables

2049 Table10 1.0

2049 Table11 1.0

51RretsigeR

7D6D5D4D3D2D1D0DnoitcA

x000xxxx )sm0(ffoyalednorewop#QRI

x100xxxx sm002yalednorewop#QRI

x101xxxx sm004yalednorewop#QRI

x110xxxx sm008yalednorewop#QRI

x111xxxx sm0061yalednorewop#QRI

xxxx1xxx #QRIsreggirttnerruc-revo1ylppuS

xxxxx1xx #QRIsreggirttnerruc-revo2ylppuS

xxxxxx1x#QRIsreggirttnerruc-revo3ylppuS

xxxxxxx1#QRIsreggirttnerruc-revo4ylppuS

91RretsigeR

7D6D5D4D3D2D1D0DnoitcA

ECROF DS_ #QRI _KRT #QRI 1TSR1TSR1TSR1TSR KCIUQ PIRT

1xxxxxxx DS_ECROFelbanE

x1xxxxxx tpurretnilareneG

xx1xxxxx tpurretniREKKART

xxx1xxxx teser1ylppuS

xxxx1xxx teser2ylppuS

xxxxx1xx teser3ylppuS

xxxxxx1xteser4ylppuS

xxxxxxx1noitidnocpirTkciuQ

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

Quick-trip Voltage Thresholds

Over-current Delay and Active Pin Level Select

2049 Table12 1.0

2049 Table13 1.0

A1RretsigeR

7D6D5D4D3D2D1D0DnoitcA

1REGANAM2REGANAM3REGANAM4REGANAM

ffO

01 Vm57

10 Vm001

11 Vm051

ffO

01 Vm57

10 Vm001

11 Vm051

ffO

01 Vm57

10 Vm001

11 Vm051

ffO

01 Vm57

10 Vm001

11 Vm051

B1RretsigeR

7D6D5D4D3D2D1D0DnoitcA

ananBCNEOPDS-FYLD-CO

1xxxxx )hgihevitca=1(tuptuoTLUAFBC

x1xxxx )hgihevitca=1(tupniELBANE

xx1xxx )hgihevitca=1(tupniNO_RWP

xxx1xx )hgihevitca=1(tupniDS_ECROF

yaledtnerruc-revO

xxxx00 sµ52

xxxx01sµ05

xxxx10 sµ001

xxxx11 sµ002

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

Timer Configuration Register

2049 Table14 1.0

C1RretsigeR

7D6D5D4D3D2D1D0DnoitcA

DOIREPTESERREMITGODGNOLREMITGODHCTAW

sm52

01 sm05

10 sm001

11 sm002

0xx

ffO

100 sm008

101 sm0061

110 sm0023

111 sm0046

0xx

ffO

100 sm004

101 sm008

110 sm0061

111 sm0023

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

Status Registers

2049 Table15 1.0

2049 Table16 1.0

2049 Table17 1.0

D1RS

7D6D5D4D3D2D1D0DnoitcA

VU-1IVVU-2IVVU-3IVVU-4IVVO-1IVVO-2IVVO-3IVVO-4IV

1xxxxxxx VU1edis-suB

x1xxxxxx VU2edis-suB

xx1xxxxx VU3edis-suB

xxx1xxxx VU4edis-suB

xxxx1xxx VO1edis-suB

xxxxx1xx VO2edis-suB

xxxxxx1xVO3edis-suB

xxxxxxx1VO4edis-suB

E1RS

7D6D5D4D3D2D1D0DnoitcA

-1OV 1VU -2OV 1VU -3OV 1VU -4OV 1VU -1OV 2VU -2OV 2VU -3OV 2VU -4OV 2VU

1xxxxxxx 1VU1edis-draC

x1xxxxxx 1VU2edis-draC

xx1xxxxx 1VU3edis-draC

xxx1xxxx 1VU4edis-draC

xxxx1xxx 2VU1edis-draC

xxxxx1xx 2VU2edis-draC

xxxxxx1x2VU3edis-draC

xxxxxxx12VU4edis-draC

F1RS

7D6D5D4D3D2D1D0DnoitcA

1KRT2KRT3KRT4KRT1CO2CO3CO4CO

1xxxxxxx 1ylppusrorreREKKART

x1xxxxxx 2ylppusrorreREKKART

xx1xxxxx 3ylppusrorreREKKART

xxx1xxxx 4ylppusrorreREKKART

xxxx1xxx 1ylppustnerruc-revO

xxxxx1xx 2ylppustnerruc-revO

xxxxxx1x3ylppustnerruc-revO

xxxxxxx14ylppustnerruc-revO

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

AC OPERATING CHARACTERISTICS

Over recommended operating conditions

Figure 2. Memory Operating Characteristics

2049 Table18 2.0

tRtLOW

tHIGH

tHD:SDA

tSU:SDA tBUF

tDH

tHD:DAT tSU:DAT tSU:STO

SCL

SDA In

SDA Out

tAA

2049 Fig02 1.0

lobmySretemaraPsnoitidnoC.niM.xaMstinU

LCS

ycneuqerfkcolcLCS 0001zHk

WOL

doirepwolkcolC 7.4sµ

HGIH

doirephgihkcolC 0.4sµ

FUB

emiteerfsuBnoissimsnartwenerofeB7.4sµ

ATS:US

emitputesnoitidnoctratS 7.4sµ

ATS:DH

emitdlohnoitidnoctratS 0.4sµ

OTS:US

emitputesnoitidnocpotS 7.4sµ

tuptuodilavotegdekcolC)nelcyc(ADSdilavotwolLCS3.05.3sµ

emitdlohtuOataDegnahcADSot)1+nelcyc(wolLCS3.0sµ

emitesirADSdnaLCS 0001sn

emitllafADSdnaLCS 003sn

TAD:US

emitputesnIataD 052sn

TAD:DH

emitdlohnIataD 0sn

ITADSdnaLCSretlifesioNnoisserppusesioN001sn

emitelcycetirW 5sm

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

Figure 3. Read and Write Operations

T ypical Write Operation

(Standard memory device type)

Current Address Read

(Alternate memory device type)

Master

SDA

Slave

010

Master

SDA

Slave

0110

Writing Configuration Registers

Master

SDA

Slave

Master

SDA

Slave

Device Type

Address Bus

Address

Reading the Configuration Register

Up to 15

additional bytes

can be written

before issuing

the stop.

The host may continue

clocking out data so long as

it provides an ACK response

after each byte.

1XB

2049 Fig03 2.0

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

MEMORY AND REGISTER OPERATION

The

TRAKKER

has a nonvolatile memory that is config-

ured as a 256 x 8 array. Configuration Registers reside in

another ‘device type’ address space.

All read and write operations to both ‘device type’ spaces

are handled via an industry standard two-wire interface.

The bus was designed for two-way, two-line serial com-

munication between different integrated circuits. The two

lines are a serial data line (SDA), and a serial clock line

(SCL). The SDA line must be connected to a positive

supply by a pull-up resistor, located somewhere on the

bus

Data Protocol

The protocol defines any device that sends data onto the

bus as a “transmitter” and any device that receives data as

a “receiver.” The device controlling data transmission is

called the “master” and the controlled device is called the

“slave.” The

TRAKKER

will always be a “slave” device

since it never initiates a data transfer.

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during clock high

time, because changes on the data line while SCL is high

will be interpreted as start or stop condition.

START and STOP Conditions

When both the data and clock lines are high, the bus is said

to be not busy. A high-to-low transition on the data line,

while the clock is high, is defined as the “START” condi-

tion. A low-to- high transition on the data line while the

clock is high is defined as the “STOP” condition.

Acknowledge (ACK)

Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either

the master or the slave, will release the bus after transmit-

ting eight bits. During the ninth clock cycle the receiver will

pull the SDA line low to ACKnowledge that it received the

eight bits of data.

The

TRAKKER

will respond with an ACKnowledge after

recognition of a START condition and its slave address

byte. If both the device and a write operation are selected

the

TRAKKER

will respond with an ACKnowledge after

the receipt of each subsequent 8-bit word. In the READ

mode the

TRAKKER

transmits eight bits of data, releases

the SDA line, and then monitors the line for an ACKnowl-

edge signal. If an ACKnowledge is detected, and no STOP

condition is generated by the master, the

TRAKKER

will

continue to transmit data. If an ACKnowledge is not

detected the

TRAKKER

will terminate further data trans-

missions and await a STOP condition before returning to

the standby power mode.

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most signifi-

cant four bits of the slave address are the device type

identifier (see the following Table). The next three bits

are the physical device address.

Read/Write Bit

The last bit of the data stream defines the operation to

be performed. When set to “1,” a read operation is

selected; when set to “0,” a write operation.

MEMORY WRITE OPERATIONS

The

TRAKKER

allows two types of write operations: byte-

write and page write. A byte-write operation writes a single

byte during the nonvolatile write period (tWR). The page

write operation allows up to 16 bytes in the same page to

be written during tWR.

Byte Write

After the slave address is sent (to identify both the slave

device and a read or write operation), a second byte is

transmitted which contains the 8-bit address of any one of

the 256 words in the array. Upon receipt of the word

address the

TRAKKER

responds with an ACKnowledge.

After receiving the next byte of data it again responds with

an ACKnowledge. The master then terminates the trans-

fer by generating a STOP condition, at which time the

TRAKKER

begins the internal write cycle. While the

internal write cycle is in progress the

TRAKKER

inputs are

disabled, and the device will not respond to any requests

from the master.

2049 Table19 1.0

epyTeciveDsserddAsuBW/R noitcA

7D6D5D4D3D2D1D0D

10 10 2A1A0A0/1 sserddaepyt-ecivedyromeM

10 11 sserddaepyt-ecivedyromemetanretlA

100 1 sserddaepyt-ecivedsretsigernoitarugifnoC

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

Page Write

The

TRAKKER

is capable of a 16-byte page-write opera-

tion. It is initiated in the same manner as the byte-write

operation, but instead of terminating the write cycle after

the first data word the master can transmit up to 15 more

bytes of data. After the receipt of each byte the

TRAKKER

will respond with an ACKnowledge.

The

TRAKKER

automatically increments the address for

subsequent data words. After the receipt of each word, the

low order address bits are internally incremented by one.

The high order bits of the address byte remain constant.

Should the master transmit more than 16 bytes, prior to

generating the STOP condition, the address counter will

“roll over” and the previously written data will be overwrit-

ten. As with the byte-write operation, all inputs are

disabled during the internal write cycle. Refer to Figure 3

for the address, ACKnowledge and data transfer se-

quence.

Acknowledge Polling

When the

TRAKKER

is performing an internal WRITE

operation it will ignore any new START conditions. Since

the device will only return an acknowledge after it accepts

the START, the part can be continuously queried until an

acknowledge is issued, indicating that the internal WRITE

cycle is complete. See the flow diagram for the proper

sequence of operations for polling.

READ OPERATIONS

Read operations are initiated with the R/W bit of the

identification field set to “1.” There are two different read

options:

1. Current Address Byte Read

2. Random Address Byte Read

Current Address Read

The

TRAKKER

contains an internal address counter

which maintains the address of the last word accessed,

incremented by one. If the last address accessed (either

a read or write) was to address location n, the next read

operation would access data from address location n+1

and increment the current address pointer. When the

TRAKKER

receives the slave address field with the R/W

bit set to “1” it issues an acknowledge and transmits the 8-

bit word stored at address location n+1. The current

address byte read operation only accesses a single byte

of data. The master does not acknowledge the transfer,

but does generate a stop condition. At this point the

TRAKKER

discontinues data transmission.

Random Address Read

Random address read operations allow the master to

access any memory location in a random fashion. This

operation involves a two-step process. First, the master

issues a write command which includes the start condition

and the slave address field (with the R/W bit set to WRITE),

followed by the address of the word it is to read. This

procedure sets the internal address counter of the

TRAK-

KER

to the desired address. After the word address

acknowledge is received by the it the master immediately

reissues a start condition followed by another slave ad-

dress field with the R/W bit set to READ. The

TRAKKER

will respond with an acknowledge and then transmit the 8

data bits stored at the addressed location. At this point, the

master does not acknowledge the transmission but does

generate the stop condition. The

TRAKKER

discontinues

data transmission and reverts to its standby power mode.

Flow Chart

Operation

a Write?

ACK

Returned

Issue

Address

Proceed

With

Write

Await

Command

Issue Stop

Issue Slave

Address and

R/W = 0

Issue Stop

Write Cycle

In Progress

Yes

Issue Start

2049 Flow01 1.0

Yes

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

Sequential READ

Sequential reads can be initiated as either a current

address READ or random access READ. The first word

is transmitted as with the other byte read modes (current

address byte READ or random address byte READ).

However, the master now responds with an ACKnowl-

edge, indicating that it requires additional data from the

TRAKKER

. The

TRAKKER

continues to output data for

each ACKnowledge received. The master terminates the

sequential READ operation by not responding with an

ACKnowledge, and issues a STOP condition. During a

sequential read operation the internal address counter is

automatically incremented with each ACKnowledge sig-

nal. For read operations all address bits are incremented,

allowing the entire array to be read using a single read

command. After a count of the last memory address the

address counter will ‘roll-over’ and the memory will con-

tinue to output data.

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

APPLICATION CIRCUIT

See Figure 4. A typical circuit soft starting the 5V supply

and TRAKKING the 3.3V, 2.5V and 1.8V supplies

Figure 4. Application Circuit

VGATE4

VGATE3

VGATE2

VGATE1

VO4

VO3

VO2

VO1

VI4

VI3

VI2

VI1

CB4

CB3

CB2

CB1

AGND

DGND

PGND

ENABLE

UV_OVERRIDE

SEATED1#

PWR_ON

FORCE_SD

SEATED2#

RST1#

RST2#

RST3#

RST4#

CROWBAR

VDD_CAP

SMT4004

RAW5V

RAW3.3V

GND

3.3V

2.5V

1.8V

10Ω

10Ω10Ω

10Ω

5mΩ

2mΩ

2.5mΩ

2mΩ

1.8V

@10A

2.5V

@4A

10kΩ

10µF

4 × 330µF

2 × 330µF

500µF

5 × 220µF

100nF

4.7µF

Pullup

GND

WLDI

WDO#

LDO#

MR#

IRQ_CLR#

1.25VREF

TRKR_IRQ#

VGG_CAP

CBFAULT

IRQ#

HEALTHY#

SCL

SDA

2049 Fig04 2.0

SMT4004

2049 2.2 9/13/00 SUMMIT MICROELECTRONICS, Inc.

ORDERING INFORMATION

SMT4004 F

Base Part Number Package

F = 48 Pin TQFP

retsigeRstnetnoCxeH:saderugifnoC

0R4BV5.4fodlohserhTOV

1R96VO.3fodlohserhT1V

2R14V2.2fodlohserht2V

3R82V7.1fodlohserhT3V

4R06V5.5ottesVOdelbaneVOdnaVU0V

5R06V6.3tatesVOdelbaneVOdnaVU1V

6R26V8.2tatesVOdelbaneVOdnaVU2V

7R76V5.2tatesVOdelbaneVOdnaVU3V

8R9BV6.4fodlohserhTOVediSdraC

9RE6V1.3fodlohserhT1VediSdraC

AR64V3.2fodlohserht2VediSdraC

BRD2V8.1fodlohserhT3VediSdraC

CR2AV5.4fo2dlohserhTOVediSdraC

DR3AVO.3fo2dlohserhT1VediSdraC

ER4AV2.2fo2dlohserht2VediSdraC

FR6AV7.1fo2dlohserhT3VediSdraC

01R500101,sesserddadesaibnipotsdnopseR

NIB

ffodnanoetarwelss/V052,

11RFFsecruosTESERllaelbanE

21RFFsecruosQRIdnaTESERllaelbanE

31RFFsecruosQRIllaelbanE

41RFFsecruosQRIllaelbanE

51RFEsecruosllaelbane,yaledQRIotROPsm008

91R18ylnopirtkciuQdnatupnilaunamnorabworCelbanE

A1RAAstiucricreganamllapirtkciuQVm001elbanE

BIR20sµ001yaledtnerrucrevo,wolevitcastuptuollA

CIR6Fsm0061godhctaW,sm0023godgnoL,sm002teseR

2049 Reg Table 1.0

2049 2.2 9/13/00

SMT4004

SUMMIT MICROELECTRONICS, Inc.

PACKAGE

48 PIN TQFP PACKAGE

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order

to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of

any circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating

parameters, and may vary depending upon a user’s specific application. While the information in this publication has

been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any

error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications

where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to

significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless

SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is

adequately protected under the circumstances.

I2C is a trademark of Philips Corporation.

Pin 1

0.50 BSC

DETAIL "A"

1 ref

DETAIL "B"

1.60 max

1.35 – 1.45

0.22

8.975 – 9.025

0.353 – 0.355

6.5 – 7.1

0.271 – 0.280

6.5 – 7.1

0.271 – 0.280

8.975 – 9.025

0.353 – 0.355

0.02

0.063

0.053 – 0.057

0.10 – 0.20

0.004 – 0.008 0.45 – 0.75

0.018 – 0.030

0.076

0.003

0.009

mm.

in.