CD74HC253M96 - Texas Instruments - Datasheet.Directory

Data sheet acquired from Harris Semiconductor

SCHS170A

Features

• Common Select Inputs

• Separate Output-Enable Inputs

• Three-State Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The CD74HC253 and CD74HCT253 are dual 4-to-1 line

selector/multiplexers having three-state outputs. One of four

sources for each section is selected by the common select

inputs, S0 and S1. When the output enable (1OE, 2OE) is

HIGH, the output is in the high-impedance state.

Pinout

CD74HC253, CD74HCT253

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC253E -55 to 125 16 Ld PDIP

CD74HC253M -55 to 125 16 Ld SOIC

CD74HC253M96 -55 to 125 16 Ld SOIC

CD74HCT253E -55 to 125 16 Ld PDIP

CD74HCT253M -55 to 125 16 Ld SOIC

CD74HCT253M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

1OE

1I3

1I2

1I1

1I0

GND

VCC

2I3

2I2

2I1

2I0

2OE

November 1997 - Revised May 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD74HC253,

CD74HCT253

High-Speed CMOS Logic

Dual 4-Input Multiplexer

[ /Title

(CD74

HC253

CD74

HCT25

Sub-

ect

(High

Speed

CMOS

Logic

Dual

4-Input

Multi-

plexer)

Functional DiagramS

TRUTH TABLE

SELECT INPUTS DATA INPUTS OUTPUT

ENABLE OUTPUT

S1 S0 I0I1I2I3OE Y

XXXXXXHZ

LLLXXXLL

LLHXXXLH

LHXLXXLL

LHXHXXLH

HLXXLXLL

HLXXHXLH

HHXXXLLL

HHXXXHLH

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance (Off).

NOTE:

1. Select inputs S1 and S0 are common to both sections.

2OE 2I32I22I12I0S0S11I01I11I21I31OE

15 13 12 11 10 14 2 6 5 4 3 1

2OE

1OE

PN PN

2OE 2OE

1OE 1OE

8VCC

GND

CD74HC253, CD74HCT253

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, IO

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 2) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

2. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

-6 4.5 - - 0.26 - 0.33 - 0.4 V

-7.8 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

CD74HC253, CD74HCT253

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND 0 5.5 - - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC

(Note 3) VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

Three-State Leakage

Current IOZ VIL or VIH VO =

VCC or

GND

5.5 - - ±0.5 - ±5-±10 µA

NOTE:

3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

1IO - 1I3, 2IO-2l30.4

1EO, 2EO, S0, S11

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Table, e.g.,

360µA max at 25oC.

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay tPLH,

tPHL CL= 50pF 2 - - 175 - 220 - 265 ns

Select to Outputs 4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

CD74HC253, CD74HCT253

Data to Outputs tPLH,

tPHL CL= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns

CL= 50pF 6 - - 30 - 37 - 45 ns

Disable Delay Times tPHZ, tPLZ CL= 50pF 2 - - 150 - 190 - 225 ns

CL= 50pF 4.5 - - 30 - 38 - 45 ns

CL = 15pF 5 - 12 - - - - - ns

CL= 50pF 6 - - 26 - 33 - 38 ns

Enable Delay Times tPZH,

tPZL CL= 50pF 2 - - 110 - 140 - 165 ns

CL = 50pF 4.5 - - 22 - 28 - 33 ns

CL = 15pF 5 - 9 - - - - - ns

CL = 50pF 6 - - 19 - 24 - 28 ns

Output Transition Times tTLH,t

THL CL= 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns

6 - - 10 - 13 - 15 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Three-State Output Capacitance CO- - - - 20 - 20 - 20 pF

Power Dissipation Capacitance

(Notes 4, 5) CPD -5-46-----pF

HCT TYPES

Propagation Delay tPLH,

tPHL

Select to Outputs CL= 50pF 4.5 - - 40 - 50 - 60 ns

CL=15pF 5 - 16 - - - - ns

Data to Outputs tPLH,

tPHL CL= 50pF 4.5 - - 38 - 48 - 57 ns

CL=15pF 5 - 16 - - - - - ns

Disable Delay Times tPLH,

tPHL CL= 50pF 4.5 - 30 - 38 - 45 ns

CL=15pF 5 - 12 - - - - - ns

Enable Delay Times tPZH,

tPZL CL= 50pF 4.5 - - 30 - 38 - 45 ns

CL=15pF 5 - 12 - - - - - ns

Output Transition Time tTLH,t

THL CL= 50pF 4.5 - - 12 - 15 - 18 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

Three-State Output Capacitance CO- - - - 20 - 20 - 20 pF

Power Dissipation Capacitance

(Notes 4, 5) CPD -5-52-----pF

NOTES:

4. CPD is used to determine the dynamic power consumption, per multiplexer.

5. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD74HC253, CD74HCT253

Test Circuits and Waveforms

FIGURE 1. HC AND HCT TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

50% 10%

90%

GND

VCC

10%

90% 50%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED OUTPUTS

DISABLED OUTPUTS

ENABLED

6ns 6ns

tPZH

tPHZ

tPZL

tPLZ

0.3

2.7

GND

10%

90%

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED OUTPUTS

DISABLED OUTPUTS

ENABLED

tr6ns

tPZH

tPHZ

tPZL

tPLZ

6ns tf

1.3

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

VCC FOR tPLZ AND tPZL

GND FOR tPHZ AND tPZH

OUTPUT

RL = 1kΩ

50pF

CD74HC253, CD74HCT253

MECHANICAL

MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

BB AC AD

0.325 (8,26)

0.300 (7,62)

0.010 (0,25) NOM

Gauge Plane

0.015 (0,38)

0.430 (10,92) MAX

1.060

(26,92)

0.940

(23,88)

0.920

0.850

0.775

0.745

(19,69)

(18,92)

0.775

(19,69)

(18,92)

0.745

A MIN

DIM

A MAX

PINS **

(23,37)

(21,59)

Seating Plane

14/18 PIN ONLY

20 pin vendor option 4040049/E 12/2002

0.070 (1,78)

0.045 (1,14) 0.020 (0,51) MIN

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

0.010 (0,25)

0.100 (2,54)

16 PINS SHOWN

MS-100

VARIATION AA

0.030 (0,76)

0.045 (1,14)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).

D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

MECHANICAL DATA

MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.197

(5,00)

A MAX

A MIN (4,80)

0.189 0.337

(8,55)

(8,75)

0.344

0.386

(9,80)

(10,00)

0.394

DIM

PINS **

4040047/E 09/01

0.069 (1,75) MAX

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.016 (0,40)

0.044 (1,12)

0.244 (6,20)

0.228 (5,80)

0.020 (0,51)

0.014 (0,35)

1 4

8 5

0.150 (3,81)

0.157 (4,00)

0.008 (0,20) NOM

0°– 8°

Gage Plane

0.004 (0,10)

0.010 (0,25)0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

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