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Thank you for your cooperation and understanding, WeEn Semiconductors TO -92 EC103D1 SCR 22 July 2014 Product data sheet 1. General description Planar passivated ultra sensitive gate Silicon Controlled Rectifier in a SOT54 (T0-92) plastic package. 2. Features and benefits * * Planar passivated for voltage ruggedness and reliability Ultra sensitive gate 3. Applications * * * * * Electronic ballasts Safety shut down and protection circuits Sensing circuits Smoke detectors Switched Mode Power Supplies 4. Quick reference data Table 1. Quick reference data Symbol Parameter VDRM Conditions Min Typ Max Unit repetitive peak offstate voltage - - 400 V VRRM repetitive peak reverse voltage - - 400 V ITSM non-repetitive peak on- half sine wave; Tj(init) = 25 C; state current tp = 10 ms; Fig. 4; Fig. 5 - - 8 A IT(AV) average on-state current half sine wave; Tlead 92 C; Fig. 1 - - 0.5 A IT(RMS) RMS on-state current half sine wave; Tlead 92 C; Fig. 2; - - 0.8 A - 3 12 A Fig. 3 Static characteristics IGT gate trigger current VD = 12 V; IT = 10 mA; Tj = 25 C; Fig. 7 Scan or click this QR code to view the latest information for this product EC103D1 NXP Semiconductors SCR 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 K Simplified outline cathode 2 G gate 3 A anode Graphic symbol A K G sym037 321 TO-92 (SOT54) 6. Ordering information Table 3. Ordering information Type number EC103D1 EC103D1 Product data sheet Package Name Description Version TO-92 plastic single-ended leaded (through hole) package; 3 leads SOT54 All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 2 / 13 EC103D1 NXP Semiconductors SCR 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDRM Conditions Min Max Unit repetitive peak off-state voltage - 400 V VRRM repetitive peak reverse voltage - 400 V IT(AV) average on-state current half sine wave; Tlead 92 C; Fig. 1 - 0.5 A IT(RMS) RMS on-state current half sine wave; Tlead 92 C; Fig. 2; - 0.8 A - 8 A - 9 A Fig. 3 ITSM non-repetitive peak on-state current half sine wave; Tj(init) = 25 C; tp = 10 ms; Fig. 4; Fig. 5 half sine wave; Tj(init) = 25 C; tp = 8.3 ms I t I t for fusing tp = 10 ms; SIN - 0.32 A s dIT/dt rate of rise of on-state current IT = 2 A; IG = 10 mA; dIG/dt = 100 mA/ - 50 A/s 2 2 2 s IGM peak gate current - 1 A VRGM peak reverse gate voltage - 5 V PGM peak gate power - 2 W PG(AV) average gate power - 0.1 W Tstg storage temperature -40 150 C Tj junction temperature - 125 C over any 20 ms period 003aaa111 0.6 a =1.57 Ptot (W) 1.9 2.2 0.4 2.8 4 0.2 0.0 0.0 0.1 0.2 0.3 conduction angle (degrees) form factor a 30 60 90 120 180 4 2.8 2.2 1.9 1.57 0.4 0.5 IT(AV) (A) 0.6 = conduction angle a = form factor = IT(RMS) / IT(AV) Fig. 1. Total power dissipation as a function of average on-state current; maximum values EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 3 / 13 EC103D1 NXP Semiconductors SCR IT(RMS) (A) 003aaa116 1 003aaa117 12 IT(RMS) (A) 0.8 10 8 0.6 6 0.4 4 0.2 2 0 -50 Fig. 2. 0 50 100 0 10-2 150 Tlead (C) RMS on-state current as a function of lead temperature; maximum values 10-1 1 10 surge duration (s) f = 50 Hz; Tlead = 92 C Fig. 3. RMS on-state current as a function of surge duration; maximum values 003aaa110 10 ITSM (A) 8 6 4 IT ITSM 2 0 t tp Tj(init) = 25 C max 1 102 10 number of cycles 103 f = 50 Hz Fig. 4. Non-repetitive peak on-state current as a function of the number of sinusoidal current cycles; maximum values EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 4 / 13 EC103D1 NXP Semiconductors SCR 003aac340 103 IT ITSM (A) ITSM t tp Tj(init) = 25 C max 102 10 10-5 10-4 10-3 tp (s) 10-2 tp = 10 ms Fig. 5. Non-repetitive peak on-state current as a function of pulse duration; maximum values EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 5 / 13 EC103D1 NXP Semiconductors SCR 8. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-lead) thermal resistance from junction to lead Fig. 6 - - 60 K/W Rth(j-a) thermal resistance from junction to ambient printed circuit board mounted: lead length = 4 mm - 150 - K/W 003aaa108 102 Zth(j-lead) (K/W) 10 1 P = tp T 10- 1 tp 10- 2 10- 5 Fig. 6. 10- 4 10- 3 10- 2 10- 1 1 t T tp (s) 10 Transient thermal impedance from junction to lead as a function of pulse duration EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 6 / 13 EC103D1 NXP Semiconductors SCR 9. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit VD = 12 V; IT = 10 mA; Tj = 25 C; - 3 12 A - 2 6 mA - 2 5 mA Static characteristics IGT gate trigger current Fig. 7 IL latching current VD = 12 V; IG = 0.5 mA; RGK = 1 k; Tj = 25 C; Fig. 8 IH holding current VD = 12 V; RGK = 1 k; Tj = 25 C; Fig. 9 VT on-state voltage IT = 1 A; Tj = 25 C; Fig. 10 - 1.2 1.35 V VGT gate trigger voltage VD = 12 V; IT = 10 mA; Tj = 25 C; - 0.5 0.8 V 0.2 0.3 - V Fig. 11 VD = 400 V; IT = 10 mA; Tj = 125 C; Fig. 11 ID off-state current VD = 400 V; Tj = 125 C; RGK = 1 k - 0.05 0.1 mA IR reverse current VR = 400 V; Tj = 125 C; RGK = 1 k - 0.05 0.1 mA VDM = 268 V; Tj = 125 C; RGK = 1 k; - 150 - V/s Dynamic characteristics dVD/dt rate of rise of off-state voltage (VDM = 67% of VDRM); exponential waveform; Fig. 12 tgt gate-controlled turn-on ITM = 2 A; VD = 400 V; IG = 10 mA; dIG/ time dt = 0.1 A/s; Tj = 25 C - 2 - s tq commutated turn-off time - 100 - s VDM = 268 V; Tj = 125 C; ITM = 1.6 A; VR = 35 V; (dIT/dt)M = 30 A/s; dVD/ dt = 2 V/s; RGK = 1 k; (VDM = 67% of VDRM) EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 7 / 13 EC103D1 NXP Semiconductors SCR 003aaa113 2.0 IGT IGT(25C) IL IL(25C) 1.6 1.6 1.2 1.2 0.8 0.8 0.4 0.4 0 - 50 Fig. 7. 0 50 100 Tj (C) 0 - 50 150 003aaa115 0 50 100 150 Normalized latching current as a function of junction temperature 003aaa109 2.5 IH IH(25C) Tj (C) RGK = 1 k Normalized gate trigger current as a function of junction temperature Fig. 8. 2.0 IT (A) 1.6 2.0 1.2 1.5 0.8 1.0 0.4 0.5 0 - 50 Fig. 9. 003aaa114 2.0 0 50 100 Tj (C) 0 0.4 150 (1) 0.8 (2) (3) 1.2 RGK = 1 k Vo = 0.895 V; Rs = 0.195 Normalized holding current as a function of junction temperature (1) Tj = 125 C; typical values VT (V) 1.6 (2) Tj = 125 C; maximum values (3) Tj = 25 C; maximum values Fig. 10. On-state current as a function of on-state voltage EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 8 / 13 EC103D1 NXP Semiconductors SCR 003aaa112 1.6 VGT VGT(25C) dVD/dt (V/s) 1.2 103 0.8 102 0.4 - 50 0 50 100 Tj (C) 003aac341 104 10 150 (1) 0 50 100 Tj (C) 150 RGK = 1 k Fig. 11. Normalized gate trigger voltage as a function of junction temperature Fig. 12. Critical rate of rise of off-state voltage as a function of junction temperature; typical values EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 9 / 13 EC103D1 NXP Semiconductors SCR 10. Package outline Plastic single-ended leaded (through hole) package; 3 leads SOT54 c E d A L b 1 e1 2 D e 3 b1 L1 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b b1 c D d E e e1 L L1(1) mm 5.2 5.0 0.48 0.40 0.66 0.55 0.45 0.38 4.8 4.4 1.7 1.4 4.2 3.6 2.54 1.27 14.5 12.7 2.5 max. Note 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 REFERENCES IEC JEDEC JEITA TO-92 SC-43A EUROPEAN PROJECTION ISSUE DATE 04-06-28 04-11-16 Fig. 13. Package outline TO-92 (SOT54) EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 10 / 13 EC103D1 NXP Semiconductors SCR In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 11. Legal information 11.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Preview -- The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Draft -- The document is a draft version only. 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EC103D1 Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 11 / 13 EC103D1 NXP Semiconductors SCR grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, IC-bus logo, ICODE, ICODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE -- are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo -- are trademarks of iBiquity Digital Corporation. EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 12 / 13 EC103D1 NXP Semiconductors SCR 12. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Limiting values .......................................................3 8 Thermal characteristics .........................................6 9 Characteristics ....................................................... 7 10 Package outline ................................................... 10 11 11.1 11.2 11.3 11.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 (c) NXP Semiconductors N.V. 2014. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 July 2014 EC103D1 Product data sheet All information provided in this document is subject to legal disclaimers. 22 July 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved 13 / 13