REVISIONS _ LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add packages T and W. Add vendor CAGE 60395 as 93-06-29 M. A. Frye source of supply. Increase data retention to 20 years, minimum. Redrawn with changes. THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV AJTATATA SHEET 35 | 36 | 37 | 38 REV A A A A A A A A A A A A A A A A A A A A SHEET 15 | 16 7 17 | 18 | 79 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 364 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1) 27 37 4] 5] 6] tf 8] 9 | tof 14 | 12] 13 | PREPARED BY , PMIC N/A Kenneth Rice DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 STANDARDIZED CHECKED BY MILITARY Charles Reusing DRAWING wrpnoveD wy MICROCIRCUIT, MEMORY, DIGITAL, CMOS THIS DRAVING 18 avatLapLe | Charles E. Besore 128K x 8 BIT EEPROM, MONOLITHIC FOR USE BY ALL DEPARTMENTS SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-07-12 SIZE CAGE CODE 5962-38267 ANSC N/A REVISION LEVEL A 67268 A SHEET 1 OF 38 DESC FORM 133 Ju 91 5962-175-93 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. M@ 9004708 0000755 471 = i A. icc acme eae ec1. SCOPE 1.1 Scope. This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes 8, Q@, and M) and space application (device classes $ and V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STO-883 in conjunction with compliant non-JAN devices". When available, a choice of radiation hardness assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 = 38267 01 T 1 T 1 on _L. _t_ Federal RHA Device Device Case Lead stock class designator type class outline finish designator (See 1.2.1) (See 71.2.2) designator (See 1.2.4) (See 1.2.5) (See 1.2.3) V/ Drawing number 1.2.1 RHA designator. Device classes M, B, and S$ RHA marked devices shall meet the MIL-M-38510 specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-1-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function Access time Write speed Write mode Endurance 01 28010 128K x 8 EEPROM 250 ns 10 ms Byte/Page 10,000 cycle 02 " 128K x 8 EEPROM 250 ns 5 ms Byte/Page 10,000 cycle 03 " 128K x 8 EEPROM 200 ns 10 ms Byte/Page 10,000 cycle 04 " 128K x 8 EEPROM 200 ns 5 ms Byte/Page 40,000 cycle 05 " 128K x 8 EEPROM 150 ns 10 ms Byte/Page 10,000 cycle 06 " 128K x 8 EEPROM 150 ns 5 ms Byte/Page 10,000 cycle 07 " 128K x 8 EEPROM 120 ns 10 ms Byte/Page 10,000 cycle 08 " 128K x 8 EEPROM 120 ns 3 ms Byte/Page 10,000 cycle 09 " 128K x 8 EEPROM 90 ns 10 ms Byte/Page 10,000 cycle 10 " 128K x 8 EEPROM 90 ns 3 ms Byte/Page 10,000 cycle 11 " 128K x & EEPROM _ Ons 10 ms Byte/Page 10,000 cycle 12 " 128K x 8 EEPROM 70 ns 3 ms Byte/Page 10,000 cycle 13 " 128K x 8 EEPROM 120 ns 3 ms Byte/Page 10,000 cycle 14 " 128K x 8 EEPROM 90 ns 3 ms Byte/Page 10,000 cycle 15 " 128K x 8 EEPROM 70 ns - 3ms Byte/Page 10,000 cycle 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: . Device class Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Bors Certification and qualification to MIL-M-38510 aor Vv Certification and qualification to MIL-1-38535 STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER ; DAYTON, OHIO 45444 REVISION LEVEL | SHEET A 2 DESC FORM 193A THT. 91 Mm 9004708 cooo75b Sod mm ra aaa a eaaaaaaasaaaaaasaaaasaaaaaaaaaaaaaaaataamaaaaaaaaaaaaaaaamaamaa sma saaaamaaaaaaaaaaaaaaaaaaaamaamaaaaaasaadaatataa daa saaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaamaasaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaacaaaacaaaiaacasaacacacaaaccaaacascasssacmaaaail1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style xX See figure 1 32 Oual in-line Y CQCC1-N44 44 Rectangular chip carrier Zz See figure 1 32 Flat package u cQcc1-N32 32 Rectangular chip carrier T See figure 1 30 Grid array W See figure 1 36 Grid array 1.2.5 Lead finish. The lead finish shall be as specified in MIL-H-38510 for classes M, B, and $ or MIL-1-38535 for classes Qand V. Finish letter "Xx" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (Vpp) - ----------- - 0.5 Vde to+6.0Vde 3/ Operating case temperature range - -------- - -55C to +125C Storage temperature range - - -----------=+ ~65C to +#150C Lead temperature (socidering, 10 seconds) - - - - - - +300C Thermal resistance, junction-to-case Oyj): Cases YandU ------------------ See MIL-STD-1835 Cases X, T, andW -------+--------- 21C/W 4/ Case Z ---------- - eee eee ee 18C/W 4/ Maximum power dissipation (Pp) ----------- 1.0 watts Junction temperature (Tj) ------------- +175C 5/ Endurance ----+------++------+-++-- 10,000 cycles/byte (minimum) Data retention ------~--------+-+---- 20 years minimum 1.4 Recommended operating conditions. Supply voltage range (Veo) - ------+------ 4.5 V de minimum to 5.5 V de maximum Supply voltage (Vgg) - - -------------- 0.0 V de High level input voltage range (Vy) ------- - 2.0 V de to Vec + 1.0 V de Low level input voltage range (Vy)) --------- -0.1 Vv de to 0.8 V de Case operating temperature range (Tc) ------- - -55C to +125C 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) - - - - 6/ percent 4/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum Levels may degrade performance and affect reliability. g/ ALL voltages referenced to Vgg (Vgg = ground), unless otherwise specified. 3/ Negative undershoots to a minimum of -1.0 V are allowed with a maximum of 20 ns pulse width. 4/ When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated herein. 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 6/ When a QML source exists, a value shall be provided. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 3 DESC FORM 193A JUL 91 ME 9004708 ooo0797? 444 A a cA aca acc; ti ekaaauaaaamamaaa amass sacs aaa sama aaa sta a tara2. APPLICABLE DOCUMENTS 2.1 Government specifications, standards, bulletin, and handbook. Unless otherwise specified, the following specifications, standards, bulletin, and handbook of the issue Listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. SPECIFICATIONS MILITARY MIL-M-38510 - Microcircuits, General Specification for. MIL-1-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS MILITARY MIL-STD-480 - Configuration Control-Engineering Changes, Deviations and Waivers. MIL-STD-883 - Test Methods and Procedures for Microelectronics. MIL-STD-1835 - Microcircuit Case Outlines BULLETIN MILITARY MIL-BUL-103 ~ List of Standardized Military Drawings (SMD's). HANDBOOK MILITARY MIL-HDBK~780 - Standardized Military Drawings. (Copies of the specifications, standards, bulletin, and handbook required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) 2.2 Non-Government publications. The following document(s) forma part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those Listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not Listed in the DODISS are the issues of the documents cited in the solicitation. . AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-88 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials, 1916 Race Street, Philadelphia, PA 19103.) ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard No. 17 - A Standardized Test Procedure for the Characterization of Latch-up in CMOS Integrated Circuits. (Applications for copies should be addressed to the Electronics Industries Association, 2001 Pennsylvania Street, N.W., Washington, DC 20006.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through Libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 4 DESC FORM 193A THT. 91 me 9004708 0000798 380 ESOV-~_E_E_EOEOE_E_E_E__ EE3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device class M shail be in accordance with 1.2.1 of MIL-STO-883, Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices" and as specified herein. The individual item requirements for device classes B and S$ shall be in accordance with MIL-M-38510 and as specified herein. This is a fully characterized military detail specification and is suitable for qualification of device classes B and S to the requirements of MIL-M-38510. The individual item requirements for device classes @ and V shall be in accordance with MIL-1-38535, the device manufacturer's Quality Management (QM) plan, and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-M-38510 for device classes M, B, and $ and MIL-I-38535 for device classes Q and V and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.2.4 Radiation exposure circuit. The radiation exposure circuit will be provided when RHA product becomes available. 3.3 Electrical performance characteristics and postirradiation parameter Limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shalt be marked with the PIN Listed in 1.2 herein. Marking for device class M shall be in accordance with MIL-STD-883 (see 3.1 herein). In addition, the manufacturer's PIN may also be marked as Listed in MIL-BUL-103. Marking for device classes 8 and S shall be in accordance with MIL-M-38510. Marking for device classes Q@ and V shall be in accordance with MIL-1-38535. 3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a "C" as required in MIL-STD-883 (see 3.1 herein). The certification mark for device classes B and S shall be a "J" or "JAN" as required in MIL-M-38510. The certification mark for device classes Q and V shall be a "QML" as required in MIL~I~-38535. 3.6 Certificate of compliance. For device class M, a certificate of compliance shall be required from a manufacturer in order to be Listed as an approved source of supply in MIL-BUL-103 (see 6.7.3 herein). For device classes Q@ and V, a certificate of compliance shail be required from a QML-38535 Listed manufacturer in order to supply to the requirements of this drawing (see 6.7.2 herein). The certificate of compliance submitted to DESC-EC prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device class M the requirements of MIL-STD-883 (see 3.1 herein), or for device classes Q and V, the requirements of MIL-1-38535 and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required for device class M in MIL-STD-883 (see 3.1 herein) or device classes B and S in MIL-M-38510 or for device classes Q and V in MIL-I-38535 shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DESC-EC of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-480. 3.9 Verification and review for device class M. For device class M, DESC, DESC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device classes M, B, and $. Device classes M, 8, and S devices covered by this drawing shall be in microcircuit group number 42 (see MIL-M-38510, appendix ). 3.11 Serialization for device classes S and V. ALL device class S devices shall be serialized in accordance with MIL-M-38510. Class V shall be serialized in accordance with MIL-1-38535, STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 5 DESC FORM 193A JUL 91 Mm 9004708 0000799 2173.12 Processing of EEPROMs: ALL testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.12.1 Conditions of the supplied devices: Devices will be supplied in cleared state (logic 1's"). No provision will be made for supplying written devices. 3.12.2 Clearing of EEPROMs: When specified, devices shall be cleared in accordance with the procedures and characteristics specified in 4.6.4. . 3.12.3 Writing of EEPROMs: When specified, devices shall be written in accordance with the procedures and characteristics specified in 4.6.3. 3.12.4 Verification of state of EEPROMs: When specified, devices shall be verified as either written to the specified pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be removed from the lot or sample. 3.12.5 Power supply sequence of EEPROMs: In order to reduce the probability of inadvertent writes, the following power supply sequences shall be observed: a. A logic high state shall be applied to WE and/or CE at the same time or before the application of Vee- b. A logic high state shall be applied to WE and/or CE at the same time or before the removal of Vcc. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device class M, sampling and inspection procedures shall be in accordance with section 4 of MIL-N-38510 to the extent specified in MIL-STD-883 (see 3.1 herein). For device classes B and S$, sampling and inspection procedures shall be in accordance with MIL-M-38510 and method 5005 of HIL-STD-883, except as modified herein. For device classes Q and V, sampling and inspection procedures shail be in accordance with MIL-I-38535 and the device manufacturer's QM plan. 4.2 Screening. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. For device classes B and S, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to qualification and quality conformance inspection. For device classes Q and V, screening shall be in accordance with MIL-1~38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 additional criteria for device classes M, B, and S. a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters of method 5004 and substitute Lines 1 through 6 of table IIA herein. b. Prior to burn in, the devices shall be programmed (see 4.6.3 herein) with a checkerboard pattern or equivalent (manufacturers at their option may employ an equivalent pattern provided it is a topologically true alternating bit pattern). (See figure 4.) The pattern shall be read before and after burn in. Devices having bits not in the proper state after burn in shall constitute a device failure and shall be included in the PDA calculation and shall be removed from the lot (see 4.2.3 herein). c. For device class M, the test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. For device classes B and S, the test circuit shall be submitted to the qualifying activity. For device classes M, B, and S, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (1) Static burn-in for device class S$ (method 1015 of MIL-STD-883, test condition A). (a) ALL inputs shall be connected to GND. Outputs may be open or connected to 4.5 V minimum. Resistors R1 are optional on both inputs and outputs, and required on outputs connected to Vcc #0.5 V. RI = 22M! to 47 Q. For static II burn-in, reverse all input connections (i.e., Vgg to Vee). (b) Vee = 4.5 V minimum. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER A 6 DESC FORM 193A JUL 91 me 9004708 0000800 469 EE _______._________,,___,_,_,_______ aa,(c) Ambient temperature (Ta) shall be +#125C minimum. (d) Test duration for the static test shall be 48 hours minimum. The 48-hour burn-in shall be broken into : two sequences of 24 hours each (static I and static I1) followed by interim electrical measurements. (2) Dynamic burn-in for device classes M, B, and S (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1c herein). d. Interim and final electrical parameters shall be as specified in table IIA herein. e. For classes S$ and B devices, post dynamic burn-in electrical parameter measurements may, at the manufacturer's option, be performed separately or included in the final electrical parameter requirements. f. An endurance test including a data retention bake, as specified in method 1033 of MIL-STD-883, prior to burn-in (e.g., may be performed at wafer sort) shall be included as part of the screening procedure, with the following conditions: (1) Cycling may be chip, block, byte or page at equipment room ambient and shall cycle all bytes a minimum of 10,000 cycles. (2) After cycling, perform a high temperature unbiased storage 48 hours at +150C minimum. The storage time may be accelerated by a higher temperature in accordance with the Arrhenius relationship and with the apparent activation energy of 0.6 eV. The maximum storage temperature shail not exceed +200C for assembled devices and +300C for unassembled devices. ALL devices shall be programmed with a charge opposite the state that the cell would read in its equilibrium state (e.g. worst case pattern, see 3.12.3 herein). (3) Read the data retention pattern and test using subgroups 1, 7, and 9 (at the manufacturer's option high temperature equivalent subgroups 2, 8A, and 10 or low temperature equivalent subgroups 3, 88, and 11 may be used in Lieu of subgroups 1, 7, and 9) after cycling and bake, but prior to burn-in. Devices having bits not in the proper state after storage shall constitute a device failure. g- After the completion of all screening, the devices shall be erased and verified prior to delivery. 4.2.2 Additional criteria for device classes Q@ and V. a. The burn-in test duration, test condition, and test temperature or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-I-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-1-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in appendix B of MIL-I-38535. 4.2.3 Percent defective allowable (PDA). a. The PDA for class $ devices shall be 5 percent for static burn-in and 5 percent for dynamic burn-in, based on the exact number of devices submitted to each separate burn-in. b. The PDA for class B devices shall be in accordance with MIL-M-38510 for dynamic burn-in. . Static burn-in I and II failures shall be cumulative for determining PDA. d. Those devices whose measured characteristics, after burn-in, exceed the specified delta (A) Limits or electrical parameter limits specified in table I, subgroup 1, are defective and shall be removed from the Lot. The verified failures divided by the total number of devices in the Lot initially submitted to burn-in shalt be used to determine the percent defective for the lot and the lot shall be accepted or rejected based on the specified PDA. e. The PDA for device classes @ and V shall be in accordance with MIL-1-38535 for dynamic burn-in. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 7 DESC FORM 193A JUL 91 M@ 9004708 0000801 7715 a 11ST icici acas aaa ta tattataaamamamaaaaaaaamaamammmmmmmmmmsasmacaassasssasasasamasstassataaaateteee aTABLE I. Electrical performance characteristics. | Test Symbol Conditions Group A Device Limits Unit -55C S$ Te S 4125C subgroups types Vss =0 v; 5VS Vec s5.5 Vv Nin Max _unless otherwise specified + High level input try Vec = 5.5 V, Vin = 5.5 1, 2,3 | ALL -5 | 5 | UA current + Low level input Tir Vee 5.5 V, Viy = 0.1 V 1, 2, 3 ALL -5 5 | MA current High impedance output Tozy Vec = 5.5 V, Vo = 5.5 V 1, 2,3 -10 10 leakage current _ V Vin S OE = Vee All HA loz. Veco = 5.5 V, Vo = 0.0 V 1, 2, 3 -10 10 Vip S OE S Vee { { { | | | Output high voltage | Vou Toy = -400 MA, Vee = 4.5 V 1, 2, 3 ALL 2.4 | Vv Vin = 2.0 V, Vy_ = 0.8 Output low voltage VoL Ig, * 2.1 MA, Veco = 4.5 V 1, 2,3 ALL | 0.4] Vv Vin = 2.0, Vin 2=O0.8V | l | i Input high voltage 2/ Vin Vec = 5.5 V 1, 2, 3 Alt 2.0 6.0] Vv Input low voltage 2/ Vin Veco = 4.5 V . 1, 2, 3 AL 0.5} 0.8] V OE high voltage Vy 1, 2, 3 ALL 12 3 LY Operating supply current lec Vec = 5.5 V, WE = Vip, 1, 2, 3 01-06, 80 | mA _ 08,13 CE = OF = Vy 07 100 f=1t min AVAV 09-12, 120 14,15 Standby supply current Icc2 Vec = 5.5 V, CE = VIK, 1, 2, 3 ALL 3 RA TTL all 1/0's = open, OE = Vz,_, f = O Hz Standby supply current lec3 Vec= 5.5 V, CE = Vee -0.3 V 1, 2,3 | 01-07 850__| pA CMOS Inputs = Vzy, 1/0's = open, | 08-72 500 = Vin- = 0 Hz 13-15 350 { | | See footnotes at end of table. STANDARDIZED SIZE 5962-38267 . MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL | SHEET A 8 DESC FORM 193A JUL 91 M@ 9004708 o000802 3] rca aman cemmammanmamaaascasaaaaaaaacaaaaamaaaasaaaatasaaaasaaaaaaaaaaaaaaaaasaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaasaasaaaaaaaaaamaaaaaaaacaaaasaasasadsaeasascaamasaaaaaiagTABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit Vee CS Tr S +125C subgroups types g=0V; SS VS VGC S55 Min Max unless otherwise specified Input capacitance 3/ 4/ Cin Vin = OV, f = 1.0 MHz, 4 | ALL 10.0| pF Tc = +25C, see 4.4.1 Output capacitance 3/ 4/ Cour Vout = OV, f = 1.0 MHz 4 ALL 12.0) pF Tc = 425C, see 4.4.1 Functional tests See 4.4.1 7,8A,8B ALL See figures 5, 6, and 7 as 01-02 250 applicable. 5/ 1 03-04 200 05-06 150 Read cycle time tavayv 9, 10, 11 07,08, 120 ns 13 120 09,10, 90 14 11,12, 70 15 01-02 250 03-04 200 Address access time tavav 9, 10, 11 05-06 150 07,08, 120 ns 13 09,10, 90 14 11,12, 70 15 . 01-02 250 _ 4.03-04 -200 CE access time teLav 9, 10, 11 05-06 150 07,08, 120 ns 3 09,10, 90 14 ___| 11,12, 70 15 OE access time toLav 9, 10, 11 01-06 55 {ns 07-15 50 CE to output in low Z terax [See figures 5, 6, and 7 as 9, 10, 11 ALL 0 ns 4/ applicable. 5/ Chip disable to output tenaz 9, 10, 11 01-06 55 ns in high Z 4/ 07-15 50 See footnotes at end of table. STANDARDIZED SIZE 5962+38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL | SHEET A 9 DESC FORM 193A JUL 91 M@@ 9004708 0000803 576 an aeTABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -5C S Te S +125C subgroups | types Vgg = OV; 4.5 V8 Ve 35.5 V Min Max unless otherwise specified OE to output in low Z toLax See figures 5, 6, and 7 as 9, 10, 11 ALL 0 ns 4/ applicable. 5/ , | | Output disable to output tonaz | 9, 10, 11 01-06 [55 ns in high Z 4/ 07-15 } 50 | -+ Output hold from address taxex 9, 10, 11 | ALL | 0 | ns change | | 01,03, 9, 10, 11 05,07, 10 Write cycle time tyHwit | 09,11 ms t 02,04 EHEL1 06 5 08,10, 3 | | [12-15 | | [ ij i | | | | Address setup time tavWL | 9, 10, 11 | ALL | 0 | ns TAVEL | | | | | L Address hold time - tyLax 9, 10, 11 01-08, 70 | ns t 13 ELAX 09-12, | 14,15 50. | Write setup time teLwe 9, 10, 11 ALL 0 | ns TWLEL | Write hold time tyHEH 9, 10, 11 ALL 0 ns TEHWH OE setup time Ttonwe 9, 10, 11 ALL 10 ns TOHEL OE hold time tWHOL 9, 10,11 | All 10 ns TEHOL Write pulse width (page tWLWH 9, 10, 11 ALL 100 ns or byte write) teLeH Data setup time tpvwH ; 9, 10, 11 01-08, 60 ns toveH 13 09-12, 40 | 14,15 _l i See footnotes at end of table. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 10 DESC FORM 193A JUL 91 Me 9004708 oo00a804 404 a Z_______________ ______.____ Ls,TABLE 1. Electrical performance characteristics - Continued. | | j Test Symbol | Conditions Group A Device Limits Unit -55C S Te S +125C subgroups types | Vss =Ov; 4.5 Vs Vec s5.5 Vv Min Max unless otherwise specified . Data hold time tyHox See figures 5, 6, and 7 as 9, 10, 11 01-07 t-3+}-_ ns tenpx applicable. 5/ 08-15 | | | Byte load cycle taHM2 | 9, 10, 11 | Aue 20 | 149 | ps | | 01-02 250 03-04 200 Last byte loaded to data tyHEL 9, 10, 11 05-06 150 polling tEHEL | 07,08, 120 ns 13 09,10, 90 14 | 11,72, 70 I 15 1 CE setup time teLwe | 9, 10, 11 ALL 5 us OE setup time tovewe 9, 10, 11 ALL 5 Hs (chip erase) _ 01-07 10 as WE pulse width (chip tut wH2 9, 10, 11 clear) 08-15 10 Us CE hold time tyHeH 9, 10, 11 ALL 5 ys (chip erase) OE hold time twHOH 9, 10, 11 ALL 5 | us High voltage Vy 9, 10, 11 ALL 12 13 V (chip erase) | | | | | { | | | | | | Clear recovery toLeL See figures 5, 6, and 7 as 9, 10, 11 ALL 50 ms applicable. 5/ | t t+ Data setup time tonwe | 9, 10, 11 ALL | 1 | Us / | it Data hold time during twHpx 9, 10, 11 All 1 ps chip erase cycle 6/ | | | | | | | i | See footnotes at end of table. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL | SHEET A ll (Osa _ a nel DESC FORM 193A JUL 91 mm 9004708 0000805 340 a emanateTABLE I. Electrical performance characteristics - Continued. 4/ Connect all address inputs and OE to Vin and measure Ip7, and Io7q with the output under test connected to Voyr. Terminal conditions for the output leakage current test shall be as follows: a. Vyy = 2.0 V: Vit = 0.8 V. b. For Igz,: Select an appropriate address to acquire a logic "1" on the designated output. Apply Vj, to cE. Measure the leakage current while applying the specified voltage. c. For Ip7y: Select an appropriate address to acquire a logic "0" on the designated output. Apply Viq to CE. Measure the leakage current while applying the specified voltage. 2/ A functional test shall verify, the dc input and output levels and applicable patterns as appropriate, all input and 1/0 pins shall be tested. Terminal conditions are as follows: a. Inputs: H = 2.0 V: L=0.8 . b. Outputs: H = 2.4 V minimum and L = 0.4 V maxinua. c. The functional tests shall be performed with Vcc = 4.5 and Vcc = 5.5 V. fu ~ ALL pins not being tested are to be open. 4/ Tested initially and after any design or process changes which may affect that parameter, and therefore shall be guaranteed to the Limits specified in table I. Im ~ Tested by application of specified timing signals and conditions. Equivalent ac test conditions: Output load: See figure 8. Input rise and fall times = 10 ns. Input pulse levels: 0.4 V and 2.4 V. Timing measurement reference levels: Inputs: 1 V and 2 V. Outputs: 0.8 V and 2 V. 6/ This parameter not applicable for internal timer controlled devices. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 12 DESC FORM 193A JUL 91 Me 9004706 gogcsob 2d? ee__oa awax&r&r_rx_au_4.3 Qualification inspection. 4.3.1 Qualification inspection for device classes B and S. Qualification inspection for device classes B and $ shall be in accordance with MIL-M-38510. Inspections to be performed shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5). Qualification data for subgroups 7, 8A, and 88 shall be attributes only. 4.3.1.1 Qualification extension for device classes B and $. When authorized by the qualifying activity, if a manufacturer qualifies one device type which is identical Ci.e., same die) to other device types on this specification, the slower device types may be part I qualified, upon the request of the manufacturer, without any further testing. The faster device types may be part I qualified by performing only group A qualification testing. 4.3.2 Qualification inspection for device classes G@ and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-1-38535. Inspections to be performed shall be those specified in MIL-I-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5). 4.4 Conformance inspection. Quality conformance inspection for device class M shall be in accordance with MIL-STD-883 (see 3.1 herein) and as specified herein. Quality conformance inspection for device classes B and S$ shall be in accordance with MIL-M-38510 and as specified herein. Inspections to be performed for device classes M, B, and S$ shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5). Technology conformance inspection for classes Q and V shall be in accordance with MIL-1-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-1-38535 permits alternate in-line control testing. 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted. c. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes B and S, subgroups 7 and 8 tests shall be sufficient to verify the truth table as approved by the qualifying activity. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. These tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). d. O/V Clatch-up) tests shall be. measured only for initial qualification and after any design or process changes which may affect the performance of the device. for device class M, procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes B and S, the procedures and circuits shall be maintained under document revision control by the manufacturer and shall be made available to the qualifying activity upon request. For device classes Q and V, the procedures and circuits shall be shalt be under the control of the device manufacturer's TRB in accordance with MIL-I-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JEDEC standard number 17 may be used for reference. e. Subgroup 4 (Cyy and Cgyy measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output terminals tested. f. All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all testing, the devices shall be erased and verified, (except devices submitted for groups B, C, and D testing). STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 13 DESC FORM 193A JUL 91 MM 95004708 G000607 1135 ence eae tasasmas acme stataccmmacaCase T .090 a> .180 . }~=. 510 :.010 [Al_a *.010 *.005 Ae 7 xX \ i ~ _{.030 @]cla le] .010 @Ic PIN 1 INDEX - a8 4 fy == = 002 Poa A \ yy -}-ee A ~| --.067 7g :.005 40h TYP oo 1 1 Vt QOO Orns T @ et es @ @ & @ @ sera a | YO @ 4,12.18,AND 26 ) @ @) OOO@ \ / FIGURE 1. Case outline. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 1 A DESC FORM 193A JUL 91 Mm 5004708 0000808 OSTCase W PIN 1 INDEX .110-=~ p- .067 A t.010 .005 . 760 .010 $0 .018 t+ 005 8e0e, @SGOHB] aio @ == =e BOTTOM @ view @) 4 DETAIL A DETAIL OF LEADS $0) 5, 14, 23, AND 32 ) O77 .100 TYP O / ALL LEADS FIGURE 1. Case outline - Continued. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET ; A 1 DESC FORM 193A JUL 91 M@! 5004708 0000805 Tob me IEEE SE EE EOCase X wal 4 OoOMmomaoMmomoooonnM Sooo o To ooo Soo { 4 | ut BASE PLANE SEATING PLANE oe c Et Dimensions Letter Inches Millimeters A 252 Max 5.89 b .014/ .023 0.36/0.58 b1 .033/.065 0.84/1.66 c -008/.015 0.20/0.38 D 1.690 max 42.93 E -570/.610 14.48/15.49 E1 -590/.620 14.99/15 .76 e -100 BSC 2.54 L -125/.200 3.18/5.08 L1 .150 min 3.81 Q .015/.060 0.38/1.51 Ss -100 max 2.54 $1 .005 min 0.13 NOTE: Index area: An identification mark shall be located adjacent to pin 1 within the shaded area shown. FIGURE 1. Case outline - Continued. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 16 DESC FORM 193A JUL 91 M 9004708 0000810 705 aera reac ace eee A LL CC tcAltCase 2 M SEE NOTE 2 Fog (SEE NOTE 8) | Yt : | LU X 4 t t 5 n EE NOTE 3 --|z}-2-| iT it ) id | Hu , X a Sl Ame CH SEE NOTE 4 i b @ | .004@Ic FIGURE 1. Case outline - Continued. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 17 DESC FORM 193A JUL 91 me 9004708 0000811 644 mm a a SACs ic: / acc acct atccacasaaaamaamaaaaaaaa aaa aaa AGOVariations (all dimensions shown in inches) Symbol. Min Max Notes A -090 -120 4 b -015 -020 b1 -015 -019 c -004 -007 c1 004 - 006 D -830 E -430 -488 E1 .498 8 2 -330 E3 .030 e .050 BSC H 1.228 k 008 .015 2, 5 k1 025 ref 2, 5 L .270 .370 Q -026 .045 3 s 005 $1 2045 N 32 6 Inches mm | Inches mm (| Inches mm -004 0.10 | -020 0.54 | .270 6.86 -005 0.13 | -025 0.64 | .350 8.89 - 006 0.15 | -026 0.66 | .370 9.40 .007 0.18 | -030 0.76 [| .472 11.99 - 008 0.20 | -045 1.14 | .488 12.40 .015 0.38 | .050 1.27 | .498 12.65 .019 0.48 | -120 3.05 | 1.228 31.19 NOTES: ALL dimensions and tolerances conform to ANSI Y14,54-1982. Index area: An identification mark shall be located adjacent to pin 1 within the shaded area shown. Alternatively, a tab (dim k) may be used as shown. Dimension Q shall be measured from the point on the Lead located opposite the braze pad. This dimension includes lid thickness. Optional, see note 2. If pin 1 identification is used instead of this tab, the minimum dimension does not apply. (N) indicates number of leads. Uses a metal lid. Includes braze fillet. Metric equivalents are given for general information only. vPw oo ODN FIGURE 1. Case outline - Continued. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 18 DESC FORM 193A JUL 91 m 9004708 oogoa81e 560 er EEEEEEEEEEE_Device types 01 through 15 Case outlines X, Zz, U Y W T {Terminal number Terminal symbol L 1 | NC | NC J NC | Aas 2 | Are j NC | NC | Mo | 3 Ais ] NC | NC | Ap | 4 Ma | NC [Aig | Ag | 5 | A7 | A16 | Aq5 | As | | 6 | Ag | A45 | M2 | Ag | | 7 | As | Aqa | a7 | Ag | 8 | Ag | Az | Ag | Ag | 9 AZ | Ag | As | Ay | 10 Ap | As | Ag | tg I 11 Ay | NC | Az | 1/05 | 12 Ao | NC | Ag | 1/0, 13 I/ | NC | Ay 1/05 16 1/04 A GND | 15 | 1/02 | Ag | 1/09 1/03 | 16 | Vss | Ap | 1/04 1/0, 17 1/03 | Aq | 1/0 1/0, | 18 1/04 | Ag I Vss 1/0 | 19 1/05 1/09 | 1/03 L/o, 20 1/06 1/0, 1/0, ce 21 1/07 1/02 1/05, Ag 22 CE Vss 1/06 OE 23 Mo NC 1/07 Aqy 24 OE 1/03 cE Ao 25 Aq4 1/04 Aig Ag 26 Ag 1/05 OE Anz 27 Ag 1/0 Ay WE 28 Aq3 1/07 Ag Vee 29 Ane cE Ag Aas 30 NC Mo Aq3 Ang 31 WE OE Ars 32 Vec NC NC ~-- 33 --- NC NC + 34 --- NC NC --- 35 --- NC WE --- 36 --- Ady Vec --- 37 --- Ag --- --- 38 --- Ag won --- 39 -- M13 --- --- 40 Aq --- --- 4A --- NC --- --- 42 --- NC -- --- 43 --- WE --- --- 44 Vee --- --- NC = no connection FIGURE 2. Terminal connections. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL | SHEET A 19 DESC FORM 193A JUL 91 @@ 9004708 0000813 417 EI eeMode cE | COE WE 1/0 Read VIL Vit Vin Dour Write Vit Vin Vin Din Standby Vin Xx x High Z Write inhibit x x Vin Dout or high Z Write inhibit | Vay x x High Z Write inhibit x VoL x Dout or high Z Write inhibit Vit VIL Vit No Operation Software chip | Viz Vin Viv Din clear Software write! Vip Vin VIL Orn protect High voltage Vit Vy Vin Vin chip clear : Vin = High logic, "1" state, Vy, = Low logic, "0" state. X = logic "don't care" state, High 2 = high impedance state. Vy = Chip clear voltage, Doyy = Data out, and Diy = Data in. : FIGURE 3. Truth table. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 20 DESC FORM 193A JUL 91 @ 9004708 goooa14 353 a nae kn emcee cereal1. ALL address numbers shown in decimal. 2. Each colusn/row address location corresponds to 1 byte. 3. ALL data numbers shown in hexadecimal. AA = 10101010 55 = 01010101 4. Manufacturers at their option may employ an equivalent pattern provided it is a topologically true alternating bit pattern. FIGURE 4. Data pattern. STANDARDIZED SIZE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 5962-38267 REVISION LEVEL SHEET A 21 DESC FORM 193A JUL 91 me 9004708 0000815 2oT= nav | ADDRESSES x ADDRESS Ay x NEXT ADDRESS X tavoy o! teHOZ tELov onl teLoxo oHOz \ t oLox taxox torte} | | HIGH Z +/F DATA 1 { DATA vay x DATA vaLD )-\ ja tayoy _+| FIGURE 5. Read mode waveforms. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 22 DESC FORM 193A JUL 91 Mm 9004708 COOOs1b leh , a aWE CONTROLLED BYTE WRITE WAVEFORMS CALL DEVICE TYPES) -" WRITE POLLING \_/ \ / \ WHOL} A 7 ADDRESSES VALID x DONT CARE OK V TO tL Axle jaee WHEL em} UN sues J \ ELM. . an WHHL 1 =emef q tytn) jee wo} WHOX DATA ATA IN HIGH Z DATA I g_oATA Xara) (pata IN) FIGURE 6. Waveforms. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING . A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 23 DESC FORM 193A JUL 91 Me 9004708 0000817 Obe reac ance reece ceacare eeeCE CONTROLLED BYTE WRITE WAVEFORMS CALL DEVICE TYPES) DATA -__ BYTE WRITE SOLLING _ t 0E ft \ / XL / \ OHEL~om tEHOL em Le ADDRESSES VAL IO x DON'T CARE Xx A q tavet-emlteLax ben eg CEE, o __\ y hy / WE tWLEL jo ~ bee SE HWH \__# CAL + *ELEH : t eS OVEH pet" EHX DATA HIGH Z OATA IN g DATA DATA OATA IN FIGURE 6. Waveforms - Continued. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 24 DESC FORM 193A JUL 91 me 9004708 00008615 TTT a i EUEAGOTLLPAGE MODE WRITE CYCLE WAVEFORMS CALL DEVICE TYPES) DATA _ YY Zz OHH ja om| SWHOL . ADoresses VALID a Xvao XX vat t0 X DONT CARE x q tava om] peeom| | i ax Fen a Aan J -* HEL SUL WH fan heap $d HHL 2 F= CHL 1 tov joeemt SHOX | on CP) CR) CE ma) ee FIGURE 6. Waveforms - Continued. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 25 DESC FORM 193A JUL 91 Mm 9004708 0000819 5935(ALL DEVICE TYPES) | tHHEH tocer =| tWHOH | ne FIGURE 7. Chip erase mode waveforms. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 26 DESC FORM 193A JUL 91 Me 9004708 o000820 657 a aVou -3.0 TO +13.0 1kna Y SWITCH -15.0 TO +15.0 -15.0 TO +4.0 100 pF rs NOTES: 1. Voy and Vo, will be adjusted to meet load conditions of table I. 2. Use this circuit or equivalent circuit. FIGURE 8. Switching load circuit. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 27 DESC FORM 193A JUL 91 Me 9004708 oo008?)] 543 aS 3:2... aaa eames amareWRITE DATA AA TO ADDRESS 5555 al WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555. WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 10 TO ADDRESS 5555 NOTES: 1. Software_chip clear timings are referenced to WE and CE inputs, whichever is last to go low, and the WE or CE inputs, whichever is first to go high. 2.. The command sequence must conform to the page write timing. FIGURE 9. Software chip clear and software write protect algorithm (all device types). STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 28 DESC FORM 193A JUL 91 Me 9004708 oO00822 42T SaWRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA AQ TO ADDRESS 5555 | Set SWP byte/page load enabled WRITE DATA XX TO ANY ADDRESS WRITE LAST BYTE TO LAST ADDRESS | AFTER tyc RE-ENTERS DATA PROTECTED STATE NOTES: 1. Reset software data protection timings are referenced to the WE or CE inputs, whichever is last to go low, and the WE or CE inputs, whichever is first to go high. 2. A minimum of one valid byte write must follow the first three bytes of the command sequence. 3. The command sequence and subsequent data must conform to page write timing. FIGURE 10. Set software write protect and software protected write algorithm. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 29 DESC FORM 193A JUL 91 @ 5004708 0000823 3bb errr ec eareeerreWRITE DATA AA To ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA SWP reset WRITE DATA 20 TO ADDRESS 5555 NOTES: _ _ 1. Reset software data_protection timings are referenced to the WE or CE inputs, whichever is last to go low, and the WE or CE inputs, whichever is first to go high. 2. The command sequence must conform to the page write timing. FIGURE 11. Reset_software write protect algorithm. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER A 30 DESC FORM 193A JUL 91 me 9004708 go00&24 eTc 1 aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaasasaaaaaaaaaaaasaaaaacaaaaaaaaaasaaaaaaaaaaaaaaasaaaaaaaaaaaasaasaaaaaaaaaasasaaaasaaaaaaaaaaaaaaasaaaaasasaaaaaaaaaaaiasasaaaaaaasasaaaasaasasassasaasamaaamaaaasaassassasaaaassasassaaasasccacsascssssssccsaaasaasccasassaaamsmssa EETABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/ Subgroups Cin Subgroups Cin accordance with method (accordance with Line Test 5005 table 1) MIL-1-38535, table IJ1) no. requirements Device Device Device Device Device class class class class class M B s Qa v 1,7,9 1,7,9 1,7,9 1,7,9 1 |Interim electrical or or or or parameters 2,8A,10 1,2,8A,10| 2,8A,10 1,2,8A,10 (see 4.2) 2 |Static burn-in I & II Not Not Required Not Required method 1015 required required required 3 |Same as Line 1 1%, 7% 1%, 7% 4 4 |Dynamic burn-in Required Required Required | Required Required (method 1015) 5 |Same as Line 1 1%, 7% 1%, 7% 4 4 6 j|Final electrical 4%,2,3,7%, |1%,2,3,7k, |1%,2,3,7%, |1%,2,3,7%, |1%,2,3,7%, parameters 8A,8B,9,10, |8A,88,9,10, |8A,88,9, |8A,88,9,10, |8A,88,9, 11 11 10,11 11 10,11 7 |Group A test 1,2,3,4k%k, | 1,2,3,4k%,|1,2,3,4%%, |1,2,3,4%%, 11,2,5,4%%, requirements 8/ 7,8A,88,9, |}7,8A,88,9, |7,8A,8B,9,17,8A,88,9, |7,8A,8B,9, 10,11 10,11 10,11 10,11 10,11 8 |Group B end-point 1,2,3,7, electrical &A,8B,9, parameters 10,11 9 |Group C end-point 2,3,7, 1,2,3,7, 1,2,3,7, |1,2,3,7, electrical 8A,8B 8A,8B,9, 8A,88,9, |8A,8B,9, parameters 10,11 9/ 10,11 9/ |10,11 A 4 4 10 [Group D end-point 2,3,7, 2,3,7, 2,3,7, 2,3,7, 2,3,7, electrical 8A, 8B 8A,8B 8A, 8B 8A,8B 8A,8B parameters 11 |Group E end-point electrical 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 parameters See footnotes on top of next page. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL | SHEET A 31 DESC FORM 193A JUL 91 me 9004708 o0006e5 135TABLE IIA. Electrical test requirements - Continued. 4/ Blank spaces indicate tests are not applicable. 2/ Any or all subgroups may be combined when using high-speed testers. 3/ Subgroups 7 and 8 functional tests shall verify the truth table. 4/ * indicates PDA applies to subgroup 1 and 7. 5/ kk see 4.4.1. 6/ A indicates delta limit (see table IIB) shail be required where specified, and the delta values shall be computed with reference to the previous electrical parameters (see table 116). 7/ See 4.4.1d. 8/ See table III. 9/ Delta Limits required for initial qualification and after any design or process change. TABLE IIB. Delta Limits at +25C. Device types Test 1/ ALL Icc3 standby 410% of specified value in table I Try, Typ 10% of specified value in table I Iouz- Ioiz 10% of specified value _in table I 1/ > The above parameters shall be recorded before and after the required burn-in and life tests to determine the deita A. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER A 32 DESC FORM 193A JUL 91 Me 5004708 oo008eb O75 . a reac cacemams aaa aa Aas ccs casa zac. aaaTABLE III. Input/output pulse levels for table 1, subgroups 7, 8, 9, 10, and 11. Symbol Terminals A B Device type| Units Vec Vec 4.5 5.5 ALL v Vin Logic inputs 2.4 2.4 ALL Vv address and control pins VIL Logic inputs 0.4 0.4 ALL Vv address and control pins Von Logic output 2.0 2.0 ALL v compare Level VoL Logic output 0.8 0.8 ALL V compare Level tavav Address 250 250 01,02 ns 200 200 03 ,04 ns 150 150 05,06 ns 120 120 07,08,13 ns 90 90 09,10,14 ns 70 70 11,12,15 ns teLav Chip enable 250 250 01,02 ns 200 200 03,04 ns 150 150 05,06 ns 120 120 07,08,13 ns 90 90 09,10,14 ns 70 70 11,12,15 ns toLav Output enable 55.0 55.0 01-06 ns 50.0 50.0 07-15 ns taxex 1/09-1/07 0.0 0.0 ALL ns STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL | SHEET A 33 DESC FORM 193A JUL 91 Me 9004706 O0008e7 TOL rena cma canara ae ae4.4.2 Group B inspection. The group B inspection end-point electrical parameters shall be as specified in table IIA herein. : a. For device class S only, steady-state life tests shall be conducted using test condition D and the circuit described in 4.2.1 herein, or equivalent as approved by the qualifying activity. b. For device class S only, end-point electrical parameters shall be as specified in table IIA herein. Delta Limits shall apply only to subgroup 5 of group B inspections and shall consist of tests specified in table IIB herein. c. All devices selected for class $ electrical testing shall be programmed with a checkerboard pattern or equivalent. After completion of all testing, the devices shall be erased and verified, (except devices submitted to group C and D). 4.4.3 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. Delta Limits shall apply only to subgroup 1 of group C inspection and shall consist of tests specified in table IIB herein. 4.4.3.1 Additional criteria for device classes M, B, and S. a. Steady-state Life test conditions, method 1005 of MIL-STD-883: (1) The devices selected for testing shall be programmed with a checkerboard pattern. After completion of all testing, the devices shall be cleared and verified (except devices submitted for group D testing). (2) Test condition D or E. For device class M, the test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. For device class B and S, the test circuit shall be submitted to the qualifying activity. For device classes M, B, and S, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. (3) Ty = 4125C, minimum. (4) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. b. An endurance test, as specified in method 1033 of MIL-STD-883, shall be added to group C1 inspection prior to performing the steady-state life test (see 4.4.3.1a) and extended data retention (see 4.4.3.1b). Cycling may be block, byte, or page from devices passing group A after the completion of the requirements of 4.2 herein. Initially two groups of devices shall be formed, cetl 1 and cell 2. The following conditions shall be met: (1) Cell 4 shall be cycled at -55C and cell 2 shail be cycled at +125C for a minimum of 10,000 cycles for device types. (2) Perform group A, subgroups 1, 7, and 9 after cycling. Form new cells (cell 3 and cell 4) for steady-state Life and extended data retention. Cell 3 for steady-state life test consists of 1/2 of the devices from cell 1 and 1/2 of the devices from cell 2. Cell 4 for extended data retention consists of the remaining devices from cell 1 and cell 2. (3) Extended data retention test shall consist of the following: (a) ALL devices shall be programmed with a charge on all memory cells in each device, such that loss of charge (e.g., leakage in the cell) can be detected (e.g., worst case pattern). (b) Unbiased bake for 1,000 hours (minimum) at +150C (minimum). The unbiased bake time may be accelerated by using higher temperature in accordance with the Arrhenius Relationship and with the apparent activation of 0.6 eV. The maximum bake temperature shall not exceed +200C for packaged devices or +300C for unassembled devices. (c) Read the pattern after bake and perform end-point electrical tests in accordance with table IIA - herein for group C. (4) The sample plans for celi 1, cell 2, cell 3, and cell 4 shall individually be the same as for group C1, as specified in method 5005 of MIL-STD-883, and shall individually pass the specified sample plan. c. After the completion of all testing, the devices shall be cleared and verified prior to delivery. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 34 DESC FORM 193A JUL 91 mM 9004708 0000628 548 nT4.4.3.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-I-38535. The test circuit shall be maintained under document revision Level control by the device manufacturer's TRB in accordance with MIL-1I-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. 4.4.4 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. The devices selected for testing shall be programmed with a checkerboard pattern (see figure 4). After completion of all testing, the devices shall be erased and verified. 4.4.5 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). RHA levels for device classes B, S, @, and V shall be M, D, R, and H and for device class M shall be M and D. a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes M, B, and S, the devices shall be subjected to radiation hardness assured tests as specified in MIL-M-38510 for the RHA level being tested. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-1-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at Tg = +25C #5C, after exposure, to the subgroups specified in table IIA herein. . When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. 4.5 Delta measurements for device classes B, S, @, and V. Delta measurements, as specified in table IIA, shall be made and recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical parameters to be measured, with associated delta Limits are listed in table IIB. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and 9. 4.6 Methods of inspection. Methods of inspection shall be as specified in the appropriate tables and as follows. 4.6.1 Voltages and current. All voltages given are referenced to the microcircuit ground terminal. Currents given are conventional and positive when flowing into the referenced terminal. 4.6.2 Life test, burn-in, cool down and electrical test procedure. When devices are measured at +25C following application of the steady state Life or burn-in test condition, all devices shall be cooled to +35C or within +10C of the power stable condition prior to removal of bias voltages/signals. Any electrical tests required shall first be performed at -55C or +#25C prior to any required tests at +125C. 4.6.3 Writing procedure. The waveforms and timing relationships shown on figure 6 and the conditions specified in table I shall be adhered to. Initially and after each chip clear (see 4.6.4), all bits are in the high state (output at Vow) - 4.6.3.1 Byte write operation. Information is introduced by selectively writing "L" (logic "0" level) or "H" (logic "i" level) into the desired bit. A written "L" can be changed to an "H" by writing an "H". No clearing is necessary (see 4.6.4), 4.6.3.2 Page write operation. The page write operation can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional_one to 127 bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE (CE) HIGH to LOW transition, must begin within 150 ps of the falling edge of the preceding WE (CE) high to low transition. If a subsequent WE HIGH to LOW transition is not detected within 150 Us, the internal automatic write cycle will commence. The successive writes need not be sequential; however, the page address (A7 through A16) for each write during @ page write operation shall be the same. 4.6.3.3 Data polling operation. During the internal writing cycle after a byte or page write operation, an attempt to read the last byte written will produce the complement of that data on all 1/0 or 1/07 (i.e., write data - Oxxx xxxx and read data - 1xxx xxx). Once the writing cycle has completed, all 1/0 or 1/07 will reflect true data (i.e. write data - Oxxx xxx, read data - Oxxx xxx). 4.6.3.4 Toggle bit. Toggle bit determines the end of the internal write cycle. While the internal write cycle is in progress I/0g toggles from 1 to 0 and 0 to 1 on sequential polling reads. When the internal write cycle js complete, the toggling stops and the device is ready for additional read/write operations. STANDARDIZED SIZE 5962-38267 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET A 35 DESC FORM 193A JUL 91 Me 9004708 0000825 664 ence a ee