intel. PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Available at 233 MHz, 266 MHz, 300 MHz, and 333 MHz core frequencies Binary compatible with applications running on previous members of the Intel microprocessor line Dynamic Execution micro architecture Dual Independent Bus architecture: Separate dedicated external System Bus and dedicated internal high-speed cache bus Intel's highest performance processor combines the power of the Pentium Pro processor with the capabilities of MMX technology Power Management capabilities System Management mode Multiple low-power states Optimized for 32-bit applications running on advanced 32-bit operating systems Single Edge Contact (S.E.C.) cartridge packaging technology; the S.E.C. cartridge delivers high performance with improved handling protection and socketability Integrated high performance 16 KB instruction and 16 KB data, nonblocking, level one cache Available with integrated 512 KB unified, nonblecking, level two cache Enables systems which are scaleable up to two processors and 64 GB of physical memory Error-correcting code for System Bus data The Intel Pentium Il processor is designed for high-performance desktops, workstations and mainstream servers, and is binary compatible with previous Intel Architecture processors. The Pentium || processor provides the best performance available for applications running on advanced operating systems such as Windows 95, Windows NT and UNIX*. This is achieved by integrating the best attributes of Intel's processors the dynamic execution performance of the Pentium Pro processor plus the capabilities of MMX technology bringing a new level of performance for system buyers. The Pentium Il processor is scaleable to two processors in a multiprocessor system and extends the power of the Pentium Pro processor with performance headroom for business media, communication and Internet capabilities. Systems based on Pentium II processors also include the latest features to simplify system management and lower the cost of ownership for large and small business environments. Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, jor sale and use of Intel producis except as provided in Iniels Terms and Conditions of Sale for such products. Iniormation contained herein superseces previously published specilications on these devices from Iniel. INTEL CORPORATION 1995 January 1998 Order Number: 24333 5-003 1/22/98 1:50 PM 24333502.D0C INTEL CONFIDENTIAL (until publication date)PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium II processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from by calling 1-800-548-4725 or by visiting Intels website at http:/Avww. intel.com. Copyright Intel Corporation 1996, 1997. * Third-party brands and names are the property of their respective owners. INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ PAGE PAGE 1.0. INTRODUCTION ....00......ccccccceceseeeeceneseeeenreees 7 3.0. SYSTEM BUS SIGNAL SIMULATIONG......... 37 1.1. Terminology..........0.ccccececeecseeeceeeeeesteeseeneeees 8 3.1. System Bus Clock (BCLK) Signal Quality 1.1.1.S.E.C. CARTRIDGE TERMINOLOGY ...8 Specifications Ween ee cee ee nena nen eneee 37 1.2. References... cece ccccccceccececesteeteeeeneeeees 8 3.2. GTL+ Signal Quality Specifications.............. 39 3.3. Non-GTL+ Signal Quality Specifications. .....39 2.0. ELECTRICAL SPECIFICATIONS .................... 9 3.3.1. OVERSHOOT/UNDERSHOOT 2.1. The Pentium || Processor System Bus and GUIDELINES oe eeereeeeeeeeneeee 39 VREF Dene ee eee cena eee eden eee neeeeene nee . 3.3.2. RINGBACK SPECIFICATION.............. At 2.2. Clock Control and Low Power States 3.3.3. SETTLING LIMIT GUIDELINE.............. At 2.2.1. NORMAL STATE STATE 1.............. 222 AUTO HALT POWER DOWN STATE 4.0. THERMAL SPECIFICATIONS AND DESIGN STATE Dooce. 1o CONSIDERATIONS ...........eeecccceteeseeeceeeeeeeeee AD 2.2.3. STOP-GRANT STATE STATE 3.....11 4.1. Thermal Specifications... sues 42 2.2.4, HALT/GRANT SNOOP STATE STATE 4 oes 11 2.2.5. SLEEP STATE STATE 5... 11 2.2.6. DEEP SLEEP STATE STATE 6....... 12 2.2.7. CLOCK CONTROL AND LOW POWER MODES. 00... cece cece ceeceeeetee cette 12 2.3. Power and Ground Pins..............:::cceee 12 2.4. Decoupling Guidelines oe 12 2.4.1. SYSTEM BUS GTL+ DECOUPLING ... 13 2.5. Pentium || Processor System Bus Clock and Processor Clocking.............::cseeceeee 13 2.5.1. MIXING PROCESSORS OF DIFFERENT FREQUENCIES.............. 16 2.6. Voltage Identification... eect eeee 16 2.7. Pentium || Processor System Bus Unused PINS oo. eee cee e cen eeeeee ene eeereneeteeeesseennnteee 18 2.8. Pentium || Processor System Bus Signal GIOUPS 00. eect ceeeteeeeeetneesnteeetnaeteeeees 18 2.8.1. ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS ooo ee 2.9. Test Access Port (TAP) Connection 2.10. Maximum Fattings 0.0.0... .eeeeseeeceeeees 2.11. Processor DC Specifications .....0.0......0. 2.12. GTL+ System Bus Specifications ............. 26 2.19. Pentium || Processor System Bus AC Specifications... eee eee 26 4.2. Pentium |I Processor Thermal Analysis ...43 4.2.1. THERMAL SOLUTION PERFORMANCE.......0.. cece 43 4.2.2. MEASUREMENTS FOR THERMAL SPECIFICATIONS. .....0. eee 44 4.2.2.1. Thermal Plate Temperature Measurement ..........ceeeeeeeeees 44 4.2.2.2. Cover Temperature Measurement. 45 4.3. Thermal Solution Attach Methods .........0..... 45 4.3.1. HEATSINK CLIP ATTACH .....0..0. 45 4.3.2. RIVSCREW* ATTACH... eee 47 5.0. S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS. .......secceceesseneecetseneererseneeeee 51 5.1. 3.E.C. Cartridge Materials Information ........ 51 5.2. Processor Edge Finger Signal Listing.......... 63 6.0. BOXED PROCESSOR SPECIFICATIONS....73 6.1. Introduction... ee eee ce eeereenteenees 73 6.2. Mechanical Specifications... eee 74 6.2.1. BOXED PROCESSOR FAN/HEATSINK DIMENSIONS 0.0... eeeerereereeeees 74 6.2.2. BOXED PROCESSOR FAN/HEATSINK WEIGHT...........0.00 76 6.2.3. BOXED PROCESSOR RETENTION MECHANISM AND FAN/HEATSINK SUPPORT ooo. tee 76 6.3. Boxed Processor Requirements ................. 79 6.3.1. FAN/HEATSINK POWER SUPPLY......79 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 6.4. Thermal Specifications... ee ai 6.4.1. BOXED PROCESSOR COOLING REQUIREMENTS .... ee 81 7.0. ADVANCED FEATURES........0..0 cc cessseeeeeees 82 A.1 ALPHABETICAL SIGNALS REFERENCE.... 83 ALA A[S5:O}F VO) oo cccccccccccccceeseeescseeeeeeeeee 83 AA.2 AQOMEE (I) ccccccccccccccccssscceeessseeeeessseeeeessssee a3 A1.3 ADS# (VO) oo cccccccscccccc eeeeesseeeeeeeen a3 A144 AERR# (VO) vocccccccccessssseesssssseseessnsee a3 ALL. AP[1-O} (VO) .occcccccccccceceesseeeeeeeeeee a3 A.1.6 BCLK (I)......... A.1.7 BERR# (I/O) A.1.8 BINIT# (I/O) AAO BNR# (VO)... cccccccsscecccseseeeseeeeeeees A110 BP[S:2}8 (iO)... ccccccccccccccceeseseeeeeeseeee a4 A111 BPM[1:O}f (VO)... ccccccccscccccecsseeeeecssee 84 A112 BPRIF (I) cocccccccccccceceeseseeeesesseeeeeeeeeee a4 A113 BRO# (/O), BRI (I) occ cess eenen 85 A114 BSEL# (VO) ooccccccccccceeseereeeeeee 85 A115 DI6S.O}# (UO) ccccccccccccceessesseeeesesee 85 A116 DBSY# (VO). cccccccccseeeeeeeeeees a5 A117 DEFER (I) .cccccccccceccceceeseeeeeeeees 85 A118 DEP[7:0}# (VO). cccccccccecseeeeeeeee 85 A119 DRDY# (VO) oc ccccccccccceeeeeecsseeeeesseee 85 A120 EMDocccccccccee. A.1.21 FERR# (0) A1.22 FLUSHE (I)..ccccccccsceesseeesseeeeeeeeee A.1.23 FRCERR (I/O)... sie A124 HIT# (I/O), HITM# (VO)... ccccccecceecseee AA.25 IERR# (O) oo ccccccccsccccsesseeesseeeeeeeees A126 IGNNEM (I)..cccccccsseccc ceseeeeeseeeeeeeees AA. 7 INITH (D).cccccccccccccccctceeceecccteseeeceseeeeeeesees AA.28 LINT[A:0] (I).cccccccccccssccceecsseeeeeessseeeeeeseee 87 A129 LOCK# (VO) ccccccssecssssseeesneeeseeees 87 A1.30 PICCLK (I) occ cccsceecseeeesseeeeeeees 87 A131 PICD[1:0] (VO) cscs 88 AA.32 PM[1O]# (O) vccccccccscccccccsecsesecsseeeeecsiee 88 A133 PRDY# (O) vccccccccccccccseeeeeessseeeessssee 88 A134 PREQH (I) .ccccccccccsescs cesses 88 A135 PWRGOOD ()...cccsccsscssseeeeeeeseeee 88 A1.36 REQ(4:0}# (VO)... ccccccssssevessssseensen 88 A.1.37 RESET# (I) A.1.38 RP# (I/O)... A.1.39 RS[2:0}# (I) A140 RSP# (Do ee 89 A141 SLOTOCC# (O) oe 89 A142 SLP# (Do cette 90 A143 SME (lee 90 A144 STPCLK# (I) oe 90 AA A454 TCK (I) ore 30 AT 46 TDI (Decrees 30 A147 TBO (0). ees 90 A148 TESTHI (I). ee 30 A149 THERMTRIP# (O} oe 90 A150 TMS (l) oo cee A151 TRDY# (I) ee A.1.52 TRST# (I) ..... A.1.53 VID[4:0] (O) A.2 SIGNAL SUMMARIES... eee eee cena 91 FIGURES Figure 1. Second Level (L2) Cache Implementations .........c cc ceeeeeeeeeeeeeee 7 Figure 2. GTL+ Bus Topology... ee 9 Figure 3. Stop Clock State Machine... Figure 4. Timing Diagram of System Bus Multiplier Signals... eee 14 Figure 5. Example Schematic for System Bus Multiplier Pin Sharing ..............0.0 15 Figure 6. BCLK to Core Logic Offset .....0.0000.0... 32 Figure 7. BOLK, TCK, PICCLK Generic Clack Wave Fortn oc ccecceececeereereeeceeeees 32 Figure 8. System Bus Valid Delay Timings......... 33 Figure 9. System Bus Setup and Hold Timings ..33 Figure 10. FRC Mode BCLK to PICCLK Timing .34 Figure 11. System Bus Reset and Configuration THMINGS eee eee eeeeeeenenteneees 34 Figure 12. Power-On Reset and Configuration THMUINGS eee eee eee ce eeeeeeeneneeneees 35 Figure 13. Test Timings (TAP Connection)......... 36 Figure 14. Test Reset Timings... 36 Figure 15. BCLK, TCK, PICCLK Generic Clock Wave form at the Processor Edge FINQETS ooo. eneeeeeeeeeetneeeeeee 37 INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Figure 16. Low to High GTL+ Receiver Ringback TOlOraAN CE oo. eee eect tees 38 Figure 17. Non-GTL+ Overshoot/Undershoot and RINQDACK 2 cere eects 40 Figure 18. Processor 8.E.C. Cartridge Thermal PH ALG cece cceeeeeeceeeeeeeeeeeeeereeeeereeates 42 Figure 19. Processor Thermal Plate Temperature Measurement Location.............006 44 Figure 20. Technique for Measuring TPLATE with O Angle Attachment... 45 Figure 21. Technique for Measuring TPLATE with 90 Angle Attachment..............0c8 45 Figure 22. Guideline Locations for Cover Temperature (TCOVER) Thermocouple Placement.............. 46 Figure 23. Processor with an Example Low Profile Heatsink Attached using Spring CHIPS oo. ec eeeceeeceeeeeneeeeeeenreeeeeenseneeates 46 Figure 24. Processor with an Example Full Height Heatsink Attached using Spring CHIPS oo. ec eeeceeeceeeeeneeeeeeenreeeeeenseneeates 47 Figure 25. Heatsink Recommendations and Guidelines for Use with Rivscrews* ... 48 Figure 26. Heatsink Rivscrew* and Thermal Plate Recommendations and Guidelines.....48 Figure 27. General Rivscrew* Heatsink Mechanical Recommendations .......... 49 Figure 28. Heatsink Attachment Mechanism Design Space 0.0... ee 50 Figure 29. 3.E.C. Cartridge Thermal Plate and Cover Side Views ...0.0. cece 52 Figure 30. 8.E.C. Cartridge Overall Cartridge DIMENSIONS 0.0... eee ee eee eeeeee 53 Figure 32. 3.E.C. Cartridge Thermal Plate and Side View Dimensions...............0.05 55 Figure 33. 8.E.C. Cartridge Thermal Plate Flatness Dimensions ...........0..0eeee 56 Figure 34. 3.E.C. Cartridge Latch Details........... 57 Figure 35. 3.E.C. Cartridge Latch Arm, Thermal Plate Lug, and Cover Lug DIM@NSIONS 0.0... eee eter eeeeeee 58 Figure 36. 3.E.C. Cartridge Mark Locations... 59 Figure 37. 8.E.C. Cartridge Bottom Side View...60 Figure 38. 3.E.C. Cartridge Substrate DIMENSIONS .........cceccceeseeesesssseeereeseeees 61 Figure 39. 3.E.C. Cartridge Substrate Dimensions, Cover Side View............ 61 Figure 40. Substrate S.E.C. Cartridge Substrate Detail Aw... ccc eeeee neers 62 Figure 41. Conceptual Boxed Pentiur || Processor in Retention Mechanism... 73 Figure 42. Side View Space Requirements for the Boxed Processor (fan heatsink supports not shown) ............. 74 Figure 43. Front View Space Requirements for the Boxed Processor ............ccee 75 Figure 44. Top View Space Requirements for the Boxed Processor ooo... ee 75 Figure 45. Heatsink Support Hole Locations and SIZES eee eeeeneeeeeneneeeeeees 7 Figure 46. Side View Space Requirements for Boxed Processor Fan/Heatsink SUPPOT HS... cere eee 78 Figure 47. Top View Space Requirements for Boxed Processor Fan/Heatsink SUPPOT HS... cere eee 7g Figure 48. Boxed Processor Fan/Heatsink Power Cable Connector Description.............. 80 Figure 49. Recommended Motherboard Power Header Placement Relative to Fan Power Connector and Slot 1......0.00..... 81 Figure 50. PWRGOOD Relationship at POWOr-O1. oc ccccccc cece eceaeenseeseeeenee ag TABLES Table 1. Core Frequency to System Bus Multiplier Configuration ..........0...0.0.. Table 2. Voltage Identification Definition Table 3. Recommended Pull-Up Resistor Values (Approximate) for CMOS Signals oe 18 Table 4. Pentium || Processor/Slot 1 System Bus Signal Groups... 19 Table 5. Pentium || Processor Absolute Maximum Ratings .........0..0 cece i Table 6. Pentium II Processor Voltage and Current Specifications... 22 Table 7. GTL+ Signal Groups BC Specifications... ee 25 Table 8. Non-GTL+ Signal Groups DC Specifications... ee 25 Table 9. Pentium || Processor GTL+ Bus Specifications... ee ceeeeeeeeeees 26 5 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 10. System Bus AC Specifications (COCK) oo eerie cree eee 27 Table 11. Valid Slot 1 System Bus, Core Frequency and Cache Bus Frequenci@s 0.0.0... e ee eeeeeeeee reece 28 Table 12. GTL+ Signal Groups System Bus AC Specifications... ee 28 Table 13. System Bus AC Specifications (CMOS Signal Group)... ee 29 Table 14. System Bus AC Specifications (Reset Conditions)... eeeeeeeeseeeeseeeeeeees 29 Table 15. System Bus AC Specifications (APIC Clack and APIC VO) oe 30 Table 16. System Bus AC Specifications (TAP Connection)... cee eceeeseerereseeererees 31 Table 17. BCLK Signal Quality Specifications ....37 Table 18. GTL+ Signal Groups Ringback TOlGPANCE oo ec cere creer ee ates 38 Table 19. Signal Ringback Specifications for Non- GTL+ Signals... ee Al Table 20. Pentium || Processor Thermal Design Specification... eeeceeeceeeeeees 43 Table 21. Example Thermal Solution Performance for 266 MHz Pentium II Processor at Thermal Plate Power of 37.0 Watts... ccc ceccseesceeeeeeenes 43 Table 22. 8.E.C. Cartridge Materials 0.00.00... Table 23. 8.E.C. Cartridge Dimensions Table 24. Description Table for Processor Markings oo... ee 59 Table 25. Signal Listing in Order by Pin NUMDBED oo. ceeeeee essere ceeeneeneeteeeeaes 63 Table 26. Signal Listing in Order by Signal La 68 Table 27. Boxed Processor Fan/Heatsink Spatial DIMONSIONS 2... eect etree eee 75 Table 28. Boxed Processor Fan/Heatsink Support Dimensions........0.00. 76 Table 29. Fan/Heatsink Power and Signal Specifications... eee 80 Table 30. BRO# (I/O) and BR1# Signals Rotating INbErCONMMEC eee ee eee eneeeee 85 Table 31. BR[1:0]# Signal Agent IDs... 85 Table 32. Slot 1 Occupation Truth Table ............ 8g Table 33. Output Signals ve Table 34. Input Signals......0.0... eects Table 35. Input/Output Signals (Single Driver)....93 Table 36. Input/Output Signals (Multiple Driver) .93 INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 1.0. INTRODUCTION The Pentium!l processor is the next in the Intel386, Intel486, Pentium and Pentium Pro line of Intel processors. The Pentium II processor, like the Pentium Pro processor, implements a Dynamic Execution micro-architecture a unique combination of multiple branch prediction, data flow analysis and speculative execution. This enables the Pentium ll processor to deliver higher performance than the Pentium processor, while maintaining binary compatibility with all previous Intel architecture processors. The Pentium Il processor also executes MMX technology instructions for enhanced media and communication performance. The Pentium ll processor utilizes multiple low-power states such as AutoHALT, Stop- Grant, Sleep and Deep Sleep to conserve power during idle times. The Pentium Il processor utilizes the same multi- processing System Bus technology as the Pentium Pro processor. This allows for a higher level of performance for both uni-processor and two-way multi-processor (2-way MP) systems. Memory is cacheable for up to 512 MB of addressable memory space, allowing significant headroom for business desktop systems. The Pentium Il processor System Bus operates in the same manner as the Pentium Pro processor System Bus. The Pentium Il processor System Bus uses GTL+ signal technology. The Pentium Il processor deviates from the Pentium Pro processor by using commercially available die for the L2 cache. The L2 cache (the TagRAM and burst pipeline synchronous static RAM (BSRAM) memories) are now multiple die. Transfer rates between the Pentium Il processor core and the L2 cache are one-half the processor core clock frequency and scale with the processor core frequency. Both the TagRAM and BSRAM receive clacked data directly from the Pentium II processor core. As with the Pentium Pro processor, the L2 cache does not connect to the Pentium II processor System Bus (see Figure 1}. As with the Pentium Pro processor, the Pentiumll processor has a dedicated L2 bus, thus maintaining the dual independent bus architecture to deliver high bus bandwidth and high performance (see Figure 1). The Pentium ll processor utilizes Single Edge Contact (8.E.C.) cartridge packaging technology. The S.E.C. cartridge allows the L2 cache to remain tightly coupled to the processor, while enabling use of high volume commercial SRAM components. The L2 cache is performance optimized and tested at the package level. The $.E.C. cartridge utilizes surface mount technology and a substrate with an edge finger connection. The S.E.C. cartridge introduced on the Pentium || processor will also be used in future Slat 1 processors. The $.E.C. cartridge has the following features: a thermal plate, a cover and a substrate with an edge finger connection. The thermal plate allows standardized heatsink attachment or customized thermal solutions. The full enclosure also protects the surface mount components. The edge finger connection maintains socketability for system configuration. The edge finger connector is noted as Slot 1 connector in this and other documentation. i rs es Daaneesed eee Processor Core L2 Pentium Pro Processor Dual Die Cavity Package Schematic only Pentium Il Processor Subsirate and Components OO0rSBc Figure 1. Second Level (L2) Cache Implementations INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 1.1. Terminology In this document, a # symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the # symbol implies that the signal is inverted. For example, D[3:0] = 'HLHL refers to a hex A, and D#[3:0] = LHLH also refers to a hex A (H= High logic level, L= Low logic level). The term System Bus refers to the interface between the processor, system core logic (a.k.a. the PClset components) and other bus agents. The System Bus is a multiprocessing interface to processors, memory and I/O. The term Cache Bus refers to the interface between the processor and the L2 cache components (TagRAM and BSRAMs). The Cache Bus does NOT connect to the System Bus, and is not visible to other agents on the System Bus. 1.1.1. S.E.c. CARTRIDGE TERMINOLOGY The following terms are used often in this document and are explained here for clarification: Pentium Il processor The entire product including internal components, substrate, thermal plate and cover. S.E.C. cartridge The new processor packaging technology is called a Single Edge Contact cartridge. Processor substrate The structure on which the components are mounted inside the S.E.C. cartridge (with or without components attached). Processor core The processor's execution engine. Thermal plate The surface used to connect a heatsink or other thermal solutions to the processor. Cover The processor casing on the opposite side of the thermal plate. Latch Arms A processor feature that can be utilized as a means for securing the processor in the retention mechanism. Additional terms referred to in this and other related documentation: Slot 1 The connector that the 3.E.C. cartridge plugs into, just as the Pentium Pro processor uses Socket 8. Retention mechanism An enabled mechanical piece which holds the package in the Slot 1 connector. Heatsink support The support pieces that are mounted on the motherboard to provide added support for heatsinks. The L2 cache (TagRAM, BSRAM}) dies keep standard industry names. 1.2. References The reader of this specification should also be familiar with material and concepts presented in the following documents: AP-485, Infef Processor Identification With the CPUID Instruction (Order Number 241618) AP-585, Pentium if Processor GTlL+ Guidelines (Order Number 243330) AP-586, Penitum Hf Processor Thermal Design Guidelines (Order Number 243333) AP-587, Pentium If Processor Power Disiribution Guidelines (Order Number 243332) AP-588, Mechanical and Assembly Technology for S.E.C. Cariridge Processors (Order Number 243333) AP-589, Pentium H Processor Efectro-Magnetic Interference (Order Number 243334) Pentium Hf Processor Specificalion Update (Order Number 243337) Pentium If Processor YO Buffer Models, IBIS Format (Electronic Form) Pentium ff Processor Developer's Manuaf (Order Number 243341} intel Architecture Software Developer's Manual Volume f Basic Architecture (Order Number 243190 Volume Hf: Instruction Set Reference (Order Number 243191} Volume Hi: System Programming Guide (Order Number 243192) INTEL SECRET (until publication date)2.0. ELECTRICAL SPECIFICATIONS 2.1. The Pentium Il Processor System Bus and Vrer Most of the Pentium Il processor signals use a variation of the low voltage Gunning Transceiver Logic {(GTL) signaling technology. The Pentium Il processor System Bus specification is similar to the GTL specification, but has been enhanced to provide larger noise margins and reduced ringing. The improvements are accomplished by increasing the termination voltage level and controlling the edge rates. Because this specification is different from the standard GTL specification, it is referred to as GTL+ in this document. For more information on GTL+ specifications, see AP-585, Pentium Ii Processor GTL+ Guidelines (Order Number 243330). The GTL+ signals are open-drain and requires termination to a supply that provides the high signal level. The GTL+ inputs use differential receivers which require a reference signal (VReF). Termination (usually a resistor at each end of the signal trace) is used to pull the bus up to the high voltage level and to control reflections on the transmission line. Vaer is used by the receivers to determine if a signal is a logical O or a logical 1, and is generated on the S.E.C. cartridge for the processor core. The processor contains termination resistors that provide termination for one end of the Pentium Il processor System Bus. Termination (usually a resistor on each end of the signal trace) is used to pull the bus up to the high voltage level and to control reflections on the transmission line. See Table 9 for the bus termination voltage specifications for GTL+ and the Penifur I! Processor Developer's Manual (Order Number intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 243341) for the GTL+ bus specification. Veer is generated on the S.E.C. cartridge for the Pentium Il processor core. Local Verr copies should be generated on the motherboard for all other devices on the GTL+ System Bus. Figure 2 is a schematic representation of GTL+ bus topology with the Pentium II processor. The GTL+ bus depends on incident wave switching. Therefore timing calculations for GTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the Pentium Il processor System Bus including trace lengths is highly recommended when designing a system with a heavily loaded GTL+ bus. See Intels World Wide Web page (http://www.intel.com) to download the buffer models, Pentium I] Processor YO Buffer Modeis, |BIS Format (Electronic Form). 2.2. Clock Control and Low Power States The Pentium |! processor allows the use of AutoHALT, Stop-Grant, Sleep and Deep Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure3 for a visual representation of the Pentium Il processor law power states. For the processor to fully realize the low current consumption of the Stop-Grant, Sleep and Deep Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at O2AH (Hex), bit 26 must be set to a 1 (this is the power on default setting) for the processor to stop all internal clocks during these modes. For more information, see the Pentum if Processor Developer's Manual (Order Number 24334 1). No Stubs Pentium |I ASIC Processor ASIC Pentium II Processor LYN /~_] OOta1B Figure 2. GTL+ Bus Topology INTEL SECRET (until publication date)PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ HALT Instruction and HALT Bus Cycle Generated 2. Auto HALT Power Down State BCLK running. INIT#, BINIT#, INTR, NMI, Snoops and interrupts allowed. | SMi# RESET# gs 1. Normal State Normal execution. Snoop STPCLK# STPCLK# Event Asserted De-asserted Occurs 4. HALT/Grant Snoop State Snoop Event Occurs 3. Stop Grant State BCLK running. BCLK running. Service snoops to caches. Snoop Event Serviced Snoops and interrupts allowed. SLP# SLP# Asserted De-asserled 5. Sleep State BCLK running. No snoops or interrupts allowed. BCLK BCLK Input Input Stopped Restarted 6. Deep Sleep State BCLK stopped. No snoops or interrupts allowed. Brora Figure 3. Stop Clock State Machine Due to the inability of processors to recognize bus transactions during Sleep state and Deep Sleep state, two-way MP systems are not allowed to have one processor in Sleep/Deep Sleep state and the other processor in Normal or Stop-Grant states simultaneously. 2.2.1. NORMAL STATE STATE 1 This is the normal operating state for the processor. 10 2.2.2. AUTO HALT POWER DOWN STATE STATE 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from the SMI handler can be to either Normal Mode or the AutoHALT Power Down state. See the Inief Architecture Software Developer's Manual, Volume Hil: Sysiem Programming Guide (Order Number 243192) for more information. INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ FLUSH# will be serviced during AutoHALT state and the processor will return to the AutoHALT state. The system can generate a STPCLK# while the processor is in the AutaHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. 2.2.3. STOP-GRANT STATE STATE 3 The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted. Since the GTL+ signal pins receive power from the System Bus, these pins should not be driven (allowing the level to return to V7q) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the System Bus should be driven to the inactive state. FLUSH# will be serviced during Stop-Grant state and the processor will return to the Stop-Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop- Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the System Bus (see Section 2.2.4.). A transition to the Sleep state (see Section 2.2.5.) will occur with the assertion of the SLP# signal. While in the Stop-Grant state, SMI#, INIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. 2.2.4, HALT/GRANT SNOOP STATE STATE 4 The processor will respond to snoop transactions on the Slot 1 processor System Bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the Slot1 processor System Bus has been serviced (whether by the processor or another agent on the Slot1 by the processor or another agent on the Slot 1 processor System Bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate. 2.2.5. SLEEP STATE STATE 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing the processor to enter the Sleep state. The SLP# pinis not recognized in the Normal or AutoHALT states. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep state, by stopping the BCLK input (see Section 2.2.6.) Once in the Sleep or Deep Sleep states, the SLP# pin can be deasserted if another asynchronous System Bus event occurs. The SLP# pin has a minimum assertion of one BCLK period. 11 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 2.2.6. DEEP SLEEP STATE STATE 6 The Deep Sleep state is the lowest power state the processor can enter while maintaining context. The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after the BCLK is stopped. It is recommended that the BCLK input be held low during the Deep Sleep state. Stopping of the BCLK input lowers the overall current consumption to leakage levels. To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals are allowed on the System Bus while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. 2.27. CLOCK CONTROL AND LOW POWER MODES The processor provides the clock signal to the L2 cache. During AutoHALT Power Down and Stop- Grant states, the processor will process the snoop phase of a System Bus cycle. The processor will not stop the clock data to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into the HALT/Grant Snoop state will allow the L2 cache to be snooped, similar to Normal state. When the processor is in Sleep and Deep Sleep states, it will not respond to interrupts or snoop transactions. During Sleep state, the clock to the L2 cache is not stopped. During the Deep Sleep state, the clock to the L2 cache is stopped. The clock to the L2 cache will be restarted only after the internal clocking mechanism for the processor is stable (i-e., the processor has re-entered Sleep state). The PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states. The PICCLK can be removed during the Sleep or Deep 12 Sleep states. When transitioning from the Deep Sleep to Sleep states, the PICCLK must be restarted with the BCLK. 2.3. Power and Ground Pins As future versions of Pentium|! processors are released, the operating voltage of the processor core and of the L2 cache die may differ from each other. There are two groups of power inputs on the Pentium Il processor package to support the possible voltage difference between the two components in the package. There are also five pins defined on the package for voltage identification (VID). These pins specify the voltage required by the processor core. These have been added to cleanly support voltage specification variations on current and future Pentium II processors. For clean on-chip power distribution, Pentium II processors have 27 Vcc (power) and 30 Vss (ground) inputs. The 27 Vcc pins are further divided to provide the different voltage levels to the components. Veccore inputs for the processor core and seme L2 cache components account for 19 of the Vcc pins, while 4 Vr7 inputs (1.5 V) are used to provide a GTL+ termination voltage to the processor and 3 Vccie inputs (3.3 V) are for use by the L2 cache TagRAM and BSRAMs. One Vccs pin is provided for use by the Slot 1 Test Kit. Vccs, Vecte, and Veccore must remain electrically separated from each other. On the circuit board, all Veccore pins must be connected to a voltage island and all Vcc_2 pins must be connected to a separate voltage island (an island is a portion of a power plane that has been divided, or an entire plane). Similarly, all Vss pins must be connected to a system ground plane. 2.4. Decoupling Guidelines Due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This causes voltages on power planes to sag below their nominal value if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in this document. Failure to do so can result in timing violations or a reduced lifetime of the component. INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep an interconnect resistance from the regulator (or VRM pins) to the Slot 1 connector of less than 0.5m. This can be accomplished by keeping a maximum distance of 1.5 inches between the regulator output and Slot 1 connector. The recommended Vcccore interconnect is a 2.0 inch wide (the width of the YVRM connector) by 1.5inch long {maximum distance between the Slot 1 connector and the VRM connector) plane segment with a standard 1-ounce plating. Bulk decoupling for the large current swings when the processor is powering on, or entering/exiting low power states, is provided on the voltage regulation module (VRM) defined in the Pentium i! Processor Power Distribution Guidelines. The Vcccore input should be capable of delivering a recommended minimum dicccore/dt (defined in Table 6) while maintaining the tolerances (also defined in Table 6). 2.4.1. SYSTEM BUS GTL+ DECOUPLING The Pentium Il processor contains high frequency decoupling capacitance on the processor substrate; however, bulk decoupling must be provided for by the system motherboard for proper GTL+ bus operation. See AP-585, Pentium Hf Processor GTL+ Guidelines (Order Number 243330); AP-587, Pentium If Processor Power Disiribution Guidelines (Order Number 243332); and Pentium if Processor Developer's Manual (Order Number 243341) for more information. 2.5. Pentium Il Processor System Bus Clock and Processor Clocking The BCLK input directly controls the operating speed of the Pentium || Processor System Bus interface. All Pentium || Processor System Bus timing parameters are specified with respect to the rising edge of the BCLK input. The Pentium ll processor core frequency must be configured during Reset by using the A2ZOM#, IGNNE#, LINT[1]//NMI and LINT[OVINTR pins. (See Table 1.) The value on these pins during Reset determines the multiplier that the PLL will use for the internal core clock. See the Pentium if Processor Developer's Manual (Order Number 243341) for the definition of these pins during Reset and the operation of the pins after Reset. See Figure 4 for the timing relationship between the System Bus multiplier signals, RESET#, CRESET# and normal processor operation. Table 1 is a list of multisliers supported. All other multipliers are not authorized or supported. Using CRESET# (CMOS reset on the baseboard), the circuit in Figure 5 can be used to share these configuration signals. The component used as the multislexer must not have outputs that drive higher than 2.5 V in order to meet the Pentium II processor's 2.5 V tolerant buffer specifications. The multiplexer output current should be limited to 200 mA maximum, in case the Vcccore supply to the processor ever fails. As shown in Figure 4, the pull-up resistors between the multiplexer and the processor (330 9) force a ratio of 42 into the processor in the event that the Pentium ll processor powers up before the multislexer and/or the core logic. This prevents the processor from ever seeing a ratio higher than the final ratio. If the multiplexer were powered by Vccos, a pull- down could be used on CRESET# instead of the four pull-up resistors between the multiplexer and the Pentium Il processor. In this case, the multiplexer must be designed such that the compatibility inputs are truly ignored, as their state is unknown. The compatibility inputs to the multiplexer must meet the input specifications of the multiplexer. This may require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already compatible. For FRC mode operation, the multiplexer will need to be clocked using BCLK to meet setup and hold times to the processors. This may require the use of high speed programmable logic. Multiplying the bus clock frequency is required to increase performance while allowing for cost effective distribution of signals within a system. The System Bus frequency multipliers supported are shown in Table 11; other combinations will not be validated nor are they authorized for implementation. 13 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 1. Core Frequency to System Bus Multiplier Configuration Ratio of System Bus to Processor Core Frequency LINT[1] LINT[O] A20M# IGNNE# 1/2 L L L 1/4 15 a7 2/9 1/2 L L L L H oe ee ee ee xioyxoyry cyst Boley ocycyrcye Ke LVI VAAL VS LJ LA LS RESET# \ df m7 ( ( y . CRESET# \. s ! . | System . . Bus <Final Ratio Final Ratio Multiplier Compatibility OOts17a Figure 4. Timing Diagram of System Bus Multiplier Signals INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 25V 254 1KQ Mux i AzoM# Pentium? Il Processors IGNNE# LINT1/NMI | LINTO/INTR Set Ratio: ? i i ? CRESET# ors Figure 5. Example Schematic for System Bus Multiplier Pin Sharing 15 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Clock multiplying within the processor is provided by the internal Phase Lock Loop (PLL), requiring a constant frequency BCLK input. The System Bus frequency ratio cannot be changed dynamically during normal operation, nor can it be changed during any low power modes. The System Bus frequency ratio can be changed when RESET# is active, assuming that all Reset specifications are met. The BCLK frequency should not be changed in Deep Sleep state. (See Section 2.2.6.) 2.5.1. MIXING PROCESSORS OF DIFFERENT FREQUENCIES Mixing processor of different internal clock frequencies is not fully supported and has not been validated by Intel. Intel recommends using identical steppings of processor running at the same core/system frequencies. 2.6. Voltage Identification There are five voltage identification pins on the Pentium Il processor/Slat 1 connector. These pins can be used to support automatic selection of power supply voltages. These pins are not signals, but are either an open circuit or a short circuit to Vsg on the processor. The combination of opens and shorts defines the voltage required by the processor core. The VID pins are needed to cleanly support voltage specification variations on the Pentium II and future processors. These pins (VID[O] through VID[4]) are defined in Table 2. A 1 in this table refers to an open pin and a 0 refers to a short to ground. The definition provided below is a superset of the definition previously defined for the Pentium Pro processor. The power supply must supply the voltage that is requested or disable itself. Table 2 provides the definition of VID[4:0]. To ensure the system is ready for Pentiumll processor variations, the range of values which are in BOLD in Table 2 must be supported. A smaller range will risk the ability of the system to migrate to a higher performance processor. A wider range provides more flexibility and is acceptable. Support for a wider range of VID settings will benefit the system in meeting the power requirements of future processors. Note that the 11111? (all opens) ID can be used to detect the absence of a processor core in a Slot 1 connector as long as the power supply used does not affect these lines. Detection logic and pull-ups should not affect VID inputs at the power source. (See Section A.1.53.) The VID pins should be pulled up to a TTL- compatible level with external resistors to the power source of the regulator only if required by the regulator or external logic monitoring the VID[4:0] signals. The power source chosen must be guaranteed to be stable whenever the supply to the voltage regulator is stable. This will prevent the possibility of the processor supply going above 2.8 V in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can be accomplished by using the input voltage to the converter for the VID line pull-ups. A resistor of greater than or equal to 10K ohms should be used to connect the VID signals to the converter input. See the Pentium il Processor Power Distribution Guidelines for further information on power supply specifications for the Pentium Il processor and future Slot 1 processors. INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 2. Voltage Identification Definition. 2. 3 Processor Pins VID2 vID1 VIDO Veccore Reserved a 4 4 = 4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1.804 1.854 1.904 1.954 2.004 2.054 No Core 2.14 2.2 4 2.34 2.44 2.54 2.64 2.74 2.84 2.9 3.0 3.1 3.2 3.3 3.4 3.5 aff ef} ep ep ep ee Pe ee ae Pe eK PR eK LO OP Os Oy Os Oy Oy oy oy oy oy oy oy ote i i 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 oOTPo;o;oy]f/e]/ eye oy oy oy oye] fy] Hy ep Oy Oy oy oy eH] eH ey ey Oy oy oy oy ey ey oO7oO;/-/oyoy Hf] Hoy oy eH] ] HP Oy oy KH] KH PO Oy eH] KP Oy oy ey Key Oy oy ey ey oy ol OF] os] os] os] oy] oye] Oye Oye Oye Oye Oy ep oOy ey oy eT ol ep orlcsy co NOTES: 1. 2, 3. 4. 0 = Processor pin connected to Vss. 1 = Open on processor; may be pulled up to TTL Viq on motherboard. See the Peniium@ 'f Processor Power Distribution Guidelines (Order Number 243332}. VRM output should be disabled for Veccore values less than 1.80 V. To ensure the system is ready for Pentium II processor variations, the values in BOLD in Table 2 must be supported. 17 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 2.7. Pentium Il Processor System Bus Unused Pins All RESERVED pins must remain unconnected. Connection of Reserved pins to Veccore, Vccie, Vss or to any signal can result in component malfunction or incompatibility with future Slot 1 products. See Section 5.2. for a pin listing of the processor and the location of each Reserved pin. All TESTHI pins must be connected to 2.5 V viaa pull-up resistor of between 1 and 10 KQ value. PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to 2.5 V even when the local APIC will not be used. A separate pull-up resistor must be provided for each PICD line (see Table 3 for recommended values). Table 3. Recommended Pull-Up Resistor Values (Approximate) for CMOS Signals. 2.3 Recommended Resistor Value (Approximate) CMOS Signal 150 TBO, TMS, PICD[O}#, PICD[1]# 150 220 FERR#, IERR#, THERMTRIP# 150 330 A20M#, IGNNE#, INIT#, LINTL1}NMI, LINTTOVINTR, PWRGOCD, SLP#, PREQG#, TDI 410 STPCLK#, SMI# 500 FLUSH# NOTES: 1. These resistor values are recommended for system implementations using open drain CMOS buffers. 2. These approximate resistor values are for proper operation of debug tools only A ~150 pull-up resistor is expected for these signals. 3. The TRST# signal must be driven low at power on reset. This can be accomplished with a 680 pull- down resistor. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. Unused GTL+ inputs should be left as no connects; GTL+ termination is provided on the processor. Unused active low CMOS inputs should be connected to 2.5V. Unused active high inputs should be connected to ground (Vss). Unused outputs can be left unconnected. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused pins, itis suggested that ~10 K2 resistors be used for pull-ups {except for PICD[1:0] as discussed above) and ~1 K& resistors be used for pull-downs. 2.8. Pentium Il Processor System Bus Signal Groups In order to simplify the following discussion, the Pentium II processor System Bus signals have been combined into groups by buffer type. All Pentium II processor System Bus outputs are open drain and require a high-level source provided externally by the termination or pull-up resistor. GTL+ input signals have differential input buffers, which use Vper as a reference signal. GTL+ output signals require termination to 1.5 V. In this document, the term GTL+ Input refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, GTL+ Output refers to the GTL+ output group as well as the GTL+ I/O group when driving. EMI pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0 ) resistors. The zero ohm resistors should be placed in close proximity to the Slot 1 connector. The path to chassis ground should be short in length and have a low impedance. The CMOS, Clock, APIC and JTAG inputs can each be driven from ground to 2.5 V. The CMOS, APIC and JTAG outputs are open drain and should be pulled high to 2.5 V. This ensures not only correct operation for the Pentium ll processor, but compatibility for future Slot 1 products as well. See Table 3 for recommended pull-up resistor values on each CMOS signal. 150 resistors are expected on the PICD[1:0] lines. Other values in Table3 are specified for proper logic analyzer and test mode operation only. The groups and the signals contained within each group are shown in Table 4. Refer to Appendix A for descriptions of these signals. INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 4. Pentium Il Processor/Slot 1 System Bus Signal Groups Group Name Signals GTL+ Input BPRI#, BRi#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# GTL+ Output PRDY# GTL+ VO A[35:3}4, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0}#, BRO#!, D[63:0}#, DBSY#, DEP[7:0]}#, DRDY#, FRCERR, HIT#, HITM#, LOCK#, REQ([4:0}#, RP# CMOS Input A20M#, FLUSH#, IGNNE#, INIT#, LINTO/INTR, LINT1/NMI, PREG#, PWRGOOD2, SMI#, SLP#3, STPCLK# CMOS Output FERR#, IERR#, THERMTRIP#4 Host Bus Clock BCLK APIC Clock PICCLK APIC I/5 PICD[1:0] TAP InputS TCK, TDI, TMS, TRST# TAP Outputs TDO Power/Others ee oORE: Vecz, Vecs, VID[4:0], Vit, Vgs, SLOTOCC#, TESTHI, BSEL#, NOTES: 1. The BRO# pin is the only BREQ signal that is bi-directional. The internal BREQ# signals are mapped onto BR# pins after the agent ID is determined. See Appendix A for more information. aur wh See Section A.1.35 for information on the PWRGOOD signal. See Section 2.2.5 and Section A.1.42 for information on the SLP# signal. See Section 4.1.49 for information an the THERMTRIP# signal. These signals are specified for 2.5 V operation. See Table 3 for recommended pull-up resistor values. Veccore is the power supply for the processor core and L2 cache I/O logic. Vecca is the power supply for the L2 cache component core logic. VID[4:0] is described in Section 2.6. V1 is used to terminate the System Bus and generate Vaer on the processor substrate. Vss is system ground. TESTHI should be connected to 2.5 V with a 1K-10K ohm resistor. Vec5 is not connected to the Pentium II processor. This supply is used for the debug purposes only. SLOTOCC# is described in Section A.1.41. BSEL# should be connected at Vss. See Appendix A for EMI pin descriptions. 19 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 2.8.1. ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS All GTL+ signals are synchronous to BCLK. All of the CMO8, Clock, APIC and TAP signals can be applied asynchronously to BCLK, except when running two processors in FRC mode. Synchronization logic is required on all signals going to both processors in order to run in FRC mode. Also note the timing requirements for FRC mode operation. With FRC enabled, PICCLK must be 14 of BCLK and synchronized with respect to BCLK. PICCLK must always lag BCLK as specified in Table 15. All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK. 2.9. Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Pentium II processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting a 2.5 V input. Similar considerations must be made for TCK, TMS and TRST#. Two copies of each signal may be required with each driving a different voltage level. A Debug Port is described in the Pentiurr It Processor Developer's Manual (Order Number 243341). The Debug Port will have to be placed at the start and end of the TAP chain with the TD! of the first component coming from the Debug Port and the TBO from the last component going to the Debug Port. In a 2-way MP system, be cautious when including an empty Slot 1 connector in the scan chain. All connectors in the scan chain must have a processor installed to complete the chain or the system must support a method to bypass empty 20 connectors; the Slot 1 terminator substrate connects TDI to TDO. See the Pentium i! Processor Developer's Manual (Order Number 243341) for more details. 2.10. Maximum Ratings Table 5 contains Pentium || processor stress ratings only. Functional operation at the absolute maximum and minimum is not implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. 2.11. Processor DC Specifications The processor DC specifications in this section are defined at the Pentium II processor edge fingers. See Appendix A for the processor edge finger signal definitions. Most of the signals on the Pentium Il processor System Bus are in the GTL+ signal group. These signals are specified to be terminated to 1.5 V. The DC specifications for these signals are listed in Table 8. To allow connection with other devices, the Clock, CMOS, APIC and TAP are designed to interface at non-GTL+ levels. The DC specifications for these pins are listed in Table 8. Table 6 through Table 9 list the DC specifications for the Pentium Il processor. Specifications are valid only while meeting specifications for case temperature, clock frequency and input voltages. Care should be taken to read all notes associated with each parameter. INTEL SECRET (until publication date)ntel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 5. Pentium Il Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Tiorage Processor storage 40 85 C temperature Vecuall Any processor supply voltage 0.5 Operating Vv 1,2,7 with respect to Vsg Voltage +1.4 Operating Voltage +1.0 Vv 1,28 VinetLy GTL+ buffer DC input voltage 0.5 3.3 V 7 with respect to Vsg -0.3 VCC coge + 0.7 Vv 8 Vinomos CMOS buffer DC input voltage 40.5 3.3 Vv 3,7 with respect to Vss P -0.3 3.3 V 3,8 lvip Max VID pin current 5 mA IsLoToce Max SLOTOCC# pin current 5 mA Mech Max | Mechanical integrity of latch 50 Cycles 4 Latch Arms | arms Mech Max =| Mechanical integrity of 50 Insertion/ 5,6 Edge substrate edge fingers Extraction Fingers NOTES: 1. Operating voltage is the voltage to which the component is designed to operate. See Table 6. 2. This rating applies to the Veccore, Vec_e, Voos and any input (except as noted below) to the processor. 3. Parameter applies to CMOS, APIC and TAP bus signal groups only. 4. The mechanical integrity of the latch arms is specitied to last a maximum of 50 cycles. 5. The electrical and mechanical integrity of the substrate edge fingers is specified to last for 50 insertion/extraction cycles. 6. Intel has performed intemal testing showing functionality of single $.E.C. cartridge processors after 5000 insertions. While insertion/extraction cycling above 50 insertions may cause an increase in the contact resistance (above 0.1 ohms) anda degradation in the material integrity of the edge finger gold plating, it is possible to have processor functionality above the specified limit. The actual number of insertions before processor failure will vary based upon system configuration and environmental conditions. This specification applies to CPU ID 63x. This specification applies to CPU ID 65x. 21 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 6. Pentium Il Processor Voltage and Current Specifications! Symbol Parameter Freq Min Typ | Max | Unit Notes Veccore Voc for processor core 233 MHz 2.80 Vo 12,3, 15,17 266 MHz 2.80 Vo 2,3, 15,17 266 MHz 2.00 Vo 12,3, 15, 18 300 MHz 2.80 Vf 2,3, 15, 17 300 MHz 2.00 Vo 12,3, 15, 18 333 MHz 2.00 Vo [2,3, 15,18 Veco Vec for L2 cache 3.135 3.30 | 3.465 Vo13 VotT Bus termination voltage 1.365 1.5 | 1.635 Vo71.5V +3%, +9%4 Baseboard Baseboard voltage, static 0.070 0.100 VodsS Tolerance, Static tolerance level Baseboard Baseboard voltage, transient | 233 MHz | 0.150 0.150 Vo o[5,17 Tolerance, Transient | tolerance level 266 MHz | -0.150 0.150 v 15,17 266 MHz] -0.120 0.120 V 15,18 300 MHz] -0.145 0.145 V5, 17 333 MHz] -0.120 0.120 Vo 15,18 Veccore Tolerance, | Veccore voltage, static 233 MHz | -0.090 0.100 Vo 16,17 Static tolerance level 266 MHz | -0.090 0.100 v |617 266 MHz] -0.085 0.100 V 16,18 300 MHz] -0.090 0.100 V 16,18 333 MHz] -0.085 0.100 V 16,18 Veccone Tolerance, | Veccore voltage, transient 233 MHz | 0.195 0.195 Vo 16,17 Transient tolerance level 266 MHz | -0.195 0.195 v 16,17 266 MHz] -0.140 0.140 V 16,18 300 MHz |] -0.185 0.185 V 16,17 333 MHz ] -0.140 0.140 Vo 16,18 IcccoRE lec for VeccorE 233 MHz 11.8 A |2, 7,8, 16, 17 266 MHz 12.7 A |2, 7,8, 16,17 266 MHz 8.492 A |2,7, 8, 16,18 300 MHz 14.2 A | 2,7, 8, 16, 17 333 MHz 9.303 A |2,7, 8, 16,18 IccLe loc for L2 cache 14 A 13,817 1.0 A 13,8, 18 vit Termination voltage supply 27 A [9,17 current 2677 | A |9. 18 22 INTEL SECRET (until publication date)Table 6. Pentium Il Processor Voltage and Current Specifications! (Cont'd) intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Core Symbol Parameter Freq Min Typ | Max | Unit Notes Iccps_p CORE loc for Deep Sleep Veccore 0.35 A 18,17 0.35 A 1/8, 18 lccsent L2 loc for Stop-Grant for Vecye2 0.2 A | 10,17 TBD A | 10,18 Iccs_p L2 loc for Sleep Vcc 2 0.2 A 18,17 TBD A |8, 18 lccps_p L2 loc for Deep Sleep Vccye2 0.1 A |8, 17 TBD A 1/8, 18 dieceore/dt Power supply current slew 30 Ajus ]11, 12, 13, 17 rate 20 | Aus | 11, 12, 13, 18 dice 2fdt L2 cache power supply 1 Ajus | 11, 12, 13 current slew rate dlecyi/dt Termination current slew 8 AJus | See Table 9 rate 12, 13 Vices 5 V supply voltage 4.75 5.00] 5.25 Voi 14 lecs Ice for 5 V supply voltage 1.0 A | 14 23 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & NOTES: 1. apron 10. 11. 12. 13. 14. 15. 16. 17. 18. 24 Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. Ieccore and Veecore supply the processor core and the L2 cache I/O buffers. Vee.e and lec_e supply the L2 cache core. Vit must be held to 1.5 +9%. It is recommended that Viz be held to 1.5 V3% during System Bus idle. These are the tolerance requirements, across a 20 MHz bandwidth, at the Slot 1 connector pins on the bottom side of the baseboard. The requirements at the Slot 1 connector pins account for voltage drops (and impedance discontinuities) across the connector, substrate edge fingers and to the processor core. The Slot 1 connector has the follawing requirements: Pin Self Inductance: 10.5 nHi{max); Pin to Pin Capacitance: 2pF (max, at 1 MHz); Contact Resistance: 12 mQ (max averaged over power/ground contacts). Contact Intel for testing conditions of these requirements. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor substrate edge fingers. The requirements at the processor substrate edge fingers account for voltage drops (and impedance discontinuities) at the substrate edge fingers and to the processor core. The typical loccore measurements are an average current draw during the execution of Winstone* 96 on a Windows* 95 operating system. These numbers are meant as a guideline only, not a guaranteed specification. Actual measurements will vary based upon system environmental conditions and configuration. Max lcc measurements are measured at Vcc nominal voltage under maximum signal loading conditions. The current specitied is the current required for a single Pentium II processor. A similar current is needed for the opposite end of the GTL+ bus. The current specitied is also for AUtoHALT Power Down state. Maximum values are specitied by design/characterization at nominal Vecoore and nominal Vec_. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance tolerable and reaction time of the voltage regulator. This parameter is not tested. dicc/dt is measured at the Slot 1 connector pins. Veo, and Ico; are not used by the Pentium II processor. This supply is used for debug purposes only. Use Typical Voltage Specification with tolerance level specification to provide correct voltage regulation to the processor. Voltage regulators may be designed with a minimum equivalent intemal resistance to ensure that the output voltage, at maximum current output, is no greater than the nominal voltage level of Veccore (VeccorE Typ}. In this case, the maximum current level for the regulator, loccore REG, can be reduced from the specified maximum current loccorReE MAX and is calculated by the equation: Icccore REG = lcccore max X Veccore Tye / VeccorRE Max This specification applies to CPU ID 63x. This specification applies to CPU ID 65x. INTEL SECRET (until publication date)Table 7. GTL+ Signal Groups DC Specifications intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0.3 0.82 Vv Vin Input High Voltage 1.22 Vir Vv VoL Output Low Voltage 0.60 Vv 1 Vou Output High Voltage Vit Vir Vv 4,5 Vi7+ 0.015 Vit Vv 4.6 lot Output Low Current 36 48 55 mA 12 IL Leakage Current +100 HA 2 lLo Output Leakage Current +15 HA 3 NOTES: 1. Parameter measured into a 500 resistor to 1.5 V. 2. (O05 Vin 52.5 V 45%). 3. (0<VouT= 2.5 V +5%). 4. See V7 max in Table 9. 5. This specification applies to CPU ID 63x. 6. This specification applies to CPU ID 65x. Table 8. Non-GTL+ Signal Groups DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0.3 0.7 Vv Vin Input High Voltage 1.7 2.625 Vv 2.5 V +5% maximum VoL Qutput Low Voltage 0.4 Vv 1 Vou Output High Voltage NWA 2.625 Vv All outputs are open- drain to 2.5 V +5% lot OCutput Low Current 14 mA lu Input Leakage Current +100 pA lLo Output Leakage Current +15 HA NOTES: 1. Parameter measured at 14 mA (for use with TTL inputs). 2. (O05 Vin=2.5 V 45%). 3. (08 VouTs 2.5 V +5%). INTEL SECRET 25 (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 2.12. GTL+ System Bus Specifications It is recommended to have the GTL+ bus routed ina daisy-chain fashion with termination resistors at each end of every signal trace. These termination resistors are placed electrically between the ends of the signal traces and the Vtr voltage supply and generally are chosen to approximate the substrate impedance. The valid high and low levels are determined by the input buffers using a reference voltage called Vaer. Table 9 lists the nominal specification for the GTL+ termination voltage (Vir). The GTL+ reference voltage (VReF) should be set to 2/3 Vt7 for the core logic using a voltage divider on the motherboard. It is important that the motherboard impedance be specified and held to a +20% tolerance, and that the intrinsic trace capacitance for the GTL+ signal group traces is Known. For more details on GTL+, see the Pentium If Processor Developer's Manual (Order Number 243341) and the Pentium ii Processor GTL+ Guidelines (Order Number 243330). 2.13. Pentium Il Processor System Bus AC Specifications The System Bus timings specified in this section are defined at the processor edge fingers. Timings will be tested at the processor core during manufacturing. Timings at the processor edge fingers will be specified by design characterization. See Appendix A for the Pentium Il processor edge finger signal definitions. Table 10 through Table 15 list the AC specifications associated with the Pentium Il processor System Bus. The System Bus AC specifications are broken into the following categories: Table 10 and Table 11 contain the System Bus clock core frequency and Cache Bus frequencies; Table 12 contains the GTL+ specifications Table 13 contains the CMOS signal group specifications; Table 14 contains timings for the reset conditions; Table 15 covers APIC bus timing; Table 16 covers TAP timing. All System Bus AC specifications for the GTL+ signal group are relative to the rising edge of the BCLK input. All GTL+ timings are referenced to Veer for both 0 and 1 logic levels unless otherwise specified. The timings specified in this section should be used in conjunction with the /O buffer models provided by Intel. These I/O buffer models, which include package information, are available in IBIS format on Intels Web site: hthp:/Avww.intel.com. GTL+ layout guidelines are also available in AP-585, Pentturn ii Processor GTL+ Guidelines (Order Number 243330). Care should be taken to read all notes associated with a particular timing parameter. Table 9. Pentium Il Processor GTL+ Bus Specifications! Symbol Parameter Min Typ Max Units Notes Vit Bus Termination Voltage 1.365 1.5 1.635 Vv 1.5 V 43%, +9%2 Rit Termination Resistor 56 Ohms | 45% VREF Bus Reference Voltage 2/3 Vit Vv +2%3 NOTES: 1. The Pentium || processor contains GTL+ termination resistors at the end of the signal trace on the processor substrate. The Pentium II processor generates Vacr, on the processor, by using a voltage divider on Vt> supplied through the Slot 1 connector. 2. Wr must be held to 1.5 V +9%; dlecy:/dt is specified in Table 6. It is recommended that V17 be held to 1.5 +3% during System Bus idle. 3. Vrer is generated by the processor to be 2/3 V7 nominally. 26 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 10. System Bus AC Specifications (Clock)!. 2 T# Parameter Min Nom Max Unit Figure Notes System Bus Frequency 66.67 MHz All processor core frequencies 3 TI: BCLK Period 15.0 ns 7 3,4 T1B: BCLK to Core Lagic Offset 0.78 ns 6 Absolute Values. 6 Te: BCLK Period Stability +300 ps 7,8 T3: BCLK High Time 4.70 ns 7 @>1.8V T4: BCLK Low Time 5.10 ns 7 @<0.7V T5: BCLK Rise Time 0.75 1.95 ns 7 (0.7 V-1.8 V}9 T: =BCLK Fall Time 0.75 1.95 ns 7 (1.8 V-0.7 V}9 NOTES: 1. All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 V. All GTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor edge fingers. All AC timings for the CMOS signals are referenced to the BGLK rising edge at 0.70 V at the processor edge fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to reference voltage of 1.25 V. All CMO signal timings (address bus, data bus, etc.) are referenced at 1.25 V at the processor edge fingers. The internal core clock frequency is derived from the System Bus clock. The System Bus clock to core clock ratio is determined during initialization as described in Section 2.5. Table 11 shows the supported ratios for each processor. The BCLK period allows a +0.5 ns tolerance for clock driver variation. The BCLK offset time is the absolute difference needed between the BCLK signal rising edge arriving at the Slot 1 edge finger at 0.7 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to account for the delay between the Slot 1 connector and processor core. The positive offset ensures both the processor core and the core logic receive the BCLK edge concurrently. See Section 3.1. for System Bus clock signal quality specifications. Due to the difficulty of accurately measuring processor clock jitter in a system, it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be measured on the rising edges of adjacent BCLKs crossing 1.25 V. The jitter present must be accounted for as a component of BCLK timing skew between devices. The clock driver's closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock driver. The -20 dB attenuation point of the clock driver, as measured into a 10 to 20 pF load, should be less than 500 kHz. This specification may be ensured by design and/or measured with a spectrum analyzer. Not 100% tested. Specified by design/characterization as a clock driver requirement. a7 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 11. Valid Slot 1 System Bus, Core Frequency and Cache Bus Frequencies! 2 BCLK Frequency Frequency Multipliers Core Frequency L2 Cache Frequency (MHz) Supported Rating (MHz) (MHz) 66.67 7/2 233.33 116.67 3 66.67 4 266.66 133.33 3 66.67 4 266.67 133.33 4 66.67 9/2 300.00 150.003 66.67 5 333.33 166.67 4 NOTES: 1. Gontact your local Intel representative for the latest information on processor frequencies and/or frequency multipliers. 2. While other bus ratios are defined, operation at frequencies other than those listed are not supported. 3. This specification applies to CPU ID 63x. 4. This specification applies to CPU ID 65x. Table 12. GTL+ Signal Groups System Bus AC Specifications'. 2 TH Parameter Min Max Unit Figure Notes T?: GTL+ Output Valid Delay 1.07 6.37 ns 3 3 Ta: GTL+ Input Setup Time 2.53 ns 9 4,5,6 T8: GTL+ Input Hold Time 1.53 ns 9 7 T10: RESET# Pulse Width 1.00 ms 12 8 NOTES: 1. Not 100% tested. Specified by design characterization. 2. All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge fingers. All GTL+ signal timings {address bus, data bus, etc.) are referenced at 1.00 V at the processor edge fingers. 3. Valid delay timings for these signals are specitied into 509 to 1.5 V. 4. Aminimum of 3 clocks must be specified between two active-to-inactive transitions of TRDY#. 5. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. 6. Specification is for a minimum 0.40 V swing. 7. Specification is for a maximum 1.0 V swing. 8. After Voocore, VeeLe and BCLK become stable. 28 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 13. System Bus AC Specifications (CMOS Signal Group). 2. 3 T# Parameter Min Max Unit Figure Notes T11: 2.5 V Output Valid Delay 1.00 10.5 ns 8 4 T12: 2.5 V Input Setup Time 5.50 ns 9 5,6 T13: 2.5 V Input Hold Time 1.75 ns 9 5 T14: 2.5 V Input Pulse Width, 2 BCLKs 8 Active and Inactive except PWRGOOD states T15: PWRGOCD Inactive Pulse 10 BCLKs 8 7 Width 13 NOTES: 1. Not 100% tested. Specified by design characterization. 2. All AC timings for the CMOS signals are referenced to the BGLK rising edge at 0.7 V at the processor edge fingers. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V at the processor edge fingers. 3. These signals may be driven asynchronously, but must be driven synchronously in FRO mode. 4. Valid delay timings for these signals are specified to 2.5 V +5%.. See Table 3 for pull-up resistor values. 5. To ensure recognition on a specific clock, the setup and hold times with respect to BCLK must be met. 6. INTR and NMI are only valid during APIG disable mode. LINT[1 :0]# are only valid during APIC enabled mode. 7. When driven inactive or after Voocore, Vec_: and BCLK become stable. Table 14. System Bus AC Specifications (Reset Conditions) TH Parameter Min Max Unit Figure Notes T16: Reset Configuration Signals 4 BCLKs 11 Before deassertion of (A[14:5]#, BRO#, FLUSH#, RESET# INIT#) Setup Time T17: Reset Configuration Signals 2 20 BCLKs 11 After clock that (A[14:5}#, BRo#, FLUSH#, deasserts RESET# INIT#) Hold Time T18: Reset Configuration Signals 1 ms 12 Before deassertion of (A20M#, IGNNE#, RESET# LINT[1 :0}#) Setup Time T19: Reset Configuration Signals 5 BCLKs 12 After assertion of (A20M#, IGNNE#, RESET# 1 LINT[1:0}#) Delay Time T20: Reset Configuration Signals 2 20 BCLKs 12 After clock that (A20M#, IGNNE#, 11 deasserts RESET# LINT[1 :0}#) Hold Time NOTE: 1. Fora Reset, the clock ratio defined by these signals must be a safe value (their final or lower multiplier) within this delay unless PWRGOOD is being driven inactive. 29 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 15. System Bus AC Specifications (APIC Clock and APIC I/O)'.2 T# Parameter Min Max Unit Figure Notes T21: PICCLK Frequency 2.0 33.3 MHz 3 T21B: FRC Mode BCLK to PICCLK 1.0 5.0 ns 10 3 Offset T22: PICCLK Period 30.0 500.0 ns 7 T23: PICCLK High Time 12.0 ns 7 T24: PICCLK Low Time 12.90 ns 7 T25: PICCLK Rise Time 1.0 5.0 ns 7 T26: PICCLK Fall Time 1.0 5.0 ns 7 T27: PICD[1:0] Setup Time 3.5 ns 9 4 728: PICD[1:0] Hold Time 3.0 ns 9 4 Tea: PICD[1:0] Valid Delay 3.0 12.0 ns 8 4,5,6 NOTES: 1. Not 100% tested. Specified by design characterization. 2. All AC timings for the CMOS signals are referenced to the PICCLK rising edge at 0.70 V at the processor edge fingers. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V at the processor edge fingers. 3. With FRC enabled PICCLK must be 1/4X BCLK and synchronized with respect to BCLK. 4. Referenced to PICGLK Rising Edge. 5. For open drain signals, Valid Delay is synonymous with Float Delay. 6. Valid delay timings for these signals are specified to 2.5 V +5%. See Table 3 for recommended pull-up resistor values. 30 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 16. System Bus AC Specifications (TAP Connection)! T# Parameter Min Max Unit Figure Notes T30: TOK Frequency 16.667 MHz T31: TCK Period 60.0 ns 7 T32: TCK High Time 25.0 ns 7 @1.7 V2 T33: TCK Low Time 25.0 ns 7 @0.7 V2 T34: TCK Rise Time 5.0 ns 7 (0.7 V-1.7 V}e2 T35: TCK Fall Time 5.0 ns 7 (1.7 V-0.7 Vie T36: TRST# Pulse Width 40.0 ns 14 Asynchronous? T37: TDI, TMS Setup Time 5.5 ns 13 4 T38: TBI, TMS Hold Time 145 ns 13 4 T39: TDO Valid Delay 2.0 13.5 ns 13 5,6 T40: TDO Float Delay 28.5 ns 13 2,5,6 T41: Non-Test Outputs Valid 2.0 27.5 ns 13 5,7,8 Delay T42: Non-Test Inputs Setup Time 27.5 ns 13 2,5, 7,8 T43: Non-Test Inputs Setup Time 55 ns 13 4,7,8 T44: Non-Test Inputs Hold Time 14.5 ns 13 4,7,8 NOTES: 1. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.70 V at the processor edge fingers. All TAP signal timings (address bus, data bus, etc.) are referenced at 1.25 V at the processor edge fingers. Not 100% tested. Specitied by design characterization. Referenced to TCK rising edge. Referenced to TCK falling edge. Valid delay timing for this signal is specified to 2.5 V 45%. See Table 3 for pull-up resistor values. Non-Test Outputs and Inputs are the normal output or input signals (besides TOK, TRST#, TDI, TDO and TMS). These timings correspond to the response of these signals due to TAP operations. 7. During Debug Port operation, use the normal specified timings rather than the TAP signal timings. aur wan 31 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & BCLK at Slot 1 BCLK at Core Logic oocso7 Figure 6. BCLK to Core Logic Offset NOTES FOR FIGURE 7 THROUGH FIGURE 14 1. Figure 7 through Figure 12 are to be used in conjunction with Table 8 through Table 16. 2. All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 V. Timings for other components on the baseboard should use a BCLK reference voltage of 1.25 V. All GTL+ signal timings (address bus, data bus, etc.) are reterenced at 1.00 V at the Slot 1 connector pin. 3. These measurements are collected at the Pentium II processor edge fingers. Tr > 1.8V NS 1.25V CLK 0.7V tT + TI }#_ T T, = T5, T25, T34 (Rise Time) Ty = T6, T26, T35 (Fall Time) Th= T3, T23, T32 (High Time) T, = T4, T24, T33 (Low Time) Tp = T1, T22, T31 (BLCK, TCK, PICCLK Periad) OO0T1b Figure 7. BCLK, TCK, PIGCLK Generic Clock Wave Form 32 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ CLK ~ = = Tpw | Tx = TY, T11, T29 (Valid Delay) T14, T15 (Pulse Waith) 1.0V for GTL+ signal group; 1.25V for CMOS, APIC and TAP signal groups Tpw V OOOTB2b Figure 8 System Bus Valid Delay Timings CLK Ts = T8, 112, T27 (Setup Time) Th = T9, 713, T28 (Hold Time) V = 1.0V for GTL+ signal group; 1.25V for CMOS, APIC and TAP signal groups OOCTBSb Figure 9. System Bus Setup and Hold Timings 33 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & BCLK PICCLK Lag = T21B (FRO Mode BCLK to PICCLK offset) oors19 Figure 10. FRC Mode BCLK to PICCLK Timing RESET# Configuration (A20M#, IGNNE#, Sate LINT(1 :0}4) Tw Configuration (iis on i TL T = 19 (GTL+ Input Hold Time} Ty = T8 (GTL+ Input Setup Tima) Ty = 710 (RESET# Pulse Width) Tw = 116 (Reset Configuration Signals (A[14:5]}#, BRO#, FLUSH#, INIT#) Setup Time) T, = 717 (Reset Configuration Signals (A[14:5}#, BRO#, FLUSH#, INIT#) Hold Time) T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[I :0}#) Hold Time) Ty = 719 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0}#) Delay Time) Tz = 118 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1 :0}#) Setup Time) PCB-7 64 Figure 11. System Bus Reset and Configuration Timings 34 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ eck TTT \\_L Nf NA NS NSN Veccore: VREF EL LF Vec Ls PWRGOOD tT, '+# Th a <+#T,+ Configuration wsonin ne, [TUTTLE Vala Ratio LINT(A:0}#4) __ =e Ta = 715 (PWRGOOCD Inactive Pulse Width) Ty = T10(RESET# Pulse Width} Te = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0#]) Hold Time) OOCTBSb Figure 12. Power-On Reset and Configuration Timings 35 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & TCK TDI, TMS Input Signals TBO Output Signals Tr = 743 (All Non-Test Inputs Setup Time} Ts = T44 (All Non-Test Inputs Hold Time) Ty = T40 (TDO Float Delay) Ty = T37 (TDI, TMS Setup Time) Tw = 738 (TDI, TMS Hold Time} Ty = T39 (TDO Valid Delay) Ty = T41 (All Non-Test Outputs Valid Delay) Tz = T42 (All Non-Test Outputs Float Delay) OOCTBBb Figure 13. Test Timings (TAP Connection) te TRST# 1.25V- Tg = 137 (TRST# Pulse Width) PCB-773 Figure 14. Test Reset Timings 36 INTEL SECRET (until publication date)3.0. SYSTEM BUS SIGNAL SIMULATIONS Many scenarios have been simulated to generate a set of GTL+ layout guidelines which are available in the Pentium if Processor GTL+ Guidelines (Order Number 243330). Refer to the Pentiurn If Processor Developer's Manual (Order Number 243341) for the GTL+ buffer specification. All wave terms described intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ below are simulated at the contact to the processor edge fingers. 3.1. System Bus Clock (BCLK) Signal Quality Specifications Table 17 describes the signal quality for the System Bus clock (BCLK) signal. Figure 15 describes the signal quality wave form for the System Bus clock. Table 17. BCLK Signal Quality Specifications T# Parameter Min Nom Max Unit Figure Notes Vi: BCLK ViL 0.7 V 7 V2: BCLK Vin 1.8 Vv 7 V3: Vin Absolute Voltage 0.5 3.3 Vv 7 Overshoot, Range Undershoot V4: Rising Edge Ringback 2.0 Vv 7 Absolute Valuet V5: Falling Edge Ringback 0.5 Vv 7 Absolute Valuet V6: Tline Ledge Voltage 1.0 1.7 V 7 At Ledge Midpoint? V7: Tline Ledge Oscillation 0.2 Vv 7 Peak-to-Peak3 NOTES: 1. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the Viq (rising) or Vi_ Calling) voltage limits. 2. The BOLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The midpoint voltage level of this ledge must be within the range specified. 3. The ledge (V13) is allowed to have peak-to-peak oscillation as specitied. <_ 13 41 V2 V3 V4 V6 V1 V7 | t 16 Va T4 15 oooso8 Figure 15. BCLK, TCK, PICCLK Generic Clock Wave form at the Processor Edge Fingers 37 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 18. GTL+ Signal Groups Ringback Tolerance TH Parameter Min Unit Figure Notes a Overshoot 100 mV 16 1,2 T: Minimum Time at High 15 ns 16 1,2 p: Amplitude of Ringback -250 mV 16 1,2,3 0: Final Settling Voltage 250 mv 16 1,2 8: Duration of Sequential Ringback NWA ns 16 1,2 NOTES: 1. Specified for the edge rate of 0.3 - 0.8 V/ns. See Figure 16 for the generic wave form. 2. All values determined by design/characterization. 3. Ringback Vaer +250 mV is not authorized. a i | +_ > Clk Ref -----4-- / ct VREF +0.2 x _ b VREF Py * VReF -0.2 / / 8 FE OT Clk Ref ene mene [Vatart_/ > Time NOTE: High to Low case is analogous. oooe14e Figure 16. Low to High GTL+ Receiver Ringback Tolerance 38 INTEL SECRET (until publication date)3.2. GTL+ Signal Quality Specifications Table 18 and Figure 16 describe the GTL+ signal quality specifications for the Pentium Il processor. For more information on the GTL+ interface, see the Pentium If Processor Developer's Manual (Order Number 24334 1). 3.3. Non-GTL+ Signal Quality Specifications Signals driven on the Pentium Il processor System Bus should meet signal quality specifications to ensure that the components read data properly and that incoming signals do not affect the long term reliability of the component. There are three signal quality parameters defined: Overshoot/Undershoot, Ringback and Settling Limit. All three signal quality parameters are shown in Figure 17 for non-GTL+ signal groups. intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 3.3.1. OVERSHOOT/UNDERSHOOT GUIDELINES Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below Vgs. The overshootfundershoot guideline limits transitions beyond Vcc or Vss due to the fast signal edge rates. (See Figure 17 for non-GTL+ signals.) The processor can be damaged by repeated overshoot events on 2.5 V tolerant buffers if the charge is large enough ({i.e., if the overshoot is great enough). However, excessive ringback is the dominant detrimental system timing effect resulting from overshoot/undershoot fi.e., violating the overshootundershoot guideline will make satisfying the ringback specification difficult). The overshoot/ undershoot guideline is 0.8 V and assumes the absence of diodes on the input. These guidelines should be verified in simulations without the on- chip ESD protection diodes present because the diodes will begin clamping the 2.5 V tolerant signals beginning at approximately 1.25 V above Veccore and 0.5 V below Vgs. If signals are not reaching the clamping voltage, this will not be an issue. A system should not rely on the diodes for overshoot/ undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult. 39 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Vu = Veco s A i \ Settling Limi Overshoot a imit NTN ET PN ON AN ee T Rising-Edge Ringback Falling-Edge Ringback Settling Limit fe at ' 1 | SS - \ | > Time Undershoot _ OOOTa7b 40 Figure 17. Non-GTL+ Overshoot/Undershoot and Ringback INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 3.3.2. RINGBACK SPECIFICATION Ringback refers to the amount of reflection seen after a signal has switched. The ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value. (See Figure 18 for an illustration of ringback.) Excessive ringback can cause false signal detection or extend the propagation delay. The ringback specification applies to the input pin of each receiving agent. Violations of the signal Ringback specification are not allowed under any circumstances for the non-GTL+ signals. Ringback can be simulated with or without the input protection diodes that can be added to the input buffer model. However, signals that reach the clamping voltage should be evaluated further. See Table 19 for the signal ringback specifications for non-GTL+ signals. 3.3.3. SETTLING LIMIT GUIDELINE Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. The amount allowed is 10 percent of the total signal swing (VHiVLo) above and below its final value. A signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again. Signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be done either with or without the input protection diodes present. Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions. Table 19. Signal Ringback Specifications for Non-GTL+ Signals Maximum Ringback Input Signal Group Transition (with Input Diodes Present) Figure Non-GTL+ Signals o-1 2.0V 17 Non-GTL+ Signals 1390 O.7V 17 41 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 4.0. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS The Pentium Il processor has a thermal plate for heatsink attachment. The thermal plate interface is intended to provide for multiple types of thermal solutions. This chapter will provide the necessary data for a thermal solution to be developed. See Figure 18 for thermal plate location. 4.1. Thermal Specifications Table 20 provides the thermal design power dissipation for the Pentium Il processor. While the processor core dissipates the majority of the thermal power, the thermal power dissipated by the L2 cache also impacts the thermal plate power specification and the overall processor power specification. Systems should design for the highest possible thermal power, even if a processor with a lower thermal dissipation is planned. The thermal plate is the attach location for all thermal solutions. The maximum allowed thermal plate temperature is specified in Table 6. A thermal solution should be designed to ensure the temperature of the thermal plate never exceeds these specifications. The processor power is a result of heat dissipated through the thermal plate and other paths. The heat dissipation is a combination of heat from bath the processor core and L2 cache. The overall system thermal design must comprehend the processor power. The combination of the processor core and the L2 cache dissipating heat through the thermal plate is the thermal plate power. The heatsink should be designed to dissipate the thermal plate power. See Table 20 for Pentium II processor thermal design specifications. Right Latch Cover Left Latch Thermal Plate oota21 Figure 18. Processor S.E.C. Cartridge Thermal Plate 42 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 20. Pentium Il Processor Thermal Design Specification! Max Processor Max Thermal Core L2 Cache | Processor Plate Frequency Size Power2 Power? | Min Tprate | Max Tetate | Min Tcover | Max Tcover (MHz) (kB) (W) (W) @c (C) (C) (c) 333 5 512 23.7 21.8 5 65 5 75 300 4 512 43.0 41.4 5 72 5 72 266 5 512 19.5 17.8 5 65 5 75 266 4 512 38.2 37.0 5 75 5 75 233 4 512 34.8 33.6 5 75 5 75 NOTES: 1. These values are specified at nominal Voccore tor the processor core and nominal Vco,2 (3.3 V) for the L2 cache. This specification applies to CPU ID 63x. This specification applies to CPU ID 65x. wOPewN 4.2. Pentium II Processor Thermal Analysis 4.2.1. THERMAL SOLUTION PERFORMANCE All processor thermal solutions should attach to the thermal plate. The thermal solution must adequately control the thermal plate and cover temperatures below the maximum and above the minimum specified in Table 20. The performance of any thermal solution is defined as the thermal resistance between the thermal plate and the ambient air around the processor (jihermal plate io ambient). The lower the thermal resistance between the thermal plate and the ambient air, the more efficient the thermal solution is. The required thermal plate to ambient is dependent upon the maximum allowed thermal plate temperature (TpLate), the ambient temperature (TLa) and the thermal plate power (PpLaTe). thermal plate to ambient = (TPLATE TLA) / PPLATE The maximum Tp_ate and the thermal plate power are listed in Table 20. TLa is a function of the system design. Table 21 provides the resultant thermal Processor power is 100% of processor core and 100% L2 cache power. Thermal plate power is 100% of the processor core power and a percentage of the L2 cache power. solution performance for a 266MHz Pentium Il processor at different ambient air temperatures around the processor. Table 21. Example Thermal Solution Performance for 266 MHz Pentium Il Processor at Thermal Plate Power of 37.0 Watts Thermal Solution (Performance) Local Ambient Temperature (TLa) 35C | 40C; 45C Ginermal plate io ambient 1.08 0.95 0.81 ( Gfwatt) The thermal plate to ambient Value is made up of two primary components: the thermal resistance between the thermal plate and heatsink (@tnermal plate to heatsink} and the thermal resistance between the heatsink and the ambient air around the processor (@neaisink to air). A critical but controllable factor to decrease the resultant value of thermal plale to heatsink is management of the thermal interface between the thermal plate and heatsink. Thermal interfaces are addressed in AP-586, Pentium li Processor Thermal Design Guidelines (Order Number 243333). The other controllable factor (heatsink to air) is resultant in the design of the heatsink and airflow around the heatsink. Heatsink design constraints are also provided in AP-586, Pentium if Processor Thermal Design Guidelines (Order Number 243333). 43 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 4.2.2. MEASUREMENTS FOR THERMAL SPECIFICATIONS 4.2.2.1. Thermal Plate Temperature Measurement To ensure functional and reliable Pentium Il processor operation, the thermal plate temperature (TpLaTeE) must be maintained at or below the maximum Tp_ate temperature specified in Table 20. Figure 19 shows the location for TpLate measurement. Special care is required when measuring TpLate to ensure an accurate temperature measurement. Thermocouples are used to measure Tp_ate. Before taking any temperature measurements, the thermocouples must be calibrated. When measuring the temperature of a surface, errors can be introduced in the measurement if not handled properly. The measurement errors can be due to a poor thermal contact between the thermocouple junction and the surface of the thermal plate, conduction through thermocouple leads, heat loss by radiation and convection, or by contact between the thermocouple cement and the heatsink base. To minimize these errors, the following approach is recommended: Use 36 gauge or finer diameter K, T, or J type thermocouples. Intel's laboratory testing was done using a thermocouple made by Omega* (part number: 5TC-TTK-38-36}. Attach the thermocouple bead or junction to the top surface of the thermal plate at the location specified in Figure 19 using high thermal conductivity cements. * The thermocouple should be attached at a 0 angle if no heatsink is attached to the thermal plate. If a heatsink is attached to the thermal plate but the heatsink does not cover the location specified for Tprare measurement, the thermocouple should be attached at a 0 angle {refer to Figure 20). }_ 2.673 }| Measure from edge of thermal plate. recommended heatsink attachment. Measure TeLate at this point. =g Approx. location for p- Cover ; S 1.089 e oO | Co Processor Oo Core o >) & e a/c ~ ) Now Recommended location of an 0.35 R thermal grease application. All dimensions in inches. Substrate Ooce74b Figure 19. Processor Thermal Plate Temperature Measurement Location 44 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ PLL] oocses Figure 20. Technique for Measuring TpLate with 0 Angle Attachment oonso0 Figure 21. Technique for Measuring Tp_ate with 90 Angle Attachment The thermocouple should be attached at a 90 angle if a heatsink is attached to the thermal plate and the heatsink covers the location specified for TpLrare measurement (refer to Figure 21). The hole size through the heatsink base to route the thermocouple wires out should be smaller than 0.150" in diameter. Make sure there is no contact between the thermocouple cement and heatsink base. This contact will affect the thermocouple reading. 4.2.2.2. Cover Temperature Measurement The maximum and minimum $.E.C. cartridge cover temperature (Tcover) for the Pentium II processor is specified in Table 20. This temperature specification is meant to ensure correct and reliable operation of the processor. Figure 22 illustrates the hottest points on the $.E.C. cartridge cover. Tcover thermal measurements should be made at these points. 4.3. Thermal Solution Attach Methods The design of the thermal plate is intended to support two different attach methods heatsink clips and Rivscrews*. Figure 41 shows the thermal plate and the locations of the attach features. Only one attach method should be used for any thermal solution. 43.1. HEATSINK CLIP ATTACH Figure 23 and Figure 24 illustrate example clip designs to support a low profile and a full height heatsink, respectively. The clips attach the heatsink by engaging with the underside of the thermal plate. The clearance of the thermal plate to the internal processor substrate is a minimum 0.124" (illustrated in Figure 23 and Figure 24). The clips should be designed such that they will engage within this space, and also not damage the substrate upon insertion or removal. Finally, the clips should be able to retain the heatsink onto the thermal plate through a system level mechanical shock and vibration test. The clips should also apply a high enough force to spread the interface material for the spot size selected. 45 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 0.8 1.0 { 28 Edge near Slot 1 connector OOCSB6 Figure 22. Guideline Locations for Cover Temperature (Tcovern) Thermocouple Placement Thermal Plate 0.124 Min Gap Spring Clip Processor Core Processor Substrate Cover All dimensions in inches. ooneT7a Figure 23. Processor with an Example Low Profile Heatsink Attached using Spring Clips 46 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Thermal Plate All dimensions in inches. 0.124 Min Gap Processor Core Processor Substrate Cover OOO Tea Figure 24. Processor with an Example Full Height Heatsink Attached using Spring Clips 43.2. RIVSCREW* ATTACH The Rivscrew attach mechanism uses a specialized rivet that is inserted through a hole in the heatsink into the thermal plate. Upon insertion, a threaded fastener is formed that can be removed if necessary. For Rivscrew attachment, the minimum gap between the thermal plate and the processor substrate is 0.139". For use of the Advel Rivscrew (part number 1712-3510), the heatsink base thickness must be 0.140 40.010". See Figure 25, Figure26 and Figure 27 for details of heatsink requirements for use with Rivscrews. For other heatsink base thickness, contact Advel for other Rivscrew parts that would be required. 47 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & \_/ 0.064 3.0 (Including Tolerance) Maximum Total Heatsink Depth | _ Ls | -t 0.305 gap in fins to allow for clearance of nose, Rivscrew* 0.140 40.010 and mandrel (Minimum) Recommended Heatsink Base Thickness All dimensions in inches. ooos04 Figure 25. Heatsink Recommendations and Guidelines for Use with Rivscrews* Mandrel Rivscrew* 0.140 40.010 Heatsink Base (Recommended) 0.144 +0.005 Thermal Grease Processor Substrate *, Heatsink Base Thermal Plate 0.139 Min. EHH All dimensions in inches. oo0s15 Figure 26. Heatsink Rivscrew* and Thermal Plate Recommendations and Guidelines 48 INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Y Hole is 4 x 0.150+0.005 - x / ] [ rT il 1 =, I J -, | ) i) i I ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ee IC) ] [ ] [ | ] [ ] [ >: 0.305 Heatsink All dimensions in inches. ooog03 Figure 27. General Rivscrew* Heatsink Mechanical Recommendations 49 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & NOTES: L. HESTENK STT#CH CUP PEPMESAGLE 20KE - PL {PePSCE) 2 HEATSM ATTACH ANSCAEWs PERMEABLE ZOME E PL (FARSICE} ALL IMERONS IH NICHES PAVSCREW GG A REGSTERED TRADEMARK OF AVUEL GROUP COMPAM ES Gh hay aT) Wait 1) yA We 2PL . [ 2PL | a tf RISC REW ATTACH ZOKE = L 125 et IT i ct cr a [ - o aie a TT mo A " 1m me 2 AL G a at in = a cP t : | ee 81 400 = 002 6 PL aa wg OED TAL PL seam L246 O08 MOS FULL PAW = 0623 3 EOE aPL Figure 28. Heatsink Attachment Mechanism Design Space INTEL SECRET (until publication date)5.0. S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS The Pentium ll processor uses S.E.C. cartridge technology. The $.E.C. cartridge contains the processor core, L2 cache and other passive components. The S.E.C. cartridge connects to the motherboard through an edge connector. Mechanical specifications for the processor are given in this section. See Section1.1.1. for a complete terminology listing. Figure 29 shows the thermal plate side view and the cover side view of the processor. Figure 30 shows the S.E.C. cartridge dimensions. Figure 38 through Figure 40 provide details of the S.E.C. cartridge substrate edge finger contacts. The processor edge connector defined in this document is referred to as Slot 1. intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 23 through Table 26 provide the processor edge fingers and Slot 1 connector signal definitions for the Pentium II processor. The signal locations on the Slot 1 edge connector are to be used for signal routing, simulation and component placement on the motherboard. 5.1. 5S.E.C. Cartridge Materials Information The .E.C. cartridge is comprised of multiple pieces to make the complete assembly. This section will provide information relevant to the use and acceptance of the package. The complete $.E.C. cartridge assembly weighs approximately 150 grams. See Table Table 22 for further piece part information. Table 22. S.E.C. Cartridge Materials .E.C. Cartridge Piece Piece Material Maximum Piece Weight (Grams) Thermal Plate Aluminum 6063-T6 67.0 Latch Arms GE Lexan 940, 30% glass filled Less than 2.0 per latch arm Cover GE Lexan 940 24.0 Skirt GE Lexan 940 6.5 Table 23. S.E.. Cartridge Dimensions Symbol Description Min Max Figure A $.E.C. Cartridge Length 5.495 5.515 37 B .E.C. Cartridge Height 2.457 2.489 31 Cc $.E.C. Cartridge Depth 0.637 0.657 30 D Thermal Plate Length 5.324 5.354 37 E Thermal Plate Height 1.917 1.927 31 NOTE: 1. This table applies to the dimensions noted in Figure 30 through Figure 35. 51 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & NOTES FOR FIGURE 29 THROUGH FIGURE 46 Unless otherwise specified, the following drawings are dimensioned in inches. All dimensions provided with tolerances are guaranteed to be met for all normal production product. Figures and drawings labeled as Reference Dimensions are provided for informational purposes. Reference Dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. Reference Dimensions are NOT checked as part of the processor manufacturing. Drawings are not to scale. Left Latch Right Latch Left Latch Thermal Plate Right Latch Cover OOneaaa Figure 29. S.E.C. Cartridge Thermal Plate and Cover Side Views 52 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 3 ; U eae) Thermal Plate \ 0 Right Right Right Sice Thermal Plate Side View Shirt Cover Side View Top View Cover Left Latch \ Right Latch 3 a L el OOC8S4b Figure 30. $.E.. Cartridge Overall Cartridge Dimensions 53 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 3605 +0 020 BS oy z E * T cD a rT o oe / 8 e| fy D 0 E 2 are CP cy B +0 016 ; a O 2070 +0 p20 oO 0 2X0 127 7 1235 +0020 6 6 | on} ? QO 2X 0.340 NN | _ +0 pos These dimensions are from the bottorn of the substrate 2X 0 285 +0 005 | +1 845 +0 005 *}*" 1 830 +0 05 edge fingers NOTE: 1. See Figure 34 for details. GOCaOB 54 Figure 31. S.E.C Cartridge Thermal Plate Side Dimensions INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ NOTE: AX 0.365. +0.005 rs 4 8X FR O.0625 +0.002 +0.004 0.002 BX 0.124 O Detail A ? 0.976 40.008 0.500 +0.008. 0.250 +0.008. 0.000 0.375 +0.008. 1. See Figure 35 for details. ok r++ \ | SD | | 2.110 40.008 0.000 oonso7 Figure 32. S.E.C. Cartridge Thermal Plate and Side View Dimensions INTEL SECRET (until publication date) 55= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & O NOTE: All dimensions without tolerance information are considered reference dimensions only. oocaos Figure 33. S.E.C. Cartridge Thermal Plate Flatness Dimensions 56 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ R 0.015 0.075 1 0.122 | 0.060 0.084 Detail A Detail B LZ\ _ fet _t (Bottom Side View) 0.277 0.058] ke 0.082 3107 i" pote f 0.055 0.291 Detail D Detail C NOTE: All dimensions without tolerance information are considered reference dimensions only. 0.216 45 os Detail E ooca0s Figure 34, S.E.C. Cartridge Latch Details INTEL SECRET (until publication date) 57= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 2X 0.238 40.0107 2X 0.103 + 0.005 * 2% 0.174 +0.005 LL \ 2X 0.488 2X 0.647 +0.010 +0.015 LA 7 2X 0.058 p 2X 0.136_] Left +0.005 +0.005 f*- 2X 0.253 40.010 oo0s10 Figure 35. S.E.C. Cartridge Latch Arm, Thermal Plate Lug, and Cover Lug Dimensions 58 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 2-D Matrix Mark . ; iCOMP2.0 index=YY it a intel. pentium sanwnaz onpencons Lid " _ OOQOCKOGNNNN te with MMX technol Pentium] Locaion Intel. oocsia Figure 36. S.E.C. Cartridge Mark Locations Table 24. Description Table for Processor Markings Code Letter Description A Logo Product Name Trademark Logo Product Name Dynamic Mark Area with 2-D matrix 59 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & , ! Right AS 3.243 40.015 os z & eo o os + o ae E iB +o 2 ay ma Ww 3 nm w 6 ira) T | Thermal Plate | | | {. Cover 2.263 40.015 Skirt Zt. Left OON8 Tid 60 Figure 37. S.E.C. Cartridge Bottom Side View INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ /- Thermal Plate oF = / = @ oO Oo 8 Co co Cover o o QO | Pin At cot e 8 Pin A121 70 7 T 4 e | | Xs ostrat * ] See Detal A 0.007 were SS {LA in Next Figure f 0.062 008 {2.836 i 11.85 Of pt 2.992 +0.008 2.008 +0.008 5.000 NOTE: All dimensions without tolerance information are considered reference dimensions only. o0oe14d Figure 38. S.E.C. Cartridge Substrate Dimensions ye Gover nS Substrate - AAA] A Pin B121 Pin B41 NOTE: Cover not completely shown to allow for substrate details to be shown. This drawing shows the pin details of the cover side of the S.E.C. cartridge. Oonessc. Figure 39. S.E.C. Cartridge Substrate Dimensions, Cover Side View 61 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 4 oe | 4k |__| ! ro | | po [ : Pin A73 Pin A74 (0.010) fe 0.356 0.008 | Min. 0.236 | 0.138 Min. + 0.146 Max. | J \ L } : 9.074 40.002 L 0.045 0.057%] | 121 X 0.016 40.002 & |.20 arg ZW OD b-121 X 0.043 40.002 @ |.05 |.002]() Pad to Pad |.20].008 z fiw @ |.05].002 Pad to Pad NOTE: All dimensions without tolerance information are considered reference dimensions only. OOM85Sb Figure 40. Substrate S.E.C. Cartridge Substrate Detail A 62 INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 5.2. Processor Edge Finger Signal Listing Table 25 is the processor substrate edge finger listing in order by pin number. Table 25. Signal Listing in Order by Pin Number No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type Al VCOC_VTT GTL+ Vir Supply Bi EMI EMI Management A2 GND Vss Be FLUSH# CMOS Input A3 VCOC_VTT GTL+ Vit Supply B3 SMI# CMOS Input A4 IERR# CMOS Output B4 INIT# CMOS Input AS A20M# CMOS Input BS VCC_VTT GTL+ Vir Supply AG GND Vss BB STPCLK# CMOS Input AT FERR# CMOS Output B7 TCK JTAG Input A8 IGNNE# CMOS Input B8 SLP# CMOS Input Ag TDI JTAG Input BS VCC_VTT GTL+ Vir Supply A1lag | GND Vss Bid | TMS JTAG Input Ail |TDO JTAG Output Bii | TRST# JTAG Input Al2 PWRGOOD CMOS Input Bi2 | Reserved Reserved for Future Use A13 TESTHI CMOS Test Input B13 VCCG_CORE Processor Core Vcc Al4 GND Vss B14 Reserved Reserved for Future Use A1S | THERMTRIP# | CMOS Output B15 | Reserved Reserved for Future Use A1i6 | Reserved Reserved for Future Use B16 | LINT[1]/NMI CMOS Input Ai7 | LINTIOVINTR CMOS Input B17 | VCC CORE Processor Core Voc Alga |GND Vss Big |PICCLK APIC Clock Input Aig | PICD[O] CMOS I/O Big | BP#[2] GTL+ lO A20 | PREQ# CMOS Input B20 | Reserved Reserved for Future Use A21 BP#[3] GTL+ VO Bei | BSEL# GND A22 | GND Vss B22 | PICD[1] CMOS I/O A23 | BPM#[0] GTL+ I/O B23 | PRDY# GTL+ Output A24 | BINIT# GTL+ VO B24 | BPM#(1] GTL+ VO AeS | DEP#0] GTL+ WO Be5 | VCC CORE Processor Core Voc INTEL SECRET 63 (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 25. Signal Listing in Order by Pin Number (Cont'd) No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type A26 | GND Vss B26 | DEP#] GTL+ VO A27 | DEP#{1] GTL+ VO B27 | DEP#[4] GTL+ VO A28 | DEP#[3] GTL+ lO B28 | DEP#{[7] GTL+ lO A2g DEP#[5] GTL+ lO Beg VGC_CORE Processor Core Vcc A30) =| GND Vss B30 | D#[62] GTL+ VO A31 DEP#{[6] GTL+ VO B31 | D#[53] GTL+ VO A32 | D#[61] GTL+ I/O B32 | D#[63] GTL+ lO A33 D#[55] GTL+ I/O B33 VOC _CORE Processor Core Voc A34 | GND Vss B34 | D#[56] GTL+ VO A35 | D#[60] GTL+ VO B35 | D#[50] GTL+ VO A36 | D#[53] GTL+ lO B36 | D#[54] GTL+ VO A837 | D#[57] GTL+ I/O B37 | VCC_CORE Processor Core Voc A338 | GND Vss B38 | D#[59] GTL+ VO A3S | D#[46) GTL+ I/O B3ag | D448] GTL+ YO A4O | D#[49] GTL+ VO B40 (| D452] GTL+ VO AAI D#[51] GTL+ lO B4i | EMI EMI Management A42 | GND Vss B42 | D#[41] GTL+ VO A43 | D#42] GTL+ VO B43 | D447] GTL+ VO A44 | D#45] GTL+ IO B44 | D#[44] GTL+ VO A45 | D#[39] GTL+ I/O B45 | VCC CORE Processor Core Vcc A46 | GND Vss B46 | D#[36] GTL+ VO A47 | Reserved Reserved for Future Use |} B47 | D#[40] GTL+ IYO A48 | D#43] GTL+ VO B48 | D434] GTL+ VO A49 | D#37] GTL+ VO B4g | VCC CORE Processor Core Voc A50 | GND Vss B50 | D#[38] GTL+ VO A51 D#[33] GTL+ VO B51 | D432] GTL+ VO A52 | D#35] GTL+ IO B52 | D#[23] GTL+ lO 64 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 25. Signal Listing in Order by Pin Number (Cont'd) No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type A53 D#[31] GTL+ I/O B53 VCC _ CORE Processor Core Vcc A54 | GND Vss B54 | D#[29] GTL+ VO A555 | D#30] GTL+ I/O B55 | D#[26] GTL+ lO A56 | D#27] GTL+ VO B56 | D#[25] GTL+ VO AS7 | D#[24] GTL+ WO B57 | VCC CORE Processor Core Vcc A538 | GND Vss B58 | D#[22] GTL+ VO A5S | D#[23] GTL+ I/O B5a | D419] GTL+ lO A6O | D#21] GTL+ IO Beo | D#[13] GTL+ VO AGI D#[16] GTL+ VO B61 | EMI EMI Management A62 | GND Vss B62 | D#[20] GTL+ VO A63 | D#[13] GTL+ lO B63 | D417] GTL+ VO A64 | D#[11] GTL+ I/O Be4 | D415] GTL+ lO A65 D#[10] GTL+ lO B5 VCC_CORE Processor Core Vcc A66 | GND Vss B66 | D#[12] GTL+ VO A67 | D#14] GTL+ VO B67 | D#{7] GTL+ I/O A688 | DHS] GTL+ lO Bes | D#[6) GTL+ I/O A69 D#[8] GTL+ lO Bg VGC _CORE Processor Core Vcc A7O | GND Vss B7o =| D#4) GTL+ VO A71 D#[5] GTL+ VO B71 | D#2] GTL+ VO A72 | DAS] GTL+ VO B72 | D#[0] GTL+ VO A73 D#[1] GTL+ I/O B73 | VCC_CORE Processor Core Voc A74 | GND Vss B74 |RESET# GTL+ Input A75 |BCLK Processor Clock Input B75 | BRIi# GTL+ Input A776 | BRO# GTL+ IO B76 | FRCERR GTL+ VO AT7 BERR# GTL+ I/O BY? VCC CORE Processor Core Vcc A7& | GND Vss B78 | A#[35] GTL+ VO A793 | A#[33] GTL+ VO B7g | A#[32] GTL+ VO INTEL SECRET (until publication date) 65= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 25. Signal Listing in Order by Pin Number (Cont'd) No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type A&G | A#[34] GTL+ VO Bsa | A#[29] GTL+ VO Aal A#([30] GTL+ VO Bal EMI EMI Management A&2 | GND Vss B82 | A#[26] GTL+ VO A83s| A#[31] GTL+ VO B83 | A#[24] GTL+ VO A84 | A#[27] GTL+ VO B84 | A#[28] GTL+ VO A85 A#[22] GTL+ /O Bas VCC_CORE Processor Core Vcc A&86 | GND Vss B86 | A#[20] GTL+ VO A87 | A#[23] GTL+ VO B87 | A#[21] GTL+ VO A88 | Reserved Reserved for Future Use B88 | A#[25] GTL+ VO A839 A#(19] GTL+ lO Bag VGC_CORE Processor Core Vcc A90) =| GND Vss Bso =| A#[15] GTL+ VO AQ1 = | A#[18] GTL+ VO BSi | A#[17] GTL+ VO A92 | A#[16] GTL+ VO Bs2 | A#[11] GTL+ VO A93 | A#[13] GTL+ WO B93. | VCC CORE Processor Core Voc A94 | GND Vss B94 | A#[12] GTL+ VO AQ5 | A#[14] GTL+ I/O BS5 | A#[8] GTL+ lO A96 | A#[10] GTL+ VO Bs | A#[7] GTL+ VO AQ? | A#[5] GTL+ VO Ba7 | VCC CORE Processor Core Voc A938 =| GND Vss Bss | A#{3] GTL+ VO Ags | A#9] GTL+ VO Bsa | A#{] GTL+ I/O A100 | A#[4] GTL+ I/O Biod | EMI EMI Management A101 | BNR# GTL+ VO Bi01 | SLOTOCC# GND Aid2 |GND Vss Bio2 | REGQ#[0] GTL+ VO A103 | BPRI# GTL+ Input B103 | REQ#[1] GTL+ lO A104 | TRDY# GTL+ Input B104 | REQ#[4] GTL+ I/O A1o5 | DEFER# GTL+ Input Bi05 | VGC _ CORE Processor Core Voc Ai06 | GND Vss B106 | LOCK# GTL+ VO 66 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 25. Signal Listing in Order by Pin Number (Cont'd) No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type A107 | REQ#[2] GTL+ VO Bio7 | DRDY# GTL+ VO A108 | REQ#[3] GTL+ VO B1i08 | RS#[0] GTL+ Input A1og | HITM# GTL+ fO Biog | VOCS Other Voc A110 | GND Vss B1i0 | HIT# GTL+ VO Alii | DBSY# GTL+ VO Bii1 | RS#[2] GTL+ Input Ail2 | R&#1] GTL+ Input B112 | Reserved Reserved for Future Use A113 | Reserved Reserved for Future Use B1i1i3 | VCC L2 Other Voc Ai14 | GND Vss B1ii4 | RP# GTL+ VO A1i5 | ADS# GTL+ VO B1i5 | RSP# GTL+ Input A116 | Reserved Reserved for Future Use | B116 | AP#1] GTL+ VO A117 | AP#[0] GTL+ I/O Bii7 | VCC _L2 Other Voc A118 | GND Vss B1i8 | AERR# GTL+ VO Aiig | VIDE] Veccore or Vss Biig | VID[3] Veccore or Vss Ai20 | VID[1] Vcccore or Vss Bi20 | VID[O] Veccore or Vsg Al21 | VID[4] Veccore or Vss Bi21 |VCC_L2 Other Voc INTEL SECRET (until publication date) 67= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 26 is the processor substrate edge connector listing in order by pin name. Table 26. Signal Listing in Order by Signal Name No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type Bos | AM3] GTL+ VO Bao | A#[29] GTL+ VO Aloo | A#4] GTL+ VO A81 | A#[30] GTL+ VO AS7 | A#{[5] GTL+ I/O A83 | A#[31] GTL+ V/O Bag | A#{6] GTL+ lO B7g_ | A#[32] GTL+ VO Bae | AM{7] GTL+ tO A79 | A[33] GTL+ VO B95 | A#{8] GTL+ VO A80 | A#[34] GTL+ V/O Aga A#{S] GTL+ tO B78 | A#[35] GTL+ VO Ag6 | A#[10] GTL+ VO AS A20M# CMOS Input Bg2 A#{11] GTL+ I/O A115 | ADS# GTL+ I/O Bo4 | A#12] GTL+ lO B118 | AERR# GTL+ VO A93 | A#{[13] GTL+ lO A117 | AP#([0] GTL+ V/O Ag5 | A#{[14] GTL+ lO B116 | AP#[1] GTL+ V/O Bsa | A#15] GTL+ WO A7S | BCLK Processor Clock Input Ag2 A#{[16] GTL+ I/O A77 | BERR# GTL+ /O Boi | A#{17] GTL+ lO A24 | BINIT# GTL+ VO AS1 | A#{18] GTL+ lO A101 | BNR# GTL+ VO A89 | A#19] GTL+ lO Big | BP#[2] GTL+ V/O Bae | A#[20] GTL+ VO A21 | BP#[3] GTL+ VO Bay | A#21] GTL+ VO A23 | BPM#[0] GTL+ VO A85 | A#[22] GTL+ VO B24 | BPM#[1] GTL+ VO A87 | A#{[23] GTL+ VO A103 | BPRIi# GTL+ Input B83 A#[24] GTL+ I/O A76 | BRO# GTL+ I/O Bas | Aa[25] GTL+ vO B75 |BRi# GTL+ Input Ba2 | A#[26] GTL+ VO B21 | BSEL# GND A84 = | A#{[27] GTL+ VO B72 | D#[0] GTL+ V/O Bad | A#[28] GTL+ VO A73 | D#[1] GTL+ V/O 68 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 26. Signal Listing in Order by Signal Name (Cont'd) No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type Bri | D#{2] GTL+ VO B54 (| D#[29] GTL+ lO A72 | D#{3] GTL+ tO A55 | D#[30] GTL+ VO B70 | D#4] GTL+ VO A53 | D#/31] GTL+ lO ATi | D#[5] GTL+ VO B51 | D#[s2] GTL+ l/O Bea | D#{6] GTL+ VO A51 | D#/33] GTL+ lO Be7 | D#{7] GTL+ VO B48 | D#[34] GTL+ l/O Asa | D#[a] GTL+ VO A52 | D#/35] GTL+ lO Asa | D#[9] GTL+ VO B46 | D#[36] GTL+ lO AB5 | D#[10] GTL+ VO Ada | D#37] GTL+ VO Ae4 = | D#[11] GTL+ lO B50 | D#[38] GTL+ VO Bes | D#f12] GTL+ VO A045 | D#39] GTL+ VO asa | D4(13] GTL+ WO B47 | D#[4o] GTL+ VO Ae7 | D#[14] GTL+ lO B42 | D#[441] GTL+ VO Be4 | D#T15] GTL+ VO A043 | D#42] GTL+ VO A61 | D#{16] GTL+ VO Ads | D#(43] GTL+ VO Bes | D#T17] GTL+ VO B44 | D#[44] GTL+ VO Beo | D#{18] GTL+ lO A044 | D#45] GTL+ VO B5a| D#f 19] GTL+ VO Aosg | D#[46] GTL+ VO Be2 | D#{20] GTL+ lO B43 | D#47] GTL+ VO Aso | D#[21] GTL+ VO B39 | D#[4a] GTL+ VO B58 | D#[22] GTL+ VO A040 | D#49] GTL+ VO Asa | D#[23] GTL+ VO B35 | D#[50] GTL+ VO As7 | D#[24] GTL+ lO Ao41 | D#51] GTL+ VO B56 | D#25] GTL+ VO B40 | #52] GTL+ VO B55 | D#/26] GTL+ VO A368 | D#53] GTL+ VO ase | D#[27] GTL+ lO B36 | D#[54] GTL+ VO B52 | D#f29] GTL+ VO A33. | D#[55] GTL+ VO 69 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 26. Signal Listing in Order by Signal Name (Cont'd) No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type B34 D#([56] GTL+ lO A2 GND Vss A387 | D#[57] GTL+ V/O AS GND Ves B31 D#[58] GTL+ I/O A1lQg | GND Vss B38 | D#[59] GTL+ l/O Al4 | GND Vss A35 D#[60] GTL+ l/O A1l& |GND Veg A382 (| D#[61] GTL+ lO A22 | GND Vss B30 | D#[62] GTL+ l/O A26 | GND Vss B32 | D#[63] GTL+ l/O A380 | GND Vss Aili | DBSY# GTL+ I/O A384 | GND Vss A105 | DEFER# GTL+ Input A38 | GND Vss A25 | DEP#([0] GTL+ l/O Ao42 | GND Vss A27 | DEP#1] GTL+ lO A46 | GND Vss B26 | DEP#[2] GTL+ l/O A50 | GND Vss A28 DEP#[3] GTL+ /O A54 | GND Ves B27 | DEP#([4] GTL+ lO A58 | GND Vss A29 DEP#[5] GTL+ /O A62 | GND Vss A31_ | DEP#{[6] GTL+ l/O As6 | GND Vss B28 DEP#[7] GTL+ l/O A7Q | GND Vss Bioy | DRDY# GTL+ lO A74 | GND Ves Bi EMI EMI Management A78 GND Vss B41 EMI EMI Management A82 GND Vss B1 EMI EMI Management A86 | GND Vss B81 EMI EMI Management Ag0) | GND Ves Bi00 | EMI EMI Management Ag4 GND Vss A? FERR# CMOS Output A98 | GND Vss B2 FLUSH# CMOS Input A102 |GND Vss B76 FRCERR GTL+ /O A106 | GND Veg 70 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 26. Signal Listing in Order by Signal Name (Cont'd) No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type A110 | GND Vss B12 Reserved Reserved for Future Use Ail4 | GND Vss B14 Reserved Reserved for Future Use A118 | GND Vss Bi5 | Reserved Reserved for Future Use B1id | HIT# GTL+ VO B20 | Reserved Reserved for Future Use A1OS | HITM# GTL+ I/O Bii2 | Reserved Reserved for Future Use Ad IERR# CMOS Output B74 | RESET# GTL+ Input A8& IGNNE# CMOS Input B1ii4 | RP# GTL+ VO B4 INIT# CMOS Input B108 | RS#[0] GTL+ Input AI? | LINT[OVINTR CMOS Input Ail2 | RS#1] GTL+ Input Bi | LINT[1}/NMI CMOS Input B1i1 | RS#P] GTL+ Input B106 | LOCK# GTL+ VO B11i5 | RSP# GTL+ Input Big | PICCLK APIC Clock Input B101 | SLOTOCC# GND Aig | PICD[O) CMOS I/O B8 SLP# CMOS Input B22 | PICD[1] CMOS I/O B3 SMI# CMOS Input B23 | PRDY# GTL+ Output B6 STPCLK# CMOS Input A20 | PREQ# CMOS Input B?7 TCK JTAG Input Al2 | PWRGOOD CMOS Input Ag TDI JTAG Input Bid2 | REQ#O] GTL+ I/O Ali | TDO JTAG Output B103 | REQ#[1] GTL+ VO A1l3 | TESTHI CMOS Test Input A107 | REQ#[2] GTL+ VO A15) | THERMTRIP# | CMOS Output A108 | REQ#[3] GTL+ VO Bio |TMS JTAG Input B104 | REQ#[4] GTL+ VO A104 | TRDY# GTL+ Input Ai6 | Reserved Reserved for Future Use |} B11 | TRST# JTAG Input AAT Reserved Reserved for Future Use B13 VCC_CORE Processor Core Voc A&B Reserved Reserved for Future Use BIf | VCC CORE Processor Core Voc A113 | Reserved Reserved for Future Use Bes | VOC CORE Processor Core Voc A116 | Reserved Reserved for Future Use B23 VCC CORE Processor Core Voc INTEL SECRET (until publication date) 71= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 26. Signal Listing in Order by Signal Name (Cont'd) No. Pin Name Signal Buffer Type No. Pin Name Signal Buffer Type B33 VCC_CORE Processor Core Vcc B1i05 | VCC CORE Processor Core Vcc B37 VCC_CORE Processor Core Vcc B113 | VCC _L2 Other Voc B45 VCC CORE Processor Core Vcc Bii7 | VCC Le Other Voc B49 VCC _CORE Processor Core Vcc Bi21 | VCC _L2 Other Voc B53. | VCC_CORE Processor Core Voc Al VCC_VTT GTL+ Vir Supply B57 VCC _ CORE Processor Core Vcc A3 VCG_VTT GTL+ Vir Supply B65 | VCC _CORE Processor Core Voc BS VCC_VTT GTL+ Vir Supply Beg VCC _CORE Processor Core Vcc Bg VCC_VTT GTL+ Vir Supply B73 VCC CORE Processor Core Voc Biog |} VCC5 Other Voc B77 VCC_CORE Processor Core Voc Bi2o0 | VID[O] Veccore or Vsg Bas VCC _CORE Processor Core Vcc A120 [| VID[1] Veccore or Vss Bag VCC _ CORE Processor Core Vcc A1ig [| VID[2] Veccore or Vss B33 VCC CORE Processor Core Voc B1i9 | VID[3] Veccore or Vss B97 VCC CORE Processor Core Voc Ai21 [| VID[4] Veccore or Vsg 72 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 6.0. BOXED PROCESSOR important for OEMs that manufacture motherboards SPECIFICATIONS for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in inches. Figure 43 shows a mechanical representation of the 6.1. Introduction Boxed Pentiumll processor in a_ retention mechanism. The Pentium Il processor is also offered as an Intel Boxed processor. Intel Boxed processors are NOTE intended for system integrators who build systems ; : . from motherboards and standard components. The The airflow of the fan/heatsink is into the Boxed Pentium Il processor will be supplied with an center and out of the sides of the fan/heatsink. attached fan/heatsink. This chapter documents The large arrows in Figure 41 denote the motherboard and system requirements for the direction of airflow. fan/heatsink that will be supplied with the Boxed Pentium Il processor. This chapter is particularly Boxed Processor Heatsink Support Mechanism Processor Shroud Gavering Heatsink Fins Retention Mechanism Fan Power Connector Motherboard Heatsink Support Mechanism OOfsh4a Figure 41. Conceptual Boxed Pentium Il Processor in Retention Mechanism 73 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 6.2. Mechanical Specifications This section documents the mechanical 6.2.1. BOXED PROCESSOR FAN/HEATSINK specifications of the Boxed Pentium ll processor DIMENSIONS fan/heatsink. The Boxed processor will be shipped with an attached fan/heatsink. Clearance is required around the fan/heat sink to ensure unimpeded air flow for proper cooling. The space requirements and dimensions for the Boxed Processor with integrated farvyheatsink are shown in Figure 42 (Side View), Figure 43 (Front View), and Figure 44 (Top View). All dimensions are in inches. 1.291 Pee Max (A 7 ____ Fan Heatsink 5.E.C. Gartridge Gover ~ Slot 1 Gonnector ~~~... : 0.485 (B) OO08o0e Figure 42. Side View Space Requirements for the Boxed Processor (fan heatsink supports not shown) 74 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Power Cable # _____- 4.90 Max Connector 1.25 > oongsta Figure 43. Front View Space Requirements for the Boxed Processor 0.40 Min Air Space (E} a * *_ (both ends) * Measure ambient temperature 0.3 above center of fan inlet | Fan Heatsink .E.C. Cartridge Cover I 0.20 Min Air space (F) ooose2 Figure 44, Top View Space Requirements for the Boxed Processor Table 27. Boxed Processor Fan/Heatsink Spatial Dimensions Fig. Ref. Label Dimensions (Inches) Min Typ Max A Fan/Heatsink Depth (off processor thermal plate) 1.291 B Fan/Heatsink Height above motherboard 0.485 c Fan/Heatsink Height (see front view) 2.19 D Fan/Heatsink Width (see front view) 4.90 E Airflow keepout zones from end of fan/heatsink 0.40 F Airflow keepout zones from face of fan/heatsink 0.20 INTEL SECRET (until publication date) Fis)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 6.2.2. BOXED PROCESSOR FAN/HEATSINK WEIGHT The Boxed processor fan/heatsink will not weigh more than 225 grames. See Section 4.0 and Section 5.0 for details on the processor weight and heatsink requirements. 6.2.3. BOXED PROCESSOR RETENTION MECHANISM AND FAN/HEATSINK SUPPORT The Boxed processor requires a processor retention mechanism as described in AP-588, Mechanical and Assembly Technology for S.E.C. Cariridge Processors (Order Number 243333) to secure the processor in Slot 1. The Boxed processor will not ship with a retention mechanism. Motherboards designed for use by system integrators should include a retention mechanism and appropriate installation instructions. The Boxed processor will ship with its own fan heatsink support. The support differs from supports for passive heatsinks. The Boxed processor far/heatsink support requires heatsink support holes in the motherboard. Location and size of these holes are give in Figure 45. Any motherboard components placed in the area beneath the fan/heatsink supports must recognize the clearance (H) give in Table 28 below. Component height restrictions for passive heatsink support designs, as described in AP-588, Mechanical and Assembly Technology for S.E.C. Cartridge Processors (Order Number 243333), still apply. Motherboards designed for use by system integrators should not have objects installed in the heatsink support holes. Otherwise, removal instructions for objects pre-installed in the heatsink support holes should be included in the motherboard documentation. Table 28. Boxed Processor Fan/Heatsink Support Dimensions'. 2 Fig. Ref. Label Dimensions (Inches) Min Typ Max G Fan/Heatsink support height 2.261 H Fan/Heatsink support clearance above motherboard 0.430 J Fan/Heatsink support standoff diameter 0.275 0.300 K Fan/Heatsink support front edge to heatsink support hole 0.240 center L Fan/Heatsink support standoff protrusion beneath 0.06 motherboard M Motherboard thickness 0.05 0.06 0.075 N Spacing between fan/heatsink support posts 4.0384 P Fan/Heatsink support width 0.600 Q Fan/Heatsink support inner edge to heatsink support hole 0.400 NOTES: 1. This table applies to the dimensions noted in Figure 45 through Figure 47. 2. Alldimensions are in inches. Unless otherwise specified, all x.xxx dimension tolerance is 0.005 inches. All x.xx dimension tolerance is +0.01 inches. 76 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Slet 1 Connector 8 0187 Thu Recommen: dations: a 2922 1950 2X 0300 dia trace keepout ~-all external layers 0250 dia trace heepout ~all internal layers All dimensions in inches ooos?s Figure 45. Heatsink Support Hole Locations and Sizes INTEL SECRET (until publication date) tT= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 2.26 1(G) 0.275 DIA (J) (0.300 MAX) 0.490 (H) | | i 5 [ 0.060 (M} I 0.060 (L} 0.240 (K) 1.769 oo0so4 Figure 46, Side View Space Requirements for Boxed Processor Fan/Heatsink Supports 8 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ 1 ST = ai: \ (eRe | p 0.600 (P} 4.084 (N} 0.400 (Q) ooosos Figure 47. Top View Space Requirements for Boxed Processor Fan/Heatsink Supports 6.3. Boxed Processor Requirements 6.3.1. FAN/HEATSINK POWER SUPPLY The Boxed processors fan/heatsink requires a +12 V power supply. A fan power cable will be shipped with the Boxed processor to draw power from a power header on the motherboard. The power cable connector and pinout are shown in Figure 48. Motherboards must provide a matched power header to support the Boxed processor. Table 29 contains specifications for the input and output signals at the fan/heatsink connector. The cable length will be 7.0 inches (+0.25"). The fan/heatsink outputs a SENSE signal, whichis an open-collector output, that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides Voy to match the motherboard-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The power header on the baseboard must be positioned to allow the fan/heatsink power cable to reach it. The power header identification and location should be documented in the motherboard documentation or on the motherboard. Figure 49 shows the recommended location of the fan power connector relative to the Slot 1 connector. The motherboard power header should be positioned within 4.75 inches (lateral) of the fan power connector. 7g INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & \ f f Pin Signal om 1 GND Straight square pin, 3-pin terminal housing with 1 1 ! cs . Aare + pedada polarizing ribs and friction locking ramp. fit dy piilil 2 +12V 0.100" pin pitch, 0.025" square pin width. itaididad i Pla C 3 SENSE Waldom*/Molex* P/N 22-01-3037 or equivalent. biti Match with straight pin, friction lock header on motherboard P L___I ] Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3, HH ] or equivalent. 1 2 3 oo0sss Figure 48, Boxed Processor Fan/Heatsink Power Cable Connector Description Table 29. Fan/Heatsink Power and Signal Specifications Description Min Typ Max +12 V: 12 volt fan power supply 7 12V 13.8V IC: Fan current draw 100 mA SENSE: SENSE frequency (motherboard should pull this pin up to appropriate Voc with resistor) revolution 2 pulses per fan 80 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Slot 1 Connector Motherboard fan power header should be positioned within 4.75 inches of fan power connector (lateral distance) Fan power connector location a (1.56 inches above motherboard} tr =4.75inches ooca13 Figure 49. Recommended Motherboard Power Header Placement Relative to Fan Power Connector and Slot 1 6.4. Thermal Specifications This section describes the cooling requirements of the fan/heatsink solution utilized by the Boxed processor. 6.4.1. BOXED PROCESSOR COOLING REQUIREMENTS The Boxed processor will be cooled with a fan/heatsink. The Boxed processor fan/heatsink will keep the thermal plate temperature, TpLate, within the specifications (see Table 20), provided airflow through the fan/heatsink is unimpeded and the air temperature entering the fan is below 45 C (see Figure 43 for measurement location). Airspace is required around the fan to ensure that the airflow through the fan/heatsink is not blocked. Blocking the airflow to the fan/heatsink reduces the cooling efficiency and decreases fan life. Figure 44 illustrates an acceptable airspace clearance for the farvheatsink. a1 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & 7.0. ADVANCED FEATURES Some nonessential information regarding the Pentium Il processor is considered Intel confidential and proprietary and is not documented in this publication. This information is available with the appropriate nondisclosure agreements in place. Please contact Intel Corporation for details. This information is specifically targeted at software developers and chipset manufacturers who develop the following types of low-level software and chipsets: * operating system kernels * virtual memory managers e BIOS and processor test software * performance monitoring tools bus cycle information 82 For software developers designing other categories of software, this information does not apply. All of the required program development details are provided in the Intel Architecture Software Developer's Manuat: Volume 2, Insiruciion Set Reference (Order Number 243191), which is publicly available from the Intel Corporation Literature Center. To obtain this document, contact the Intel Corporation Literature Center at: Intel Corporation Literature Center P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 and reference Order Number 243191 INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ APPENDIX A This appendix provides an alphabetical listing of all Pentium Il processor signals. The tables at the end of this appendix summarize the signals by direction: output, input, and I/O. A.1 ALPHABETICAL SIGNALS REFERENCE AAA A[35:0}# (/0) The A[35:3}# (Address) signals define a 236-byte physical memory address space. When ADS# is active, these pins transmit the address of a transaction; when ADS# is inactive, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Pentium II processor System Bus. The A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]# signals are parity-protected by the APO# parity signal. On the active-to-inactive transition of RESET#, the processors sample the A[35:3]# pins to determine their power-on configuration. See the Pentium it Processor Developer's Manual (Order Number 243341) for details. A112 A20M# (I) lf the AZOM# (Address-20 Mask) input signal is asserted, the Pentium Il processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20OM# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A2OM# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding /O Write bus transaction. During active RESET#, each processor begins sampling the A20M#, IGNNE#, and LINT[1:0] values to determine the ratio of core-clock frequency to bus- clock frequency. (See Table 1.) On the active-to- inactive transition of RESET#, each processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals for normal operation; see Figure 6 for an example implementation of this logic. A1.3 ADS#(V/0) The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must connect the appropriate pins on all Pentium Il processor System Bus agents. A1.4 AERR# (I/O) The AERR# (Address Parity Error) signal is observed and driven by all Pentium Il processor System Bus agents, and if used, must connect the appropriate pins on all Pentium Il processor System Bus agents. AERR# observation is optionally enabled during power-on configuration; if enabled, a valid assertion of AERR# aborts the current transaction. lf AERR# observation is disabled during power-on configuration, a central agent may handle an assertion of AERR# as appropriate to the Machine Check Architecture (MCA) of the system. A115 AP[1 :0]# (1/0) The AP[1:0}# (Address Parity) signals are driven by the request initiator along with ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and 83 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & APO# covers A[23:3]}#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0}# should connect the appropriate pins of all Pentium Il processor System Bus agents. A1.6 BCLK (I) The BCLK (Bus Clock) signal determines the bus frequency. All Pentium ll processor System Bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters are specified with respect to the BCLK signal. AA7 BERR (I/O) The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all Pentium II processor System Bus agents, and must connect the appropriate pins of all such agents, if used. However, Pentium Il processors do not observe assertions of the BERR# signal. BERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: Enabled or disabled. Asserted optionally for internal errors along with IERR#. Asserted optionally by the request initiator of a bus transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus transaction. A1.8 _ BINIT# (I/O) The BINIT# (Bus Initialization) signal may be observed and driven by all Pentium ll processor System Bus agents, and if used must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information. 84 lf BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state machines are reset and any data which was in transit is lost. All agents reset their rotating ID for bus arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches are not affected. lf BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the Machine Check Architecture (MCA) of the system. A1.9 BNR# (/0) The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must connect the appropriate pins of all Pentium Il processor System Bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges. A110 BP[3:2]# (1/0) The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the status of breakpoints. A111 BPNI[1 :0}# (1/0) The BPM[1:0}# (Breakpoint Monitor) signals are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. A112 BPRI# (I) The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Pentium Il processor System Bus. It must connect the appropriate pins of INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ all Pentium || processor System Bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an angoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. A113 BRo# (I/O), BR1# (1) The BRO# and BR1# (Bus Request) pins drive the BREOQ[1:0}# signals in the system. The BREQ[1:0}# signals are interconnected in a rotating manner to individual processor pins. Table 30 gives the rotating interconnect between the processor and bus signals. Table 30. BRO# (I/O) and BR1# Signals Rotating Interconnect Bus Signal Agent 0 Pins | Agent1 Pins BREQO# BROo# BRi# BREQi# BRi# BRo# During power-up configuration, the central agent must assert the BRO# bus signal. All symmetric agents sample their BR[1:0}# pins on active-to- inactive transition of RESET#. The pin on which the agent samples an active level determines its agent ID. All agents then configure their pins to match the appropriate bus signal protocol, as shown in Table 31. Table 31. BR[1:0}# Signal Agent IDs Pin Sampled Active in RESET# Agent ID BRO# 0 BRi# 1 A114 BSEL#(I/0) The BSEL# (Bus Select) signal is used for future Slot 1 processors and motherboards. This signal must be tied to GND for proper processor operation. A115 D[63:0}# (1/0) The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between the Pentium Il processor System Bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. A1.16 DBSY# (I/O) The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the Pentium Il processor System Bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all Pentium Il processor System Bus agents. A117 DEFER? (I) The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in- order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the appropriate pins of all Pentium || processor System Bus agents. A118 DEP[?:0]# (I/O) The DEP[?7:0}# (Data Bus ECC Protection) signals provide optional ECC protection for the data bus. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all Pentium || processor System Bus agents which use them. The DEP[7:0]# signals are enabled or disabled for ECC protection during power on configuration. A119 DRDY# (I/O) The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all Pentium II processor System Bus agents. 85 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & A.1.20 EMI EMI pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0 ) resistors. The zero ohm resistors should be placed in close proximity to the Slot 1 connector. The path to chassis ground should be short in length and have a low impedance. A121 FERR# (0) The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating- point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. A.1.22 FLUSH# (I) When the FLUSH# input signal is asserted, processors write back all data in the Modified state from their internal caches and invalidate all internal cache lines. At the completion of this operation, the processor issues a Flush Acknowledge transaction. The processor does not cache any new data while the FLUSH# signal remains asserted. FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction. On the active-to-inactive transition of RESET#, each processor samples FLUSH# to determine its power- on configuration. See the Pentium i! Processor Developer's Manual (Order Number 243341) for details. A.1.23 FRCERR (I/O) If two processors are configured in a Functional Redundancy Checking (FRC) master/checker pair, as a single logical processor, the FRCERR (Functional Redundancy Checking Error) signal is asserted by the checker if a mismatch is detected between the internally sampled outputs and the masters outputs. The checker's FRCERR output pin 86 must be connected with the masters FRCERR input pin in this configuration. For point-to-point connections, the checker always compares against the masters outputs. For bussed single-driver signals, the checker compares against the signal when the master is the only allowed driver. For bussed multiple-driver wired-OR signals, the checker compares against the signal only if the master is expected to drive the signal low. When a processor is configured as an FRC checker, FRCERR is toggled during its reset action. A checker asserts FRCERR for approximately 1second after the active-to-inactive transition of RESET# if it executes its BuiltIn Self-Test (BIST). When BIST execution completes, the checker processor deasserts FRCERR if BIST completed successfully, and continues to assert FRCERR if BIST fails. If the checker processor does not execute the BIST action, then it keeps FRCERR asserted for approximately 20 clocks and then deasserts it. All asynchronous signals must be externally synchronized to BCLK by system logic during FRC mode operation. A1.24 HIT# (1/3), HITMH (I/O) The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, and must connect the appropriate pins of all Pentium II processor System Bus agents. Any such agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. A.1.25 IERR# (0) The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the Pentium II processor System Bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted uniil it is handled in software, or with the assertion of RESET#, BINIT#, or INIT#. INTEL SECRET (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ A.1.26 IGNNE#F (1) The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to execute nonconirol floating- point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bitin control register 0 is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding /O Write bus transaction. During active RESET#, the Pentiuml| processor begins sampling the A20M#, IGNNE#, and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. (See Table 1.) On the active- to-inactive transition of RESET#, the Pentium Il processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals for normal operation; Figure 6 for an example implementation of this logic. A.1.27 INIT# (1) The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal (L1 or L2) caches or floating- point registers. Each processor then begins execution at the power-on reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all Pentium ll processor System Bus agents. lf INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-In Self-Test (BIST). A1.28 LINTT1:6] (I) The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all processors and the core logic or I/O APIC component. When the APIC is disabled, the LINTO signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the default configuration. During active RESET#, the Pentiumll processor begins sampling the A20M#, IGNNE#, and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clack frequency. (See Table 1.) On the active- to-inactive transition of RESET#, the Pentium Il processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals for normal operation; see Figure 6 for an example implementation of this logic. A.1.29 LOCK# (I/O) The LOCK# signal indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all Pentium ll processor System Bus agents. For a_ locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the Pentium II processor System Bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the Pentium Il processor System Bus throughout the bus lacked operation and ensure the atomicity of lock. A.1.30 PICCLK (I) The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or I/O APIC which is required for operation of all processors, core logic, and I/O APIC components on the APIC bus. During FRC mode operation, PICCLK must be 1% of (and synchronous to) BCLK. 87 INTEL SECRET (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & A.1.31 PICD[1:0] (I/O) The PICD[1:0] (APIC Data) signals are used for bi- directional serial message passing on the APIC bus, and must connect the appropriate pins of all processors and core logic or IMO APIC components on the APIC bus. A.1.32 PM[1 :0]# (O) The PM[1:0}# (Performance Monitor) signals are outputs from the processor which indicate the status of programmable counters used for monitoring processor performance. A133 PRDY# (0) The PRDY (Probe Ready) signal is a processor output used by debug tools to determine processor debug readiness. See the Pentiurn Processor Developer's Manual (Order Number 243341) for more information on this signal. A.1.34 PREQ# (I) The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processors. See the Pentium I! Processor Developers Manual (Order Number 243341) for more information on this signal. A.1.35 PWRGOOD (1) The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The processor requires this signal to be a clean indication that the clocks and power supplies (Vcccore, etc.) are stable and within their specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high (2.5 V) state. Figure 50 illustrates the relationship of PWRGOOD to ather system signals. PWRGOOD can be driven inactive at any time, but clocks and power must again be 88 stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 13 and be follawed by a 1 ms RESET# pulse. The PWRGOOD signal must be supplied to the processor as it is used to protect internal circuits against voltage sequencing issues. The PWRGOOD signal does not need to be synchronized for FRC operation. It should be driven high throughout boundary scan operation. A.1.36 REQ[4:0]# (1/0) The REQ[4:0}# (Request Command) signals must connect the appropriate pins of all Pentium ll processor System Bus agents. They are asserted by the current bus owner over two clock cycles to define the currently active transaction type. A137 RESET# (I) Asserting the RESET# signal resets all processors to known states and invalidates their Li and L2 caches without writing back any of their contents. RESET# must remain active for one microsecond for a warm reset; for a power-on reset, RESET# must stay active for at least one millisecond after Veccore and CLK have reached their proper specifications. On observing active RESET#, all Pentium Il processor System Bus agents will deassert their outputs within two clocks. A number of bus signals are sampled at the active- to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Pentium I! Processor Developer's Manual (Order Number 243341). The processor may have its outputs tristated via power-on configuration. Otherwise, if INIT# is sampled active during the active-to-inactive transition of RESET#, the processor will execute its Built-In Self-Test (BIST). Whether or not BIST is executed, the processor will begin program execution at the reset-vector (default O_FFFF_FFFOh). RESET# must connect the appropriate pins of all Pentium Il processor System Bus agents. INTEL SECRET (until publication date)intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ ck TTT NS Nf NSF NS NAN VeGcore: 7 Vee 1 TLL) PWRGOOD reset TMM LTTLLLLLID a < 1 ms oroek Ratio WELD OOO760b Figure 50. PWRGOOD Relationship at Power-On A.1.38 RP# (I/O) The RP# (Request Parity) signal is driven by the request initiator, and provides parity protection on ADS# and REQ(4:0}#. It must connect the appropriate pins of all Pentium Il processor System Bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This definition allows parity to be high when all covered signals are high. A139 RS[2 :0]# (1) The R8[2:0}## (Response Status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all Pentium ll processor System Bus agents. A.1.40 RSP# (1) The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of R[2:0]#, the signals for which RSP# provides parity protection. It must connect the appropriate pins of all Pentium || processor System Bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0}# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. A141 SLOTOCC# (QO) The SLOTOCC# signal is defined to allow a system design to detect the presence of a terminator card or processor in a Pentium II connector. Combined with the VID combination of VID[4:0] = 11111 (see Section 2.6.), a system can determine if a Pentium Il connector is occupied, and whether a processor core is present. See Table 32 for states and values for determining the type of package in the Slot1 connector. Table 32. Slot 1 Occupation Truth Table Signal Value Status SLOTOCC# | 0 Processor with core in VID[4:0] Anything | Slot 1 connector. other than 11111 SLOTOCC# | 0 Terminator cartridge in VID[4:0] 11111 Slot 1 connector {i.e., no core present). SLoTocce | 1 VID[4:0] Slot 1 connector nat Any value | occupied. 8g 12/15/97 5:47 PM 24333502.doc INTEL CONFIDENTIAL (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & A.1.42 SLP# (I) The SLP# (Sleep) signal, when asserted in Stop Grant state, causes processors to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop Grant state, restarting its internal clock signals to the bus and APIC processor core units. A143 SMif# (I) The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. A.1.44 STPCLK# (I) The STPCLK# (Stop Clock) signal, when asserted, causes processors fo enter a low power Stop Grant state. The processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. A1454 TCK (I) The TCK (Test Clock) signal provides the clock input for the Pentium II processor Test Bus (also Known as the Test Access Port). A146 TDI(I) The TDI (Test Data In) signal transfers serial test data into the Pentium || processor. TDI provides the serial input needed for JTAG support. 90 A147 TDO (0) The TDO (Test Data Out) signal transfers serial test data out of the Pentium Il processor. TDO provides the serial output needed for JTAG support. A.1.48 TESTHI (I) The TESTHI signal must be connected to a 2.5 V power source through a 1 10k resistor for proper processor operation. A.1.49 THERMTRIP# (0} The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 130 C. This is signaled to the system by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched, and the processor stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a RESET# pulse will reset the processor and execution will continue. If the temperature has not dropped below the trip level, the processor will continue to drive THERMTRIP# and remain stopped. A.1.50 TMS (I) The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools. A151 TRDVY# (I) The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit write back data transfer. TRDY# must connect the appropriate pins of all Pentium ll processor System Bus agents. A.1.52 TRST# (1) The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST# must be driven low during power on reset. This can be accomplished with a 680 pull-down resistor. 12/15/97 5:47 PM 24333502.doc INTEL CONFIDENTIAL (until publication date)= intel PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ A.1.53 VID[4:0] (0) The VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not signals, but are either an open circuit or a short circuit to Vgg on the A.2. SIGNAL SUMMARIES processor. The combination of opens and shorts defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification variations on Pentium Il processors. See Table 2 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself. The following tables list attributes of the Pentium II processor output, input and I/O signals. Table 33. Output Signals Name Active Level Clock Signal Group FERR# Low Asynch CMOS Output IERR# Low Asynch CMOS Output PRDY# Low BOLK GTL+ Output SLOTOCC# Low Asynch Power/Other TBO High TCK JTAG Output THERMTRIP# Low Asynch CMOS Output VID[4:0] High Asynch Power/Other NOTE: 1. Outputs are not checked in FRG mode. a1 12/15/97 5:47 PM 24333502.doc INTEL CONFIDENTIAL (until publication date)= PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ intel & Table 34. Input Signals! Name Active Level Clock Signal Group Qualified A20M# Low Asynch CMOS Input Always2 BPRIl# Low BOLK GTL+ Input Always BRi# Low BCLK GTL+ Input Always BCLK High _ Clock Always DEFER# Low BCLK GTL+ Input Always FLUSH# Low Asynch CMOS Input Always2 IGNNE# Low Asynch CMOS Input Always2 INIT# Low Asynch CMOS Input Always? INTR High Asynch CMOS Input APIC disabled mode LINTT1 :0] High Asynch CMOS Input APIC enabled mode NMI High Asynch CMOS Input APIC disabled mode PICCLK High _ APIC Clack Always PREQ# Low Asynch CMOS Input Always PWRGCOD High Asynch CMOS Input Always RESET# Low BOLK GTL+ Input Always RS[2 :0}# Low BCLK GTL+ Input Always RSP# Low BOLK GTL+ Input Always SLP# Low Asynch CMOS Input During Stop Grant state SMl# Low Asynch CMOS Input STPCLK# Low Asynch CMOS Input TCK High JTAG Input TDI High TOK JTAG Input TESTHI High Asynch Power/Other Always TMS High TOK JTAG Input TRST# Low Asynch JTAG Input TRDY# Low BOLK GTL+ Input NOTES: 1. All asynchronous input signals except PWRGOOD must be synchronous in FRC. 2. Synchronous assertion with active TDRY# ensures synchronization. 92 12/15/97 5:47 PM 24333502.doc INTEL CONFIDENTIAL (until publication date)intel. PENTIUM Il PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ Table 35. Input/Output Signals (Single Driver) Name Active Level Clock Signal Group Qualified A[35:3]# Low BCLK GTL+ VO ADS#, ADS#+1 ADS# Low BCLK GTL+ lO Always AP[1:0}# Low BCLK GTL+ VO ADS#, ADS#+1 BRo# Low BCLK GTL+ I/O Always BP[B:2]# Low BCLK GTL+ VO Always BPM{[i :0]# Low BCLK GTL+ VO Always BSEL# Low Asynch Power/Other Always D[63 :O]# Low BCLK GTL+ lO DRDY# DBSY# Low BCLK GTL+ VO Always DEP[?7:0]}# Low BCLK GTL+ VO DRDY# DRDY# Low BCLK GTL+ I/O Always FRCERR High BCLK GTL+ I/O Always LOCK# Low BCLK GTL+ VO Always REQ/4:0]# Low BCLK GTL+ VO ADS#, ADS#+1 RP# Low BCGLK GTL+ VO ADS#, ADS#+1 Table 36. Input/Output Signals (Multiple Driver) Name Active Level Clock Signal Group Qualified AERR# Low BCGLK GTL+ lO ADS#+3 BERR# Low BCLK GTL+ VO Always BNR# Low BCLK GTL+ VO Always BINIT# Low BCLK GTL+ VO Always HIT# Low BCLK GTL+ VO Always HITM# Low BCLK GTL+ VO Always PICD[1:0] High PICCLK APIC I/O Always 93 12/15/97 5:47 PM 24333502.doc INTEL CONFIDENTIAL (until publication date)intel. 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