FemtoClock® NG Crystal-to-HCSL
Clock Generator
841654
DATASHEET
841654 REVISION A 4/20/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 841654 is an optimized PCIe and sRIO clock generator.
The device uses a 25MHz parallel crystal to generate 100MHz
and 125MHz clock signals, replacing solutions requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (< 1ps rms) suitable to clock components requiring precise and
low-jitter PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the 841654 can also drive the
high-speed sRIO and PCIe SerDes clock inputs of communication
processors, DSPs, switches and bridges.
FEATURES
• Four differential HCSL clock outputs: confi gurable for PCIe
(100MHz) and sRIO (100MHz or 125MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
• Selectable crystal oscillator interface, 25MHz, 18pF parallel reso-
nant crystal or LVCMOS/LVTTL single-ended reference
clock input
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• RMS phase jitter at 100MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
841654
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
VDD
REF_OUT
GND
QA0
nQA0
VDDOA
GND
QA1
nQA1
nREF_OE
BYPASS
REF_IN
REF_SEL
VDDA
IREF
FSEL0
FSEL1
QB0
nQB0
VDDOB
GND
QB1
nQB1
MR/nOE
VDD
XTAL_IN
XTAL_OUT
GND
0
1
1
0
M = ÷20
÷NA
÷NB
OSC
FemtoClock
PLL
VCO = 500MHz
XTAL_IN
XTAL_OUT
REF_IN
REF_SEL
IREF
BYPASS
FSEL[0:1]
MR/nOE
nREF_OE
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
REF_OUT
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
2 REVISION A 4/20/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1, 18 VDD Power Core supply pins.
2 REF_OUT Output Single-ended reference frequency clock output.
LVCMOS/LVTTL interface levels.
3, 7, 15, 22 GND Power Power supply ground.
4, 5,
8, 9
QA0, nQA0,
QA1, nQA1 Ouput Differential Bank A output pairs. HCSL interface levels.
6V
DDOA Power Output supply pin for Bank A outputs.
10 nREF_OE Input Pullup Active low REF_OUT enable/disable. See Table 3E.
LVCMOS/LVTTL interface levels.
11 BYPASS Input Pulldown Selects PLL operation/PLL bypass operation.
See Table 3C. LVCMOS/LVTTL interface levels.
12 REF_IN Input Pulldown Single-ended PLL reference clock input.
LVCMOS/LVTTL interface levels.
13 REF_SEL Input Pulldown Reference select. Selects the input reference source.
See Table 3B. LVCMOS/LVTTL interface levels.
14 VDDA Power Analog supply pin.
16, 17 XTAL_OUT,
XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
19 MR/nOE Input Pulldown
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the differential outputs are in high impedance
(HiZ). When logic LOW, the internal dividers and the differential outputs are
enabled. See Table 3D. LVCMOS/LVTTL interface levels.
20, 21
24, 25
nQB1, QB1
nQB0, QB0 Output Differential Bank B output pairs. HCSL interface levels.
23 VDDOB Power Output supply pin for Bank B outputs.
26, 27 FSEL1,
FSEL0 Input Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
28 IREF Output
HCSL current reference external resistor output. A fi xed precision resistor
(RREF = 475Ω) from this pin to ground provides a reference current used
for differential current-mode QA[0:1]/nQA[0:1] and QB[0:1]/nQB[0:1] clock
outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
RPULLUP Input PullupResistor 51 kΩ
RPULLDOWN Input Pulldown Resistor 51 kΩ
REVISION A 4/20/15
841654 DATA SHEET
3 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
TABLE 3B. REF_SEL FUNCTION TABLE
TABLE 3D. MR/nOE FUNCTION TABLE
TABLE 3C. BYPASS FUNCTION TABLE
Input
REF_SEL Input Reference
0 XTAL (default)
1 REF_IN
Input
BYPASS PLL Confi guration NOTE 1
0 PLL on (default)
1 PLL bypassed (QA, QB = fref/N)
NOTE 1: Asynchronous function.
Input
MR/nOE FunctionNOTE 1
0 Outputs enabled (default)
1 Device reset, outputs disabled (High Impedance)
NOTE 1: Asynchronous function.
TABLE 3A. FSELX FUNCTION TABLE (fref = 25MHZ)
TABLE 3E. nREF_OE FUNCTION TABLE
Input
nREF_OE FunctionNOTE 1
0 REF_OUT enabled
1 REF_OUT disabled (High Impedance) (default)
NOTE 1: Asynchronous function.
Inputs Outputs Frequency Settings
FSEL1 FSEL0 M QA0:1/nQA0:1 QB0:1/nQB0:1
0 0 20 VCO/5 (100MHz) VCO/5 (100MHz) (default)
0 1 20 VCO/5 (100MHz) VCO/4 (125MHz)
1 0 20 VCO/5 (100MHz) QB0:1 = L, nQB0:1 = H
1 1 20 VCO/4 (125MHz) VCO/4 (125MHz)
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
4 REVISION A 4/20/15
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI -0.5V to VDD + 0.5V
Outputs, VO -0.5V to VDDOX + 0.5V
Package Thermal Impedance, θJA 64.4°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 4A. POWER SUPPLY CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage VDD – 0.20 3.3 3.465 V
VDDOA,
VDDOB
Output Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current Unterminated 85 mA
IDDA Analog Supply Current Unterminated 20 mA
IDDOA and
IDDOB
Output Supply Current Unterminated, RREF = 475Ω ± 1% 5 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH Input High Current
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
VDD = VIN = 3.465 V 150 µA
nREF_OE VDD = VIN = 3.465V 5 µA
IIL Input Low Current
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
VDD = 3.465V, VIN = 0V -5 µA
nREF_OE VDD = 3.465V, VIN = 0V -150 µA
VOH
Ouput High Voltage;
NOTE 1 REF_OUT VDD = 3.465V 2.6 V
VOL
Ouput Low Voltage;
NOTE 1 REF_OUT VDD = 3.465V 0.5 V
ZOUT Output Impedance REF_OUT VDD = 3.465V 20 Ω
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagram.
REVISION A 4/20/15
841654 DATA SHEET
5 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 25 MHz
Equivalent Series Resistance (ESR) 50 Ω
Shunt Capacitance 7pF
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6A. LVCMOS AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency REF_OUT 25 MHz
tR / tFOutput Rise/Fall Time 20% to 80% 0.60 1.80 ns
odc Output Duty Cycle 49 51 %
TABLE 6B. HCSL AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency VCO/5 100 MHz
VCO/4 125 MHz
tjit(Ø) RMS Phase Jitter (Random);
NOTE 1
100MHz,
(1.875MHz - 20MHz) 0.44 ps
125MHz,
(1.875MHz - 20MHz) 0.44 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3 35 ps
tsk(o) Output Skew;
NOTE 2, 3
QAx/nQAx,
QBx/nQBx 100 ps
tLPLL Lock Time 100 ms
VHIGH Voltage High 125MHz 650 700 950 mV
VLOW Voltage Low -150 150 mV
VOVS Max. Voltage, Overshoot 0.3 V
VUDS Min. Voltage, Undershoot -0.3 V
Vrb Ringback Voltage 0.2 V
VCROSS Absolute Crossing Voltage 200 550 mV
ΔVCROSS Total Variation of VCROSS over all edges 160 mV
tR / tFOutput Rise/Fall Time QAx/nQAx,
QBx/nQBx
measured between
0.175V to 0.525V 100 700 ps
ΔtR /ΔtFRise/Fall Time Variation 125 ps
odc Output Duty Cycle QAx/nQAx,
QBx/nQBx 48 52 %
NOTE: All specifi cations are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
6 REVISION A 4/20/15
TYPICAL PHASE NOISE AT 125MHZ
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
OFFSET FREQUENCY (HZ)
➤
➤
➤
dBc
Hz
NOISE POWER
TYPICAL PHASE NOISE AT 100MHZ
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
OFFSET FREQUENCY (HZ)
➤
➤
➤
dBc
Hz
NOISE POWER
Filter
Raw Phase Noise Data
Phase Noise Result by adding
an Filter to raw data
Filter
Raw Phase Noise Data
Phase Noise Result by adding
a Filter to raw data
REVISION A 4/20/15
841654 DATA SHEET
7 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
HCSL OUTPUT LOAD AC TEST CIRCUIT
3.3V±5%
HCSL OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
CYCLE-TO-CYCLE JITTER
3.3V±5%
VDD,
VDDOA,
VDDOB
3.3V±5% 3.3V±5%
VDDA
VDD,
VDDOA,
VDDOB VDDA
HCSL OUTPUT SKEW
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
nQA[0:1],
nQB[0:1]
QA[0:1],
QB[0:1]
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
8 REVISION A 4/20/15
PARAMETER MEASUREMENT INFORMATION, CONTINUED
LVCMOS OUTPUT RISE/FALL TIME
20%
80% 80%
20%
t
R
t
F
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME
0.175V
0.525V 0.525V
0.175V
t
R
t
F
V
SWING
DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD
SE MEASUREMENT POINTS FOR DELTA CROSS POINT DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK
REF_OUT
nQAx,
nQBx
QAx, QBx
REVISION A 4/20/15
841654 DATA SHEET
9 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The 841654
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, VDDOA and
VDDOB should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic VDD
pin and also shows that VDDA requires that an additional10Ω
resistor along with a 10µF bypass capacitor be connected to the
VDDA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
VDDA
10μF
.01μF
3.3V
.01μF
VDD
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left fl oating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left fl oating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
HCSL OUTPUTS
All unused HCSL outputs can be left fl oating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left fl oating or terminated.
LVCMOS OUTPUT
The unused LVCMOS output can be left fl oating. We recommend
that there is no trace attached.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
10 REVISION A 4/20/15
CRYSTAL INPUT INTERFACE
The 841654 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
FIGURE 2. CRYSTAL INPUt INTERFACE
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can be left fl oating.
The input edge rate can be as slow as 10ns. For LVCMOS inputs,
it is recommended that the amplitude be reduced from full swing
to half swing in order to prevent signal interference with the power
rail and to reduce noise. This confi guration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and making R2 50Ω.
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
XTAL _ I N
XTAL _ OU T
VCC
R2
Ro
R1
Zo = 50
Rs
VCC
.1uf
VDD VDD
Zo = Ro + Rs
REVISION A 4/20/15
841654 DATA SHEET
11 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
SCHEMATIC LAYOUT
Figure 4 shows an example of 841654 application schematic.
In this example, the device is operated at VCC = 3.3V. The 18pF
parallel resonant 25MHz crystal is used. The C1 = 27pF and
C2 = 27pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
FIGURE 4. 841654 SCHEMATIC LAYOUT
nREF_OE
TL3
Zo = 50
+
-
RU2
Not Install
R8
10
R4
475
TL5
Zo = 50
C8
.1uf
Zo = 50
R5 33
V DDOA =3. 3V
VDD
C4
27pF
V DDOB=3.3 V
MR/ nOE
VDD
VCCOA
C2
10u
+
-
VDDOA
R12
50
LVCMOS
X1
25MHz
RD2
1K
R1 33
To Logic
Input
pins
C1
0.1u
VDD
C5
0.1u
VDDA
VDD
R7
50
C6
0.1u
Set Logic
Input to
'0'
BYPASS
Logic Control Input Examples
R13
50
Using for PCI Express
Add-In Card
To Logic
Input
pins
R2 33
RD1
Not Install
VDD=3.3V
VDD
VCCOB
C7
.1uf
REF_SEL
R6
50
VDDOB
U1
ICS841654I
1
2
3
4
5
14
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
12
13
28
27
26
25
VDD
REF_OUT
GND
QA0
nQA0
VDDA
VDDOA
GND
QA1
nQA1
nREF_OE
BYPASS
GND
XTAL_OUT
XTAL_IN
VDD
MR/ nOE
nQB1
QB1
GND
VDDOB
nQB0
REF_IN
REF_SEL
IREF
FSEL0
FSEL1
QB0
TL2
Zo = 50
C3
27pF
Set Logic
Input to
'1'
VDD
TL4
Zo = 50
FSEL0
18pF
HCSL Termination
FSEL1
REF_OUT
VDD
VDD
RU1
1K
Using for PCI Express
Point-to-Point
Connection
for optimizing frequency accuracy. One example of HCSL
and one example of LVCMOS terminations are shown in this
schematic. The decoupling capacitors should be located as
close as possible to the power pin.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
12 REVISION A 4/20/15
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 841654.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 841654 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 85mA = 294.5mW
• Power (outputs)MAX = 50.06mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 50.06mW = 200.24mW
Total Power_MAX (3.465V, with all outputs switching) = 294.5mW + 200.24mW = 494.74mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow
and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.495W * 64.5°C/W = 116.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 28-LEAD TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 64.5°C/W 60.4°C/W 58.5°C/W
REVISION A 4/20/15
841654 DATA SHEET
13 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 4.
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD is HIGH.
Power = (VDD_HIGH – VOUT ) * IOUT, since VOUT = IOUT * RL
= (VDD_HIGH – IOUT * RL) * IOUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 50.06mW
FIGURE 4. HCSL DRIVER CIRCUIT AND TERMINATION
V
DD
V
OUT
R
L
50
IC
I
OUT = 17mA
R
REF =
475
± 1%
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
14 REVISION A 4/20/15
RECOMMENDED TERMINATION
Figure 5A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
FIGURE 5A. RECOMMENDED TERMINATION
Figure 5B is the recommended termination for applications which
require a point to point connection and contain the driver and
receiver on the same PCB. All traces should all be 50Ω impedance.
FIGURE 5B. RECOMMENDED TERMINATION
REVISION A 4/20/15
841654 DATA SHEET
15 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 841654 is: 2954
TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 64.5°C/W 60.4°C/W 58.5°C/W
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
SYMBOL Millimeters
Minimum Maximum
N28
A -- 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 9.60 9.80
E 8.10 BASIC
E1 6.00 6.20
e 0.65 BASIC
L 0.45 0.75
α0° 8°
aaa -- 0.10
PACKAGE OUTLINE AND PACKAGE DIMENSIONS
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
16 REVISION A 4/20/15
TABLE 10. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature
ICS841654AGILF ICS841654AGILF 28 Lead “Lead-Free” TSSOP tube -40°C to 85°C
ICS841654AGILFT ICS841654AGILF 28 Lead “Lead-Free” TSSOP tape & reel -40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
REVISION A 4/20/15
841654 DATA SHEET
17 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
REVISION HISTORY SHEET
Rev Table Page Description of Change Date
A T10 16 Ordering Information - removed leaded devices.
Updated data sheet format. 4/20/15
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth-
er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason-
ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or
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Copyright 2015. All rights reserved.
