AD537–SPECIFICATIONS
(typical @ +25
ⴗ
C with V
S
(total) = 5 V to 36 V, unless otherwise noted)
AD537KD AD537SD
1
Model AD537JH AD537JD AD537KH AD537SH
1
CURRENT-TO-FREQUENCY CONVERTER
Frequency Range 0 kHz to 150 kHz * * *
Nonlinearity
1
f
MAX
= 10 kHz 0.15% max (0.1% typ) * 0.07% max **
f
MAX
= 100 kHz 0.25% max (0.15% typ) * 0.1% max **
Full-Scale Calibration Error
C = 0.01 µF, I
IN
= 1.000 mA ±10% max ±7% max ±5% max * *
vs. Supply (f
MAX
< 100 kHz) ±0.1%/V max (0.01% typ) * * *
vs. Temp (T
MIN
to T
MAX
)±150 ppm/°C max (50 ppm typ) * 50 ppm/°C max (30 ppm typ)
2
250 ppm/°C max
ANALOG INPUT AMPLIFIER
(Voltage-to-Current Converter)
Voltage Input Range
Single Supply 0 to (+V
S
– 4) Volts (min) * * *
Dual Supply –V
S
to (+V
S
– 4) Volts (min) * * *
Input Bias Current
(Either Input) 100 nA * * *
Input Resistance (Noninverting) 250 MΩ** *
Input Offset Voltage
(Trimmable in “D” Package Only) 5 mV max * 2 mV max **
vs. Supply 200 µV/V max 100 µV/V max 100 µV/V max **
vs. Temp (T
MIN
to T
MAX
)5µV/°C*1µV/°C10µV/°C max
Safe Input Voltage
3
±V
S
** *
REFERENCE OUTPUTS
Voltage Reference
Absolute Value 1.00 Volt ± 5% max * * *
vs. Temp (T
MIN
to T
MAX
) 50 ppm/°C * 100 ppm/°C max **
vs. Supply ±0.03%/V max * * *
Output Resistance
4
380 Ω** *
Absolute Temperature Reference
5
Nominal Output Level 1.00 mV/K * * *
Initial Calibration @ +25°C 298 mV (±5 mV typ) * 298 mV (±5 mV max) **
Slope Error from 1.00 mV/K ±0.02 mV/K * * *
Slope Nonlinearity ±0.1 K * * *
Output Resistance
5
900 Ω** *
OUTPUT INTERFACE (Open Collector Output)
(Symmetrical Square Wave)
Output Sink Current in Logic “0”
V
OUT
= 0.4 V max (T
MIN
to T
MAX
) 20 mA min 20 mA min 20 mA min 10 mA min
Output Leakage Current in Logic “1”
(T
MIN
to T
MAX
) 200 nA max * * 2 µA max
Logic Common Level Range –V
S
to (+V
S
– 4) Volts * * *
Rise/Fall Times (C
T
= 0.01 µF)
I
IN
= l mA 0.2 µs** *
I
IN
= 1 µA1µs** *
POWER SUPPLY
Voltage, Rated Performance
Single Supply 4.5 V to 36 V * * *
Dual Supply ±5 V to ±18 V * * *
Quiescent Current 1.2 mA (2.5 mA max) * * *
TEMPERATURE RANGE
Rated Performance 0°C to +70°C** –55°C to +125°C
Storage –65°C to +150°C** *
PACKAGE OPTIONS
6, 7
D-14 Ceramic DIP AD537JD AD537KD AD537SD
H-10A Header AD537JH AD537KH AD537SH
NOTES
*Specifications same as AD537JH.
**Specifications same as AD537K.
1
Nonlinearity is specified for a current input level (I
IN
) to the converter from 0.1 µA to 1000 µA. Converter has 100% overrange capability up to I
IN
= 2000 µA with slightly
reduced linearity. Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a percentage of full scale.
2
Guaranteed not tested.
3
Maximum voltage input level is equal to the supply on either input terminal. However, large negative voltage levels can be applied to the negative terminal if the input is scaled to
a nominal 1 mA full scale through an appropriate value resistor (See Figure 2).
4
Loading the 1.0 volt or 1 mV/K outputs can cause a significant change in overall circuit performance, as indicated in the applications section. To maintain normal operation,
these outputs should be operated into the external buffer or an external amplifier.
5
Temperature reference output performance is specified from 0°C to +70°C for “J” and “K” devices, –55°C to +125°C for “S” model.
6
D = Ceramic DIP; H = Hermetic Metal Can. For outline information see Package Information section.
7
For AD537/883B specifications, refer to Analog Devices Military Products Databook.
Specifications subject to change without notice.
REV. C
–2–
Applying the AD537
CIRCUIT OPERATION
Block diagrams of the AD537 are shown above. A versatile
operational amplifier (BUF) serves as the input stage; its pur-
pose is to convert and scale the input voltage signal to a drive
current in the NPN follower. Optimum performance is achieved
when, at the full-scale input voltage, a 1 mA drive current is
delivered to the current-to-frequency converter. The drive cur-
rent to the current-to-frequency converter (an astable
multivibrator) provides both the bias levels and the charging
current to the externally connected timing capacitor. This
“adaptive” bias scheme allows the oscillator to provide low non-
linearity over the entire current input range of 0.1 µA to
2000 µA. The square wave oscillator output goes to the output
driver which provides a floating base drive to the NPN power
transistor. This floating drive allows the logic interface to be ref-
erenced to a different level than –V
S
. The “SYNC” input (“D”
package only) allows the oscillator to be slaved to an external
master oscillator; this input can also be used to shut off the
oscillator.
The reference generator uses a bandgap circuit (this allows
single-supply operation to 4.5 volts which is not possible with
low T.C. Zeners) to provide the reference and bias levels for the
amplifier and oscillator stages. The reference generator also pro-
vides the precision, low T.C. 1.00 volt output and the V
TEMP
output which tracks absolute temperature at 1 mV/K.
V-F CONNECTION FOR POSITIVE INPUT VOLTAGES
The positive voltage input range is from –V
S
(ground in single
supply operation) to 4 volts below the positive supply. The con-
nection shown in Figure 1 provides a very high (250 MΩ) input
impedance. The input voltage is converted to the proper drive
current at Pin 3 by selecting a scaling resistor. The full-scale
current is 1 mA, so, for example a 10 volt range would require a
nominal 10 kΩ resistor. The trim range required will depend on
capacitor tolerance. Full-scale currents other than 1 mA can be
chosen, but linearity will be reduced; 2 mA is the maximum
allowable drive.
As indicated by the scaling relationship in Figure 1, a 0.01 µF
timing capacitor will give a 10 kHz full-scale frequency, and
0.001 µF will give 100 kHz with a 1 mA drive current. The
maximum frequency is 150 kHz. Polystyrene or NPO ceramic
capacitors are preferred for T.C. and dielectric absorption;
polycarbonate or mica are acceptable; other types will degrade
linearity. The capacitor should be wired very close to the
AD537.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
GUARD RING
R2 R1
V
IN
10kΩ10µF
OPTIONAL
INPUT
FILTER
C
R
T
20k
R
OUT
f
OUT
+V
S
F
O
=
V
IN
10 (R
1
+ R
2
) C
BUF
Figure 1. Standard V-F Connection for Positive Input
Voltages
V-F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENT
A wide range of negative input voltages can be accommodated
with proper selection of the scaling resistor, as indicated in Fig-
ure 2. This connection, unlike the buffered positive connection,
is not high impedance since the 1 mA F.S. drive current must be
supplied by the signal source. However, very large negative volt-
ages beyond the supply can be handled easily; just modify the
scaling resistors appropriately. Diode CR1 (HP50822811) is
necessary for overload and latchup protection for current or
voltage inputs.
If the input signal is a true current source, R1 and R2 are not
used. Full-scale calibration can be accomplished by connecting a
200 kΩ pot in series with a fixed 27 kΩ from Pin 7 to –V
S
(see
calibration section, below).
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
VT
VR
VIN
0 TO –10V
C
20kΩ
5kΩ (TYP) fOUT
+VS
FO = VIN
10 (R1 + R2) C
CR1
0 TO –1mA
IIN
R1
R2
FOUT = IIN
10C
Figure 2. V-F Connections for Negative Input Voltage or
Current
CALIBRATION
There are two independent adjustments: scale and offset. The
first is trimmed by adjustment of the scaling resistor R and the
second by the (optional) potentiometer connected to +V
S
and
the V
OS
pins (“D” package only). Precise calibration requires the
use of an accurate voltage standard set to the desired FS value
and a frequency meter; a scope is useful for monitoring output
waveshape. Verification of linearity requires the availability of a
switchable voltage source (or a DAC) having a linearity error
below ±0.005%, and the use of long measurement intervals to
minimize count uncertainties. Every AD537 is automatically tested
for linearity, and it will not usually be necessary to perform this
verification, which is both tedious and time-consuming.
Although drifts are small it is good practice to allow the operat-
ing environment to attain stable temperature and to ensure that
the supply, source and load conditions are proper. Begin by set-
ting the input voltage to 1/10,000 of full scale. Adjust the offset
pot until the output frequency is 1/10,000 of full scale (for ex-
ample 1 Hz for FS of 10 kHz). This is most easily accomplished
using a frequency meter connected to the output. Then apply
the FS input voltage and adjust the gain pot until the desired FS
frequency is indicated. In applications where the FS input is
small, this adjustment will very slightly affect the offset voltage,
due to the input bias current of the buffer amplifier. A change of
lkΩ in R will affect the input by approximately 100 µV, which is
as much as 0.1% of a 100 mV FS range. Therefore, it may be
necessary to repeat the offset and scale adjustments for the high-
est accuracy. The design of the input amplifier is such that the
input voltage drift after offset nulling is typically below l µV/°C.
REV. C –3–
AD537
REV. C
–4–
The –V
IN
, +V
IN
and I
IN
pins should not be driven more than
300 mV below –V
S
. This would cause internal junctions to con-
duct, possibly damaging the IC. The AD537 can be protected
from “below –V
S
” inputs by a Schottky diode, CR1 (HP5082-
2811) as shown in Figure 3. It is also desirable not to drive
+V
IN
, –V
IN
and I
IN
above +V
S
. In operation, the converter will
become very nonlinear for inputs above (+V
S
– 3.5 V). Control
currents above 2 mA will also cause nonlinearity.
The 80 dB dynamic range of the AD537 guarantees operation
from a control current of 1 mA (nominal FS) down to 100 nA
(equivalent to 1 mV to 10 V FS). Below 100 nA improper op-
eration of the oscillator may result, causing a false indication of
input amplitude. In many cases this might be due to short-lived
noise spikes which become added to the input. For example,
when scaled to accept a FS input of 1 V, the –80 dB level is
only 100 µV, so when the mean input is only 60 dB below FS
(1 mV), noise spikes of 0.9 mV are sufficient to cause momen-
tary malfunction.
This effect can be minimized by using a simple low-pass filter
ahead of the converter and a guard ring around the I
IN
or –V
IN
pins. For a FS of 10 kHz a single-pole filter with a time-constant
of 100 ms (Figure 2) will be suitable, but the optimum configu-
ration will depend on the application and type of signal process-
ing. Noise spikes are only likely to be a cause of error when the
input current remains near its minimum value for long periods
of time; above 100 nA (1 mV) full integration of additive input
noise occurs.
The AD537 is somewhat susceptible to interference from other
signals. The most sensitive nodes (besides the inputs) are the
capacitor terminals and the SYNC pin. The timing capacitor
should be located as close as possible to the AD537 to minimize
signal pickup in the leads. In some cases, guard rings or shield-
ing may be required. The SYNC pin should be decoupled
through a 0.005 µF (or larger) capacitor to Pin 13 (+V
S
). This
minimizes the possibility that the AD537 will attempt to syn-
chronize to a spurious signal. This precaution is unnecessary on
the metal can package since the SYNC function is not brought
out to a package pin and is thus not susceptible to pickup.
DECOUPLING
It is good engineering practice to use bypass capacitors on the
supply-voltage pins and to insert small-valued resistors (10 Ω to
100 Ω) in the supply lines to provide a measure of decoupling
between the various circuits in a system. Ceramic capacitors of
0.1 µF to 1.0 µF should be applied between the supply-voltage
pins and analog signal ground for proper bypassing on the
AD537.
A decoupling capacitor may also be useful from +V
S
to SYNC
in those applications where very low cycle-to-cycle period varia-
tion (jitter) is demanded. By placing a capacitor across +V
S
and
SYNC this noise is reduced. On the 10 kHz FS range, a 6.8 µF
capacitor reduces the jitter to one in 20,000 which adequate for
most applications. A tantalum capacitor should be used to avoid
errors due to dc leakage.
In some cases the signal may be in the form of a negative cur-
rent source. This can be handled in a similar way to a negative
input voltage. However, the scaling resistor is no longer re-
quired, eliminating the capability of trimming full scale in this
fashion. Since it will usually be impractical to vary the capaci-
tance, an alternative calibration scheme is needed. This is
shown in Figure 3. A resistor-potentiometer connected from
the V
R
output to –V
S
will alter the internal operating conditions
in a predictable way, providing the necessary adjustment range.
With the values shown, a range of ±4% is available; a larger
range can be attained by reducing R1. This technique does not
degrade the temperature-coefficient of the converter, and the
linearity will be as for negative input voltages. The minimum
supply voltage may be used.
Unless it is required to set the input node at exactly ground
potential, no offset adjustment is needed. The capacitor C is se-
lected to be 5% below the nominal value; with R2 in its
midposition the output frequency is given by:
f=I
10.5 ×C
where f is in kHz, I is in mA and C is in µF. For example, for a
FS frequency of 10 kHz at a FS input of 1 mA, C = 9500 pF.
Calibration is effected by applying the full-scale input and ad-
justing R2 for the correct reading.
This alternative adjustment scheme may also be used when it is
desired to present an exact input resistance in the negative volt-
age mode. The scaling relationship is then
f=V
REXACT
×1
10.5 C
The calibration procedure is then similar to that used for posi-
tive input voltages, except that the scale adjustment is by means
of R2.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
R1
27k
R2
200k
C
+VS
IIN
10C
f =
OUTPUT
VLOGIC
CAP
–VS
VOS
VOS
LOGIC GND
I
V
ADJ.
SCALE
DEC/SYN
VTEMP
VREF
BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
VT
VR
IIN
Figure 3. Scale Adjustment for Current Inputs
INPUT PROTECTION
The AD537 was designed to be used with a minimum of addi-
tional hardware. However, the successful application of a preci-
sion IC involves a good understanding of possible pitfalls and
the use of suitable precautions.
AD537
REV. C –5–
NONLINEARITY SPECIFICATION
The preferred method for specifying linearity error is in terms of
the maximum deviation from the ideal relationship after cali-
brating the converter at full scale and “zero”. This error will
vary with the full-scale frequency and the mode of operation.
The AD537 operates best at a 10 kHz full-scale frequency with
a negative voltage input; the linearity is typically within ±0.05%.
Operating at higher frequencies or with positive inputs will
degrade the linearity as indicates in the Specification table. The
shape of a typical linearity plot is given in Figure 4.
0.18
0.04
0.10
0.06
10
0.08
1
0.16
0.12
0.14
10k1k100
OUTPUT FREQUENCY – Hz
NONLINEARITY – % OF FULL SCALE
–0.08
–0.02
–0.06
–0.04
0
0.02
AD537J
AD537K, S
TEST CONDITIONS:
+VS = +15V
–VS = 0V
CT = 0.01µF
RT = 10kΩ
VFS = ±10V
POS INPUT – FIG. 3
NEG INPUT – FIG. 4
Figure 4a. Typical Nonlinearity Error Envelopes with
10 kHz F.S. Output
0.18
0.04
0.10
0.06
100
0.08
10
0.16
0.12
0.14
100k10k1k
OUTPUT FREQUENCY – Hz
NONLINEARITY – % OF FULL SCALE
–0.08
–0.02
–0.06
–0.04
0
0.02
AD537J
AD537K, S
TEST CONDITIONS:
+VS = +15V
–VS = 0V
CT = 0.001µF
RT = 10kΩ
VFS = ±10V
POS INPUT – FIG. 3
NEG INPUT – FIG. 4
Figure 4b. Typical Nonlinearity Error with 100 kHz F.S.
Output
OUTPUT INTERFACING CONSIDERATIONS
The design of the output stage allows easy interfacing to all digi-
tal logic families. The collector and emitter of the output NPN
transistor are both uncommitted; the emitter can be tied to any
voltage between –V
S
and 4 volts below +V
S
. The open collector
can be pulled up to a voltage 36 volts above the emitter regard-
less of +V
S
. The high power output stage can supply up to
20 mA (10 mA for “H” package) at a maximum saturation volt-
age of 0.4 volts. The stage limits the output current at 25 mA; it
can handle this limit indefinitely without damaging the device.
Figure 5 shows the AD537 with a standard 0 to +10 volt input
connection and the output stage connections. The values for the
logic common voltage, pull-up resistor, positive logic level, and
–V
S
supply are given in the accompanying chart for several logic
forms.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
C
f
OUT
+V
S
(+15V)
10k
V
IN
R
L
LOGIC V
CC
LOGIC COM
V
EE
V
OS
20k
–V
S
TTL/DTL
5V CMOS
15V CMOS/
HNIL
ECL 10k
ECL2.5k
PMOS
V
CC
+5
+5
+15
0
+1.3
0
V
EE
GND
GND
GND
–8
–2
–15
R
L
5k
20k
10k
5k
5k
10k
–V
S
GND
GND
GND
–8 TO
–15
–5
–15
BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
Figure 5. Interfacing Standard Logic Families
APPLICATIONS
The diagrams and descriptions of the following applications are
provided to stimulate the discerning engineer with alternative
circuit design ideas. “Applications of the AD537 IC Voltage-
to-Frequency Converter”, available from Analog Devices on
request, covers a wider range of topics and concepts in data
conversion and data transmission using voltage-to-frequency
converters.
TRUE TWO-WIRE DATA TRANSMISSION
Figure 6 shows the AD537 in a true two-wire data transmission
scheme. The twisted-pair transmission lines serves the dual pur-
pose of supplying power to the device and also carrying fre-
quency data in the form of current modulation. The PNP circuit
at the receiving end represents a fairly simple way for converting
the current modulation back into a voltage square wave which
will drive digital logic directly. The 0.6 volt square wave which
will appear on the supply line at the device terminals does not
affect the performance of the AD537 because of its excellent
supply rejection. Also, note that the circuit operates at nearly
constant average power regardless of frequency.
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
BUF
AD537
+V
IN
V
TEMP
V
REF
LOGIC
GND
+V
S
–V
S
(CONNECTED TO CASE)
10
9
8
7
6
5
4
3
2
1
RSCALE
RCAL
CTWO-WIRE
LINK
VS
+5
+15
RS
0
1k
RL
1k
3.3k
120
RS
220Ω
+VS
OUTPUT
RL
V
IN
Figure 6. True Two-Wire Operation
AD537
REV. C
–6–
F-V CONVERTERS
The AD537 can be used as a high linearity VCO in a phase-
locked loop to accomplish frequency-to-voltage conversion. By
operating the loop without a low-pass filter in the feedback path
(first-order system), it can lock to any frequency from zero to an
upper limit determined by the design, responding in three or
four cycles to a step change of input frequency. In practice, the
overall response time is determined by the characteristics of the
averaging filter which follows the PLL.
Figure 7 shows a connection using a low power TTL quad
open-collector nand gate which serves as the phase comparator.
The input signal should be a pulse train or square wave with
characteristics similar to TTL or 5-volt CMOS outputs. Any
duty cycle is acceptable, but the minimum pulse width is 40 µs.
The output voltage is one volt for a 10 kHz input frequency.
The output as shown here is at a fairly high impedance level; for
many situations an additional buffer may be required.
Trimming is similar to V-F application trimming. First set the
V
OS
trimmer to mid-scale. Apply a 10 kHz input frequency and
trim the 2 kΩ potentiometer for 1.00 volts out. Then apply a
10 Hz waveform and trim the V
OS
for 1 mV out. Finally, retrim
the full-scale output at 10 kHz. Other frequency scales can be
obtained by appropriate scaling of timing components.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
DRIVER
PRECISION
VOLTAGE
REFERENCE
CURR
-TO-
FREQ
CONV
BUF
20k
V
OS
f
IN
(0-10kHz)
2k
10k
0.001µF
1N4148
0.005µF 3.9k 120k OUTPUT
1V F.S.
0.33µF
10k
10k
74LO3
+
5V
10k
9.09k
Figure 7. 10 kHz F-V Converter
TEMPERATURE-TO-FREQUENCY CONVERSION
The linear temperature-proportional output of the AD537 can
be used as shown in these applications to perform various direct
temperature-to-frequency conversion functions; it can also be
used with other external connections in a temperature sensing
or compensation scheme. If the sensor output is used externally,
it should be buffered through an op amp since loading that
point will cause significant error in the sensor output as well as
in the main V-F converter circuitry.
An absolute temperature (Kelvin)-to-frequency converter is very
easily accomplished, as shown in Figure 8. The 1 mV per K out-
put serves as the input to the buffer amplifier, which then scales
the oscillator drive current to a nominal 298 µA at +25°C
(298K). Use of a 1000 pF capacitor results in a corresponding
frequency of 2.98 kHz. Setting the single 2 kΩ trimmer for the
correct frequency at a well-defined temperature near +25°C will
normally result in an accuracy of ±2°C from –55°C to +125°C
(using an AD537S). An NPO ceramic capacitor is recom-
mended to minimize nonlinearity due to capacitance drift.
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
AD537
+V
V
TEMP
V
REF
LOGIC
GND
+V
S
–V
S
(CONNECTED TO CASE)
10
9
8
7
6
5
4
3
2
1
9.1kΩ
10kΩ
f = 10Hz/K
1000pF
2kΩ
BUF
Figure 8. Absolute Temperature to Frequency Converter
OFFSET TEMPERATURE SCALES
Many other temperature scales can be set up by offsetting the
temperature output with the voltage reference output. Such a
scheme is shown by the Celsius-to-frequency converter in
Figure 9. Corresponding component values for a Fahrenheit-to-
frequency converter which give 10 Hz/°F are given in parentheses.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
10k
fOUT
10Hz/°C
(10Hz/°F)
+5V
2.74k
(4.02k)
500Ω
3900 pF
(1500pF)
2k
6.04k
(10k)
49Ω
(205Ω)BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
VT
VR
Figure 9. Offset Temperature Scale Converters Centigrade
and (Fahrenheit) to Frequency
A simple calibration procedure which will provide ±2°C accu-
racy requires substitution of a 7.27k resistor for the series com-
bination of the 6.04k with the 2k trimmer; then simply set the
500 Ω trimmer to give 250 Hz at +25°C.
High accuracy calibration procedure:
1. Measure room temperature in K.
2. Measure temperature output at Pin 6 at that temperature.
3. Calculate offset adjustment as follows:
Offset Voltage ( mV ) = VTEMP (Pin 6 ) ( mV )
Room temp ( K ) ×273.2
4. Temporarily disconnect 49 Ω resistor (or 500 Ω pot) and
trim 2 kΩ pot to give the offset voltage at the indicated node.
Reconnect 49 Ω resistor.
5. Adjust slope trimmer to give proper frequency at room tem-
perature (+25°C = 250 Hz).
Adjustment for °F or any other scale is analogous.
AD537
REV. C –7–
SYNCHRONOUS OPERATION
The SYNC terminal at pin 2 of the DIP package can be used to
synchronize a free running AD537 to a master oscillator, either
at a multiple or a sub-multiple of the primary frequency. The
preferred connection is shown in Figure 10. The diodes are used
to produce the proper drive magnitude from high level signals.
The SYNC terminal can also be used to shut off the oscillator.
Shorting the terminal to +V
S
will stop the oscillator, and the
output will go high (output NPN off).
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
R+V
S
C
T
f
OUT
V
IN
C
S
V
SYNC
1000pF
2
C
S
V
SYNC
1N4148
10k
NOTE: IF V
SYNC
>2V p-p
USE THIS LIMITER
BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
Figure 10. Connection for Synchronous Operation
Figure 11 shows the maximum pull-in range available at a given
signal level; the optimum signal is a 0.8 to 1.0 volt square wave;
signals below 0.1 volt will have no effect; signals above 2 volts
p-p will disable the oscillator. The AD537 can normally be syn-
chronized to a signal which forces it to a higher frequency up to
30% above the nominal free-running frequency, it can only be
brought down about 1–2%.
0.2 0.4 0.6 0.8 1.0
V
SYNC
SQUARE-WAVE INPUT VOLTS p-p
30%
20%
10%
FREQUENCY
LOCK-IN
RANGE
Figure 11. Maximum Frequency Lock-ln Range vs.
Sync Signal
LINEAR PHASE LOCKED LOOP
The phase-locked-loop F/V circuit described earlier operates
from an essentially noise-free binary input. PLL’s are also used
to extract frequency information from a noisy analog signal. To
do this, the digital phase-comparator must be replaced by a lin-
ear multiplier. In the implementation shown in Figure 12, the
triangular waveform appearing across the timing capacitor is
used as one of the multiplier inputs; the signal provides the
other input. It can be shown that the mean value of the multi-
plier output is zero when the two signals are in quadrature. In
this condition, the ripple in the error signal is also quite small.
Thus, the voltage at Pin 5 is essentially zero, and the frequency
is determined primarily by the current in the timing resistor,
controlled either manually or by a control voltage.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
CAP
0.01µF
OUTPUT
+V
S
V
OS
–V
S
SIGNAL
INPUT
±12V PK
1
2
6
7810
12
11
14
+15V
COM-
POSITE
ERROR
SIGNAL
±1V PK
–15V
10k
DEC/
SYN
FREQ
CONTROL
INPUT
0 TO –10V
V
TEMP
V
REF
RECOVERED
FREQUENCY
SIGNAL
3.9V
DRIVER
PRECISION
VOLTAGE
REFERENCE
CURR
-TO-
FREQ
CONV
BUF
LOGIC
GND
V
R
V
T
Figure 12. Linear Phase-Locked Loop
Noise on the input signal affects the loop operation only slightly;
it appears as noise in the timing current, but this is averaged out
by the timing capacitor. On the other hand, if the input fre-
quency changes there is a net error voltage at Pin 5 which acts
to bring the oscillator back into quadrature. Thus, the output at
Pin 14 is a noise-free square-wave having exactly the same fre-
quency as the input signal. The effectiveness of this circuit can
be judged from Figure 13 which shows the response to an input
of 1 V rms 1 kHz sinusoid plus 1 V rms Gaussian noise. The
positive supply to the AD537 is reduced by about 4 V in order
to keep the voltages at Pins 11 and 12 within the common-mode
range of the AD534.
Since this is also a first-order loop the circuit possesses a very
wide capture range. However, even better noise-integrating
properties can be achieved by adding a filter between the multi-
plier output and the VCO input. Details of suitable filter charac-
teristics can be found in the standard texts on the subject.
1V RMS SIGNAL
+1V RMS NOISE
OUTPUT
Figure 13. Performance of AD537 Linear Phase Locked
Loop
By connecting the multiplier output to the lower end of the tim-
ing resistor and moving the control input to Pin 5, a high resis-
tance frequency-control input is made available. However, due
to the reduced supply voltage, this input cannot exceed +6 V.
TRANSDUCER INTERFACE
The AD537 was specifically designed to accept a broad range of
input signals, particularly small voltage signals, which may be
converted directly (unlike many V-F converters which require
signal preconditioning). The 1.00 V stable reference output is
also useful in interfacing situations, and the high input resis-
tance allows nonloading interfacing from a source of varying
resistance, such as the slider of a potentiometer.
AD537
REV. C
–8–
PRINTED IN U.S.A. C397f–0–4/00 (rev. C)
THERMOCOUPLE INPUT
The output of a Chromel-Constantan (Type E) thermocouple,
using a reference junction at 0°C, varies from 0 mV to 53.14 mV
over the temperature range 0°C to +700°C with a slope of
80.678 µV/degree over most of its range and some nonlinearity
over the range 0°C to +200°C. For this example, we assume
that it is desired to indicate temperature in Degrees Celsius
using a counter/display with a 100 ms gate width. Thus, the V-F
converter must deliver an output of 7 kHz for an input of
53.14 mV. If very precise operation down to 0°C is imperative,
some sort of linearizing is necessary (see, for example, Analog
Devices’ Nonlinear Circuits Handbook, pp. 92–97) but in many
cases operation is only needed over part of the range.
The circuit shown in Figure 14 provides good accuracy from
+300°C to +700°C. The extrapolation of the temperature volt-
age curve back to 0°C shows that an offset of –3.34 mV is
required to fit the curve most exactly. This small amount of
voltage can be introduced without an additional calibration step
using the +1.00 V output of the AD537. To adjust the scale, the
thermocouple should be raised to a known reference tempera-
ture near 500°C and the frequency adjusted to value using R1.
The error should be within ±0.2% over the range 400°C to
700°C.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
+5V
V
LOGIC
10Hz/
°
C
0.005µF
47k
I
OFFSET
≈ 21µA
120
R1 SCALE
50
T
MEAS
T
REF
(0
°
C)
0 TO 53mV
BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
360µA
F
S
Figure 14. Thermocouple Interface with First-Order
Linearization
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Side-Brazed Ceramic DIP (TO–116)
(D–14)
PIN 1
0.310 (7.87)
0.220 (5.59)
0.098 (2.49) MAX
0.005 (0.13) MIN
8
7
14
1
0.200
(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
PLANE
0.785 (19.94) MAX
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
10-Lead Metal Can (TO-100)
(H-10A)
36°
BSC
0.034 (0.86)
0.028 (0.71)
0.045 (1.14)
0.029 (0.74)
0.115
(2.92)
BSC
0.230
(5.84)
BSC
6
8
57
1
4
2
39
10
REFERENCE PLANE
BASE & SEATING PLANE
0.355 (9.02)
0.305 (7.75)
0.370 (9.40)
0.335 (8.51)
0.562 (14.30)
0.500 (12.70)
0.040 (1.01)
0.010 (0.25)
0.050
(1.27)
MAX
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
0.185 (4.70)
0.165 (4.19)
0.044 (1.12)
0.032 (0.81)
