Product Flyer December 1996 MB86689A Version 2.05 Address Translation Controller (ATC) FML/NPD/ATC/FL/1206 The Fujitsu MB86689A Address Translation Controller provides an autonomous high speed translation function of ATM cell header information in real time at 155Mb/s. It replaces ATM virtual path identifiers (VPI) and virtual channel identifiers (VCI) and can append a 1-3 byte routing tag if required. PLASTIC PACKAGE QFP-80 The device can be used with the MB86683B Network Termination Controller (NTC) or placed directly in the cell stream. When used with the NTC, ATM cell headers are received and transmitted through a dedicated port. When used in the cell stream, ATM cells are received and transmitted through 8-bit parallel cell stream interfaces. The ATC is ideally suited to UNI and NNI applications in ATM hubs, switches and adapter cards. FEATURES * 1024 entry content addressable memory. * Full 28 bit comparison for each entry. * Selectable VPI and VCI mask for each entry. * Supports UNI and NNI cell header formats. * Supports multiple matches (NTC Mode only). * Supports flexible tag sizes. * Supports the provision of translation data suitable for Usage Parameter Control. * Supports CLP and congestion indication and removal for each entry. * Multiple ATCs can be cascaded to support larger translation tables (NTC mode only). * Translation is completed in less than one cell period at 155Mb/s. * Entries can be updated on-the-fly without affecting the translation process. * JTAG pins compliant to IEEE1149.1 are provided. * Fabricated in 0.8 micron CMOS technology with CMOS/TTL compatible I/O and single +5V power supply. Copyright (c) 1996 Fujitsu Microelectronics Limited Page 1 of 6 December 1996Version 2.05 FML/NPD/ATC/FL/1206 MB86689A Address Translation Controller (ATC) Cell Stream Interface Processor Interface Cell Stream Interface Controller NTC Interface MPU Interface Controller Input Data Formatter CAM Array Output Data Formatter Output RAM Controller JTAG JTAG Interface Cascade Interface Fig. 1 - ATC Block Diagram General A top level logical block diagram of the ATC is shown in Fig. 1 above. The main modules are as shown and are described below. The ATC provides high speed translation (<1 cell period at 155Mbps) of header information for 1024 entries, each entry being associated with up to 3 bytes routing tag. The ATC also provides two interface modes; NTC Interface mode and Cell Stream Interface mode. Fig. 2 on page 4 illustrates how the ATC may be configured when the NTC Interface mode is selected and the alternative mode of configuration - Cell Stream Interface mode - enables in-line address translation. Data Formatters The Input Data Formatter is responsible for removing an incoming cell's Virtual Path and Virtual Channel Identifiers (VPI and VCI) and for providing this data as a comparend to the ATC's Content Addressable Memory Array (CAM Array). The Output Data Formatter is responsible for providing the newly-translated VPI/VCI data and routing tags for the cell awaiting transmission. Copyright (c) 1996 Fujitsu Microelectronics Limited Page 2 of 6 December 1996Version 2.05 FML/NPD/ATC/FL/1206 MB86689A Address Translation Controller (ATC) CAM Array On receiving the 28-bit VPI/VCI comparend, the ATC compares the data against each active match entry in the CAM Array. Output RAM If a match is found between the 28-bit VPI/VCI comparend and an entry within the CAM Array then the ATC activates both the Output RAM and Output Data Formatter. The Output RAM will contain the newly-translated VPI/VCI data and up to 3 bytes of routing tag information. In NTC mode of operation, if more than one match is detected for the same input data, then the ATC will sequentially output associated RAM data for each match. Multiple matches are not supported within Cell Stream Interface mode. NTC Interface This interface allows the ATC to communicate directly with the Network Termination Controller. Transfer of information is across a dedicated bidirectional databus controlled via a 4-wire handshake mechanism. Only header information is transferred across this interface. Cascade Interface In NTC Mode, this 3-bit interface allows 2 ATCs to be connected together to form a larger translation table. Each ATC will perform its search in parallel hence incurring no increase in search time. Larger translation tables can be implemented with minimal glue logic. Cell Stream Interface This interface allows the ATC to buffer and process entire ATM cells received across a 9-bit cell based interface. Processor Interface A 16-bit bi-directional Microprocessor interface allows entries in the CAM Array and Input RAM to be updated on the fly without affecting the translation process. UPC Port On detecting a match, the 4-bit UPC port provides a 2-bit ATC code and a 10bit output RAM address. JTAG The ATC provides boundary scan test circuitry compliant with IEEE 1149.1 (JTAG). The ATC's JTAG circuitry permits easier board level testing to be carried out by allowing the signal pins on the device to form a serial scan chain around the device. JTAG test modes are controlled by accessing an internal test access port controller, which is in turn controlled by the 4 provided test access ports. Copyright (c) 1996 Fujitsu Microelectronics Limited Page 3 of 6 December 1996Version 2.05 FML/NPD/ATC/FL/1206 MB86689A Address Translation Controller (ATC) ATM Terminal Equipment ATC MB86687A ALC MB86683B NTC MB582A/583A Transceiver User Network Interface (UNI) Host CPU ATM Switch - UNI Port ATC UNI MB582A/583A Transceiver MB86683B NTC Switch Matrix ATC ATM Switch - Signalling controller MB86687A ALC ATC Switch Matrix Host CPU Fig. 2 - Example Configurations Copyright (c) 1996 Fujitsu Microelectronics Limited Page 4 of 6 December 1996Version 2.05 FML/NPD/ATC/FL/1206 MB86689A Address Translation Controller (ATC) NTC Interface NTCD0-7 Microprocessor Interface D0 - D15 RD WR CS DREQ FTM RESET TEST JTAG NTC_RFD ATC_RFD ATC_DAV NTC_DAV CLK Clock IPSOC IPD0 - IPD7 OPD0 - OPD7 MB86689A ATC TDI TDO TMS TCK CRFDO CDAVI CRFDI Cascade Interface Cell Stream Interface OPSOC TAGSEL TSIZE0 TSIZE1 HEC CSMODE OPCTL Mode Select Inputs UPCO_0-UPCO_3 UPC Port Fig. 3 - MB86689A I/O Block Diagram This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Copyright (c) 1996 Fujitsu Microelectronics Limited Page 5 of 6 December 1996Version 2.05 FML/NPD/ATC/FL/1206 MB86689A Address Translation Controller (ATC) Worldwide Headquarters Japan Fujitsu Limited Asia Tel: +81 44 754 3753 Fax: +81 44 754 3332 1015 Kamiodanaka Nakaharaku Kawasaki 211 Japan Tel: Fax: +65 336 1600 +65 336 1609 http://www.fujitsu.co.jp/ http://www.fsl.com.sg/ USA Europe Tel: +1 408 922 9000 Fax: +1 408 922 9179 Fujitsu Microelectronics Inc 3545 North First Street San Jose CA 95134-1804 USA Tel: +49 6103 6900 Fax: +49 6103 690122 Tel: +1 800 866 8608 Fax: +1 408 922 9179 Customer Response Center Mon-Fri: 7am-5pm (PST) http://www.fujitsu-ede.com/ Fujitsu Microelectronics Asia PTE Limited No. 51 Bras Basah Road Plaza by the Park #06-04/07 Singapore 0718 Fujitsu Mikroelektronik GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany http://www.fujitsumicro.com/ This document is proprietary to Fujitsu. No part of this document may be copied or reproduced in any form or by any means, or disclosed or transferred to any third party without written prior consent of Fujitsu. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any title or licence under the copyright, patent rights or trade marks claimed and owned by Fujitsu or its licensors. Fujitsu reserves the right to change specifications without notice. FML/NPD/ATC/FL/1206 - 2.05 Copyright (c) 1996 Fujitsu Microelectronics Limited Page 6 of 6