2144x-DSH-001-N Mindspeed Technologies®November 2013
Preliminary Information / Mindspeed Proprietary and Confidential
M21440/M21441 - 1.0625 to 10.3125 Gbps
8 Channel/12 Channel 1.0625 Gbps to 10.3125 Gbps CDR
with Adaptive DFE
Preliminary Information
This document contains information on a new product. The parametric information, although not
fully characterized, is the result of testing initial devices.
Features
• Data rates from 1.0625 to 10.3125 Gbps
• Support for proprietary data rates
• 8x8/12x12 non-blocking crosspoint switch
• Individual channel LOS (Loss Of Signal) detection and squelch
• Integrated PRBS pattern generator/checker
• Auto-rate detecting CDRs
• Post-equalization eye monitors
• Up to 27 dB of programmable/adaptive input equalization
• Up to 12 dB of post-cursor de-emphasis, 4 dB pre-cursor
de-emphasis
• Single 1.2 V supply option
• Electrical idle pass-through
The M21440/M21441 are eight/twelve channel equalizers and CDRs designed to operate up to 10.3125 Gbps. The devices
feature specialized ports for both backplane and intra-PCB communications. On the backplane side, the M2144x is equipped
with high- performance inputs featuring an adaptive Continuous Time Linear Equalizer (CTLE) and an adaptive Decision
Feedback Equalizer (DFE). Each channel has a programmable output driver, with post-tap and pre-tap de-emphasis (up to
12 dB total). The devices are designed to compensate for 10GBase-KR electrical backplanes.
To counter the effects of non-equalizable jitter, the M2144x are equipped with sophisticated clock and data recovery (CDR)
circuits. The CDRs are equipped with auto-rate detect, further reducing configuration requirements. The M2144x is able to
support many proprietary data rates up to 10.3125 Gbps. The M2144x devices also provide the user with a full suite of link
assessment tools including loopbacks, pattern generator/checker, and post-equalization eye monitors. All devices feature fully
non-blocking crosspoint switch cores that allow any input of the device to be connected to any output without restriction.
Block Diagram
M21440
4
4
4
Xpt
Switch
4
PCB
Driver
Backplane
Driver
Adaptive EQ
+
CDR
Adaptive EQ
+
CDR
CPU
Interface
Ref Clk
M21441
4
4
4
Xpt
Switch
PCB
Driver
Adaptive EQ
+
CDR
CPU
Interface
Ref Clk
4
Backplane
Driver
Adaptive EQ
+
CDR
Backplane
Driver
Adaptive EQ
+
CDR
Primary
Interface
Secondary
Interface
4
4
Applications
• Backplane switching and signal conditioning
• LAN switches
• Blade servers
• Datacom, telecom, enterprise switchers/routers
• Wireless base stations
• Redundancy switching
2144x-DSH-001-N Mindspeed Technologies®2
Preliminary Information / Mindspeed Proprietary and Confidential
Ordering Information
Part Number Channel Count Maximum Data Rate Package Case Operating Temperature
M21440G-15P* 8x8 10.3125 Gbps 12x12 mm, 88-pin QFN -40 °C to + 85 °C
M21441G-14* 12x12 6.25 Gbps 19x19 mm, 324-pin BGA -40 °C to + 85 °C
M21441G-15* 12x12 10.3125 Gbps 19x19 mm, 324-pin BGA -40 °C to + 85 °C
* The letter “G” designator after the part number indicates that the device is RoHS compliant. Refer to www.mindspeed.com/RoHS for additional
information. The M21440G-14P is backward compatible with the standard SnPb reflow temperature per J-STD-220D. However, part numbers
M21441G-14 and M21441G-15P are not backward compatible.
Revision History
Revision Level Date Description
N Release November 2013 Updated M21440 Package Drawing (Figure 3-2).
M Release June 2013 Update M21441 pinout diagram to correct typo errors for NC pins
L Release May 2013 Updated ordering part numbers
Added specification for maximum skew between any channels
Added maximum power consumption specifications for M21440
K Released April 2012 Removed references to M21430 and M21431 part numbers since they have been
discontinued.
Updated M21441G-14 device for production release supporting a maximum data rate of
6.25 Gbps. M21440G-14P and M21441G-15P devices are pre-production and support data
rates of up to 10.3125 Gbps.
J Preliminary December 2011 Updated Section 5.0.
I Preliminary November 2011 Corrected silicon revision to -14P.
H Preliminary September 2011 Updated to reflect new silicon revision -14.
Revised typical sinusiodal jitter tolerance typical value from 120 to 300 mUI in Table 1-4.
G Advance July 2011 Refer to previous revisions for details.
F Advance January 2011 Refer to previous revisions for details.
E Advance July 2010 Refer to previous revisions for details.
D Advance May 2010 Refer to previous revisions for details.
C Advance December 2009 Refer to previous revisions for details.
B Advance October 2009 Refer to previous revisions for details.
A Advance August 2009 Initial release.
2144x-DSH-001-N Mindspeed Technologies®3
Preliminary Information / Mindspeed Proprietary and Confidential
M2144x Marking Diagrams
Part Num ber
Lot N um ber
Date and Country Code
RoHS Symbol
M21441 G-14
YYWW CC
XXXX.X
E1
M21441 G-15
YYWW CC
E1
XXXX.X
M21440 G-15P
YYWW CC
XXXX.X
E1
2144x-DSH-001-N Mindspeed Technologies®4
Preliminary Information / Mindspeed Proprietary and Confidential
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.0 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.0 Typical Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.0 Pinout Diagram, Pin Descriptions, and Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 M21440 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2 M21440 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3 M21440 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.4 M21441 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.5 M21441 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.6 M21441 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.0 Functional Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.2 Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3 Device Register Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.6 High-Speed Input and Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.7 Input Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.8 Driver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.9 Alarms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.9.1 Loss-Of-Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.9.2 Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.9.3 CDR Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.9.3.1 Loss-Of-Lock (LOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.10 Electrical Idle Pass-through. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.11 Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.12 Crosspoint Switch Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.13 PRBS Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.14 PRBS Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.15 Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.16 Clock and Data Recovery Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table of Contents
2144x-DSH-001-N Mindspeed Technologies®5
Preliminary Information / Mindspeed Proprietary and Confidential
4.16.1 Automatic Rate Detection (ARD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.17 In Circuit Eye Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.18 Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.19 Two-wire Serial Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.20 MDIO Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.21 4-Wire Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.22 Memory Interface Control (MIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.23 JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5.0 Control Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1 Page 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.2 Page 01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
5.3 Page 02h & 04h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
2144x-DSH-001-N Mindspeed Technologies®6
Preliminary Information / Mindspeed Proprietary and Confidential
1.0 Electrical Characteristics
Unless noted otherwise, specifications in this section are valid with DVDDO = 3.3 V, AVDDO_KR = 1.2 V, AVDDO_XFI =
1.2 V, AVDD = 1.2 V power supplies, 25 °C ambient temperature, 800 mVPPD differential input data swing, default
output data swing, PRBS31 test pattern at 10.3125 Gbps, RLOAD = 50 Ω.
Table 1-1. Absolute Maximum Ratings
Symbol Parameter Note Minimum Typical Maximum Unit
DVDDO Digital Output Supply Voltage — -0.5 — 3.6 V
AVDDO_KR Analog Output Supply Voltage — -0.5 — 2.1 V
AVDDO_XFI Analog Output Supply Voltage — -0.5 — 2.1 V
AVDD Analog Core Supply Voltage — -0.5 — 1.5 V
VIN DC Input Voltage (PCML) — VSS – 0.5 — AVDD + 0.5 V
VIN, CMOS DC Input Voltage (CMOS) — VSS – 0.5 — DVDDO + 0.5 V
TSTORE Storage Temperature 1 –65 — 150 °C
TJUNC Junction Temperature — — — 125 °C
VESD, HBM Electrostatic Discharge Voltage (HBM) 2 -2000 — 2000 V
VESD, CDM Electrostatic Discharge Voltage (CDM) 2 -500 — 500 V
NOTES:
1. Exposure of the device beyond the minimum/maximum limits may cause permanent damage.
2. HBM and CDM per JEDEC Class 2 (JESD22-A114-B).
Table 1-2. Recommended Operating Conditions
Symbol Parameter Minimum Typical Maximum Unit
DVDDO Digital Output Supply Voltage 1.14 1.2/1.8/2.5/3.3 3.47 V
AVDDO_KR Analog Output Supply Voltage 1.14 1.2 / 1.8 1.89 V
AVDDO_XFI Analog Output Supply Voltage 1.14 1.2 / 1.8 1.89 V
AVDD Analog Core Supply Voltage 1.14 1.2 1.26 V
TCASE M21440 Case Temperature -40 — 85 °C
M21441 Case Temperature -40 — 85 °C
NOTES:
1. 1.8 V operation required for AC-coupling, while 1.2 V operation can support DC-coupling.
Electrical Characteristics
2144x-DSH-001-N Mindspeed Technologies®7
Preliminary Information / Mindspeed Proprietary and Confidential
Table 1-3. Power Consumption Specifications
Symbol Parameter Note Minimum Typical Maximum Unit
DIDDO Digital Output Supply Current (DVDDO = 3.3 V) — — 4 7.1 mA
AIDDO_KR Analog Output Supply Current KR 1 — 128 167 mA
AIDDO_XFI Analog Output Supply Current XFI 1 — 64 83 mA
AIDDCORE M21440 Analog Supply Current 1, 2 — 3.3 4.5 A
M21441 Analog Supply Current 1, 2 — 5.0 6.1 A
PTOTAL M21440 Power Dissipation 1, 2 — 4.3 6.5 W
M21441 Power Dissipation 1, 2 — 6.4 8.5 W
NOTES:
1. Typical with AVDDO=1.2 V, nominal (800 mVPPD) output data swing and DC-coupled on all channels. All 8/12 channels running at 10.3125 Gbps.
2. Maximum with AVDDO=1.8 V, AC-coupled and max output swing for all channels. All 8/12 channels running at 10.3125 Gbps.
Table 1-4. PCML Input and Output Electrical Characteristics (1 of 2)
Symbol Parameter Note Minimum Typical Maximum Unit
DR NRZ data rate (M21441-14) — 1.0625 — 6.25 Gbps
NRZ data rate (M21441-15P, M21440-14P) — 1.0625 — 10.3125 Gbps
ROUT Output Termination Resistance — 80 100 120 Ω
VOUT Differential Output Voltage (Low swing setting) 1 250 360 — mVPPD
Differential Output Voltage (High swing setting) 1, 2 — 1040 1250 mVPPD
VOCM Output Common Mode Voltage — — — 1.9 V
tPD Propagation Delay (any input to any output) 4 — 1.5 2.0 ns
tSKEW, CH Inter-pair skew within any group of four channels 4 — — 1.5 UI
tSKEW Inter-pair skew within all channels 4 — — 2.0 UI
tR/tFRise/Fall Time (20%–80%) 1, 3 24 47 — ps
tDJ Output deterministic jitter 3, 4 — 120 250 mUI
tRJ Output random jitter 3, 4, 5 — 6 15 mUIpp
Pstcur DE Transmitter post-cursor de-emphasis 6 0 — 12 dB
Precur DE Transmitter pre-cursor de-emphasis 7 0 — 4 dB
VIN Input range 5, 10 200 — 1200 mVPPD
Electrical Characteristics
2144x-DSH-001-N Mindspeed Technologies®8
Preliminary Information / Mindspeed Proprietary and Confidential
RIN Input termination resistance — 80 100 120 Ω
DCDDATA Duty cycle distortion tolerance 5, 8, 9 — — 35 mUI
NOTES:
1. Measured using CID patterns in excess of 10.
2. Nominal AVDD0 of 1.8 V is required for output swing greater than 800 mVPPD.
3. Measured point blank @ Tx using an 800 mVPPD launch.
4. Test pattern PRBS15. Propagation delay measured at 10.3125 Gbps.
5. Tested to bit error rate of 1E-12 with system jitter de-embedded.
6. Pre-cursor de-emphasis turned off.
7. Post-cursor de-emphasis turned off.
8. Test pattern is PRBS31.
9. A 10GBASE-KR compliant channel at frequencies ranging from 0.1 MHz to 300 MHz. RJ and DCD jitter also applied.
10. If the inputs are DC-coupled, then an I/O supply of 1.8 V is recommended. If a 1.2 V I/O supply is used and the inputs are DC-coupled, then the
input common mode voltage must be between 0.8-1.2 V.
Table 1-5. CDR Performance Specifications
Symbol Parameter Note Minimum Typical Maximum Unit
JTOL Jitter Tolerance @ 6.25 Gbps 6 0.4 — — UI
Jitter Tolerance @ 10.3125 Gbps 6 TBD 0.5 — UI
JPK Jitter Peaking (up to LBW)2, 4——1dB
LBW Loop Bandwidth 1, 2 — DR/1667 — Hz
REFFREQ Reference Clock Frequency 3 62.5 156.25 312.5 MHz
REFACC Reference Clock Accuracy — -100 — 100 ppm
REFAMP Reference Clock Amplitude 5 500 — 1200 mV
NOTES:
1. Example: 6.19 MHz for 10.3125 Gbps data rate.
2. Measured with 150 mUI input sinusoidal modulation.
3. See Section 4.16 (recommended reference frequency for application data rates).
4. Jitter peaking for SONET applications is 0.1 dB max.
5. Must be AC-coupled.
6. Jitter at frequencies above 20 MHz. Jitter tolerance measured with fixed insertion loss connected to device input. Fixed insertion loss is 10 dB
measured at 3.125 GHz (for 6.25 Gbps JTOL) and 14 dB measured at 5.16 GHz (for 10.3125 Gbps JTOL).
Table 1-4. PCML Input and Output Electrical Characteristics (2 of 2)
Symbol Parameter Note Minimum Typical Maximum Unit
Electrical Characteristics
2144x-DSH-001-N Mindspeed Technologies®9
Preliminary Information / Mindspeed Proprietary and Confidential
Table 1-6. Control/Interface Logic Input/Output Characteristics
Symbol Parameter Note Minimum Typical Maximum Unit
VOH Output Logic High IOH = –1/3 mA 1 0.85 x DVDDO DVDDO —V
VOL Output Logic Low IOL = 1/3 mA 1 — 0 0.15 x DVDDO V
VIF CMOS input floating level — 0.25 x DVDDO 0.5 x DVDDO 0.75 x DVDDO —
VIH Input Logic High — 0.85 x DVDDO —DV
DDO V
VIL Input Logic Low — 0 — 0.15 x DVDDO V
NOTES:
1. When using the two-wire programming interface, IOH and IOL max is 3 mA. When using the MDIO or four-wire programming interfaces, IOH
and IOL max is 1 mA.
2144x-DSH-001-N Mindspeed Technologies®10
Preliminary Information / Mindspeed Proprietary and Confidential
2.0 Typical Performance
Characteristics
Unless noted otherwise, typical performance applies for DVDDO = 3.3 V, AVDDO_KR = 1.8 V, AVDDO_XFI = 1.8 V,
AVDD = 1.2 V, 25 °C ambient temperature, 1000 mVPPD differential input/output data swing, PRBS 215 – 1 data
pattern at 10.3125 Gbps.
Figure 2-1. Eye Diagram @ 10.3125 Gbps without
M2144x, After Approximately 27 dB of
Insertion Loss at Nyquist Frequency
Figure 2-2. Eye Diagram @ 10.3125 Gbps with
M2144x, After Approximately 27 dB of
Insertion Loss at Nyquist Frequency
Figure 2-3. Eye Diagram @ 8 Gbps without
M2144x, After Approximately 27 dB of
Insertion Loss at Nyquist Frequency
Figure 2-4. Eye Diagram @ 8 Gbps with M2144x,
After Approximately 27 dB of
Insertion Loss at Nyquist Frequency
Typical Performance Characteristics
2144x-DSH-001-N Mindspeed Technologies®11
Preliminary Information / Mindspeed Proprietary and Confidential
Figure 2-5. Eye Diagram @ 6.25 Gbps with
M2144x, After Approximately 27 dB of
Insertion Loss at Nyquist Frequency
Figure 2-6. Eye Diagram @ 6.25 Gbps with
M2144x, After Approximately 27 dB of
Insertion Loss at Nyquist Frequency
Figure 2-7. Input Equalization Test Setup Utilizing Test Backplane
Pattern
Generator
Data Out P
Data Out N
M2144 x
Error Detector/
Digital
Communications
Analyzer
10G-Base KR Backplane
M2144 x
Figure 2-8. Output De-Emphasis Test Setup Utilizing Test Backplane
Pattern
Generator
Data Out P
Data Out N
M2144 x
Error Detector/
Digital
Communications
Analyzer
10G-Base KR Backplane
2144x-DSH-001-N Mindspeed Technologies®12
Preliminary Information / Mindspeed Proprietary and Confidential
3.0 Pinout Diagram, Pin Descriptions,
and Package Outline Drawing
3.1 M21440 Pinout Diagram
Figure 3-1. M21440 Pinout Diagram (Top View of the Package)
M21440
88-PIN QFN
(12x12)
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
26
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
27
TDI
XFI_IN0N
XFI_IN0P
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
KR_IN0N
KR_IN0P
KR_IN1P
KR_IN1N
XFI_IN1P
XFI_IN1N
REFCK2
REFCK1
xSET
AVDD
AVDD
AVDD
AVDD
AVDD
N/C
AVDD
AVDD
CONFIG0
CONFIG1
CONFIG2
XFI_IN2P
XFI_IN2N
KR_IN2P
KR_IN2N
KR_IN3P
KR_IN3N
XFI_IN3P
XFI_IN3N
N/C
AVDD
AVDD
AVDD
TDO
CDR_HW1
CDR_HW0
MF3
RESET_N
ALARM
DRVR_PWR
XFI_OUT0P
XF I_ OU T0N
XF I_ OU T1N
XFI_OUT1P
XFI_OUT2P
XFI_OUT2N
AVDDO_XFI
XFI_OUT3N
XFI_OUT3P
MF0
MF1
MF2
DVDDO
AVDDO_XFI
AVDD
AVDD
KR_OUT0P
KR_OUT3P
KR_OUT3N
KR_OUT2N
KR_OUT2P
AVDD
KR_OUT1P
KR_OUT1N
KR_OUT0N
AVDD
AVDDO_KR
AVDD
AVDD
N/C
N/C
AVDD
AVDD
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
AVDD
AVDD
AVDDO_KR
AVDDO_KR
N/C
N/C
AVDD
Pinout Diagram, Pin Descriptions, and Package Outline Drawing
2144x-DSH-001-N Mindspeed Technologies®13
Preliminary Information / Mindspeed Proprietary and Confidential
3.2 M21440 Pin Description
Table 3-1. M21440 Pin Description
Pin Name Pin Number(s) Type Description
AVDDO_KR 83,77,73 Power Analog IO positive supply on KR side
AVDDO_XFI 30, 36 Power Analog IO positive supply on XFI side
AVDD 1, 4, 5, 8, 9, 12, 13, 14,17,
18,21, 27, 33, 39, 49, 52, 55,
56, 57, 60, 63, 68, 71, 72, 74,
80, 86
Power Analog positive supply
DVDDO 43 Power Digital output positive supply
VSS Exposed Pad on bottom of
package
Ground Ground
NC 2, 3, 69, 70, 87, 88 N/A Do not connect
REFCK1, REFCK2 48, 22 CMOS input CMOS Reference Clock Inputs (AC-coupled)
RESET_N 24 CMOS input Device Reset input pin
ALARM 25 CMOS output Alarm output pin
DRVR_PWR 26 Control Power down control on output drivers
MF0,1,2, 3 40, 41, 42, 44 CMOS input Multifunction pins
TDO 47 CMOS output JTAG TDO pin
TDI 23 CMOS input JTAG TDI pin
CDR_HW[1:0] 45, 46 CMOS input CDR preset configurations
xSET 64 CMOS input Switch control pin
CONFIG0, 1, 2 67, 66, 65 Control Multifunction decode pins
KR_IN0P, N 11, 10 PCML input Channel0 KR inputs P, N
KR_IN1P, N 15, 16 PCML input Channel1 KR inputs P, N
KR_IN2P, N 58, 59 PCML input Channel2 KR inputs P, N
KR_IN3P, N 54, 53 PCML input Channel3 KR inputs P, N
XFI_IN0P, N 7, 6 PCML input Channel4 XFI inputs P, N
XFI_IN1P, N 19, 20 PCML input Channel5 XFI inputs P, N
XFI_IN2P, N 61, 62 PCML input Channel6 XFI inputs P, N
XFI_IN3P, N 51, 50 PCML input Channel7 XFI inputs P, N
KR_OUT0P, N 75, 76 PCML output Channel0 KR outputs P, N
KR_OUT1P, N 79, 78 PCML output Channel1 KR outputs P, N
KR_OUT2P, N 81, 82 PCML output Channel2 KR outputs P, N
KR_OUT3P, N 85, 84 PCML output Channel3 KR outputs P, N
XFI_OUT0P, N 28, 29 PCML output Channel4 XFI outputs P, N
Pinout Diagram, Pin Descriptions, and Package Outline Drawing
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Preliminary Information / Mindspeed Proprietary and Confidential
XFI_OUT1P, N 32, 31 PCML output Channel5 XFI outputs P, N
XFI_OUT2P, N 34, 35 PCML output Channel6 XFI outputs P, N
XFI_OUT3P, N 38, 37 PCML output Channel7 XFI outputs P, N
Table 3-1. M21440 Pin Description
Pin Name Pin Number(s) Type Description
Pinout Diagram, Pin Descriptions, and Package Outline Drawing
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Preliminary Information / Mindspeed Proprietary and Confidential
3.3 M21440 Package Information
Figure 3-2. M21440 Packaging Drawing
NOTES:
FROM THE TERMINAL TIP (BOTH ROWS). IF THE TERMINAL HAS OPTIONAL RADIUS ON THE END OF THE TERMINAL,
2. DIMENSION OF LEAD WIDTH APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15mm AND 0.30mm
THE LEAD WIDTH DIMENSION SHOULD NOT BE MEASURED IN THAT RADIUS AREA
1. DIMENSIONING AND TOLERANCE IS IN CONFORMANCE TO ASME Y14.5-1994
ALL DIMENSIONS ARE IN MILLIMETERS ˚ IN DEGREES
DETAIL B (SCALE 2:1)
0.50
DATUM A OR B
88X
0.50/2
0.10 C A B
0.05 C
DETAIL A (SCALE 3:1)
0.40±0.10
0.45 REF
R0.20 REF
0.23+0.07
-0.05
0.20 REF
C
0.02+0.03
-0.02
0.90±0.10
SEATING PLANE
0.10 C
0.08 C
8
8X
12.00
B
12.00 A
PIN 1 AREA
0.10 C
2X
0.10 C
2X
9.40±0.10 0.10 C A B
9.40±0.10
0.10 C A
B
DETAIL A
DATUM A
DATUM B
DETAIL B
Pinout Diagram, Pin Descriptions, and Package Outline Drawing
2144x-DSH-001-N Mindspeed Technologies®16
Preliminary Information / Mindspeed Proprietary and Confidential
3.4 M21441 Pinout Diagram
Figure 3-3. M21441 Pinout Diagram (Top View of the Package)
123456789101112131415161718
A
AVSS AVSS AVDDT
_BP NC AVDD XIN2P AVDD KIN2PR AVDD KIN2P AVDD KIN3P AVDD KIN3PR AVDD XIN3P AVDD AVSS
A
B
AVDDT
_BP AVSS AVSS NC AVSS XIN2N AVSS KIN2NR AVSS KIN2N AVSS KIN3N AVSS KIN3NR AVSS XIN3N AVSS AVSS
B
C
KOUT0
PR
KOUT0
NR AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS MF2
C
D
AVDDT
_BP AVSS AVSS CONFI
G1
CONFI
G2 XSET AVDD AVDD AVDD AVDD AVDD AVDD TDI TDO CDR_H
W1
CDR_H
W0 MF1 MF0
D
E
KOUT1
PR
KOUT1
NR AVSS CONFI
G0 AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD MF3 AVSS AVSS AVDDT
_ASIC
E
F
AVDDT
_BP AVSS AVSS AVDDT
_BP AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD DVDDO AVSS XOUT3
N
XOUT3
P
F
G
KOUT2
PR
KOUT2
NR AVSS AVDDT
_BP AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD DVDDO AVSS AVSS AVDDT
_ASIC
G
H
AVDDT
_BP AVSS AVSS AVDDT
_BP AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD AVDDT
_ASIC AVSS XOUT2
N
XOUT2
P
H
J
KOUT3
PR
KOUT3
NR AVSS AVDDT
_BP AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD AVDDT
_ASIC AVSS AVSS AVDDT
_ASIC
J
K
AVDDT
_BP AVSS AVSS AVDDT
_BP AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD AVDDT
_ASIC AVSS XOUT1
N
XOUT1
P
K
L
KOUT0
P
KOUT0
NAVSS AVDDT
_BP AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD AVDDT
_ASIC AVSS AVSS AVDDT
_ASIC
L
M
AVDDT
_BP AVSS AVSS AVDDT
_BP AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD DRVR_
PWR AVSS XOUT0
N
XOUT0
P
M
N
KOUT1
P
KOUT1
NAVSS AVDD AVDD AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD ALARM AVSS AVSS AVDDT
_ASIC
N
P
AVDDT
_BP AVSS AVSS AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD RESET
_N AVSS AVSS AVDD
P
R
KOUT2
P
KOUT2
NAVSS AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD CKREF
1
CKREF
2AVSS XIN1N XIN1P
R
T
AVDDT
_BP AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD
T
U
KOUT3
P
KOUT3
NAVSS NC AVSS NC AVSS XIN0N AVSS KIN0NR AVSS KIN0N AVSS KIN1N AVSS KIN1NR AVSS AVSS
U
V
AVDDT
_BP AVSS AVDDT
_BP NC AVDD NC AVDD XIN0P AVDD KIN0PR AVDD KIN0P AVDD KIN1P AVDD KIN1PR AVDD AVSS
V
123456789101112131415161718
Pinout Diagram, Pin Descriptions, and Package Outline Drawing
2144x-DSH-001-N Mindspeed Technologies®17
Preliminary Information / Mindspeed Proprietary and Confidential
3.5 M21441 Pin Description
Table 3-2. M21441 Pin Description
Pin Name Pin Number(s) Type Description
AVDDO_KR A3,B1,D1,F1,F4,G4,H1,H4,J4,K1,K4,L4,
M1,M4,P1,T1,V1,V3
Power Analog IO positive supply on KR side
AVDDO_XFI E18,G18,H15,J15,J18,K15,L15,L18,N18 Power Analog IO positive supply on XFI side
AVDD A11,A13,A15,A17,A5,A7,A9,D10,D11,D1
2,D7,D8,D9,E10,E11,E12,E13,E14,E5,E6,
E7,E8,E9,F14,F5,G14,G5,H14,H5,J14,J5,
K14,K5,L14,L5,M14,M5,N14,N4,N5,P10,
P11,P12,P13,P14,P18,P4,P5,P6,P7,P8,
P9,R10,R11,R12,R13,R4,R5,R6,R7,R8,
R9,T18,V11,V13,V15,V17,V5,V7,V9
Power Analog positive supply
DVDDO F15,G15 Power Digital output positive supply
VSS A1,A18,A2,B11,B13,B15,B17,B18,B2,B3,
B5,B7,B9,C10,C11,C12,C13,C14,C15,C1
6,C17,C3,C4,C5,C6,C7,C8,C9,D2,D3,E16
,E17,E3,F10,F11,F12,F13,F16,F2,F3,F6,F
7,F8,F9,G10,G11,G12,G13,G16,G17,G3,
G6,G7,G8,G9,H10,H11,H12,H13,H16,H2
,H3,H6,H7,H8,H9,J10,J11,J12,J13,J16,J
17,J3,J6,J7,J8,J9,K10,K11,K12,K13,K16
,K2,K3,K6,K7,K8,K9,L10,L11,L12,L13,L1
6,L17,L3,L6,L7,L8,L9,M10,M11,M12,M
13,M16,M2,M3,M6,M7,M8,M9,N10,N11
,N12,N13,N16,N17,N3,N6,N7,N8,N9,P16
,P17,P2,P3,R16,R3,T10,T11,T12,T13,T1
4,T15,T16,T17,T2,T3,T4,T5,T6,T7,T8,T9,
U11,U13,U15,U17,U18,U3,U5,U7,U9,V1
8,V2
Ground Ground
NC V4,U4,A4,B4,V6,U6 N/A Do not connect
REFCK1, REFCK2 D13,R14 CMOS input CMOS Reference Clock Inputs (AC-coupled)
RESET_N P15 CMOS input Device Reset input pin
ALARM N15 CMOS output Alarm output pin
DRVR_PWR M15 Control Power down control on output drivers
MF0,1,2, 3 D18,D17,C18,E15 CMOS input Multifunction pins
TDO D14 CMOS output JTAG TDO pin
TDI R15 CMOS input JTAG TDI pin
CDR_HW[1:0] D15,D16 CMOS input CDR preset configurations
xSET D6 CMOS input Switch control pin
CONFIG0, 1, 2 E4,D4,D5 Control Multifunction decode pins
KR_IN0P, N V12,U12 PCML input Channel0 KR inputs P, N
KR_IN1P, N V14,U14 PCML input Channel1 KR inputs P, N
Pinout Diagram, Pin Descriptions, and Package Outline Drawing
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Preliminary Information / Mindspeed Proprietary and Confidential
KR_IN2P, N A10,B10 PCML input Channel2 KR inputs P, N
KR_IN3P, N A12,B12 PCML input Channel3 KR inputs P, N
KR_IN0PR, NR V10,U10 PCML input Channel8 KR redundant inputs P, N
KR_IN1PR, NR V16,U16 PCML input Channel9 KR redundant inputs P, N
KR_IN2PR, NR A8,B8 PCML input Channel10 KR redundant inputs P, N
KR_IN3PR, NR A14,B14 PCML input Channel11 KR redundant inputs P, N
XFI_IN0P, N V8,U8 PCML input Channel4 XFI inputs P, N
XFI_IN1P, N R18,R17 PCML input Channel5 XFI inputs P, N
XFI_IN2P, N A6,B6 PCML input Channel6 XFI inputs P, N
XFI_IN3P, N A16,B16 PCML input Channel7 XFI inputs P, N
KR_OUT0P, N L1,L2 PCML output Channel0 KR outputs P, N
KR_OUT1P, N N1,N2 PCML output Channel1 KR outputs P, N
KR_OUT2P, N R1,R2 PCML output Channel2 KR outputs P, N
KR_OUT3P, N U1,U2 PCML output Channel3 KR outputs P, N
KR_OUT0PR, NR C1,C2 PCML output Channel8 KR redundant outputs P, N
KR_OUT1PR, NR E1,E2 PCML output Channel9 KR redundant outputs P, N
KR_OUT2PR, NR G1,G2 PCML output Channel10 KR redundant outputs P, N
KR_OUT3PR, NR J1,J2 PCML output Channel11 KR redundant outputs P, N
XFI_OUT0P, N M18,M17 PCML output Channel4 XFI outputs P, N
XFI_OUT1P, N K18,K17 PCML output Channel5 XFI outputs P, N
XFI_OUT2P, N H18,H17 PCML output Channel6 XFI outputs P, N
XFI_OUT3P, N F18,F17 PCML output Channel7 XFI outputs P, N
Table 3-2. M21441 Pin Description
Pin Name Pin Number(s) Type Description
Pinout Diagram, Pin Descriptions, and Package Outline Drawing
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Preliminary Information / Mindspeed Proprietary and Confidential
3.6 M21441 Package Information
Figure 3-4. M21441 Packaging Drawing
2144x-DSH-001-N Mindspeed Technologies®20
Preliminary Information / Mindspeed Proprietary and Confidential
4.0 Functional Descriptions
4.1 General Description
The M21440/M21441 are eight/twelve channel signal conditioner crosspoints with adaptive/programmable input
equalization, programmable output de-emphasis, an embedded 8x8/12x12 crosspoint switch matrix, and a clock
data recovery unit (CDR) per channel. A reference clock is required for the CDR operation. See Section 4.16 for
details. Functional block diagrams of the devices are shown in Figure 4-1 and Figure 4-2. The KR [0:3] and
KRr[0:3] are designed for a higher attenuation cable or backplane interfaces, while the XFI [0:3] channels are
designed for lower attenuation PCB interfaces. All paths on the M2144x are fully differential to maintain signal
integrity. Figure 4-3 illustrates a typical backplane retimer application with M2144x devices and Figure 4-4
illustrates a failover switch application using M2144x devices.
Figure 4-1. M21441 Functional Block Diagram
12x12
Crosspoint
XFI_IN2
XFI_OUT2
KRr_OUT0
KR_IN0
KR_OUT0
XFI_IN0
KRr_IN0
XFI_OUT0
KR_IN1
KR_OUT1
XFI_IN1
KRr_IN1
XFI_OUT1
KRr_OUT1
KR_IN2
KRr_IN2
KR_OUT2
KRr_OUT2
XFI_IN3
XFI_OUT3
KR_IN3
KRr_IN3
KR_OUT3
KRr_OUT3
PLL[0]
CDR
RX
RX
RX
TX
TX
TX
PLL[1]
CDR
RX
RX
RX
TX
TX
TX
Eye Monitor PRBS
Generator/Detector
CDR
PLL[2]
TX
TX
TX
RX
RX
RX
CDR
PLL[3]
TX
TX
TX
RX
RX
RX
MDIO
I
2
CPROM
Interface JTAG
Alarm
4-wire
Functional Descriptions
2144x-DSH-001-N Mindspeed Technologies®21
Preliminary Information / Mindspeed Proprietary and Confidential
Figure 4-2. M21440 Functional Block Diagram
Functional Descriptions
2144x-DSH-001-N Mindspeed Technologies®22
Preliminary Information / Mindspeed Proprietary and Confidential
Figure 4-3. Typical 10GBase-KR Application
Figure 4-4. Application Example - Failover Switch
M21440
KR Device
Backplane
I2C / MD IO / PR OM
MAC
FPGA
ASIC
SFP+
XFI
Connectors
Line Card / CPU BLADE Switch Card
10 GBASE- KR Channel
Ref Clk
44 4
M 2144x
Device
Backplane
MAC
FPGA
ASIC
SFP+
XFI
Connectors
Line Card / CPU BLADE
Primary Switch Card
10GBASE - KR Channels
44
4
M 21441
44
Secondary Switch Card
4
4
4
M 2144x
Device
Functional Descriptions
2144x-DSH-001-N Mindspeed Technologies®23
Preliminary Information / Mindspeed Proprietary and Confidential
4.2 Register Initialization
For robust operation of the device across specified data rates, Mindspeed recommends that the following register
values are modified from their default values after initial powerup. Registers 47h, 57h, 67h, 77h, 4Bh, 5Bh, 6Bh,
7Bh, 4Fh, 5Fh, 6Fh, and 7Fh should be changed from their default value of 00h to a value of 60h. After these
register values are modified, then the other device registers should be modified as needed in order to configure
parameters such as switch settings, data rate programming, and output settings.
4.3 Device Register Nomenclature
The purpose of this section to clarify the M2144x device channel nomenclature. The channel names and
associated group names are described in Ta bl e 4 - 3 . The differences between backplane and ASIC interface are
described in more detail in Section 4.7.
Table 4-1. M2144x Channel Names and Associated Group Names
Device Group Name Input Channel Output Channel Interface Type
M21441 Group KR KR_IN0 KR_OUT0 Backplane
KR_IN1 KR_OUT1 Backplane
KR_IN2 KR_OUT2 Backplane
KR_IN3 KR_OUT3 Backplane
Group XFI XFI_IN0 XFI_OUT0 ASIC
XFI_IN1 XFI_OUT1 ASIC
XFI_IN2 XFI_OUT2 ASIC
XFI_IN3 XFI_OUT3 ASIC
Group KRr KR_IN0r KR_OUT0r Backplane Redundant
KR_IN1r KR_OUT1r Backplane Redundant
KR_IN2r KR_OUT2r Backplane Redundant
KR_IN3r KR_OUT3r Backplane Redundant
M21440 Group KR KR_IN0 KR_OUT0 Backplane
KR_IN1 KR_OUT1 Backplane
KR_IN2 KR_OUT2 Backplane
KR_IN3 KR_OUT3 Backplane
Group XFI XFI_IN0 XFI_OUT0 ASIC
XFI_IN1 XFI_OUT1 ASIC
XFI_IN2 XFI_OUT2 ASIC
XFI_IN3 XFI_OUT3 ASIC
Functional Descriptions
2144x-DSH-001-N Mindspeed Technologies®24
Preliminary Information / Mindspeed Proprietary and Confidential
The M21440/M21441 have four different PLL banks and three channels within a bank. The channel names and
associated banks are described in Table 4-2.
4.4 Power Supply
The M21440 and M21441 have four distinct power supply domains: AVDD, AVDDO_KR, AVDDO_XFI, and DVDDO.
The AVDD power domain is used to power both the analog and digital cores of the device and must be set to 1.2 V.
There are two IO power domains on the M21440 and M21441: AVDDO_KR and AVDDO_XFI; both can support
either 1.2 V or 1.8 V. The AVDDO_KR is used to power the backplane side of the device whereas the AVDDO_XFI
is used to power the PCB side of the device. In order to achieve output swings greater than 800 mVPPD or for use
when AC-coupled, AVDDO should be set to 1.8 V.
The fourth power domain is DVDDO which is used to power the digital logic and control interfaces of the M21440
and M21441. DVDDO supports 1.2 V, 1.8 V, 2.5 V, or 3.3 V to allow for various external devices to interface with the
M21440 and M21441. It is recommended to connect DVDDO to the same plane as the device connected to it.
4.5 Reset
The M2144x initiates a power-on reset upon application of supply power. A hardware reset pin and software reset
are also provided. The hardware reset is invoked by an active low pin (RESET_N). The software reset is invoked by
Table 4-2. Channel and PLL Bank Mapping
Device PLL Bank Channels
M21441 PLL[0] KR [0], XFI[0], KR[0]r
PLL[1] KR [1], XFI[1], KR[1]r
PLL[2] KR [2], XFI[2], KR[2]r
PLL[3] KR [3], XFI[3], KR[3]r
M21440 PLL[0] KR [0], XFI[0]
PLL[1] KR [1], XFI[1]
PLL[2] KR [2], XFI[2]
PLL[3] KR [3], XFI[3]
Figure 4-5. Power Supply Domains
AV
DDO
KR= 1.2 or 1.8V
AV
DD
= 1.2V
AV
DDO
XFI= 1.2 or 1.8V
DV
DDO
= 1.2 or 1.8 or 2.5 or 3.3V
M2144x
Functional Descriptions
2144x-DSH-001-N Mindspeed Technologies®25
Preliminary Information / Mindspeed Proprietary and Confidential
writing the value AAh to the master reset register (page0, Addr E0h). All registers are set to their default state
upon reset.
4.6 High-Speed Input and Output Buffers
The input buffers in the M2144x are designed to be AC-coupled and 0.1 µF is the suggested capacitor value. The
output buffers are designed with PCML logic, and can operate in either AC-coupled or DC-coupled systems. If the
inputs are DC-coupled, then an I/O supply of 1.8 V is recommended. If a 1.2 V I/O supply is used and the inputs
are DC-coupled, then the input common mode voltage must be between 0.8-1.2 V. Both the input and output
buffers have integrated 50 Ω termination and support boundary scan. Note that for applications where a common
mode pulse may be sent to the Rx device for a receive detect function, the M2144x input impedance will look to be
approximately 150 Ω instead of the expected 50 Ω.
The driver swing can be programmed in 200 mV steps up to 1200 mVPPD. For example, to choose the amplitude
level of 800 mVPPD on the KR drivers, set the TXswing bits to be "011" on the KR global output configuration
register1 (pg1, Addr 10h<7:5>).
The output drivers are squelched to the output common-mode during an OOB/EBI event. The outputs can also be
configured to squelch during Alarm events (such as LOS and over temperature). The alarm squelch level can be
configured to be squelch-high, squelch-low, or squelch-to-output common mode. For example, to choose the
squelch level on the KR drivers, program the squelch-level bits on the KR global output configuration register2
(pg1, Addr 11h<1:0>). The specific events that cause such a squelch can be selected and is covered in the alarm
section.
Figure 4-6. Input Equivalent Circuit
50Ω
Vcm
Open/100Ω
DinpDinn
AVDD
50Ω
Functional Descriptions
2144x-DSH-001-N Mindspeed Technologies®26
Preliminary Information / Mindspeed Proprietary and Confidential
4.7 Input Channel Configuration
Each input channel of the M2144x includes an equalizer, designed to compensate for bandwidth limitations in
either the backplane or the PCB traces. The equalizer can operate in automatic (adaptive) or in manual
(programmable) mode. The input equalizer is the only difference between the XFI channels and KR channels.
The XFI inputs are intended to be used in a chip-to-chip connection and are made up of a fixed, passive linear
equalizer and a programmable/adaptive DFE. The XFI input can provide up to 11 dB of equalization at
5.16 GHz.The XFI inputs are channels XFI[0:3] on all variants of the device.
The KR inputs are intended to be used to receive a signal from a backplane trace and are made up of an adaptive/
programmable linear equalizer and a programmable/adaptive DFE. The KR inputs can provide up to 27 dB of
equalization at 5.16 GHz. The KR inputs are channels KR[0:3] and KR[0:3]r on the M21441 and channels KR[0:3]
on the M21440.
The input equalization can be programmed individually and LOS and OOB can be programmed either individually
or globally. The KR and XFI input channels are grouped separately for programming. For example, writing to a KR
input global register (pg1, Addr 01h) will program all KR channels on the device with that particular register setting.
This single global write removes the necessity of eight individual channel register writes on the M21441. Writing to
an individual KR input Channel - KR[0] configuration register1 (pg1, Addr 30h), will configure KR[0] with that
register setting, overwriting any previous global register1 setting for that particular channel. Boost and gain can
only be programmed individually where as e.g. LOS/OOB threshold levels can be configured either globally or
individually.
It is possible to power down an individual receive channel by setting bit7 of the EQ control register. For example,
the KR[0] RX channel can be powered down by writing a "1" to bit7 of the pg0, addr 47h register.
Figure 4-7. Output Equivalent Circuit
Doutp
50 Ω
AVddo
Doutn
50 Ω
AVddo AVddo
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4.8 Driver Configuration
Each output of the M2144x includes multiple drive levels and a three-tap de-emphasis circuit that is programmable
by the user. In addition to the adjustable output swing and de-emphasis, the M2144x also provides a slew rate
adjustment. The three-tap de-emphasis is designed for individual control of each tap, allowing for improved control
over signal integrity issues. There is approximately 12 dB of de-emphasis available (in steps of 2 dB) on the post-
cursor tap and a further 4 dB available (in steps of 1.3 dB) on the pre-cursor tap. A block diagram of the output
driver is shown in Figure 4-7.
In the same manner as the input channels described earlier, the output channels can be programmed individually
or on a global basis. The KR and XFI input channels are grouped separately for programming. For example, writing
to a KR output global register1 (pg1, Addr 10h) will program the output swing, and the amount of pre-cursor and
post-cursor de-emphasis on all KR output channels of the device. Whereas writing to an individual channel e.g.
Ch0 configuration register1 (pg1, Addr 74h), will configure Ch0 with that register setting, overwriting any previous
global register1 setting for that particular channel.
The driver swing can be programmed in 200 mV steps up to 1200 mVPPD. For example, to choose the amplitude
level of 800 mVPPD on the KR drivers, set the TXswing bits to be "011" on the KR global output configuration
register1 (pg1, Addr 10h<7:5>).
The output drivers are squelched to the output common-mode during an OOB/EBI event. The outputs can also be
configured to squelch during Alarm events (such as LOS and over temperature). The alarm squelch level can be
configured to be squelch-high, squelch-low, or squelch-to-output common mode. For example, to choose the
squelch level on the KR drivers, program the squelch-level bits on the KR global output configuration register2
(pg1, Addr 11h<1:0>). The specific events that cause such a squelch can be selected and is covered in the alarm
section.
4.9 Alarms
There are several status alarms to help insure that a system is running error-free. The M2144x supports Loss of
Signal (LOS) and over temperature alarms and the CDR alarms comprising Loss of Lock (LOL both PLL and
CDR), Loss of Reference (LOR) and PRBS error. The device provides both the real-time status and latch of each
alarm. Each alarm also has the ability to be masked to avoid any false alarms from unused channels.
4.9.1 Loss-Of-Signal (LOS)
The threshold setting at which LOS is detected can be set on a global basis for all KR channels (pg1, Addr
01h<2:0>) or for all XFI channels (pg1, Addr 06h<2:0>). It is also possible to set it on an individual channel basis by
writing to that input channel configuration register. This threshold is programmable between 80 and 250 mVPP
. It is
also possible to select between 2.3 µs or 6 µs for the LOS time constant (e.g. on the KR global channels, to set to
6 µs, set pg1, Addr 01h<4>=1). A LOS event at a given input channel is flagged as a bit setting in the registers,
LOS alarm (pg0, Addr E3-4h) and stat alarm (pg0, Addr E8-9h). The LOS alarm register values indicate the current
status of the LOS alarm (not latched) when read. The stat alarm register values are user read-only and will be
asserted when there is a change in status in the LOS alarm circuit. A wired'OR of all the LOS signals can be
monitored on the hardware ALARM pin. An added feature of this mode is the availability of masking registers. Bit
settings in mask alarm registers (pg0, Addr E6-7h) mask out unwanted channels from the logical OR function
permitting simple user configuration. The driver outputs can be squelched during a LOS event. It is possible to set
the squelch level to either high, low, or CM (default) by writing to e.g. KR input config reg6 (pg1 addr 05h<5:4>).
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4.9.2 Temperature
A temperature monitor with a range of +40 °C to 130 °C is integrated into the device. At temperatures below
+40 °C, the temperature monitor does not report accurate temperature readings should not be used. The monitor is
designed to measure in approximate 10 °C steps. The temperature to code mapping is detailed in the register table
(pg0, Addr EBh<3:0>). For example, code 0000b is mapped to temperatures below -47 °C and 1111b is mapped to
temperatures above 132 °C.
The temperature sensor configuration register allows the user to read the die temperature sensor value (an
uncalibrated, approximate temperature). To meet a better accuracy of ±10 °C per reading, it is recommended to
first perform a calibration (at ambient temperature). This requires placing the device in standby, so that minimum
power is consumed, reading the case temperature and on-die temperature sensor register. In this configuration,
the case and die junction temperature can be considered identical. Increase the power consumption (or
temperature if possible) until the on-die temperature sensor register transitions. The difference between the data
sheet value for this transition point and the actual case temperature plus, the Theta-JC by the power consumption,
is the correction delta that must be applied to all on-die temperature sensor register readings.
Per default at power up, the temperature sensor is disabled. It can be enabled by setting the temp monitor enable
bit (pg0, Addr EAh<5>). When enabled, the temperature measurement cycle is achieved by writing the strobe bit of
the temperature sensor configuration register (pg0, Addr EAh<3>). Afterwards, the correct temperature can be
read from the Junction Temp register (pg0, Addr EBh<3:0>). The temperature read is the die junction temperature
and correction factor depending on the customer application will be needed to transform the junction temperature
to the case temperature.
The device contains circuitry that detects the approximate temperature of the die and flags an alarm if it exceeds a
user-selected threshold, as defined in the temperature sensor configuration register (pg0, Addr EAh<2:0>). This
alarm can disable the output drivers to reduce power and lower the temperature or can just squelch the driver
outputs. To disable the drivers upon this alarm activation, the user can set the thermal flag bit in temperature
sensor configuration register (pg0, Addr EAh<4>). The alarm squelch level can be selected on e.g. the KR driver
outputs by writing to the global KR output config reg2 (pg1 addr 11h<1:0>). This squelch level is overriden by the
driver outputs disable thermal flag bit. This alarm activation can also, if desired, drive the package alarm pin low. To
prevent this from occurring, the user should mask the temperature alarm by setting the temp mask pin of Mask
alarm2 register (pg0, Addr E7h<4>). The status of the temperature alarm can be determined by reading the temp
alarm bit of the status alarm2 register (pg0, Addr E9h<4>).
It is not possible to clear this bit unless the temperature alarm activation has been deactivated by a reduction in the
on-die temperature.
4.9.3 CDR Alarms
The input channels in the device are allocated to banks. Each bank comprises three channels and a single PLL.
The CDR alarms comprise LOL for the PLL and individual Channel CDR, LOR for the PLL, and PRBS error
detection on each channel. These alarms are wiredOR together for each Bank and can activate the hardware
alarm pin unless masked out. It is possible to mask out a bank alarm by writing a "1" to the Mask CDR alarm
register (Bank[A,B,C,D], pg0, Addr E5h<3:0>). The status register for the CDR alarms provide the present PLL
LOL, LOR, Channel LOL, and PRBS error alarm status for that bank (Bank[A,B,C,D]: pg2 Addr 40h, pg2 Addr C0h,
pg4 Addr 40h, pg4 Addr C0h). Since the sampling of this register is quite sparse, there is also a delta register
associated with the status register (Bank[A,B,C,D]: pg2 Addr 41h, pg2 Addr C1h, pg4 Addr 41h, pg4 Addr C1h).
Either an assertion of any error condition or the de-assertion of the error condition will trigger the delta register to
read as a "1". Writing to a delta register resets all bits to "0". This alarm can also be configured to squelch the driver
outputs. The alarm squelch level can be selected on e.g. the KR driver outputs by writing to the global KR output
config reg2 (pg1 addr 11h<1:0>).
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4.9.3.1 Loss-Of-Lock (LOL)
The threshold setting at which LOL is detected can be set individually for each channel by writing to the CDR Bank
CRU control registerA (e.g. BankA Ch0, KR Input Ch0: pg0, Addr 44h<6:3>). This threshold is programmable
between the default 90 ppm and 8 k ppm. This channel LOL alarm can also be masked out of the Alarm generation
by writing a "1" to the Interrupt Mask register (e.g. BankA Ch0, KR Input Ch0: pg0, Addr 43h<0>). This alarm can
also be configured to squelch the driver outputs. The alarm squelch level can be selected on e.g. the KR driver
outputs by writing to the global KR output config reg2 (pg1 addr 11h<1:0>).
See the PRBS detector section for a discussion on handling PRBS errors.
4.10 Electrical Idle Pass-through
Some protocols define a third logic state at the common mode for transmission of an Electrical Idle (EI) level. When
the EI feature of the M21441 is enabled, the device will detect and pass EI signals with minimal distortion of the
signal.
On this device the user has the option of EI/OOB detection at either the EQ input or the EQ output for the KR
channels. The location of the OOB detector can be selected through the "front end oob" bit of KR input channel
configuration register3 (e.g. global KR input channel config reg3, pg1, Addr 02h<5>). For the XFI channels, the
detector is at the EQ input. The EI/OOB threshold can be adjusted between 65 to 175 mVPP by writing to the OOB
threshold value bits of the input configuration registers (e.g. global KR input channel config reg3, pg1, Addr
02h<2:0>).
4.11 Squelch
To avoid random chattering of the output due to noise when there is no signal present at the inputs, the M2144x
includes a squelch feature to automatically inhibit the output when there is a LOS alarm. There is an option to
inhibit to either logic H, or logic L, or output common-mode, on squelch. This squelch level can be selected globally
or individually through the squelch level bits on the output configuration register2 (e.g. the Global KR outputs, pg1,
Addr 11h <1:0>). In addition to the automatic squelch feature, a manual squelch can be forced through a register
setting (e.g. the Global KR outputs, pg1, Addr 11h <2>). When an input channel experiences a LOS event, any
output channel connected through the crosspoint to this input will be squelched to H, L or CM (depending on
chosen squelch level).
4.12 Crosspoint Switch Core
The M2144x crosspoint switch core is configured through the Active Switch Configuration (ASC), Intermediate
Switch Configuration #1 (ISC#1), and Intermediate Switch Configuration #2 (ISC#2) registers. All crosspoint switch
configuration registers are assigned to page0. The switch supports multicast and broadcast modes.
The crosspoint can be configured in several different modes. In the asynchronous update mode, the ASC register
can be written to and the crosspoint state will change with each write. In the synchronous mode, the desired switch
setting can be written in advance into one of the ISC registers and upon strobe (hardware or register based) the
ASC register contents are now over-written with those of the selected ISC register. The two ISC latches are
provided so the device can switch between two pre-configured settings.
When a "strobe" event occurs, the ASC registers will be updated with the contents from the appropriate ISC
register, and the entire switch core configuration is updated. The switch core can be updated through either a
software "strobe" or a hardware strobe by toggling the xSet hardware pin. To use the software strobe mode, it is
first necessary to set the strobe mode bit of the General Switch config register to software strobe (pg0, addr
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01h<4>=1) and then write the strobe pattern "101010" to the strobe register (pg0, addr 3Fh<5:0>). The icl_sel bit of
the strobe register (pg0, addr 3Fh<7>) determines which ISC register content is written to the ASC register upon
strobe. When the device is configured for hardware strobe mode, set the strobe mode bit of the General Switch
config register to hardware strobe (pg0, addr 01h<4>=0), the xSet hardware pin is used to update the ASC
contents. The device can be configured in two different hardware strobe modes by adjusting the xset bit of the
Strobe register (pg0, addr 3Fh<6>). With this bit set to "0", a low-to-high transition on the xSet hardware pin would
select ISC#1 as the active switch configuration while a high-to-low transition would select ISC#2. With this bit set to
"1", a high-to-low transition on the xSet pin will update the active switch configuration register with ISC#1 or ISC#2
as determined by the icl_sel bit of the strobe register (pg0, addr 3Fh<7>).
The switch core can be programmed in two modes, group switch mode and channel switch mode. This allows for
simplified multi-casting and broadcasting configuration. See Ta bl e 4 - 3 for a mapping of groups and single channels
to input/output differential pairs. In group switch mode, four high-speed channels are treated as one group and
switched together. Group KR includes KR Input/Output channels 0, 1, 2, and 3; Group XFI includes XFI Input/
Output channels 4, 5, 6, and 7; Group KRr includes KRr Input/Output channels 8, 9, 10, and 11. In Channel switch
mode, each high-speed channel is independent and switched individually. It is possible to switch between group or
Channel modes by writing to the mode bit of the General Switch config register (pg0, addr 01h<2>). The default
setting is group mode and the default switch configuration for M21441 is as follows:
Group XFI input channels ---> Group KR Output channels
Group KR input channels ---> Group XFI Output channels
Group XFI input channels ---> Group KRr Output channels
The default group switch configuration for M21440 is as follows:
Group XFI input channels ---> Group KR Output channels
Group KR input channels ---> Group XFI Output channels
Table 4-3. M2144x Channel Names and Associated Group Names
Device Group Name Input Channel Output Channel Interface Type
M21441 Group KR KR_IN0 KR_OUT0 Backplane
KR_IN1 KR_OUT1 Backplane
KR_IN2 KR_OUT2 Backplane
KR_IN3 KR_OUT3 Backplane
Group XFI XFI_IN0 XFI_OUT0 ASIC
XFI_IN1 XFI_OUT1 ASIC
XFI_IN2 XFI_OUT2 ASIC
XFI_IN3 XFI_OUT3 ASIC
Group KRr KR_IN0r KR_OUT0r Backplane Redundant
KR_IN1r KR_OUT1r Backplane Redundant
KR_IN2r KR_OUT2r Backplane Redundant
KR_IN3r KR_OUT3r Backplane Redundant
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4.13 PRBS Generation
Inside each receiver there is the ability to generate PRBS data instead of the re-generated data stream. This ability
can be used during system debug and bring-up. Since the PRBS generation is done at the receiver, the crosspoint
core must be programmed to route the PRBS generator to the desired output. The EI/OOB and LOS circuits should
be disabled when using the PRBS generator, as these circuits can cause an interrupt in PRBS generation when
they are enabled.
There are two basic modes of operation of the generator. In the first mode (CDR mode), the input locks normally to
data, but the output is replaced with a PRBS stream. Since the PRBS generator can also generate clock patterns,
this mode can be used to generate a data-synchronous clock if needed. The second mode (PLL mode) of
operation outputs the PRBS data at the PLL rate. This mode doesn't require the CDR, so it can power-down
unused circuitry and use less power. It also doesn't require a valid input signal in order to function. The polarity
inversion might be required to use this feature for some test equipment.
All of the PRBS Generator functions are controlled by the CDR Bank PRBS Generator Control register PLL[0],
Channels KR[0], XFI[0] and KRr[0]: pg2 Addr 19h, 29h, 39h; PLL[1], Channels KR[1], XFI[1] and KRr[1]: pg2 Addr
99h, A9h, B9h; PLL[2] and PLL[3] on pg4). Bit 5 controls the mode of operation (0 = CDR Active, 1=CDR powered
down). Bit 4 enables/disables PRBS generation and bits [3:0] control the output pattern. Bits [2:0] define the
pattern, and bit 3 either inverts the pattern or keeps it as is. The pattern selection is shown in Ta b l e 4- 4 .
M21440 Group KR KR_IN0 KR_OUT0 Backplane
KR_IN1 KR_OUT1 Backplane
KR_IN2 KR_OUT2 Backplane
KR_IN3 KR_OUT3 Backplane
Group XFI XFI_IN0 XFI_OUT0 ASIC
XFI_IN1 XFI_OUT1 ASIC
XFI_IN2 XFI_OUT2 ASIC
XFI_IN3 XFI_OUT3 ASIC
Table 4-4. PRBS Generator Pattern Selection
Bits [2:0] Pattern Selected
000 Fbaud/2 Clock
001 Fbaud/4 Clock
010 Fbaud/8 Clock
011 Fbaud/16 Clock
100 PRBS7
101 PRBS15
110 PRBS23
111 PRBS31
Table 4-3. M2144x Channel Names and Associated Group Names
Device Group Name Input Channel Output Channel Interface Type
Functional Descriptions
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4.14 PRBS Detector
In addition to generating PRBS patterns, the device can detect PRBS patterns at its inputs. The PRBS detector is
not recommended for use with data rates higher than 6.25 Gbps as the detector may falsely indicate errors on an
error-free data stream. There are two basic modes of operation. The first mode (unlatched) only detects the
presence/absence of PRBS errors, and can be used for gross functionality. The second mode (latched) allows an
actual error rate to be measured. The polarity inversion might be required to use this feature for some test
equipment.
Both modes have their major controls in the PRBS Detector control register, (e.g. The PLL[0], Channel KR[0]
PRBS detector control register is located at pg2, Addr 1Ah). Bits [4:0] enable the detector, and select the pattern.
For unlatched mode, once these bits are set, the PRBS status can be read out in the status register, and interrupts
can be generated on a PRBS error.
For latched mode, more setup must be done. First, bits [7:5] of the PRBS Detection control register need to be
programmed with the length of the error counter. The PRBS error counter can be programmed in length from 8 bits
to 32 bits, meaning error rates as low as 2e-10 can be detected, with full accounting of all errors. In some cases,
even lower rates may be desired, and the counter length can be extended up to 52 bits (minimum BER of 2e-16)
via bits [6:4] in the PRBS Detection status register (e.g. the PLL[0], Channel KR [0] PRBS detector status register
is located at pg2, Addr 1Bh). In these extended counter length modes, the error counter has a maximum resolution
of 231, so these modes are only useful for detecting low bit error rates. Finally, to enable latched mode, bit 7 of the
PRBS Detection B register must be set.
Latched mode works by looking for an error free region of the input data. This error free region is then latched into
a LFSR (Linear Feedback Shift Register). After latching, the LFSR output is updated and compared to the input
data, and any errors are accumulated in an error counter. After a certain amount of time (determined by the counter
length, discussed above), the error accumulation is stopped, and a flag is set.
To begin the latching process, a 1 is written into bit 0 of the PRBS Detection status register. If the latch is
successful, bit 1 of the PRBS Detection status register will read back a 0. If the latch was unsuccessful (there were
PRBS errors when the latch LFSR was latched), bit 1 will read back as a 1 - this should only happen with very high
input BER. Bit 0 will read back 0 when the PRBS Detector is still accumulating PRBS errors. When the PRBS
Detector is done accumulating errors, bit 0 will read as a 1.
After the error accumulation is complete, the error count can be read back from the CDR Bank PRBS Error count 0,
1, 2, and 3 registers (e.g. The PLL[0], Channel KR[0] Ch0 PRBS error count 0 register is located at pg2, Addr 1Ch).
The "0" register contains the LSB's of the count, and the "3" register contains the MSB's. In extended error count
mode, the MSB can only go from 0 to a 1, so error values above 8000_0000h cannot be deemed reliable.
4.15 Reference Clock
The M2144x requires an external reference clock in order for the clock data recovery unit to properly lock to the
incoming data. The M2144x has two different single ended reference clocks that provide flexibility to run each CDR
bank at a different data rate. The reference clock signal should be AC-coupled; for input levels greater than 1.2 V, a
capacitor divider circuit should be used. Terminate unused single ended signal when connecting differential
reference clocks in a system. The jitter performance of the reference clock will be better with a square signal
compared to a sinusoidal signal.
Refer to Ta b l e 4 - 7 for proper reference clock rate selection.
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4.16 Clock and Data Recovery Operation
The M2144x includes an integrated Clock Data Recovery (CDR). The M2144x is organized as four banks of three
channels. Each bank contains an XFI input and two KR inputs (refer to Figure 4-8). Since the three channels within
each bank share a PLL (described later), each bank must run at the same data rate (or at a power-of-two
relationship with each other). The organization of the CDR Banks is outlined in Ta b l e 4 - 5 . The device provides two
reference clock inputs. The different protocols can choose between the two reference clocks. It is required that only
one reference clock be enabled and driven into the device at a time.
Note that the M2144x devices do not include an option to bypass the CDR.
Each input channel of the M2144x contains a clock and data recovery (CDR) unit. The easiest and recommended
method to set up the CDR is to use one of the presets. There are two types of presets - pin presets and register
presets. The preset register allows bank-by-bank control of the preset value, while the pin presets act on all
channels at once. The page0 PLL[0:3] Preset registers are located at addresses 40h, 50h, 60h, and 70h
respectively. There are two external package pins that determine the HW presets (CDR_HW[1:0]).
To have a bank use the pin preset value, the preset register must be programmed to a value of 00h. The
CDR_HW1 and CDR_HW0 pins are then used to determine the configuration of the bank. Programming any value
other than 00h into the preset register will override the pin preset value. When reading back from the preset
register, it will always report the actual preset being used (regardless of whether it is set via the pin preset or the
register preset). As a result, at reset, if the CDR_HW0 and CDR_HW1 pins are not both low, the preset register will
not read back its default value of 00h.
Ta bl e 4 - 6 illustrates how the CDR_HW1 and CDR_HW0 pins map to actual presets (along with what the prescale
register will read back when the pin preset is active).
Table 4-5. CDR/PLL Bank Details
PLL[0] PLL[1] PLL[2] PLL[3]
Channel KR[0] Channel KR[1] Channel KR[2] Channel KR[3]
Channel XFI[0] Channel XFI[1] Channel XFI[2] Channel XFI[3]
Channel KR[0]r
M21441
Channel KR[1]r
M21441
Channel KR[2]r
M21441
Channel KR[3]r
M21441
Table 4-6. Hardware Pin Preset Configurations
CDR_HW1
Pin Setting
CDR_HW0
Pin Setting Protocol Data Rates (Gbps) Refclk
Used
Refclk
Frequency
(MHz)
Register
Readback
L L Ethernet 1.25 / 3.125 /
10.3125
2 156.25 00
F L Fibre Channel 1.0625 / 2.125 /
4.25 / 8.5
1 125 08
F H 10G ~10 2 Fbaud/50 34
L F InfiniBand 2.5 / 5 / 10 1 125 18
H F SONET 1.24416 / 2.48832 /
4.97664 / 9.95328
2 155.52 28
F F SONET 1.24416 / 2.48832 /
4.97664 / 9.95328
2 77.76 29
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To control the preset on a bank-by-bank basis, use the Preset register. This register allows for many more possible
data rate and reference clock combinations than the pin presets. The mapping for this register is shown in
Ta bl e 4 - 7 .
Table 4-7. Preset Register Protocol/Reference Selection (1 of 2)
Preset
Register
Value
Protocol Data Rates
(Gbps)
Refclk
Used
Refclk
Frequency
(MHz)
00 Ethernet
(XFI Master)
1.25 / 3.125 /
10.3125
2 156.25
01 10G Base KR 10.3125 2 156.25
02 Gigabit Ethernet 1.25 1 125
03 2 156.25
04 XAUI 3.125 1 125
05 2 156.25
06 2 62.5
08 Fibre Channel 1.0625 / 2.125 /
4.25 / 8.5
1125
09 2 106.25
0A 2 62.5
0B 2212.5
18 InfiniBand 1.25 / 2.5 /
5 / 10
1125
19 2100
1A 2 62.5
28 SONET 1.24416 / 2.48832 /
4.97664 / 9.95328
2 155.52
29 2 77.76
2A 2 311.04
30 Various 10G ~10G 2 Fbaud/64
31 2 Fbaud/128
32 2 Fbaud/32
33 2 Fbaud/80
34 2 Fbaud/100
35 2 Fbaud/120
36 2 Fbaud/160
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The Preset register is a shortcut to set up all the various CDR-related registers. The presets are designed to allow
the M2144x to have a 125 MHz reference clock on REFCLK1 and a secondary reference on REFCLK2. All of the
values that the preset register sets are visible (from the register values that the preset register controls), and can be
overwritten.
For robust CDR operation, the values in registers 47h, 57h, 67h, 77h, 4Bh, 5Bh, 6Bh, 7Bh, 4Fh, 5Fh, 6Fh, and 7Fh
should be changed from their default value of 00h to a value of 60h.
Mindspeed recommends that the preset registers are used to configure the CDRs for various data rates. If the
device is used for a non-standard data rate, then the CDR can be manually configured using the PLL[n]: PLL Divide
Ratio register at page 00h, address HEX[65 + n*16] to set the PLL multiplier ratio and also the CDR[m]:ARD
Control[n] register at page 00h, address HEX[70 + 4n + 10 m] to set the prescale divider ratio. In addition, the Low
VCO or High VCO setting is configured using the PLL[n]:PLL Control register at page 00h, address HEX[66 +
n*16]. Ta b l e 4 - 9 below lists the data rate ranges that can be manually configured in the device:
4.16.1 Automatic Rate Detection (ARD)
The device has Automatic Rate Detection (ARD) circuits that work to automatically select the power-of-2 divisors
for each channel. In order for this circuit to function, it is necessary that the data stream contain 0101 or 1010 bit
sequences.
The ARD behavior can be modified from the values defined by the Bank Preset register by changing the ARD
Control register (e.g. PLL[0], channel KR[0] ARD control, pg0, Addr 46h). Writing to bits [7:6] will set the divide-by-
1/divide-by-2/divide-by-4/divide-by-8 value of the loop. Bit 5 allows ARD to be enabled or disabled. Bits [3:0] show
Table 4-8. Preset Register Protocol/Reference Selection (2 of 2)
Preset
Register
Value
Protocol Data Rates
(Gbps)
Refclk
Used
Refclk
Frequency
(MHz)
50 Ethernet
(Redundant KR
Master)
1.25 / 3.125 /
10.3125
2156.25
60 Ethernet
(Primary KR
Master)
1.25 / 3.125 /
10.3125
2156.25
Table 4-9. Manual Configuration Settings
Data Rate Range Prescale Setting VCO
0.78125-1.0625 Gbps 8 Low
1.2375-1.375 Gbps 8 High
1.5625-2.125 Gbps 4 Low
2.475-2.75 Gbps 4 High
3.125-4.25 Gbps 2 Low
4.95-5.5 Gbps 2 High
6.25-8.5 Gbps 1 Low
9.9-10.3125 Gbps 1 High
Functional Descriptions
2144x-DSH-001-N Mindspeed Technologies®36
Preliminary Information / Mindspeed Proprietary and Confidential
the valid divide values for the ARD circuitry. When bit 4 is a 1, the register value of bits [3:0] is used. When bit 4 is
a 0, the default value (as defined by the Preset register) is used, and will show up when the register is read.
Normally, the ARD just determines power-of-two divisors. When the "Ethernet" setting is configured, the ARD
engine will automatically select between 10G-base KR (10.3125 Gbps), XAUI (3.125 Gbps), and Gigabit Ethernet
(1.25 Gbps). When changing rates, the PLL frequency will also be changed. In this special case, one channel of
the trio needs to be declared the master, and it will be used to set the PLL frequency. The Ethernet presets allow
any of the three channels per bank to be the master.
4.17 In Circuit Eye Monitor
The M2144x includes an in-circuit eye monitor that provides the user with a detailed 2-D visual image of the signal
on any of its input channels. The monitor is located at the input to the DFE and can be read out of the device for
more detailed post processing. All of the eye monitor control registers can be found on page2 and page4 of the
register map. The eye monitor is not recommended for use with data rates higher than 6.5 Gbps, as the results
displayed using the eye monitor show higher jitter than what is actually present on the signal. For data rates below
5.5 Gbps, the data from the eye monitor should be post-processed to yield valid results. Also, when the eye monitor
is first enabled for a channel, a burst of bit errors can be present on that channel for up to 500 ms.
Figure 4-8. PLL and CDR Distribution
Crosspoint
KR_IN[3]
KR_IN[3]r
XFI_IN[3]
KR_IN[2]
KR_IN[2]r
XFI_IN[2]
PLL [0]
KR_IN[0]
KR_IN[0]r
XFI_IN[0]
KR_IN[1]
KR_IN[1]r
XFI_IN[1]
EQ
Channel
KR_IN[0]
Digital
Processing
ARD
FF
Recover ed
data
Recover ed
clock
R ate _adjus t
Phase
adjust
Mixer
KR_IN[0]
EQ
Channel
KR_IN[0]r
Digital
Processing
ARD
FF
Recover ed
data
Recover ed
clock
R ate _adjus t
Phase
adjust
Mixer
KR_IN[0]r
EQ
Channel
XFI_IN[0]
Digital
Processing
ARD
FF
Recover ed
data
Recover ed
clock
R ate _adjus t
Phase
adjust
Mixer
XFI_IN[0]
PLL
Digital
Interface
Ref clk
select
Refclk1
Refclk2
Divider select
PLL [0]
PLL [1] PLL [2]
PLL [3]
Functional Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
At rates below 6.5 Gbps, the eye monitor will report the sum of the input jitter and the CDR jitter. This results in a
reporting of 150 mUI of increased jitter that is not present on the signal.
4.18 Control Options
There are four digital interfaces supported on the M2144x: 2-wire, 4-wire, MDIO, and JTAG. Ta b le 4 - 1 0 shows the
configuration pins (config[2:0]) mapping to determine the active interface mode. The multifunction pins (MF[3:0])
functionality is also listed for each interface.
4.19 Two-wire Serial Programming Interface
The two-wire serial interface uses multi-function pins 1 and 2 as SCL and SDA respectively and multi-function pins
2 and 3 are assigned to addr 0 and 1 respectively. Addr 0 and 1 are used to select the two-wire slave address as
shown in Tab l e 4 - 11 .
Table 4-10. Digital Interface Configuration
External Pins 2-wire 4-wire MDIO JTAG
Config[2:0] 000 (MIC download)
100 (no download)
X01 00F (MIC download)
10F (no download)
111
MF0 SCL (MSCL) SCLK MDC TCLK
MF1 SDA (MSDA) SO MDIO TMS
MF2 addr0 SI addr0 —
MF3 addr1 xCS addr1 —
TDI — — — TDI
TDO — — — TDO
reset_n reset_n reset_n reset_n reset_n
Table 4-11. Addr 0 and 1 Mapping
Addr1 Addr0 2-wire Slave
ID Address Mode Slave
Device #
E E P R O M A d d r e s s
(A2=A1=A0=VSS)
MMD
PHYADR
L L 010 0000b MIC mode 0 A0 (1010 000) 00000b
L H 010 0001b SIC mode 1 00001b
H L 010 0010b SIC mode 2 00010b
H H 010 0011b SIC mode 3 00011b
F L 010 0100 b SIC mode 4 00100b
F H 010 0101b SIC mode 5 00101b
L F 010 0110b SIC mode 6 00110b
H F 010 0111b SIC mode 7 00111b
F F 010 1000b SIC mode 8 01000b
Functional Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
The M21440/M21441 two-wire interface is designed to drive 500 pF at 100 and 400 kHz, and 100 pF at 3.4 MHz.
During a write operation the data is latched into the M21440/M21441 registers on the rising edge of SCL during the
acknowledge phase (ACK) of communication. The timing waveforms are shown in Figure 4-10 and the timing
specifications in Ta b l e 4 - 1 2 and Ta b l e 4 - 1 3 for the standard/fast and high-speed modes respectively. Starting in the
standard/fast mode it is then possible to switch to the high-speed mode by issuing the 8-bit reserved master-code
(00001XXX).
Figure 4-9. 2-wire Bit Operations
Figure 4-10. Two-wire Timing Waveforms
Table 4-12. Two-wire Slave Timing Specifications (Standard Mode/Fast Mode)
Symbol Parameter Min Typ Max Unit
fSCL Clock Frequency, SCL — — 400 kHz
tLOW Clock Pulse Width Low 1.3 — — µs
tHIGH Clock Pulse Width High 0.6 — — µs
START R/xW ACK ACK ACK ACK ACK STOP
da6da5da4da3da2da1da0 0 XXXXXXXa8 a7a6a5a4a3a2a1a0 X XXXXXXd8 d7d6d5d4d3d2d1d0
START R/xW ACK ACK ACK START R/xW ACK ACK ACK STOP
da6da5da4da3da2da1da0 0 A XXXXXXXa8 A a7a6a5a4a3a2a1a0 A da6da5da4da3da2da1da0 1 A XXXXXXX d8 A d7d6d5d4d3d2d1d0xA
A
xA
R/xW '0"forWrite,'1'forRead
Write
Operation
FromControllertoDevice
FromDevicetoController
Acknowledge(SDALow)
NotAcknowledge(SDAHigh)
Read
Operation
7ͲbitDeviceAddress SecondWordData
FirstWordAddress SecondWordAddress7ͲbitDeviceAddress FirstWordData SecondWordData
FirstWordAddress SecondWordAddress 7ͲbitDeviceAddress FirstWordData
Functional Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
4.20 MDIO Programming Interface
When configured in MDIO Manageable Devices interface (MMD) controlled by a Station Management Entity (STA)
MF 0 and 1 are mapped to MDC (max input frequency of 2.5 MHz) and MDIO respectively. MF 2 and 3 are used to
decode the physical ID addresses for the MMD (see Ta bl e 4 - 1 1 ). This device supports expansion clause 45 of
IEEE 802.3ae but does not support clause 22. The frame composition is shown in Ta bl e 4 - 1 4 . After POR, a
minimum of three MDIO clock cycles is required to get the device "out of reset" before any Read/WRITE operation.
The MDIO timing waveforms are shown in Figure 4-11 and the timing specifications are listed in Ta bl e 4 - 1 5 . For
further details, please refer to the IEEE Std 802-3-2005 (section 45.3).
tAA Clock Low to Data Out Valid 0.05 — 0.9 µs
tHDSTA Start Hold Time 200 — — ns
tSUSTA Start Set-up Time 200 — — ns
tHDDAT Data In Hold Time 0 — — ns
tSUDAT Data In Set-up Time 100 — — ns
tSUSTO Stop Set-up Time 200 — — ns
tDH Data Out Hold Time 50 — — ns
Tsp Pulse width spike noise suppressed out by input filter 0 50 ns
Table 4-13. Two-wire Slave Timing Specification (High-speed Mode)
Symbol Parameter Min Typ Max Unit
fSCL Clock Frequency, SCL — — 3.4* MHz
tLOW Clock Pulse Width Low 160 — — ns
tHIGH Clock Pulse Width High 60 — — ns
tAA Clock Low to Data Out Valid 0 — 70 ns
tHDSTA Start (repeated) Hold Time 160 — — ns
tSUSTA Start (repeated) Set-up Time 160 — — ns
tHDDAT Data In Hold Time 0 — — ns
tSUDAT Data In Set-up Time 10 — — ns
tSUSTO Stop Set-up Time 160 — — ns
tDH Data Out Hold Time 5 — — ns
Table 4-12. Two-wire Slave Timing Specifications (Standard Mode/Fast Mode)
Symbol Parameter Min Typ Max Unit
Functional Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
Table 4-14. MDIO — Frame Composition
PRE(32) ST(2) OP(2) PRTAD(5) DEVAD(5) TA(2) ADDR/DATA (16 bits) Idle
FFFFFFFFh 0 0 *0 0 0 0 1
Address 0 0 1 0 Driven by STA z
Write 0 1 1 0 Driven by STA z
Read 1 1 z 0 Driven by MMD (M21441) z
Read + ( Address +1) 1 0 z 0 Driven by MMD (M21441) z
NOTES:
1. PREamble: A sequence of 32 one “1” bits on MDIO with 32 corresponding MDC clock cycles is required before MMD responds to any
transaction.
2. Start of Frame: clause 22: 01b and clause 45: 00b (not supporting clause 22).
3. OPcode: Two bits opcode controlled by STA.
4. PRTAD (port of address): Five bits (see Table 4-11: MMD Port Address) supporting maximum of nine (9) M21441 port addresses (decoding
from addr1 and addr0) on the same MDIO bus.
5. DEVAD(Device address): Five bits: * Default value is 00001b (could be changed by optional downloading from external EEPROM or by a STA to
register 03h/page0).
6. TA(turn around): “10” in Write cycle. M21441 drives TA bits in Read cycle with “z0”. This is followed by the 16 bits of data
“00000000dddddddd”). 8MSBs used for Read, while 8LSBs are used for write data/addr.
7. Idle: M21441 disable output MDIO pad. STA should also disable its driver and let MDIO pulling high by external pull-up resistor.
Figure 4-11. MDIO Timing
sample
Tdelay
TholdTsetup
Tdelay
TperiodTperiod
MDC (input clock)
MDIO (Input)
MDC (input clock)
MDIO (out)
Functional Descriptions
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4.21 4-Wire Programming Interface
The four-wire 4-wire interface is selected when config pins[2:0] = x01. When configured in 4-wire mode, MF0 is
assigned as the serial clock input SCLK, MF3 as the slave select input xCS, MF1 as the slave output SO, and MF2
as the slave input SI.
Following an H-to-L transition on XCS, the 4-wire master will transfer a two-bit instruction (indicating the type of
read or write operation, see Ta bl e 4 - 1 6 below), followed by one byte address (and one byte data for Write mode).
SI is sampled on the falling edge of SCLK and SO is shifted out on the rising edge of SCLK.
Table 4-15. MDIO Timing Specifications
Symbol Description Minimum Maximum Unit
Tsetup MDIO Set up time to MDC XX 10 ns
Thold MDIO HOLD time to MDC XX 10 ns
Tdelay MDIO delay from MDC XX in reading 0 300 ns
TPERIOD Period of MDC 400 ns
Tpwl MDC minimum Low 160 ns
Tpwh MDC minimum High 160 ns
Figure 4-12. 4-wire Serial Digital Interface
D[8:0]A[8:0]R/W1
LSB
9
MSB
17
LSB
0
MSB
81819
Start Bit Read / Write
Address Data
D[8:0]A[8:0]R/W1
LSB
9
MSB
17
LSB
0
MSB
81819
Start Bit Read / Write
Address Data
Functional Descriptions
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The timing diagrams for the four different 4-wire operations are shown in Figure 4-13 through Figure 4-16. The
timing specifications are outlined in Ta b le 4 - 1 7 .
Table 4-16. 4-Wire Operations
Instruction Instruction Format xCS at End of Current R/W Operation Operation
R-Read 11 H Random Read
R-Write 10 H Random Write
S-Read 11 L Sequential Read
S-Write 10 L Sequential Write
Non-Operate 0X Non-operate (SO remain tristate), reset to
new operation after xCS transitioning High
to Low
NOTES:
1. In a random R/W operation, if the xCS low time is extended by n*8 4-wire clock cycles, a sequential R/W then proceeds.
2. A minimum of one 4-wire clock pulse is required on xCS in order to deselect between Read-Write, Read-Read, Write-Read, and Write-Write
operations.
3. A minimum of one 4-wire clock pulse is required after the de-assertion of xCS, for that de-assertion to be recognized.
4. The sequential R/W continues to roll over the 256 byte address if the XCS remains low. In a sequential write, the page select at address FFh
could be overwritten to extend to the next page address. It is up to the user to decide when to deselect xCS.
5. After a POR, a minimum of three 4-wire clock cycles is required to take the device out of reset before any Read/Write operation can be
performed. A dummy Read could be used for this purpose.
Figure 4-13. 4-Wire Sequential WRITE
Figure 4-14. 4-Wire Random WRITE
t
DH
t
DS
t
CS
1 2 31011121314 21222328 2820 30
01address (A8 ...A 0) 2nd data ( D8... D0) 3rd data1s t D ata ( D 8 ... D 0)
SCLK
xCS
SI
SO
tDH
tCH
tCS
tCS
1 2 3 1011121314 1718 19202114 22
01 address (A8 .. . A0 ) Data (D8 ... D0)
SCLK
xCS
SI
SO
Functional Descriptions
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4.22 Memory Interface Control (MIC)
In Memory Interface Control (MIC) mode the M2144x can be used to both self-configure and to configure other
M2144x devices on the bus.
Out of reset or at power-on the device will act as a two-wire master and download a configuration from an
EEPROM or other storage device at address 1010000b. The M2144x if configured will then sequentially configure
any other M2144x device on the bus before switching to Slave Interface Control (SIC) mode. It's important to note
that only one M2144x device should be configured in MIC mode. The host master in the system should be held in a
way that will not interfere with the M2144x during MIC operation. This can be ensured by allowing one second for
Figure 4-15. 4-Wire Sequential READ
Figure 4-16. 4-Wire Random READ
Table 4-17. 4-Wire Timing Specifications
Symbol Description Min Typ Max Units
TDS Data set-up time 3 ns
TDH Data hold time 3 ns
TCS Enable xCS set-up time 3 ns
TCH xCS hold time 3 ns
TFREQ Write 4-wire clock frequency 50-100 MHz
TDCD SCLK pulse width 45 55 %
TRDD Read data output delay following rising edge of SCLK 1 16 ns
t
DS
t
CS
1 2 3 11 12 13 14 21 20 21 26
1s t 9 - b its MISO
30
9-bit address
20
2 nd 9-bit s MI SO
31
3rd 9 - bit s MI SO (D8,D7 ....D0)
SCLK
xCS
SI
SO
t
DD
t
DD
t
DS
t
CS
1 2 3 10 11 12 13 14 16 17 18 19 20
9-bi t addr ess
15
D1
20
D8 D7 D6 D5 D3 D2D4 D0
SCLK
xCS
SI
SO
Functional Descriptions
2144x-DSH-001-N Mindspeed Technologies®44
Preliminary Information / Mindspeed Proprietary and Confidential
each M2144x on the bus. The memory storage device needs to be fully powered on and operational prior to the
M2144x starting MIC.
In Slave Interface Control (SIC) mode the M2144x is configured as a slave device on the bus and is accessed via a
host master.
For 2-wire/MDIO mode (Config[2:0] = 000 or 00F), one M2144x device in an array can be configured as a quasi
master with addr1=addr0 = LL. All others devices (up to an additional 8 more devices) are configured as Slave
devices (add1 & addr0 ≠ LL.)
For 4-wire mode with option to download (Config[2:0] = 001) a configuration from an EEPROM or other storage
device, only one M2144x device is configured as quasi master device and the external EEPROM is downloaded to
this device only. There is no subsequent downloading from the master to other slave devices.
Upon POR without external host intervention, the quasi master initials a sequential read command at max 400 kHz
SCL clock from an EEPROM or other storage device at address 1010000b. The 244 bytes (at EEPROM addresses
from 00h to F3h) data are loaded sequentially to page0 and page1 [00h-7Fh to page0 and 30h-B3h to page 1].
See the EEPROM mapping in Table 4-18. The M2144x device also calculates the checksum of the 244 bytes data
(00h-F3h), and the result of eight LSBs of the computed checksum is compared with a fix value of "2Eh." If the
checksum value does not equal the fixed value of 2Eh, it tries again up to 512 times and is finally timed out if the
checksum is still does not equal 2Eh. The result of eight (LSB) checksum is written to the read-only register
checksum_cal register (pg0, Addr FEh). When the checksum passes in the quasi master device, the self-
configuration process starts to copy the setup registers from the master to the slave devices. If the checksum fails,
the self configuration process starts and loads to the master but not the slaves.
The quasi-master determines the number of slave M2144x devices on the array by reading the micdev register
(pg0, Addr 02h[7:0]) and copies the registers to each of the Slave M2144x devices consecutively through the two-
wire interface at 400 kHz. After completing the configuration process for all the 10G KR devices on the array, the
quasi master becomes a slave device (its slave device address is 0100000b (00000b is PRTADR in MDIO mode).
All of the M2144x devices in the array now behave as SIC slave devices (an optional external host can read all
internal registers for monitoring, debugging and reconfiguring the parts if desired).
After POR, the quasi master initials a "two wired software reset" and start condition following with the A0 (1010
0000) device address (in write cycle to start a random read at loc 00h and proceed with sequential read starting at
loc 00h and end at F3h). If there is NO EEPROM in the module, or by some reason, the AT24C02C does not
respond or "acknowledge", after approximately 128 tries, the quasi master is timed out. The self-downloading
process from the master device to other slave devices is then started. After completing the self downloading
process, SCL_M SDA_M are left floating by the device and are pulled high by a weak external pull-up.
During the self-configuring process, if a slave device in the array does not respond to the quasi master's start
condition within 128 tries, the quasi master will then move on to start the downloading process to the next slave
M2144x device.
A typical SCL clock frequency derived from the M2144x quasi-master device is approximately 312 kHz.
Table 4-18. Mapping from EPROM to M2144x
AT24C02C M21441x
Address (hex) Address (hex) Page
00 - 07 00 - 07 Page 0
08 - 13 10 – 1B Page 0
14 – 1F 20 -2B Page0
Functional Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
4.23 JTAG Interface
JTAG mode is configured with the config pins[2:0]="111". In JTAG mod, the MF0 pin is mapped to "TCLK" and the
MF1 pin is mapped to "TMS". The twelve RX channel input pair pins (KR_IN[3:0]p/n, XFI_IN[3:0]p/n, and
KRr_IN[3:0]p/n) can be scanned through the TAP controller.
20 – 2F 30 -3F Page 0
30 – 6F 40-7F Page0
70 - F3 30-B3 Page 1
Table 4-18. Mapping from EPROM to M2144x
AT24C02C M21441x
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Preliminary Information / Mindspeed Proprietary and Confidential
5.0 Control Register Descriptions
Table 5-1. Register Summary
Page Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
Page 00h
00h 00h Checksum seed checksum 55'h R/W
00h 01h Gen SW Config RSVD strobe RSVD mode RSVD standby 04'h R/W
00h 02h MIC Reg slave devices 00'h R/W
00h 03h MDIO device
addr
RSVD MDIO device addr 01'h R/W
00h 10h-1Bh :
01h
Active SW state
Output[n]
RSVD o/p Ch/Port[n] map See Note R/W
00h 20h-2Bh :
01h
Intermediate
SW state#1
Output[n]
RSVD o/p Ch/Port[n] map See Note R/W
00h 30h-3Bh :
01h
Intermediate
SW state#2
Output[n]
RSVD o/p Ch/Port[n] map See Note R/W
00h 3Fh Strobe icl_sel xSET_mode strobe 00'h R/W
00h 40h-70h :
10h
PLL[n]: Preset Preset 00'h R/W
00h 41h-71h :
10h
PLL[n]: PLL
Divide Ratio
div2 enable div ratio 00'h R/W
00h 42h-72h :
10h
PLL[n]: PLL
Control
Bank pd VCO over-ride VCO select lbw over-
ride
PLL LBW Refclk
over-ride
Refclk
Select
00'h R/W
00h 43h-73h :
10h
PLL[n]: Inter-
rupt Mask
PLL LOL Mask LOR Mask PRBS KR
Mask
PRBS KRr
Mask
PRBS XFI
Mask
LOL KR
Mask
LOL KRr
Mask
LOL XFI
Mask
00'h R/W
00h 44h-4Ch :
04h*
CDR[m]: CRU
Control A[n]
leak override leak gain LOL Limits 00'h R/W
00h 45h-4Dh :
04h*
CDR[m]: CRU
Control B[n]
peaking lbw 00'h R/W
00h 46h-4Eh :
04h*
CDR[m]: ARD
Control [n]
Divide Value ARD Disable Range over-
ride
Div8_Valid Div4_Valid Div2_valid Div1_valid 00'h R/W
00h 47h-4Fh :
04h*
CDR[m]: EQ
Control [n]
CH pd scaling_override peak_scaling soft reset RSVD 00'h R/W
00h E0h MasterRst reset 00'h R/W
00h E1h ChipCode chipcode E1'h R
00h E2h Reserved RSVD (set to default) 06'h R
00h E3h LOS alarm1 XFI3 LOS XFI2 LOS XFI1 LOS XFI0 LOS KR3 LOS KR2 LOS KR1 LOS KR0 LOS 00'h R/W
00h E4h LOS alarm2 RSVD Temp alarm KR3r LOS KR2r LOS KR1r LOS KR0r LOS 00'h R/W
00h E5h Mask PLL alarm RSVD PLL0 mask PLL1 mask PLL2 mask PLL3 mask 00'h R/W
00h E6h Mask alarm1 XFI3 LOS
mask
XFI2 LOS mask XFI1 LOS
mask
XFI0 LOS
mask
KR3 LOS mask KR2 LOS
mask
KR1 LOS
mask
KR0 LOS
mask
00'h R/W
Control Register Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
00h E7h Mask alarm2 RSVD Temp mask KR3r LOS
mask
KR2r LOS
mask
KR1r LOS
mask
KR0r LOS
mask
00'h R/W
00h E8h Stat alarm1 XFI3 LOS stat XFI2 LOS stat XFI1 LOS stat XFI0 LOS
stat
KR3 LOS stat KR2 LOS
stat
KR1 LOS
stat
KR0 LOS
stat
00'h R
00h E9h Stat alarm2 RSVD Temp stat KR3r LOS stat KR2r LOS
stat
KR1r LOS
stat
KR0r LOS
stat
00'h R
00h EAh Temp Sensor
config
RSVD temp mon en thermal flag stobe sens Threshold adjust 27'h R/W
00h EBh Junction Temp RSVD JuncT meas 0B'h R
00h EDh Reserved RSVD (set to default) 00'h R
00h FEh Checksum_cal checksum_cal 00'h R
00h FFh Page Address RSVD page addr 00'h R/W
Page 01h
01h 00h Reserved RSVD (set to default) 3F'h R/W
01h 01h Global KR Input
channel con-
fig_reg2
RSVD LOS time
ctrl
RSVD LOS threshold val 00'h R/W
01h 02h Global KR Input
channel con-
fig_reg3
RSVD Front End
OOB
Enable OOB OOB deglitch
en
OOB threshold val 03'h R/W
01h 03h Reserved RSVD (set to default) 00'h R/W
01h 04h Global KR Input
channel con-
fig_reg5
RSVD Polarity
invert
RSVD 00'h R/W
01h 05h Global KR Input
channel con-
fig_reg6
RSVD Output squelch level for
LOS
RSVD 00'h R/W
01h 06h Global XFI Input
channel con-
fig_reg1
RSVD LOS time
ctrl
RSVD LOS threshold val 00'h R/W
01h 07h Global XFI Input
channel con-
fig_reg2
RSVD Enable OOB OOB deglitch
en
OOB threshold val 03'h R/W
01h 08h Reserved RSVD (set to default) 00'h R/W
01h 09h Global XFI Input
channel con-
fig_reg4
RSVD Polarity
invert
RSVD 00'h R/W
01h 0Ah Global XFI Input
channel con-
fig_reg5
RSVD Output squelch level for
LOS
RSVD 00'h R/W
01h 10h Global KR Out-
put channel
config_reg1
TX swing ppd Postcur de-emph Precur de-emph 60'h R/W
01h 11h Global KR Out-
put channel
config_reg2
polarity inv RSVD Alarm Squelch level 01'h R/W
01h 12h Global KR Out-
put channel
config_reg3
Enable outputs RSVD 00'h R/W
01h 13h Global KR Out-
put channel
config_reg4
RSVD Tap0 magni-
tude adj
Tap0 mag adj val 0B'h R/W
01h 14h Reserved RSVD (set to default) 00'h R/W
Table 5-1. Register Summary
Page Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
Control Register Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
01h 15h Global XFI Out-
put channel
config_reg1
TX swing ppd Postcur de-emph Precur de-emph 60'h R/W
01h 16h Global XFI Out-
put channel
config_reg2
polarity inv RSVD Alarm Squelch level 01'h R/W
01h 17h Global XFI Out-
put channel
config_reg3
Enable outputs RSVD 00'h R/W
01h 18h Global XFI Out-
put channel
config_reg4
RSVD Tap0 magni-
tude adj
Tap0 mag adj val 0B'h R/W
01h 19h Reserved RSVD (set to default) 00'h R/W
01h 30h-42h :
06h
Reserved RSVD (set to default) 3F'h R/W
01h 31h-43h :
06h
KR[m] Input
config_reg2
RSVD LOS time
ctrl
RSVD LOS threshold val 00'h R/W
01h 32h-44h :
06h
KR[m] Input
config_reg3
RSVD Front End
OOB
Enable OOB OOB deglitch
en
OOB threshold val 03'h R/W
01h 33h-45h :
06h
Reserved RSVD (set to default) 00'h R/W
01h 34h-46h :
06h
KR[m] Input
config_reg5
RSVD Polarity
invert
RSVD 00'h R/W
01h 35h-47h :
06h
KR[m] Input
config_reg6
RSVD Output squelch level for
LOS
RSVD 00'h R/W
01h 48h-57h :
05h
XFI[m] Input
config_reg1
RSVD LOS time
ctrl
RSVD LOS threshold val 00'h R/W
01h 49h-58h :
05h
XFI[m] Input
config_reg2
RSVD Enable OOB OOB deglitch
en
OOB threshold val 03'h R/W
01h 4Ah-59h :
05h
Reserved RSVD (set to default) 00'h R/W
01h 4Bh-5Ah :
05h
XFI[m] Input
config_reg4
RSVD Polarity
invert
RSVD 00'h R/W
01h 4Ch-5Bh :
05h
XFI[m] Input
config_reg5
RSVD Output squelch level for
LOS
RSVD 00'h R/W
01h 5Ch-6Eh :
06h
Reserved RSVD (set to default) 3F'h R/W
01h 5Dh-6Fh :
06h
KRr[0] Input
config_reg2
RSVD LOS time
ctrl
RSVD LOS threshold val 00'h R/W
01h 5Eh-70h :
06h
KRr[m] Input
config_reg3
RSVD Front End
OOB
Enable OOB OOB deglitch
en
OOB threshold val 03'h R/W
01h 5Fh-71h :
06h
Reserved RSVD (set to default) 00'h R/W
01h 60h-72h :
06h
KRr[m] Input
config_reg5
RSVD Polarity
invert
RSVD 00'h R/W
01h 61h-73h :
06h
KRr[m] Input
config_reg6
RSVD Output squelch level for
LOS
RSVD 00'h R/W
01h 74h-ABh :
05h*
Output chan-
nel[m] con-
fig_reg1
TX swing ppd Postcur de-emph Precur de-emph 60'h R/W
01h 75h-ACh :
05h*
Output chan-
nel[m] con-
fig_reg2
polarity inv RSVD Alarm Squelch level 01'h R/W
Table 5-1. Register Summary
Page Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®49
Preliminary Information / Mindspeed Proprietary and Confidential
01h 76h-ADh :
05h*
Output chan-
nel[m] con-
fig_reg3
Enable outputs RSVD 00'h R/W
01h 77h-AEh :
05h*
Output chan-
nel[m] con-
fig_reg4
RSVD Tap0 magni-
tude adj
Tap0 mag adj val 0B'h R/W
01h 78h-AFh :
05h*
Reserved RSVD (set to default) 00'h R/W
01h B0h KR Output
channel slew
rate reg1
RSVD Slew RateA RSVD Slew RateB 88'h R/W
01h B1h Reserved RSVD (set to default) 00'h R/W
01h B2h XFI Output
channel slew
rate reg1
RSVD Slew RateA RSVD Slew RateB 88'h R/W
01h B3h Reserved RSVD (set to default) 00'h R/W
01h FFh Page Addr RSVD page addr 00'h R/W
Page 02h and 04h
02h-04h : 02h 00h-80h :
80h
PLL_Bank[m]:
EyeMon Con-
fig0
Finished/Start length Encode Control RSVD channel 03'h R/W
02h-04h : 02h 01h-81h :
80h
PLL_Bank[m]:
EyeMon Con-
fig1
RSVD condition mask RSVD 00'h R/W
02h-04h : 02h 02h-82h :
80h
PLL_Bank[m]:
EyeMon Voltage
RSVD Voltage 00'h R/W
02h-04h : 02h 03h-83h :
80h
PLL_Bank[m]:
EyeMon Con-
fig2
RSVD ext_phase_en RSVD extended
phase 1
extended
phase 0
00'h R/W
02h-04h : 02h 04h-84h :
80h
PLL_Bank[m]:
EyeMon Phase
value 00'h R/W
02h-04h : 02h 05h-85h :
80h
PLL_Bank[m]:
EyeMon Rota-
tion
Auto Align Transfer Control Alignment 00'h R/W
02h-04h : 02h 06h-86h :
80h
Reserved RSVD (set to default) 00'h R/W
02h-04h : 02h 07h-87h :
80h
Reserved RSVD (set to default) 10'h R/W
02h-04h : 02h 08h-88h :
80h
PLL_Bank[m]:
EyeMon
Result0
Err count 00'h R
02h-04h : 02h 09h-89h :
80h
PLL_Bank[m]:
EyeMon
Result1
Err count 00'h R
02h-04h : 02h 0Ah-8Ah :
80h
PLL_Bank[m]:
EyeMon
Result2
Err count 00'h R
02h-04h : 02h 0Bh-8Bh :
80h
PLL_Bank[m]:
EyeMon
Result3
Err count 00'h R
02h-04h : 02h 0Ch-8Ch :
80h
PLL_Bank[m]:
EyeMon
Result4
Mask count 00'h R
Table 5-1. Register Summary
Page Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®50
Preliminary Information / Mindspeed Proprietary and Confidential
02h-04h : 02h 0Dh-8Dh :
80h
PLL_Bank[m]:
EyeMon
Result5
Mask count 00'h R
02h-04h : 02h 0Eh-8Eh :
80h
PLL_Bank[m]:
EyeMon
Result6
Mask count 00'h R
02h-04h : 02h 0Fh-8Fh :
80h
PLL_Bank[m]:
EyeMon
Result7
Mask count 00'h R
02h-04h : 02h 10h-30h :
10h
Reserved RSVD (set to default) C0'h R/W
02h-04h : 02h 11h-31h :
10h
PLL_Bank[m]:
CH[n] Gain
Value
RSVD gain value 7F'h R/W
02h-04h : 02h 12h-32h :
10h
PLL_Bank[m]:
CH[n] DFE0
Value
RSVD Tap 0 value 40'h R/W
02h-04h : 02h 13h-33h :
10h
PLL_Bank[m]:
CH[n] DFE1
Value
RSVD Tap 1 value 40'h R/W
02h-04h : 02h 14h-34h :
10h
PLL_Bank[m]:
CH[n] DFE2
Value
RSVD Tap 2 value 40'h R/W
02h-04h : 02h 15h-35h :
10h
PLL_Bank[m]:
CH[n] DFE3
Value
RSVD Tap 3 value 40'h R/W
02h-04h : 02h 16h-36h :
10h
PLL_Bank[m]:
CH[n] FFE Value
RSVD FFE value 00'h R/W
02h-04h : 02h 17h-37h :
10h
PLL_Bank[m]:
CH[n] Goal
Value
RSVD Goal Value 2A'h R/W
02h-04h : 02h 18h-38h :
10h
PLL_Bank[m]:
CH[n] DFE
adaption
hold goal hold DFE3 hold DFE2 hold DFE1 hold DFE0 hold offset hold gain stream FFE 18'h R/W
02h-04h : 02h 19h-39h :
10h
PLL_Bank[m]:
CH[n] PRBS
Gen
RSVD PRBS Mode enable pattern invert pattern 00'h R/W
02h-04h : 02h 1Ah-3Ah :
10h
PLL_Bank[m]:
CH[n] PRBS
Detector Con-
trol
len enable pattern invert pattern 00'h R/W
02h-04h : 02h 1Bh-3Bh :
10h
PLL_Bank[m]:
CH[n] PRBS
Detector Status
Latch Enable Extended Length RSVD Latch Error full/start 00'h R/W
02h-04h : 02h 1Ch-3Ch :
10h
PLL_Bank[m]:
CH[n] PRBS
Error Count 0
count 00'h R
02h-04h : 02h 1Dh-3Dh :
10h
PLL_Bank[m]:
CH[n] PRBS
Error Count 1
count 00'h R
02h-04h : 02h 1Eh-3Eh :
10h
PLL_Bank[m]:
CH[n] PRBS
Error Count 2
count 00'h R
02h-04h : 02h 1Fh-3Fh :
10h
PLL_Bank[m]:
CH[n] PRBS
Error Count 3
count 00'h R
Table 5-1. Register Summary
Page Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®51
Preliminary Information / Mindspeed Proprietary and Confidential
02h-04h : 02h 40h PLL_Bank[m]:
Channel CDR
Status
PLL_LOL LOR KR_PRBS KRr_PRBS XFI_PRBS KR_LOL KRr_LOL XFI_LOL NA R
02h-04h : 02h 41h PLL_Bank[m]:
CDR Delta
PLL_LOL Delta LOR Delta KR_PRBS
Delta
KRr_PRBS
Delta
XFI_PRBS
Delta
KR_LOL
Delta
KRr_LOL
Delta
XFI_LOL
Delta
NA R
02h-04h : 02h 42h Reserved RSVD (set to default) 00'h R/W
02h-04h : 02h 43h Reserved RSVD (set to default) 00'h R/W
02h-04h : 02h FFh Page Addr RSVD page addr 00'h R/W
06h FFh Page Addr RSVD page addr 00'h R/W
NOTES:
* Additional addresses apply. Please see Register Details.
Table 5-1. Register Summary
Page Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®52
Preliminary Information / Mindspeed Proprietary and Confidential
5.1 Page 00h
Page: 00h
Address: 00h
Register Name: Checksum seed
Default Value: 55'h
Description: Checksum seed. EEPROM downloadable.
The value of this registers is added to the sum of addresses 01h-F3h of the EEPROM to verify that the configuration is valid. The
sum of address 00h-F3h needs to have a value of the lower 8 bits be 2Eh.
Page: 00h
Address: 01h
Register Name: Gen SW Config
Default Value: 04'h
Description: Strobe mode selection made with hardware pin or control register. Set control to Channel or Port mode and power down device.
EEPROM downloadable.
Page: 00h
Address: 02h
Register Name: MIC Reg
Default Value: 00'h
Description: Number of additional M2144x SIC devices to be configured from the MIC device. self configure. EEPROM downloadable.
Bit(s) Name Description Default Type
[7:0] checksum 01010101b: Checksum offset to make the sum of addresses 00h-F3h = 2Eh 01010101b R/W
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] strobe 0b: Strobe pin xSET to change SW config
1b: Strobe control reg to change SW config (ACL regs only written to when this bit=1)
0b R/W
[3] RSVD Reserved (set to default) 0b R/W
[2] mode 0b: Channel mode
1b: Group mode
1b R/W
[1] RSVD Reserved (set to default) 0b R/W
[0] standby 0b: Normal operation
1b: Place device in standby
0b R/W
Bit(s) Name Description Default Type
[7:0] slave devices 00000000b: Number of devices 00000000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®53
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: 03h
Register Name: MDIO device addr
Default Value: 01'h
Description: MDIO device address. EEPROM downloadable.
Page: 00h
Address: HEX( 16 + n*1 ) n=0...11
KR0 = 10h, KR1 = 11h, KR2 = 12h, KR3 = 13h
XFI0 = 14h, XFI1 = 15h, XFI2 = 16h, XFI3 = 17h
KR0r = 18h, KR1r = 19h, KR2r = 1Ah, KR3r = 1Bh (M21441 only)
Register Name: Active SW state Output[n]
Default Value: See Note
Description: Changes active switch configuration. In single channel mode this control register is used to map an input channel to output channel
[n], and in group mode this control register is used to map an input group to output group [n].
EEPROM downloadable.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4:0] MDIO device addr 00000b: Address 00h
00001b: Address 01h
11111b: Address 1Fh
00001b R/W
Bit(s) Name Description Default Type
[7:4] RSVD Reserved (set to default) 0000b R/W
[3:0] Output Channel
[n]
0000b: Input KR0 / Group KR
0001b: Input KR1 / Group XFI
0010b: Input KR2 / Group KRr (M21441 only)
0011b: Input KR3
0100b: Input XFI0
0101b: Input XFI1
0110b: Input XFI2
0111b: Input XFI3
1000b: Input KR0r (M21441 only)
1001b: Input KR1r (M21441 only)
1010b: Input KR2r (M21441 only)
1011b: Input KR3r (M21441 only)
1100b: Not used
1101b: Not used
1110b: Not used
1111b: Not used
R/W
NOTES:
1. The Defaults are as follows.
XFI0 -> KR0, XFI1 -> KR1, XFI2 -> KR2, XFI3 -> KR3.
KR0 -> XFI0, KR0 -> XFI1, KR2 -> XFI2, KR3 -> XFI3.
XFI0 -> KR0r, XFI1 -> KR1r, XFI2 -> KR2r, XFI3 -> KR3r (M21441 only).
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®54
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX( 32 + n*1 ) n=0...11
KR0 = 20h, KR1 = 21h, KR2 = 22h, KR3 = 23h
XFI0 = 24h, XFI1 = 25h, XFI2 = 26h, XFI3 = 27h
KR0r = 28h, KR1r = 29h, KR2r = 2Ah, KR3r = 2Bh (M21441only)
Register Name: Intermediate SW state#1 Output[n]
Default Value: See Note
Description: This control register is used to select a switch configuration without changing the current or active switch configuration (ASC).
Upon strobe to a hardware pin or control register, this intermediate switch configuration (ISC#1) is made active and is latched to the
ASC control registers. In channel mode this control register is used to map an input channel to output channel [n], and in group
mode this control register is used to map an input group to output group [n].
EEPROM downloadable.
Bit(s) Name Description Default Type
[7:4] RSVD Reserved (set to default) 0000b R/W
[3:0] Output Channel
[n]
0000b: Input KR0 / Group KR
0001b: Input KR1 / Group XFI
0010b: Input KR2 / Group KRr (M21441 only)
0011b: Input KR3
0100b: Input XFI0
0101b: Input XFI1
0110b: Input XFI2
0111b: Input XFI3
1000b: Input KR0r (M21441 only)
1001b: Input KR1r (M21441 only)
1010b: Input KR2r (M21441 only)
1011b: Input KR3r (M21441 only)
1100b: Not used
1101b: Not used
1110b: Not used
1111b: Not used
R/W
NOTES:
1. The Defaults are as follows.
XFI0 -> KR0, XFI1 -> KR1, XFI2 -> KR2, XFI3 -> KR3.
KR0 -> XFI0, KR0 -> XFI1, KR2 -> XFI2, KR3 -> XFI3.
XFI0 -> KR0r, XFI1 -> KR1r, XFI2 -> KR2r, XFI3 -> KR3r (M21441 only).
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®55
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX( 48 + n*1 ) n=0...11
KR0 = 30h, KR1 = 31h, KR2 = 32h, KR3 = 33h
XFI0 = 34h, XFI1 = 35h, XFI2 = 36h, XFI3 = 37h
KR0r = 38h, KR1r = 39h, KR2r = 3Ah, KR3r = 3Bh (M21441 only)
Register Name: Intermediate SW state#2 Output[n]
Default Value: See Note
Description: This control register is used to select a switch configuration without changing the current or active switch configuration (ASC).
Upon strobe to a hardware pin or control register, this intermediate switch configuration (ISC#2) is made active and is latched to the
ASC control registers. In channel mode this control register is used to map an input channel to output channel [n], and in group
mode this control register is used to map an input group to output group [n].
EEPROM downloadable.
Bit(s) Name Description Default Type
[7:4] RSVD Reserved (set to default) 0000b R/W
[3:0] Output Channel
[n]
0000b: Input KR0 / Group KR
0001b: Input KR1 / Group XFI
0010b: Input KR2 / Group KRr (M21441 only)
0011b: Input KR3
0100b: Input XFI0
0101b: Input XFI1
0110b: Input XFI2
0111b: Input XFI3
1000b: Input KR0r (M21441 only)
1001b: Input KR1r (M21441 only)
1010b: Input KR2r (M21441 only)
1011b: Input KR3r (M21441 only)
1100b: Not used
1101b: Not used
1110b: Not used
1111b: Not used
R/W
NOTES:
1. The Defaults are as follows.
XFI0 -> KR0, XFI1 -> KR1, XFI2 -> KR2, XFI3 -> KR3.
KR0r -> XFI0, KR0r -> XFI1, KR2r -> XFI2, KR3r -> XFI3.
XFI0 -> KR0r, XFI1 -> KR1r, XFI2 -> KR2r, XFI3 -> KR3r (M21441 only).
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®56
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: 3Fh
Register Name: Strobe
Default Value: 00'h
Description: Changes switch configuration with strobe to this self-clearing control register. Intermediate switch configuration (ISC) transferred
to active switch configuration (ASC) upon strobe. EEPROM downloadable.
Page: 00h
Address: HEX( 64 + n*16 ) n=0...3
PLL0 (XFI0_in, KR0r_in, KR0_in) = 40h
PLL1 (XFI1_in, KR1r_in, KR1_in) = 50h
PLL2 (XFI2_in, KR2r_in, KR2_in) = 60h
PLL3 (XFI3_in, KR3r_in, KR3_in) = 70h
Register Name: PLL[n]: Preset
Default Value: 00'h
Description: Loads the PLL with a built in preset for some common protocols. EEPROM Downloadable
Bit(s) Name Description Default Type
[7] icl_sel 0b: Sets ISC#1 as the active state to become ACL upon strobe
1b: Sets ISC#2 as the active state to become ACL upon strobe
0b R/W
[6] xSET_mode 0b: xSET: L->H= select ISC#1 & H->L= ISC#2 as the active state (when Gen SW config
reg<4>=0)
1b: xSET: H->L changes active state to either ISC#1 or ISC#2 depending on bit7 above
(when Gen SW config reg<4>=0)
0b R/W
[5:0] strobe 000000b: Normal operation
101010b: Change Switch configuration
000000b R/W
Bit(s) Name Description Default Type
[7:0] Preset 00000000b: 10G KR / XAUI / GbE with 156.25 MHz Reference Clock 2
00000001b: 10G KR Only with 156.25 MHz Reference Clock 2
00000010b: GbE Only with 125 MHz Reference Clock 1
00000011b: GbE Only with 156.25 MHz Reference Clock 2
00000100b: XAUI Only with 125 MHz Reference Clock 1
00000101b: XAUI Only with 156.25 MHz Reference Clock 2
00000110b: XAUI Only with 62.5 MHz Reference Clock 2
00001000b: FibreChannel with 125 MHz Reference Clock 1
00001001b: FibreChannel with 106.25 MHz Reference Clock 2
00001010b: FibreChannel with 62.5 MHz Reference Clock 2
00001011b: FibreChannel with 212.5 MHz Reference Clock 2
00011000b: InfiniBand with 125 MHz Reference Clock 1
00011001b: InfiniBand with 1005 MHz Reference Clock 2
00011010b: InfiniBand with 62.5 MHz Reference Clock 2
00101000b: SONET with 155.52 MHz Reference Clock 2
00101001b: SONET with 77.76 MHz Reference Clock 2
00101010b: SONET with 311.04 MHz Reference Clock 2
00110000b: 10G FEC with 32x Clock Multiplier
00000000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®57
Preliminary Information / Mindspeed Proprietary and Confidential
[7:0]
(continued)
Preset 00110001b: 10G FEC with 64x Clock Multiplier
00110010b: 10G FEC with 16x Clock Multiplier
00110011b: 10G FEC with 40x Clock Multiplier
00110100b: 10G FEC with 50x Clock Multiplier
00110101b: 10G FEC with 60x Clock Multiplier
00110110b: 10G FEC with 80x Clock Multiplier
01000000b: 7.5 GHz with 125 MHz Reference Clock
01000001b: 7.5 GHz with 156.25 MHz Reference Clock
01000010b: 7.5 GHz with 62.5 MHz Reference Clock
01000011b: 7.5 GHz with 312.5 MHz Reference Clock
01010000b: 10G KR / XAUI / GbE with 156.25 MHz Reference Clock, Redundant KR
input is Master
01100000b: 10G KR / XAUI / GbE with 156.25 MHz Reference Clock, Primary KR input
is Master
00000000b R/W
NOTES:
1. See preset tab to see default values for all registers.
2. For codes not shown above, default is 10G with 125 MHz reference clock.
3. Defaults for CDR_HW[1:0] pins both set to low.
Bit(s) Name Description Default Type
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®58
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX( 65 + n*16 ) n=0...3
PLL0 (XFI0_in, KR0r_in, KR0_in) = 41h
PLL1 (XFI1_in, KR1r_in, KR1_in) = 51h
PLL2 (XFI2_in, KR2r_in, KR2_in) = 61h
PLL3 (XFI3_in, KR3r_in, KR3_in) = 71h
Register Name: PLL[n]: PLL Divide Ratio
Default Value: 00'h
Description: PLL[n] div2 enable and div ratio (min of 32). EEPROM Downloadable
Bit(s) Name Description Default Type
[7] div2 enable 0b: Reference clock treated normally
1b: Reference clock divided by two before multiplication
0b R/W
[6:0] div ratio 0000000b: Use default value
0001000b: Multiply Refclk by 32
1000000b: Multiply Refclk by 128
1111111b: Multiply Refclk by 254
0000000b R/W
NOTES:
1. When set to 00h, this register will contain the default value, based on the PLL[m] preset register.
2. When set to any value other than 00h, the register value will be used instead of the default value.
3. Since the default of this register is 00h, it will not read back 00h at reset.
4. The 7 LSB's represent a number (0-127), with values less than 16 treated as being 16. The number in these bits is multiplied by two to create the
effective PLL multiplication ratio. As an example, to get to 10.3125 GHz in the PLL with a 156.25 MHz Reference clock, these bits should be set
to 21h (multiply by 66).
5. The reference clock divide-by-two circuit should be enabled only for threee possible reasons: The first is when the reference clock frequency is
greater than 250 MHz. The second is when a muliplier less than 32 is required. The final reason is to get a non-modulo-two multiplication factor
(e.g. 65).
6. Defaults for CDR_HW[1:0] pins both set to low.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®59
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX( 66 + n*16 ) n=0...3
PLL0 (XFI0_in, KR0r_in, KR0_in) = 42h
PLL1 (XFI1_in, KR1r_in, KR1_in) = 52h
PLL2 (XFI2_in, KR2r_in, KR2_in) = 62h
PLL3 (XFI3_in, KR3r_in, KR3_in) = 72h
Register Name: PLL[n]: PLL Control
Default Value: 00'h
Description: PLL[n] control. EEPROM Downloadable
Bit(s) Name Description Default Type
[7] Bank pd 0b: Normal operation
1b: Power down
0b R/W
[6] VCO over-ride 0b: Use default value
1b: Over-ride
0b R/W
[5] VCO select 0b: VCO low
1b: VCO high
0b R/W
[4] lbw over-ride 0b: Normal operation
1b: Over-ride
0b R/W
[3:2] PLL LBW 00b: Lowest
01b: ...
10b: ...
11b: Highest
00b R/W
[1] Refclk over-ride 0b: Use default value
1b: Override the reference clock selection
0b R/W
[0] Refclk Select 0b: Select Reference Clock 1
1b: Select Reference Clock 2
0b R/W
NOTES:
1. When bit 6 is 0, bit 5 will read back the default value, based on the CDR Bank[m] preset register.
2. When bit 4 is 0, bits [3:2] will read back the default value, based on the CDR Bank[m] preset register.
3. When bit 1 is 0, bit 0 will read back the default value, based on the CDR Bank[m] preset register.
4. Since the default state of bits 6, 4, and 1 is 0, this register will not read back 00h at reset.
5. Defaults for CDR_HW[1:0] pins both set to low.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®60
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX( 67 + n*16 ) n=0...3
PLL0 (XFI0_in, KR0r_in, KR0_in) = 43h
PLL1 (XFI1_in, KR0r_in, KR1_in) = 53h
PLL2 (XFI2_in, KR0r_in, KR2_in) = 63h
PLL3 (XFI3_in, KR0r_in, KR3_in) = 73h
Register Name: PLL[n]: Interrupt Mask
Default Value: 00'h
Description: PLL[n] Interrupt Mask. EEPROM Downloadable
Bit(s) Name Description Default Type
[7] PLL LOL Mask 0b: PLL LOL change does not generate interrupt
1b: PLL LOL change generates interrupt
0b R/W
[6] LOR Mask 0b: NOREF change does not generate interrupt
1b: NOREF change generates interrupt
0b R/W
[5] PRBS KR Mask 0b: Channel KR PRBS Detector change does not generate interrupt
1b: Channel KR PRBS Detector change generates interrupt
0b R/W
[4] PRBS KRr Mask 0b: Channel KRr PRBS Detector change does not generate interrupt
1b: Channel KRr PRBS Detector change generates interrupt
0b R/W
[3] PRBS XFI Mask 0b: Channel XFI PRBS Detector change does not generate interrupt
1b: Channel XFI PRBS Detector change generates interrupt
0b R/W
[2] LOL KR Mask 0b: Channel KR LOL change does not generate interrupt
1b: Channel KR LOL change generates interrupt
0b R/W
[1] LOL KRr Mask 0b: Channel KRr LOL change does not generate interrupt
1b: Channel KRr LOL change generates interrupt
0b R/W
[0] LOL XFI Mask 0b: Channel XFI LOL change does not generate interrupt
1b: Channel XFI LOL change generates interrupt
0b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®61
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX (68 + 4n + 10 m) n = 0..3, m = 0..2
XFI0 = 44h, XFI1 = 54h, XFI2 = 64h, XFI3 = 74h
KR0r = 48h, KR1r = 58h, KR2r = 68h, KR3r = 78h
KR0 = 4Ch, KR1 = 5Ch, KR2 = 6Ch, KR3 = 7Ch
Register Name: CDR[m]: CRU Control A[n]
Default Value: 00'h
Description: CDR CRU Control A. Leakage introduces an offset into the loop to facilitate lock determination. The ppm limit should be set to the
reference clock tolerance. EEPROM Downloadable.
Bit(s) Name Description Default Type
[7] leak override 0b: Use default value
1b: Override leakage control
0b R/W
[6:4] leak gain 000b: 0.48 ppm Leakage
001b: 0.96 ppm Leakage
010b: 1.91 ppm Leakage
011b: 3.82 ppm Leakage
100b: 7.65 ppm Leakage
101b: 15.25 ppm Leakage
110b: 30.5 ppm Leakage
111b: Disable Leakage
000b R/W
[3:0] LOL Limits 0000b: 91 ppm Assert Limit, 61 ppm De-Assert Limit
0001b: 122 ppm Assert Limit, 91 ppm De-Assert Limit
0010b: 183 ppm Assert Limit, 122 ppm De-Assert Limit
0011b: 244 ppm Assert Limit, 183 ppm De-Assert Limit
0100b: 366 ppm Assert Limit, 244 ppm De-Assert Limit
0101b: 488 ppm Assert Limit, 366 ppm De-Assert Limit
0110b: 732 ppm Assert Limit, 488 ppm De-Assert Limit
0111b: 1k ppm Assert Limit, 732 ppm De-Assert Limit
1000b: 1.5k ppm Assert Limit, 1k ppm De-Assert Limit
1001b: 2k ppm Assert Limit, 1.5k ppm De-Assert Limit
1010b: 3k ppm Assert Limit, 2k ppm De-Assert Limit
1011b: 4k ppm Assert Limit, 3k ppm De-Assert Limit
1100b: 6k ppm Assert Limit, 4k ppm De-Assert Limit
1101b: 8k ppm Assert Limit, 6k ppm De-Assert Limit
1110b: LOL Disabled; Leakage sign set to 1
1111b: LOL Disabled; Leakage sign set to 0
0000b R/W
NOTES:
1. When bit 7 is 1, bits [6:0] read out the default value, based on the CDR Preset[m] register value.
2. Because the default value of bit 7 Is 0, this register will not read 00h at reset.
3. Defaults for CDR_HW[1:0] pins both set to low.
Control Register Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX (69 + 4n + 10 m) n = 0..3, m = 0..2
XFI0 = 45h, XFI1 = 55h, XFI2 = 65h, XFI3 = 75h
KR0r = 49h, KR1r = 59h, KR2r = 69h, KR3r = 79h
KR0 = 4Dh, KR1 = 5Dh, KR2 = 6Dh, KR3 = 7Dh
Register Name: CDR[m]: CRU Control B[n]
Default Value: 00'h
Description: CDR CRU Control B. Peaking controls the amount of peaking and the LBW controls the amount of jitter tracking at higher
frequencies. EEPROM Downloadable
Bit(s) Name Description Default Type
[7:4] peaking 0000b: Use default value
0001b: Minimum Peaking
0010b: ...
0011b: ...
0100b: ...
0101b: ...
0110b: ...
0111b: ...
1000b: ...
1001b: ...
1010b: ...
1011b: ...
1100b: ...
1101b: ...
1110b: Maximum Peaking
1111b: Disable second order loop
0000b R/W
[3:0] lbw 0000b: Use default value
0001b: Normal
0010b: 1.5X Normal
0011b: 2X Normal
0100b: 3X Normal
0101b: 4X Normal
0110b: 6X Normal
0111b: 8X Normal
1000b: 12X Normal
1001b: 0.75X Normal
1010b: 0.5X Normal
1011b: 0.375X Normal
1100b: 0.25X Normal
1101b: 0.1875X Normal
1110b: 0.125X Normal
1111b: CDR Tracking disabled
0000b R/W
Control Register Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX (70 + 4n + 10 m) n = 0..3, m = 0..2
XFI0 = 46h, XFI1 = 56h, XFI2 = 66h, XFI3 = 76h
KR0r = 4Ah, KR1r = 5Ah, KR2r = 6Ah, KR3r = 7Ah
KR0 = 4Eh, KR1 = 5Eh, KR2 = 6Eh, KR3 = 7Eh
Register Name: CDR[m]: ARD Control [n]
Default Value: 00'h
Description: CDR ARD (Automatic rate detection) control [0,1,2]. The two MSBs report the current pre-scale value, while the 5 LSBs control the
valid ranges for ARD searching. EEPROM Downloadable.
NOTES:
1. When bits [7:4] are set to 0h, they will read back the default value, as determined by the CDR Preset[m] register value.
2. When bits [3:0] are set to 0h, they will read back the default value, as determined by the CDR Preset[m] register value.
3. Since the default value for this register is 00h, at reset it will not read back 00h.
4. Min peaking expected <0.15UI.
5. Defaults for CDR_HW[1:0] pins both set to low.
Bit(s) Name Description Default Type
[7:6] Divide Value 00b: Divide-by-1 (6.25 Gbps-8.5 Gbps and 9.9 Gbps-10.3125 Gbps operation)
01b: Divide-by-2 (3.125 Gbps-4.25 Gbps and 4.95 Gbps-5.5 Gbps operation)
10b: Divide-by-4 (1.5625 Gbps-2.125 Gbps and 2.475 Gbps-2.75 Gbps operation)
11b: Divide-by-8 (781.25 Mbps-1.0625 Gbps and 1.2375 Gbps-1.375 Gbps operation)
00b R/W
[5] ARD Disable 0b: ARD Enabled
1b: ARD Disabled
0b R/W
[4] Range over-ride 0b: Use default valid ranges
1b: Over-ride valid ranges
0b R/W
[3] Div8_Valid 0b: Divide-by-8 is invalid for ARD searching
1b: Divide-by-8 is valid for ARD searching
0b R/W
[2] Div4_Valid 0b: Divide-by-4 is invalid for ARD searching
1b: Divide-by-4 is valid for ARD searching
0b R/W
[1] Div2_valid 0b: Divide-by-2 is invalid for ARD searching
1b: Divide-by-2 is valid for ARD searching
0b R/W
[0] Div1_valid 0b: Divide-by-1 is invalid for ARD searching
1b: Divide-by-1 is valid for ARD searching
0b R/W
NOTES:
1. Writing bits [7:6] will set the divide value; if ARD is enabled, the divide value may change before readback.
2. The valid range bits [3:0] read back the default values as set by the CDR Preset[m] register value when bit 4 is set to 0.
3. When bit 4 is set to 1, the valid range bits [3:0] read back their actual value; for normal operation, at least 1 of these bits should be set to 1, or
ARD must be disabled.
4. Because the range over-ride bit is set to 0, bits [3:0] will not read back as 0h at reset.
5. Because ARD is enabled by default, bits [7:6] may or may not read back as 00b at reset.
6. Defaults for CDR_HW[1:0] pins both set to low.
Bit(s) Name Description Default Type
Control Register Descriptions
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Preliminary Information / Mindspeed Proprietary and Confidential
Page: 00h
Address: HEX (71 + 4n + 10 m) n = 0..3, m = 0..2
XFI0 = 47h, XFI1 = 57h, XFI2 = 67h, XFI3 = 77h
KR0r = 4B, KR1r = 5Bh, KR2r = 6Bh, KR3r = 7Bh
KR0 = 4Fh, KR1 = 5Fh, KR2 = 6Fh, KR3 = 7Fh
Register Name: CDR[m]: EQ Control [n]
Default Value: 00'h
Description: CDR EQ control [0,1,2]. Bits[6:5] control how the CDR peaking behaves with prescale. EEPROM Downloadable.
Page: 00h
Address: E0h
Register Name: MasterRst
Default Value: 00'h
Description: Master Reset
writing AAh generates an internal self-clear pulse for self_reset
Page: 00h
Address: E1h
Register Name: ChipCode
Default Value: E1'h
Description: ChipCode
Bit(s) Name Description Default Type
[7] CH pd 0b: Normal operation
1b: Power down
0b R/W
[6] scaling_override 0b: Use default prescale scaling value
1b: Override prescale scaling value
0b R/W
[5] peak_scaling 0b: Constant peaking with prescale
1b: Peaking increases with prescale
0b R/W
[4] soft reset 0b: Normal operation
1b: Reset DFE & CDR registers
0b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
NOTES:
1. LOS takes priority over OOB, as both will be asserted with LOS.
2. Bit [5] reads back the default value when bit [6] is set to 0.
Bit(s) Name Description Default Type
[7:0] reset 00000000b: Normal operation
10101010b: Reset
00000000b R/W
Bit(s) Name Description Default Type
[7:0] chipcode 11100001b: M21440
11100011b: M21441
R
Control Register Descriptions
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Page: 00h
Address: E3h
Register Name: LOS alarm1
Default Value: 00'h
Description: Used to monitor loss-of-signal (LOS) for each ch. Clear the alarm bit by writing a "1" to that bit.
Page: 00h
Address: E4h
Register Name: LOS alarm2
Default Value: 00'h
Description: Used to monitor loss-of-signal (LOS) for each ch. Clear the alarm bit by writing a "1" to that bit, except for bit4, the temp alarm,
which cannot be de-asserted unless the temp alarm signal is inactive.
Bit(s) Name Description Default Type
[7] XFI3 LOS 0b: LOS alarm de-asserted for Input XFI3
1b: LOS alarm asserted for Input XFI3
0b R/W
[6] XFI2 LOS 0b: LOS alarm de-asserted for Input XFI2
1b: LOS alarm asserted for Input XFI2
0b R/W
[5] XFI1 LOS 0b: LOS alarm de-asserted for Input XFI1
1b: LOS alarm asserted for Input XFI1
0b R/W
[4] XFI0 LOS 0b: LOS alarm de-asserted for Input XFI0
1b: LOS alarm asserted for Input XFI0
0b R/W
[3] KR3 LOS 0b: LOS alarm de-asserted for Input KR3
1b: LOS alarm asserted for Input KR3
0b R/W
[2] KR2 LOS 0b: LOS alarm de-asserted for Input KR2
1b: LOS alarm asserted for Input KR2
0b R/W
[1] KR1 LOS 0b: LOS alarm de-asserted for Input KR1
1b: LOS alarm asserted for Input KR1
0b R/W
[0] KR0 LOS 0b: LOS alarm de-asserted for Input KR0
1b: LOS alarm asserted for Input KR0
0b R/W
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Temp alarm 0b: Temp alarm not active
1b: Temp alarm asserted
0b R/W
[3] KR3r LOS 0b: LOS alarm de-asserted for Input KR3r LOS
1b: LOS alarm asserted for Input KR3r LOS
0b R/W
[2] KR2r LOS 0b: LOS alarm de-asserted for Input KR2r LOS
1b: LOS alarm asserted for Input KR2r LOS
0b R/W
[1] KR1r LOS 0b: LOS alarm de-asserted for Input KR1r LOS
1b: LOS alarm asserted for Input KR1r LOS
0b R/W
[0] KR0r LOS 0b: LOS alarm de-asserted for Input KR0r LOS
1b: LOS alarm asserted for Input KR0r LOS
0b R/W
Control Register Descriptions
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Page: 00h
Address: E5h
Register Name: Mask PLL alarm
Default Value: 00'h
Description: Used to mask PLL interrupt alarm signals.
Page: 00h
Address: E6h
Register Name: Mask alarm1
Default Value: 00'h
Description: Used to mask alarm generation for LOS signals.
Bit(s) Name Description Default Type
[7:4] RSVD Reserved (set to default) 0000b R/W
[3] PLL0 mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[2] PLL1 mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[1] PLL2 mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[0] PLL3 mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
Bit(s) Name Description Default Type
[7] XFI3 LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[6] XFI2 LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[5] XFI1 LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[4] XFI0 LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[3] KR3 LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[2] KR2 LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[1] KR1 LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[0] KR0 LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
Control Register Descriptions
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Page: 00h
Address: E7h
Register Name: Mask alarm2
Default Value: 00'h
Description: Used to mask alarm generation for LOS signals.
Page: 00h
Address: E8h
Register Name: Stat alarm1
Default Value: 00'h
Description: Used to show alarm1 status for the LOS signals. Cannot be cleared by writing a one
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Temp mask 0b: Normal operation
1b: Mask temp alarm generation
0b R/W
[3] KR3r LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[2] KR2r LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[1] KR1r LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
[0] KR0r LOS mask 0b: Normal operation
1b: Mask alarm generation
0b R/W
Bit(s) Name Description Default Type
[7] XFI3 LOS stat 0b: Normal operation
1b: Alarm active
0b R
[6] XFI2 LOS stat 0b: Normal operation
1b: Alarm active
0b R
[5] XFI1 LOS stat 0b: Normal operation
1b: Alarm active
0b R
[4] XFI0 LOS stat 0b: Normal operation
1b: Alarm active
0b R
[3] KR3 LOS stat 0b: Normal operation
1b: Alarm active
0b R
[2] KR2 LOS stat 0b: Normal operation
1b: Alarm active
0b R
[1] KR1 LOS stat 0b: Normal operation
1b: Alarm active
0b R
[0] KR0 LOS stat 0b: Normal operation
1b: Alarm active
0b R
Control Register Descriptions
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Page: 00h
Address: E9h
Register Name: Stat alarm2
Default Value: 00'h
Description: Used to show alarm2 status for the LOS signals. Cannot be cleared by writing a one.
Page: 00h
Address: EAh
Register Name: Temp Sensor config
Default Value: 27'h
Description: Used to enable/disable die junction temperature sensor, strobe the temp sensor to initiate another temperature reading, and set the
threshold for temp alarm activation.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved 000b R
[4] Temp stat 0b: Normal operation
1b: Temp alarm active
0b R
[3] KR3r LOS stat 0b: Normal operation
1b: Alarm active
0b R
[2] KR2r LOS stat 0b: Normal operation
1b: Alarm active
0b R
[1] KR1r LOS stat 0b: Normal operation
1b: Alarm active
0b R
[0] KR0r LOS stat 0b: Normal operation
1b: Alarm active
0b R
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5] temp mon en 0b: Enable Temperature monitor
1b: Disable Temperature monitor
1b R/W
[4] thermal flag 0b: Thermal warning flag does not disable output stages
1b: Thermal warning flag does disable output stages
0b R/W
[3] stobe sens 0b: No effect
1b: Strobe sensor to read temp
0b R/W
[2:0] Threshold adjust 000b: 50 °C
Temperature thresholds for asserting over temperature alarm.
These threshold values are approximate and are NOT guaranteed.
001b: 65 °C
010b: 80 °C
011b: 95 °C
100b: 115 °C
101b: 120 °C
110b: 130 °C
111b: 135 °C
111b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®69
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Page: 00h
Address: EBh
Register Name: Junction Temp
Default Value: 0B'h
Description: Used to read the die junction temperature. To update temp reading the sensor must be strobed using control register Temp Sensor
Config; alarm bit updates even if sensor is not strobed. Temperature readings to be treated as coarse indication. Temperature
monitor readings of 0111b and below should be ignored as the temperature monitor is not reliable for temperatures below 40 °C.
Page: 00h
Address: FEh
Register Name: Checksum_cal
Default Value: 00'h
Description: Checksum result
Page: 00h
Address: FFh
Register Name: Page Address
Default Value: 00'h
Description: Page Address
Bit(s) Name Description Default Type
[7:4] RSVD Reserved 0000b R
[3:0] JuncT meas 0000b-0111b: Disregard, temperature is less than reliable operating range of
temperature monitor circuit.
1000b: range TCASE [50 : 65] °C
1001b: range TCASE [65 : 80] °C
1010b: range TCASE [80 : 95] °C
1011b: range TCASE [95 : 110] °C
1100b: range TCASE [110 : 115] °C
1101b: range TCASE [115 : 125] °C
1110b: range TCASE [125 : 130] °C
1111b: range TCASE > 130 °C
1011b R
Bit(s) Name Description Default Type
[7:0] checksum_cal 00000000b: Tbd 00000000b R
Bit(s) Name Description Default Type
[7:3] RSVD Reserved (set to default) 00000b R/W
[2:0] page addr 000b: Page 0
001b: Page 1
010b: Page 2
011b: Not used
100b: Page 4
101b: Not used
110b: Reserved
111b: Reserved
000b R/W
Control Register Descriptions
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5.2 Page 01h
Page: 01h
Address: 01h
Register Name: Global KR Input channel config_reg2
Default Value: 00'h
Description: Used to power down input termination amplifier, power down the complete front-end, force LOS event, control the LOS time
constant, disable LOS DC calibration, and set the LOS threshold (approximate values). Global configuration for KR inputs
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] LOS time ctrl 0b: Default LOS time control constant (~2 µs)
1b: Increased LOS time control constant (~6 µs)
0b R/W
[3] RSVD Reserved (set to default) 0b R/W
[2:0] LOS threshold val 000b: 40 mV ppd
001b: 60 mV ppd
010b: 90 mV ppd
011b: 140 mV ppd
100b: Reserved
101b: Reserved
110b: Reserved
111b: Disable LOS
000b R/W
NOTES:
1. LOS threshold values are approximate for PRBS15 data (calibration performed with valid Data present on inputs).
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®71
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Page: 01h
Address: 02h
Register Name: Global KR Input channel config_reg3
Default Value: 03'h
Description: Used to enable EQ test outputs, choose between front or Back OOB detect, enable the OOB circuit, and disable OOB deglitch, and set
the OOB threshold. Global configuration for KR inputs
Page: 01h
Address: 04h
Register Name: Global KR Input channel config_reg5
Default Value: 00'h
Description: Used to power down the LOS hysteresis, enable LOS test outputs, force LOS calibration value, flip EQ output polarity, and set the
LOS calibration value. Global configuration for KR inputs
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5] Front End OOB 0b: Normal operation
1b: Selects OOB monitor at Back of EQ
0b R/W
[4] Enable OOB 0b: Disable OOB detection
1b: Enable OOB detection
0b R/W
[3] OOB deglitch en 0b: Disable OOB deglitch
1b: Enable OOB deglitch
0b R/W
[2:0] OOB threshold val 000b: 130 mV ppd
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: 200 mV ppd
111b: Disable OOB
011b R/W
NOTES:
1. OOB threshold values are approximate for PRBS15 data, at point blank, with Front-end option.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Polarity invert 0b: Normal Operation
1b: Flip EQ output polarity
0b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Control Register Descriptions
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Page: 01h
Address: 05h
Register Name: Global KR Input channel config_reg6
Default Value: 00'h
Description: Global LOS configuration for KR inputs.
Page: 01h
Address: 06h
Register Name: Global XFI Input channel config_reg1
Default Value: 00'h
Description: Used to force LOS event, control the LOS time constant, and set the LOS threshold. Global configuration for XFI inputs.
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5:4] Output squelch
level for LOS
00b: LOS squelch to CM
01b: LOS squelch to low
10b: LOS squelch to high
11b: Reserved
00b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] LOS time ctrl 0b: Default LOS time control constant (~2 µs)
1b: Increased LOS time control constant (~6 µs)
0b R/W
[3] RSVD Reserved (set to default) 0b R/W
[2:0] LOS threshold val 000b: 40 mV ppd
001b: 60 mV ppd
010b: 90 mV ppd
011b: 140 mV ppd
100b: Reserved
101b: Reserved
110b: Reserved
111b: Disable LOS
000b R/W
NOTES:
1. LOS threshold values are approximate for PRBS15 data (calibration performed with valid Data present on inputs).
Control Register Descriptions
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Page: 01h
Address: 07h
Register Name: Global XFI Input channel config_reg2
Default Value: 03'h
Description: Used to enable the OOB circuit, and disable OOB deglitch, and set the OOB threshold. Global configuration for XFI inputs.
Page: 01h
Address: 09h
Register Name: Global XFI Input channel config_reg4
Default Value: 00'h
Description: Used to flip EQ output polarity. Global configuration for XFI inputs.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Enable OOB 0b: Disable OOB detection
1b: Enable OOB detection
0b R/W
[3] OOB deglitch en 0b: Disable OOB deglitch
1b: Enable OOB deglitch
0b R/W
[2:0] OOB threshold val 000b: 130 mV ppd
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: 200 mV ppd
111b: Disable OOB
011b R/W
NOTES:
1. OOB threshold values are approximate for PRBS15 data, at point blank.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Polarity invert 0b: Normal Operation
1b: Flip EQ output polarity
0b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Control Register Descriptions
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Page: 01h
Address: 0Ah
Register Name: Global XFI Input channel config_reg5
Default Value: 00'h
Description: Global LOS configuration for XFI inputs.
Page: 01h
Address: 10h
Register Name: Global KR Output channel config_reg1
Default Value: 60'h
Description: Used to select output swing level, select output de-emphasis levels. Global configuration for KR outputs
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5:4] Output squelch
level for LOS
00b: LOS squelch to CM
01b: LOS squelch to low
10b: LOS squelch to high
11b: Reserved
00b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Bit(s) Name Description Default Type
[7:5] TX swing ppd 001b: ~350 mV
010b: ~530 mV
011b: ~700 mV
100b: ~880 mV
101b: ~1060 mV
110b: Not used
111b: Not used
011b R/W
[4:2] Postcur de-emph 000b: No de-emphasis
001b: ~2 dB
010b: ~4 dB
011b: ~6 dB
100b: ~8 dB
101b: ~10 dB
110b: Max ~12 dB
111b: Not used
000b R/W
[1:0] Precur de-emph 00b: No de-emphasis
01b: Min de-emphasis (~1.3 dB)
10b: Med de-emphasis (~2.7 dB)
11b: Max de-emphasis (~4 dB)
00b R/W
NOTES:
1. The TX swing setting also includes the impact of the fine tune register default adjustment of -12%. If the fine tune register attenuation impact is
not included, the amplitude options from this register would be as follows: ~200 mV, ~400 mV, ~600 mV, ~800 mV, ~1000 mV, and ~1200 mV.
2. The maximum combined post and pre-cursor de-emphasis settings are as follows:
a) 4 dB pre-cursor and 8 dB post-cursor
b) 2.7 dB pre-cursor and 10 dB post-cursor
c) 1.3 dB pre-cursor and 12 dB post-cursor
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®75
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: 11h
Register Name: Global KR Output channel config_reg2
Default Value: 01'h
Description: Used to reverse polarity and to set squelch result level for alarms other than LOS. Global configuration for KR outputs.
Page: 01h
Address: 12h
Register Name: Global KR Output channel config_reg3
Default Value: 00'h
Description: Used to enable/disable outputs. Global configuration for KR outputs
Bit(s) Name Description Default Type
[7] polarity inv 0b: Normal polarity
1b: Reversed polarity
0b R/W
[6:2] RSVD Reserved (set to default) 00000b R/W
[1:0] Alarm Squelch
level
00b: Squelch level set at logic high for true & logic low for complementary outputs
01b: Squelch level set at common-mode
10b: Squelch level set at logic low for true & logic high for complementary outputs
11b: Alarm does not squelch outputs
01b R/W
NOTES:
1. Thermal flag bit (pg0 Eah<4>) set to "1" over-rides the Alarm squelch level resulting in all output drivers being disabled during an over-
temperature alarm event.
Bit(s) Name Description Default Type
[7] Enable outputs 0b: Enable high-speed outputs
1b: Disable high-speed outputs
0b R/W
[6:0] RSVD Reserved (set to default) 0000000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®76
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Page: 01h
Address: 15h
Register Name: Global XFI Output channel config_reg1
Default Value: 60'h
Description: Used to select output swing level, select output de-emphasis levels. Global configuration for XFI outputs
Bit(s) Name Description Default Type
[7:5] TX swing ppd 001b: ~350 mV
010b: ~530 mV
011b: ~700 mV
100b: ~880 mV
101b: ~1060 mV
110b: Not used
111b: Not used
011b R/W
[4:2] Postcur de-emph 000b: No de-emphasis
001b: ~2 dB
010b: ~4 dB
011b: ~6 dB
100b: ~8 dB
101b: ~10 dB
110b: Max ~12 dB
111b: Not used
000b R/W
[1:0] Precur de-emph 00b: No de-emphasis
01b: Min de-emphasis (~1.3 dB)
10b: Med de-emphasis (~2.7 dB)
11b: Max de-emphasis (~4 dB)
00b R/W
NOTES:
1. The TX swing setting also includes the impact of the fine tune register default adjustment of -12%. If the fine tune register attenuation impact is
not included, the amplitude options from this register would be as follows: ~200 mV, ~400 mV, ~600 mV, ~800 mV, ~1000 mV, and ~1200 mV.
2. The maximum combined post and pre-cursor de-emphasis settings are as follows:
a) 4 dB pre-cursor and 8 dB post-cursor
b) 2.7 dB pre-cursor and 10 dB post-cursor
c) 1.3 dB pre-cursor and 12 dB post-cursor
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®77
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: 16h
Register Name: Global XFI Output channel config_reg2
Default Value: 01'h
Description: Used to reverse polarity and to set squelch result level during Alarm events other than a LOS alarm event. Global configuration for
XFI outputs.
Page: 01h
Address: 17h
Register Name: Global XFI Output channel config_reg3
Default Value: 00'h
Description: Used to enable/disable outputs. Global configuration for XFI outputs.
Bit(s) Name Description Default Type
[7] polarity inv 0b: Normal polarity
1b: Reversed polarity
0b R/W
[6:2] RSVD Reserved (set to default) 00000b R/W
[1:0] Alarm Squelch
level
00b: Squelch level set at logic high for true & logic low for complementary outputs
01b: Squelch level set at common-mode
10b: Squelch level set at logic low for true & logic high for complementary outputs
11b: Alarm does not squelch outputs
01b R/W
NOTES:
1. Thermal flag bit (pg0 Eah<4>) set to "1" over-rides the Alarm squelch level resulting in all output drivers being disabled during an over-
temperature alarm event.
Bit(s) Name Description Default Type
[7] Enable outputs 0b: Enable high-speed outputs
1b: Disable high-speed outputs
0b R/W
[6:0] RSVD Reserved (set to default) 0000000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®78
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: HEX( 49 + n*6 ) n=0...3
31h 37h 3Dh 43h
Register Name: KR[m] Input config_reg2
Default Value: 00'h
Description: For m=0,1,2,3
Used to control the LOS time constant and set the LOS threshold. EEPROM downloadable.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] LOS time ctrl 0b: Default LOS time control constant (~2 µs)
1b: Increased LOS time control constant (~6 µs)
0b R/W
[3] RSVD Reserved (set to default) 0b R/W
[2:0] LOS threshold val 000b: 40 mV ppd
001b: 60 mV ppd
010b: 90 mV ppd
011b: 140 mV ppd
100b: Reserved
101b: Reserved
110b: Reserved
111b: Disable LOS
000b R/W
NOTES:
1. LOS threshold values are approximate for PRBS15 data (calibration performed with valid Data present on inputs).
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®79
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: HEX( 50 + n*6 ) n=0...3
32h 38h 3Eh 44h
Register Name: KR[m] Input config_reg3
Default Value: 03'h
Description: For m=0,1,2,3
Used to choose between front or Back OOB detect, enable the OOB circuit, and disable OOB deglitch, and set the OOB threshold.
EEPROM downloadable.
Page: 01h
Address: HEX( 52 + n*6 ) n=0...3
34h 3Ah 40h 46h
Register Name: KR[m] Input config_reg5
Default Value: 00'h
Description: For m=0,1,2,3
Used to flip EQ output polarity. EEPROM downloadable.
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5] Front End OOB 0b: Normal operation
1b: Selects OOB monitor at Back of EQ
0b R/W
[4] Enable OOB 0b: Disable OOB detection
1b: Enable OOB detection
0b R/W
[3] OOB deglitch en 0b: Disable OOB deglitch
1b: Enable OOB deglitch
0b R/W
[2:0] OOB threshold val 000b: 130 mV ppd
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: 200 mV ppd
111b: Disable OOB
011b R/W
NOTES:
1. OOB threshold values are approximate for PRBS15 data, at point blank, with Front-end option.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Polarity invert 0b: Normal Operation
1b: Flip EQ output polarity
0b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®80
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Page: 01h
Address: HEX( 53 + n*6 ) n=0...3
35h 3Bh 41h 47h
Register Name: KR[m] Input config_reg6
Default Value: 00'h
Description: For m=0,1,2,3
Individual LOS configuration for KR inputs.
Page: 01h
Address: HEX( 72 + n*5 ) n=0...3
48h 4Dh 52h 57h
Register Name: XFI[m] Input config_reg1
Default Value: 00'h
Description: For m=4,5,6,7
Used to control the LOS time constant and set the LOS threshold. EEPROM downloadable.
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5:4] Output squelch
level for LOS
00b: LOS squelch to CM
01b: LOS squelch to low
10b: LOS squelch to high
11b: Reserved
00b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] LOS time ctrl 0b: Default LOS time control constant (~2 µs)
1b: Increased LOS time control constant (~6 µs)
0b R/W
[3] RSVD Reserved (set to default) 0b R/W
[2:0] LOS threshold val 000b: 40 mV ppd
001b: 60 mV ppd
010b: 90 mV ppd
011b: 140 mV ppd
100b: Reserved
101b: Reserved
110b: Reserved
111b: Disable LOS
000b R/W
NOTES:
1. LOS threshold values are approximate for PRBS15 data (calibration performed with valid Data present on inputs).
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®81
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: HEX( 73 + n*5 ) n=0...3
49h 4Eh 53h 58h
Register Name: XFI[m] Input config_reg2
Default Value: 03'h
Description: For m=4,5,6,7
Used to enable the OOB circuit, and disable OOB deglitch, and set the OOB threshold. EEPROM downloadable.
Page: 01h
Address: HEX( 75 + n*5 ) n=0...3
4Bh 50h 55h 5Ah
Register Name: XFI[m] Input config_reg4
Default Value: 00'h
Description: For m=4,5,6,7
Used to flip EQ output polarity. EEPROM downloadable.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Enable OOB 0b: Disable OOB detection
1b: Enable OOB detection
0b R/W
[3] OOB deglitch en 0b: Disable OOB deglitch
1b: Enable OOB deglitch
0b R/W
[2:0] OOB threshold val 000b: 130 mV ppd
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: 200 mV ppd
111b: Disable OOB
011b R/W
NOTES:
1. OOB threshold values are approximate for PRBS15 data, at point blank.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Polarity invert 0b: Normal Operation
1b: Flip EQ output polarity
0b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®82
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: HEX( 76 + n*5 ) n=0...3
4Ch 51h 56h 5Bh
Register Name: XFI[m] Input config_reg5
Default Value: 00'h
Description: For m=4,5,6,7
Individual LOS configuration for XFI inputs.
Page: 01h
Address: HEX( 93 + n*6 ) n=0...3
5Dh 63h 69h 6Fh
Register Name: KRr[0] Input config_reg2
Default Value: 00'h
Description: For m=8,9,10,11
Used to control the LOS time constant and set the LOS threshold. EEPROM downloadable.
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5:4] Output squelch
level for LOS
00b: LOS squelch to CM
01b: LOS squelch to low
10b: LOS squelch to high
11b: Reserved
00b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] LOS time ctrl 0b: Default LOS time control constant (~2 µs)
1b: Increased LOS time control constant (~6 µs)
0b R/W
[3] RSVD Reserved (set to default) 0b R/W
[2:0] LOS threshold val 000b: 40 mV ppd
001b: 60 mV ppd
010b: 90 mV ppd
011b: 140 mV ppd
100b: Reserved
101b: Reserved
110b: Reserved
111b: Disable LOS
000b R/W
NOTES:
1. LOS threshold values are approximate for PRBS15 data (calibration performed with valid Data present on inputs).
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®83
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: HEX( 94 + n*6 ) n=0...3
5Eh 64h 6Ah 70h
Register Name: KRr[m] Input config_reg3
Default Value: 03'h
Description: For m=8,9,10,11
Used to enable the OOB circuit, and disable OOB deglitch, and set the OOB threshold. EEPROM downloadable.
Page: 01h
Address: HEX( 96 + n*6 ) n=0...3
60h 66h 6Ch 72h
Register Name: KRr[m] Input config_reg5
Default Value: 00'h
Description: For m=8,9,10,11
Used to flip EQ output polarity. EEPROM downloadable.
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5] Front End OOB 0b: Normal operation
1b: Selects OOB monitor at Back of EQ
0b R/W
[4] Enable OOB 0b: Disable OOB detection
1b: Enable OOB detection
0b R/W
[3] OOB deglitch en 0b: Disable OOB deglitch
1b: Enable OOB deglitch
0b R/W
[2:0] OOB threshold val 000b: 130 mV ppd
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: 200 mV ppd
111b: Disable OOB
011b R/W
NOTES:
1. OOB threshold values are approximate for PRBS15 data, at point blank, with Front-end option.
Bit(s) Name Description Default Type
[7:5] RSVD Reserved (set to default) 000b R/W
[4] Polarity invert 0b: Normal Operation
1b: Flip EQ output polarity
0b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®84
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: HEX( 97 + n*6 ) n=0...3
61h 67h 6Dh 73h
Register Name: KRr[m] Input config_reg6
Default Value: 00'h
Description: For m=8,9,10,11
Individual LOS configuration for KRr inputs.
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5:4] Output squelch
level for LOS
00b: LOS squelch to CM
01b: LOS squelch to low
10b: LOS squelch to high
11b: Reserved
00b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®85
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: HEX( 116 + 5n + 10 m) n = 0..3, m = 0..2
KR0 = 74h KR1 = 79h KR2 = 7Eh KR3 = 83h
XFI0 = 88h XFI1 = 8Dh XFI2 = 92h XFI3 = 97h
KR0r = 9Ch KR1r = A1h KR2h = A6 KR3r = ABh (M21441 only)
Register Name: Output channel[m] config_reg1
Default Value: 60'h
Description: For m=0..11
Used to select output swing level, select output de-emphasis levels. EEPROM downloadable.
Bit(s) Name Description Default Type
[7:5] TX swing ppd 001b: ~350 mV
010b: ~530 mV
011b: ~700 mV
100b: ~880 mV
101b: ~1060 mV
110b: Not used
111b: Not used
011b R/W
[4:2] Postcur de-emph 000b: No de-emphasis
001b: ~2 dB
010b: ~4 dB
011b: ~6 dB
100b: ~8 dB
101b: ~10 dB
110b: Max ~12 dB
111b: Not used
000b R/W
[1:0] Precur de-emph 00b: No de-emphasis
01b: Min de-emphasis (~1.3 dB)
10b: Med de-emphasis (~2.7 dB)
11b: Max de-emphasis (~4 dB)
00b R/W
NOTES:
1. The TX swing setting also includes the impact of the fine tune register default adjustment of -12%. If the fine tune register attenuation impact is
not included, the amplitude options from this register would be as follows: ~200 mV, ~400 mV, ~600 mV, ~800 mV, ~1000 mV, and ~1200 mV.
2. The maximum combined post and pre-cursor de-emphasis settings are as follows:
a) 4 dB pre-cursor and 8 dB post-cursor
b) 2.7 dB pre-cursor and 10 dB post-cursor
c) 1.3 dB pre-cursor and 12 dB post-cursor
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®86
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: HEX ( 117 + 5n + 10 m) n = 0..3, m = 0..2
KR0 = 75h KR1 = 7Ah KR2 = 7Fh KR3 = 84h
XFI0 = 89h XFI1 = 8Eh XFI2 = 93h XFI3 = 98h
KR0r = 9Dh KR1r = A2h KR2h = A7 KR3r = ACh (M21441 only)
Register Name: Output channel[m] config_reg2
Default Value: 01'h
Description: For m=0..11
Used to reverse polarity and to set squelch result level for Alarm events other than a LOS alarm event. EEPROM downloadable.
Page: 01h
Address: HEX ( 118 + 5n + 10 m) n = 0..3, m = 0..2
KR0 = 76h KR1 = 7Bh KR2 = 80h KR3 = 85h
XFI0 = 8Ah XFI1 = 8Fh XFI2 = 94h XFI3 = 99h
KR0r = 9Eh KR1r = A3h KR2h = A8 KR3r = ADh (M21441 only)
Register Name: Output channel[m] config_reg3
Default Value: 00'h
Description: For m=0..11
Used to enable/disable outputs. EEPROM downloadable.
Bit(s) Name Description Default Type
[7] polarity inv 0b: Normal polarity
1b: Reversed polarity
0b R/W
[6:2] RSVD Reserved (set to default) 00000b R/W
[1:0] Alarm Squelch
level
00b: Squelch level set at logic high for true & logic low for complementary outputs
01b: Squelch level set at common-mode
10b: Squelch level set at logic low for true & logic high for complementary outputs
11b: Alarm does not squelch outputs
01b R/W
NOTES:
1. Thermal flag bit (pg0 Eah<4>) set to "1" over-rides the Alarm squelch level resulting in all output drivers being disabled during an over-
temperature alarm event.
Bit(s) Name Description Default Type
[7] Enable outputs 0b: Enable high-speed outputs
1b: Disable high-speed outputs
0b R/W
[6:0] RSVD Reserved (set to default) 0000000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®87
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: B0h
Register Name: KR Output channel slew rate reg1
Default Value: 88'h
Description: Global configuration for Channels[3:0] and [11:8]. EEPROM downloadable.
Bit(s) Name Description Default Type
[7] RSVD Reserved (set to default) 1b R/W
[6:4] Slew RateA 000b: Fastest slew rate
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: ...
111b: Slowest slew rate
000b R/W
[3] RSVD Reserved (set to default) 1b R/W
[2:0] Slew RateB 000b: Fastest slew rate
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: ...
111b: Slowest slew rate
000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®88
Preliminary Information / Mindspeed Proprietary and Confidential
Page: 01h
Address: B2h
Register Name: XFI Output channel slew rate reg1
Default Value: 88'h
Description: Global configuration for Channels[7:4]. EEPROM downloadable.
Page: 01h
Address: FFh
Register Name: Page Addr
Default Value: 00'h
Description: Page Address
Bit(s) Name Description Default Type
[7] RSVD Reserved (set to default) 1b R/W
[6:4] Slew RateA 000b: Fastest slew rate
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: ...
111b: Slowest slew rate
000b R/W
[3] RSVD Reserved (set to default) 1b R/W
[2:0] Slew RateB 000b: Fastest slew rate
001b: ...
010b: ...
011b: ...
100b: ...
101b: ...
110b: ...
111b: Slowest slew rate
000b R/W
NOTES:
1. The fastest slew rate is approximately 40 ps. Each LSB step in Slew rateA & Slew rateB adds an additional approximate 1.5 ps to this slew rate.
Bit(s) Name Description Default Type
[7:3] RSVD Reserved (set to default) 00000b R/W
[2:0] page addr 000b: Page 0
001b: Page 1
010b: Page 2
011b: Not used
100b: Page 4
101b: Not used
110b: Reserved
111b: Reserved
000b R/W
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®89
Preliminary Information / Mindspeed Proprietary and Confidential
5.3 Page 02h & 04h
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 0 + n*128 ) n=0...1
pg2 addr 00h, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 80h, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 00h, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 80h, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Config0
Default Value: 03'h
Description: PLL Bank Eye Monitor Configuration Register0 used for count configuration and selecting Channel for monitoring
Bit(s) Name Description Default Type
[7] Finished/Start 0b: Error count not finished
1b: Error count Finished/Start Error Count
0b R/W
[6:4] length 000b: 8-bit count
001b: 10-bit count
010b: 12-bit count
011b: 16-bit count
100b: 20-bit count
101b: 24-bit count
110b: 28-bit count
111b: 32-bit count
000b R/W
[3] Encode Control 0b: Encode Error Count
1b: Do Not Encode Error Count
0b R/W
[2] RSVD Reserved (set to default) 0b R/W
[1:0] channel 00b: Use XFI[m] for eye monitor
01b: Use KRr[m] for eye monitor
10b: Use KR[m] for eye monitor
11b: Eye Monitor Disabled
11b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. Writing a 1 into bit 7 initiates an error count measurement. When read, bit 7 indicates whether or not the error count measurement has
completed or not.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®90
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 1 + n*128 ) n=0...1
pg2 addr 01h, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 81h, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 01h, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 81h, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Config1
Default Value: 00'h
Description: PLL Bank Eye Monitor Configuration Register1 used for masking
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 2 + n*128 ) n=0...1
pg2 addr 02h, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 82h, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 02h, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 82h, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Voltage
Default Value: 00'h
Description: PLL Bank Eye Monitor Voltage Register used to indicate voltage
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5:4] condition mask 00b: No condition masking used
01b: No condition masking used
10b: Mask such that only data 0's are evaluated
11b: Mask such that only data 1's are evaluated
00b R/W
[3:0] RSVD Reserved (set to default) 0000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Bit(s) Name Description Default Type
[7] RSVD Reserved 0b R
[6:0] Voltage 0000000b: Minimum
1000000b: Mid
1111111b: Max
0000000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®91
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 3 + n*128 ) n=0...1
pg2 addr 03h, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 83h, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 03h, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 83h, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Config2
Default Value: 00'h
Description: PLL Bank Eye Monitor Configuration Register2 used for extended phase selection
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 4 + n*128 ) n=0...1
pg2 addr 04h, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 84h, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 04h, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 84h, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Phase
Default Value: 00'h
Description: PLL Bank Eye Monitor Phase Register used to indicate phase
Bit(s) Name Description Default Type
[7:4] RSVD Reserved (set to default) 0000b R/W
[3] ext_phase_en 0b: Use 256 phases for all prescale values, sacrificing resolution at prescaled rates
1b: Use 256*Prescale phases, increasing eye map width as prescale increases
0b R/W
[2] RSVD Reserved (set to default) 0b R/W
[1] extended phase 1 0b: Phase bit 9, used in /4 mode, with extended phase enabled
1b: ...
0b R/W
[0] extended phase 0 0b: Phase bit 8, used in /2, /4 prescale rates with extended phase enabled
1b: ...
0b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. The extended phase only works with the divide_mask bits set to 0'h.
Bit(s) Name Description Default Type
[7:0] value 00000000b: Min
10000000b: Mid
11111111b: Max
00000000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. This register represents 2 UI of phase control in prescale 1.
3. The phase value is relative.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®92
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 5 + n*128 ) n=0...1
pg2 addr 05h, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 85h, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 05h, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 85h, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Rotation
Default Value: 00'h
Description: PLL Bank Eye Monitor Rotation Register used for alignment and clock domain transfer cycle stretching
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 8 + n*128 ) n=0...1
pg2 addr 08h, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 88h, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 08h, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 88h, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Result0
Default Value: 00'h
Description: PLL Bank Eye Monitor Result Register0
Bit(s) Name Description Default Type
[7] Auto Align 0b: Manually align, using bits [6:0]
1b: Automatically align/Alignment Complete
0b R/W
[6] Transfer Control 0b: Disable clock domain transfer cycle stretch
1b: Enable clock domain transfer cycle stretch
0b R/W
[5:0] Alignment 000000b: Alignment of -32
100000b: Alignment of 0
111111b: Alignment of +31
000000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When a 1 is written into bit [7] auto alignment will start; readback will indicate status in bit [7] (1=alignment complete), and bits [6:0] will report
the alignment value.
Bit(s) Name Description Default Type
[7:0] Err count 00000000b: Encoded Result/Bits [7:0] of error count, or bits [7:0] of error count 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When encoding is used, this register will contain the encoded result, otherwise it will contain the lowest 8 bits of the error count.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®93
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 9 + n*128 ) n=0...1
pg2 addr 09h, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 89h, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 09h, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 89h, PLL2 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Result1
Default Value: 00'h
Description: PLL Bank Eye Monitor Result Register1
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 10 + n*128 ) n=0...1
pg2 addr 0ah, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 8Ah, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 0ah, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 8Ah, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Result2
Default Value: 00'h
Description: PLL Bank Eye Monitor Result Register2
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 11 + n*128 ) n=0...1
pg2 addr 0Bh, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 8Bh, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 0Bh, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 8Bh, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Result3
Default Value: 00'h
Description: PLL Bank Eye Monitor Result Register3
Bit(s) Name Description Default Type
[7:0] Err count 00000000b: Bits [15:8] of error count 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Bit(s) Name Description Default Type
[7:0] Err count 00000000b: Bits [23:16] of error count 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Bit(s) Name Description Default Type
[7:0] Err count 00000000b: Bits [31:24] of error count 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®94
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 12 + n*128 ) n=0...1
pg2 addr 0Ch, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 8Ch, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 0Ch, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 8Ch, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Result4
Default Value: 00'h
Description: PLL Bank Eye Monitor Result Register4
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 13 + n*128 ) n=0...1
pg2 addr 0Dh, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 8Dh, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 0Dh, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 8Dh, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Result5
Default Value: 00'h
Description: PLL Bank Eye Monitor Result Register5
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 14 + n*128 ) n=0...1
pg2 addr 0Eh, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 8Eh, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 0Eh, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 8Eh, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Result6
Default Value: 00'h
Description: PLL Bank Eye Monitor Result Register6
Bit(s) Name Description Default Type
[7:0] Mask count 00000000b: Bits [7:0] of mask count 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Bit(s) Name Description Default Type
[7:0] Mask count 00000000b: Bits [15:8] of mask count 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Bit(s) Name Description Default Type
[7:0] Mask count 00000000b: Bits [23:16]of mask count 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®95
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 15 + n*128 ) n=0...1
pg2 addr 0Fh, PLL0 = XFI_in0, KRr_in0, KR_in0
pg2 addr 8Fh, PLL1 = XFI_in1, KRr_in1, KR_in1
pg4 addr 0Fh, PLL2 = XFI_in2, KRr_in2, KR_in2
pg4 addr 8Fh, PLL3 = XFI_in3, KRr_in3, KR_in3
Register Name: PLL_Bank[m]: EyeMon Result7
Default Value: 00'h
Description: PLL Bank Eye Monitor Result Register7
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 17 + n*16 ) n=0...2
pg2 addr 11h: XFI_in0, pg2 addr 21h: KRr_in0, pg2 addr 31h: KR_in0
pg2 addr 91h: XFI_in1, pg2 addr A1h: KRr_in1, pg2 addr B1h: KR_in1
pg4 addr 11h: XFI_in2, pg4 addr 21h: KRr_in2, pg4 addr 31h: KR_in2
pg4 addr 91h: XFI_in3, pg4 addr A1h: KRr_in3, pg4 addr B1h: KR_in3
Register Name: PLL_Bank[m]: CH[n] Gain Value
Default Value: 7F'h
Description: PLL Bank Gain Value Register used to indicate the Channel Gain Value
Bit(s) Name Description Default Type
[7:0] Mask count 00000000b: Bits [31:24] of mask count 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Bit(s) Name Description Default Type
[7] RSVD Reserved (set to default) 0b R/W
[6:0] gain value 0000000b: Minimum
1111111b: Maximum
1111111b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When read, this register reports the value that the DFE coefficient algorithm has for the GAIN value; when written, the register value is deposited
into the GAIN coefficient, and adaptation proceeds (unless held).
3. Due to DFE coefficient adaptation, after reset, this register may not read 7Fh.
4. Typical approximate Range from -7 to +20 dB.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®96
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 18 + n*16 ) n=0...2
pg2 addr 12h: XFI_in0, pg2 addr 22h: KRr_in0, pg2 addr 32h: KR_in0
pg2 addr 92h: XFI_in1, pg2 addr A2h: KRr_in1, pg2 addr B2h: KR_in1
pg4 addr 12h: XFI_in2, pg4 addr 22h: KRr_in2, pg4 addr 32h: KR_in2
pg4 addr 92h: XFI_in3, pg4 addr A2h: KRr_in3, pg4 addr B2h: KR_in3
Register Name: PLL_Bank[m]: CH[n] DFE0 Value
Default Value: 40'h
Description: PLL Bank DFE0 Value Register used to indicate the DFE Tap0 co-efficient value
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 19 + n*16 ) n=0...2
pg2 addr 13h: XFI_in0, pg2 addr 23h: KRr_in0, pg2 addr 33h: KR_in0
pg2 addr 93h: XFI_in1, pg2 addr A3h: KRr_in1, pg2 addr B3h: KR_in1
pg4 addr 13h: XFI_in2, pg4 addr 23h: KRr_in2, pg4 addr 33h: KR_in2
pg4 addr 93h: XFI_in3, pg4 addr A3h: KRr_in3, pg4 addr B3h: KR_in3
Register Name: PLL_Bank[m]: CH[n] DFE1 Value
Default Value: 40'h
Description: PLL Bank DFE1 Value Register used to indicate the DFE Tap1 co-efficient value
Bit(s) Name Description Default Type
[7] RSVD Reserved (set to default) 0b R/W
[6:0] Tap 0 value 0000000b: Maximum negative DFE tap 0 value
1000000b: Minimum DFE Tap 0 value
1111111b: Maximum positive DFE tap 0 value
1000000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When read, this register reports the value that the DFE coefficient algorithm has for the TAP 0 value; when written, the register value is deposited
into the TAP 0 coefficient, and adaptation proceeds (unless held).
3. Due to DFE coefficient adaptation, after reset, this register may not read 40h.
4. A typical Tap0 boost value is approximately 1.5 dB.
Bit(s) Name Description Default Type
[7] RSVD Reserved (set to default) 0b R/W
[6:0] Tap 1 value 0000000b: Maximum negative DFE tap 1 value
1000000b: Minimum DFE Tap 1 value
1111111b: Maximum positive DFE tap 1 value
1000000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When read, this register reports the value that the DFE coefficient algorithm has for the TAP 1 value; when written, the register value is deposited
into the TAP 1 coefficient, and adaptation proceeds (unless held).
3. Due to DFE coefficient adaptation, after reset, this register may not read 40h.
4. A typical Tap1 boost value is approximately 1.5 dB.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®97
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 20 + n*16 ) n=0...2
pg2 addr 14h: XFI_in0, pg2 addr 24h: KRr_in0, pg2 addr 34h: KR_in0
pg2 addr 94h: XFI_in1, pg2 addr A4h: KRr_in1, pg2 addr B4h: KR_in1
pg4 addr 14h: XFI_in2, pg4 addr 24h: KRr_in2, pg4 addr 34h: KR_in2
pg4 addr 94h: XFI_in3, pg4 addr A4h: KRr_in3, pg4 addr B4h: KR_in3
Register Name: PLL_Bank[m]: CH[n] DFE2 Value
Default Value: 40'h
Description: PLL Bank DFE2 Value Register used to indicate the DFE Tap2 co-efficient value
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 21 + n*16 ) n=0...2
pg2 addr 15h: XFI_in0, pg2 addr 25h: KRr_in0, pg2 addr 35h: KR_in0
pg2 addr 95h: XFI_in1, pg2 addr A5h: KRr_in1, pg2 addr B5h: KR_in1
pg4 addr 15h: XFI_in2, pg4 addr 25h: KRr_in2, pg4 addr 35h: KR_in2
pg4 addr 95h: XFI_in3, pg4 addr A5h: KRr_in3, pg4 addr B5h: KR_in3
Register Name: PLL_Bank[m]: CH[n] DFE3 Value
Default Value: 40'h
Description: PLL Bank DFE3 Value Register used to indicate the DFE Tap3 co-efficient value
Bit(s) Name Description Default Type
[7] RSVD Reserved (set to default) 0b R/W
[6:0] Tap 2 value 0000000b: Maximum negative DFE tap 2 value
1000000b: Minimum DFE Tap 2 value
1111111b: Maximum positive DFE tap 2 value
1000000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When read, this register reports the value that the DFE coefficient algorithm has for the TAP 2 value; when written, the register value is deposited
into the TAP 2 coefficient, and adaptation proceeds (unless held).
3. Due to DFE coefficient adaptation, after reset, this register may not read 40h.
4. A typical Tap2 boost value is approximately 1.5 dB.
Bit(s) Name Description Default Type
[7] RSVD Reserved (set to default) 0b R/W
[6:0] Tap 3 value 0000000b: Maximum negative DFE tap 3 value
1000000b: Minimum DFE Tap 3 value
1111111b: Maximum positive DFE tap 3 value
1000000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When read, this register reports the value that the DFE coefficient algorithm has for the TAP 3 value; when written, the register value is deposited
into the TAP 3 coefficient, and adaptation proceeds (unless held).
3. Due to DFE coefficient adaptation, after reset, this register may not read 40h.
4. A typical Tap3 boost value is approximately 1.5 dB.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®98
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 22 + n*16 ) n=0...2
pg2 addr 16h: XFI_in0, pg2 addr 26h: KRr_in0, pg2 addr 36h: KR_in0
pg2 addr 96h: XFI_in1, pg2 addr A6h: KRr_in1, pg2 addr B6h: KR_in1
pg4 addr 16h: XFI_in2, pg4 addr 26h: KRr_in2, pg4 addr 36h: KR_in2
pg4 addr 96h: XFI_in3, pg4 addr A6h: KRr_in3, pg4 addr B6h: KR_in3
Register Name: PLL_Bank[m]: CH[n] FFE Value
Default Value: 00'h
Description: PLL Bank FFE Value Register used to indicate the FFE value
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 23 + n*16 ) n=0...2
pg2 addr 17h: XFI_in0, pg2 addr 27h: KRr_in0, pg2 addr 37h: KR_in0
pg2 addr 97h: XFI_in1, pg2 addr A7h: KRr_in1, pg2 addr B7h: KR_in1
pg4 addr 17h: XFI_in2, pg4 addr 27h: KRr_in2, pg4 addr 37h: KR_in2
pg4 addr 97h: XFI_in3, pg4 addr A7h: KRr_in3, pg4 addr B7h: KR_in3
Register Name: PLL_Bank[m]: CH[n] Goal Value
Default Value: 2A'h
Description: PLL Bank Goal Value Register used to indicate the Goal value
Bit(s) Name Description Default Type
[7] RSVD Reserved (set to default) 0b R/W
[6:0] FFE value 0000000b: Minimum FFE value
1000000b: Middle FFE value
1111111b: Maximum FFE Value
1111111b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When read, this register reports the value that the DFE coefficient algorithm has for the FFE value; when written, the register value is deposited
into the FFE coefficient, and adaptation proceeds (unless held).
3. Due to FFE coefficient adaptation, after reset, this register may not read 7Fh.
4. Typical boost range on the FFE is approximately 3 to 15 dB at 5 GHz.
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5:0] Goal Value 000000b: Minimum Goal value
101010b: Goal Value at Reset
111111b: Maximum Goal Value
101010b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. When read, this register reports the value that the GOAL coefficient algorithm has for the GOAL value; when written, the register value is
deposited into the FFE coefficient, and adaptation proceeds (unless held).
3. Due to DFE coefficient adaptation, after reset, this register may not read default value.
4. Default Goal value is set to 500 mV ppd.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®99
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 24 + n*16 ) n=0...2
pg2 addr 18h: XFI_in0, pg2 addr 28h: KRr_in0, pg2 addr 38h: KR_in0
pg2 addr 98h: XFI_in1, pg2 addr A8h: KRr_in1, pg2 addr B8h: KR_in1
pg4 addr 18h: XFI_in2, pg4 addr 28h: KRr_in2, pg4 addr 38h: KR_in2
pg4 addr 98h: XFI_in3, pg4 addr A8h: KRr_in3, pg4 addr B8h: KR_in3
Register Name: PLL_Bank[m]: CH[n] DFE adaption
Default Value: 18'h
Description: PLL Bank DFE adaptation Register used to control the DFE adaptation
Bit(s) Name Description Default Type
[7] hold goal 0b: Normal operation
1b: Stop GOAL from being updated
0b R/W
[6] hold DFE3 0b: Normal operation
1b: Stop DFE Tap 3 from being updated
0b R/W
[5] hold DFE2 0b: Normal operation
1b: Stop DFE Tap 2 from being updated
0b R/W
[4] hold DFE1 0b: Normal operation
1b: Stop DFE Tap 1 from being updated
0b R/W
[3] hold DFE0 0b: Normal operation
1b: Stop DFE Tap 0 from being updated
0b R/W
[2] hold offset 0b: Normal operation
1b: Stop Offset from being updated
0b R/W
[1] hold gain 0b: Normal operation
1b: Stop Gain from being updated
0b R/W
[0] stream FFE 0b: Normal operation
1b: Stop FFE from being updated
0b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®100
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 25 + n*16 ) n=0...2
pg2 addr 19h: XFI_in0, pg2 addr 29h: KRr_in0, pg2 addr 39h: KR_in0
pg2 addr 99h: XFI_in1, pg2 addr A9h: KRr_in1, pg2 addr B9h: KR_in1
pg4 addr 19h: XFI_in2, pg4 addr 29h: KRr_in2, pg4 addr 39h: KR_in2
pg4 addr 99h: XFI_in3, pg4 addr A9h: KRr_in3, pg4 addr B9h: KR_in3
Register Name: PLL_Bank[m]: CH[n] PRBS Gen
Default Value: 00'h
Description: PLL Bank PRBS Generator Register used to control the channel PRBS generator
Bit(s) Name Description Default Type
[7:6] RSVD Reserved (set to default) 00b R/W
[5] PRBS Mode 0b: PRBS generator runs off extracted clock of Rx
1b: PRBS Generator runs off PLL clock
0b R/W
[4] enable 0b: Disable PRBS Generation
1b: Enable PRBS Generation
0b R/W
[3] pattern invert 0b: Use normal polarity for output pattern
1b: Invert polarity of output pattern
0b R/W
[2:0] pattern 000b: 1010 clock pattern
001b: 1100 clock pattern
010b: 11110000 clock pattern
011b: 1111111100000000 clock pattern
100b: PRBS7
101b: PRBS15
110b: PRBS23
111b: PRBS31
000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®101
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 26 + n*16 ) n=0...2
pg2 addr 1Ah: XFI_in0, pg2 addr 2Ah: KRr_in0, pg2 addr 3Ah: KR_in0
pg2 addr 9Ah: XFI_in1, pg2 addr AAh: KRr_in1, pg2 addr BAh: KR_in1
pg4 addr 1Ah: XFI_in2, pg4 addr 2Ah: KRr_in2, pg4 addr 3Ah: KR_in2
pg4 addr 9Ah: XFI_in3, pg4 addr AAh: KRr_in3, pg4 addr BAh: KR_in3
Register Name: PLL_Bank[m]: CH[n] PRBS Detector Control
Default Value: 00'h
Description: PLL Bank PRBS Detector Register used to control the channel PRBS detector
Bit(s) Name Description Default Type
[7:5] len 000b: Count errors in 2^8 bits
001b: Count errors in 2^10 bits
010b: Count errors in 2^12 bits
011b: Count errors in 2^16 bits
100b: Count errors in 2^20 bits
101b: Count errors in 2^24 bits
110b: Count errors in 2^28 bits
111b: Count errors in 2^32 bits
000b R/W
[4] enable 0b: Disable PRBS Detection
1b: Enable PRBS Detection
0b R/W
[3] pattern invert 0b: Use normal polarity for input pattern
1b: Invert polarity of input pattern
0b R/W
[2:0] pattern 000b: 1010 clock pattern
001b: 1100 clock pattern
010b: 11110000 clock pattern
011b: 1111111100000000 clock pattern
100b: PRBS7
101b: PRBS15
110b: PRBS23
111b: PRBS31
000b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®102
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 27 + n*16 ) n=0...2
pg2 addr 1Bh: XFI_in0, pg2 addr 2Bh: KRr_in0, pg2 addr 3Bh: KR_in0
pg2 addr 9Bh: XFI_in1, pg2 addr ABh: KRr_in1, pg2 addr BBh: KR_in1
pg4 addr 1Bh: XFI_in2, pg4 addr 2Bh: KRr_in2, pg4 addr 3Bh: KR_in2
pg4 addr 9Bh: XFI_in3, pg4 addr ABh: KRr_in3, pg4 addr BBh: KR_in3
Register Name: PLL_Bank[m]: CH[n] PRBS Detector Status
Default Value: 00'h
Description: PLL Bank PRBS Detector Status Register used to control the channel PRBS Detector
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 28 + n*16 ) n=0...2
pg2 addr 1Ch: XFI_in0, pg2 addr 2Ch: KRr_in0, pg2 addr 3Ch: KR_in0
pg2 addr 9Ch: XFI_in1, pg2 addr ACh:KRr_in1, pg2 addr BCh: KR_in1
pg4 addr 1Ch: XFI_in2, pg4 addr 2Ch: KRr_in2, pg4 addr 3Ch: KR_in2
pg4 addr 9Ch: XFI_in3, pg4 addr ACh: KRr_in3, pg4 addr BCh: KR_in3
Register Name: PLL_Bank[m]: CH[n] PRBS Error Count 0
Default Value: 00'h
Description: PLL Bank PRBS Error Count Register0 used to indicate the channel PRBS Error count
Bit(s) Name Description Default Type
[7] Latch Enable 0b: Use unlatched PRBS detection (gross pass/fail indication only)
1b: Use Latched PRBS detection (able to read error rate)
0b R
[6:4] Extended Length 000 - No extension to counter length
001 - 4 bit extension to counter length
010 - 8 bit extension to counter length
011 - 10 bit extension to counter length
100 - 12 bit extension to counter length
101 - 16 bit extension to counter length
110 - 20 bit extension to counter length
111 - Untimed error count
000b R/W
[3:2] RSVD Reserved 00b R
[1] Latch Error 0b: Error free when PRBS detection latched
1b: Not Error free when PRBS detection latched
0b R
[0] full/start 0b: PRBS Error Counter has not reached limit
1b: PRBS Error counter is at limit
0b R/W
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
2. Writing a 1 to bit 0 starts the PRBS error counter.
Bit(s) Name Description Default Type
[7:0] count 00000000b: PRBS Errors counted, bits [7:0] 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®103
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 29 + n*16 ) n=0...2
pg2 addr 1Dh: XFI_in0, pg2 addr 2Dh: KRr_in0, pg2 addr 3Dh: KR_in0
pg2 addr 9Dh: XFI_in1, pg2 addr ADh: KRr_in1, pg2 addr BDh: KR_in1
pg4 addr 1Dh: XFI_in2, pg4 addr 2Dh: KRr_in2, pg4 addr 3Dh: KR_in2
pg4 addr 9Dh: XFI_in3, pg4 addr ADh: KRr_in3, pg4 addr BDh: KR_in3
Register Name: PLL_Bank[m]: CH[n] PRBS Error Count 1
Default Value: 00'h
Description: PLL Bank PRBS Error Count Register1 used to indicate the channel PRBS Error count
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 30 + n*16 ) n=0...2
pg2 addr 1Eh: XFI_in0, pg2 addr 2Eh: KRr_in0, pg2 addr 3Eh: KR_in0
pg2 addr 9Eh: XFI_in1, pg2 addr AEh: KRr_in1, pg2 addr BEh: KR_in1
pg4 addr 1Eh: XFI_in2, pg4 addr 2Eh: KRr_in2, pg4 addr 3Eh: KR_in2
pg4 addr 9Eh: XFI_in3, pg4 addr AEh: KRr_in3, pg4 addr BEh: KR_in3
Register Name: PLL_Bank[m]: CH[n] PRBS Error Count 2
Default Value: 00'h
Description: PLL Bank PRBS Error Count Register2 used to indicate the channel PRBS Error count
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: HEX( 31 + n*16 ) n=0...2
pg2 addr 1Fh: XFI_in0, pg2 addr 2Fh: KRr_in0, pg2 addr 3Fh: KR_in0
pg2 addr 9Fh: XFI_in1, pg2 addr AFh: KRr_in1, pg2 addr BFh: KR_in1
pg4 addr 1Fh: XFI_in2, pg4 addr 2Fh: KRr_in2, pg4 addr 3Fh: KR_in2
pg4 addr 9Fh: XFI_in3, pg4 addr AFh: KRr_in3, pg4 addr BFh: KR_in3
Register Name: PLL_Bank[m]: CH[n] PRBS Error Count 3
Default Value: 00'h
Description: PLL Bank PRBS Error Count Register3 used to indicate the channel PRBS Error count
Bit(s) Name Description Default Type
[7:0] count 00000000b: PRBS Errors counted, bits [15:8] 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Bit(s) Name Description Default Type
[7:0] count 00000000b: PRBS Errors counted, bits [23:16] 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Bit(s) Name Description Default Type
[7:0] count 00000000b: PRBS Errors counted, bits [31:24] 00000000b R
NOTES:
1. PLL 0&1 on pg2, PLL 3&4 on pg4.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®104
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: pg2 addr 40h PLL0
pg2 addr C0h PLL1
pg 4 addr 40h PLL2
Pg 4 addr C0h PLL3
Register Name: PLL_Bank[m]: Channel CDR Status
Default Value: NA
Description: PLL Bank CDR status Register used to indicate the channel CDR status
Bit(s) Name Description Default Type
[7] PLL_LOL 0b: PLL is in lock
1b: PLL is out of lock
0b R
[6] LOR 0b: PLL is receiving a reference clock
1b: PLL is not receiving a reference clock
0b R
[5] KR_PRBS 0b: Channel KR PRBS detector has no errors
1b: Channel KR PRBS detector has errors
1b R
[4] KRr_PRBS 0b: Channel KRr PRBS detector has no errors
1b: Channel KRr PRBS detector has errors
1b R
[3] XFI_PRBS 0b: Channel XFI PRBS detector has no errors
1b: Channel XFI PRBS detector has errors
1b R
[2] KR_LOL 0b: Channel KR is in lock
1b: Channel KR is out of lock
0b R
[1] KRr_LOL 0b: Channel KRr is in lock
1b: Channel KRr is out of lock
0b R
[0] XFI_LOL 0b: Channel XFI is in lock
1b: Channel XFI is out of lock
0b R
NOTES:
1. Since this register represents the status of the part, it may not read 00'h at reset.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®105
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: pg2 addr 41h PLL0
pg2 addr C1h PLL1
pg 4 addr 41h PLL2
Pg 4 addr C1h PLL3
Register Name: PLL_Bank[m]: CDR Delta
Default Value: NA
Description: PLL Bank CDR Delta Register used to indicate the channel CDR Delta
Bit(s) Name Description Default Type
[7] PLL_LOL Delta 0b: No change in PLL_LOL since last write to this register
1b: PLL_LOL has changed since last write to this register
0b R/W
[6] LOR Delta 0b: No Change in LOR since last write to this register
1b: LOR has changed since last write to this register
0b R/W
[5] KR_PRBS Delta 0b: No change in KR_PRBS since last write to this register
1b: KR_PRBS has changed since last write to this register
0b R/W
[4] KRr_PRBS Delta 0b: No change in KRr_PRBS since last write to this register
1b: KRr_PRBS has changed since last write to this register
0b R/W
[3] XFI_PRBS Delta 0b: No Change in XFI_PRBS since last write to this register
1b: XFI_PRBS has changed since last write to this register
0b R/W
[2] KR_LOL Delta 0b: No change in KR_LOL since last write to this register
1b: KR_LOL has changed since last write to this register
0b R/W
[1] KRr_LOL Delta 0b: No change in KRr_LOL since last write to this register
1b: KRr_LOL has changed since last write to this register
0b R/W
[0] XFI_LOL Delta 0b: No change in XFI_LOL since last write to this register
1b: XFI_LOL has changed since last write to this register
0b R/W
NOTES:
1. Writing to this register clears all delta bits.
2. Since this register represents the state of the part, at reset, it may not read 00 at reset.
Control Register Descriptions
2144x-DSH-001-N Mindspeed Technologies®106
Preliminary Information / Mindspeed Proprietary and Confidential
Page: HEX( 2 + n*2 ) n=0...1
02h 04h
Address: FFh
Register Name: Page Addr
Default Value: 00'h
Description: Page Address
Bit(s) Name Description Default Type
[7:3] RSVD Reserved (set to default) 00000b R/W
[2:0] page addr 000b: Page 0
001b: Page 1
010b: Page 2
011b: Not used
100b: Page 4
101b: Not used
110b: Reserved
111b: Reserved
000b R/W
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